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[media] rtl2830: add parent for I2C adapter
[mirror_ubuntu-artful-kernel.git] / drivers / media / i2c / mt9p031.c
CommitLineData
418d93ac
JM		 1/*
2 * Driver for MT9P031 CMOS Image Sensor from Aptina
3 *
4 * Copyright (C) 2011, Laurent Pinchart <laurent.pinchart@ideasonboard.com>
5 * Copyright (C) 2011, Javier Martin <javier.martin@vista-silicon.com>
6 * Copyright (C) 2011, Guennadi Liakhovetski <g.liakhovetski@gmx.de>
7 *
8 * Based on the MT9V032 driver and Bastian Hecht's code.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
d6749258 15#include <linux/clk.h>
418d93ac
JM		 16#include <linux/delay.h>
17#include <linux/device.h>
15693b57 18#include <linux/gpio.h>
418d93ac
JM		 19#include <linux/i2c.h>
20#include <linux/log2.h>
8d4da37c
LP		 21#include <linux/module.h>
22#include <linux/of_gpio.h>
418d93ac 23#include <linux/pm.h>
97f21276 24#include <linux/regulator/consumer.h>
418d93ac 25#include <linux/slab.h>
418d93ac
JM		 26#include <linux/videodev2.h>
27
28#include <media/mt9p031.h>
418d93ac
JM		 29#include <media/v4l2-ctrls.h>
30#include <media/v4l2-device.h>
8d4da37c 31#include <media/v4l2-of.h>
418d93ac
JM		 32#include <media/v4l2-subdev.h>
33
08cd43cc
LP		 34#include "aptina-pll.h"
35
418d93ac
JM		 36#define MT9P031_PIXEL_ARRAY_WIDTH 2752
37#define MT9P031_PIXEL_ARRAY_HEIGHT 2004
38
39#define MT9P031_CHIP_VERSION 0x00
40#define MT9P031_CHIP_VERSION_VALUE 0x1801
41#define MT9P031_ROW_START 0x01
42#define MT9P031_ROW_START_MIN 0
43#define MT9P031_ROW_START_MAX 2004
44#define MT9P031_ROW_START_DEF 54
45#define MT9P031_COLUMN_START 0x02
46#define MT9P031_COLUMN_START_MIN 0
47#define MT9P031_COLUMN_START_MAX 2750
48#define MT9P031_COLUMN_START_DEF 16
49#define MT9P031_WINDOW_HEIGHT 0x03
50#define MT9P031_WINDOW_HEIGHT_MIN 2
51#define MT9P031_WINDOW_HEIGHT_MAX 2006
52#define MT9P031_WINDOW_HEIGHT_DEF 1944
53#define MT9P031_WINDOW_WIDTH 0x04
54#define MT9P031_WINDOW_WIDTH_MIN 2
55#define MT9P031_WINDOW_WIDTH_MAX 2752
56#define MT9P031_WINDOW_WIDTH_DEF 2592
57#define MT9P031_HORIZONTAL_BLANK 0x05
58#define MT9P031_HORIZONTAL_BLANK_MIN 0
59#define MT9P031_HORIZONTAL_BLANK_MAX 4095
60#define MT9P031_VERTICAL_BLANK 0x06
5266c98b
LP		 61#define MT9P031_VERTICAL_BLANK_MIN 1
62#define MT9P031_VERTICAL_BLANK_MAX 4096
63#define MT9P031_VERTICAL_BLANK_DEF 26
418d93ac
JM		 64#define MT9P031_OUTPUT_CONTROL 0x07
65#define MT9P031_OUTPUT_CONTROL_CEN 2
66#define MT9P031_OUTPUT_CONTROL_SYN 1
67#define MT9P031_OUTPUT_CONTROL_DEF 0x1f82
68#define MT9P031_SHUTTER_WIDTH_UPPER 0x08
69#define MT9P031_SHUTTER_WIDTH_LOWER 0x09
70#define MT9P031_SHUTTER_WIDTH_MIN 1
71#define MT9P031_SHUTTER_WIDTH_MAX 1048575
72#define MT9P031_SHUTTER_WIDTH_DEF 1943
73#define MT9P031_PLL_CONTROL 0x10
74#define MT9P031_PLL_CONTROL_PWROFF 0x0050
75#define MT9P031_PLL_CONTROL_PWRON 0x0051
76#define MT9P031_PLL_CONTROL_USEPLL 0x0052
77#define MT9P031_PLL_CONFIG_1 0x11
78#define MT9P031_PLL_CONFIG_2 0x12
79#define MT9P031_PIXEL_CLOCK_CONTROL 0x0a
80#define MT9P031_FRAME_RESTART 0x0b
81#define MT9P031_SHUTTER_DELAY 0x0c
82#define MT9P031_RST 0x0d
83#define MT9P031_RST_ENABLE 1
84#define MT9P031_RST_DISABLE 0
85#define MT9P031_READ_MODE_1 0x1e
86#define MT9P031_READ_MODE_2 0x20
87#define MT9P031_READ_MODE_2_ROW_MIR (1 << 15)
88#define MT9P031_READ_MODE_2_COL_MIR (1 << 14)
89#define MT9P031_READ_MODE_2_ROW_BLC (1 << 6)
90#define MT9P031_ROW_ADDRESS_MODE 0x22
91#define MT9P031_COLUMN_ADDRESS_MODE 0x23
92#define MT9P031_GLOBAL_GAIN 0x35
93#define MT9P031_GLOBAL_GAIN_MIN 8
94#define MT9P031_GLOBAL_GAIN_MAX 1024
95#define MT9P031_GLOBAL_GAIN_DEF 8
96#define MT9P031_GLOBAL_GAIN_MULT (1 << 6)
dfea0019 97#define MT9P031_ROW_BLACK_TARGET 0x49
418d93ac 98#define MT9P031_ROW_BLACK_DEF_OFFSET 0x4b
dfea0019
LP		 99#define MT9P031_GREEN1_OFFSET 0x60
100#define MT9P031_GREEN2_OFFSET 0x61
101#define MT9P031_BLACK_LEVEL_CALIBRATION 0x62
102#define MT9P031_BLC_MANUAL_BLC (1 << 0)
103#define MT9P031_RED_OFFSET 0x63
104#define MT9P031_BLUE_OFFSET 0x64
418d93ac
JM		 105#define MT9P031_TEST_PATTERN 0xa0
106#define MT9P031_TEST_PATTERN_SHIFT 3
107#define MT9P031_TEST_PATTERN_ENABLE (1 << 0)
108#define MT9P031_TEST_PATTERN_DISABLE (0 << 0)
109#define MT9P031_TEST_PATTERN_GREEN 0xa1
110#define MT9P031_TEST_PATTERN_RED 0xa2
111#define MT9P031_TEST_PATTERN_BLUE 0xa3
112
1c542ba8
LP		 113enum mt9p031_model {
114 MT9P031_MODEL_COLOR,
115 MT9P031_MODEL_MONOCHROME,
116};
117
418d93ac
JM		 118struct mt9p031 {
119 struct v4l2_subdev subdev;
120 struct media_pad pad;
121 struct v4l2_rect crop; /* Sensor window */
122 struct v4l2_mbus_framefmt format;
418d93ac
JM		 123 struct mt9p031_platform_data *pdata;
124 struct mutex power_lock; /* lock to protect power_count */
125 int power_count;
418d93ac 126
d6749258 127 struct clk *clk;
7997196c 128 struct regulator_bulk_data regulators[3];
97f21276 129
1c542ba8 130 enum mt9p031_model model;
08cd43cc 131 struct aptina_pll pll;
15693b57 132 int reset;
418d93ac 133
dfea0019
LP		 134 struct v4l2_ctrl_handler ctrls;
135 struct v4l2_ctrl *blc_auto;
136 struct v4l2_ctrl *blc_offset;
137
418d93ac
JM		 138 /* Registers cache */
139 u16 output_control;
140 u16 mode2;
141};
142
143static struct mt9p031 *to_mt9p031(struct v4l2_subdev *sd)
144{
145 return container_of(sd, struct mt9p031, subdev);
146}
147
148static int mt9p031_read(struct i2c_client *client, u8 reg)
149{
c27e3050 150 return i2c_smbus_read_word_swapped(client, reg);
418d93ac
JM		 151}
152
153static int mt9p031_write(struct i2c_client *client, u8 reg, u16 data)
154{
c27e3050 155 return i2c_smbus_write_word_swapped(client, reg, data);
418d93ac
JM		 156}
157
158static int mt9p031_set_output_control(struct mt9p031 *mt9p031, u16 clear,
159 u16 set)
160{
161 struct i2c_client *client = v4l2_get_subdevdata(&mt9p031->subdev);
162 u16 value = (mt9p031->output_control & ~clear) | set;
163 int ret;
164
165 ret = mt9p031_write(client, MT9P031_OUTPUT_CONTROL, value);
166 if (ret < 0)
167 return ret;
168
169 mt9p031->output_control = value;
170 return 0;
171}
172
173static int mt9p031_set_mode2(struct mt9p031 *mt9p031, u16 clear, u16 set)
174{
175 struct i2c_client *client = v4l2_get_subdevdata(&mt9p031->subdev);
176 u16 value = (mt9p031->mode2 & ~clear) | set;
177 int ret;
178
179 ret = mt9p031_write(client, MT9P031_READ_MODE_2, value);
180 if (ret < 0)
181 return ret;
182
183 mt9p031->mode2 = value;
184 return 0;
185}
186
187static int mt9p031_reset(struct mt9p031 *mt9p031)
188{
189 struct i2c_client *client = v4l2_get_subdevdata(&mt9p031->subdev);
190 int ret;
191
192 /* Disable chip output, synchronous option update */
193 ret = mt9p031_write(client, MT9P031_RST, MT9P031_RST_ENABLE);
194 if (ret < 0)
195 return ret;
196 ret = mt9p031_write(client, MT9P031_RST, MT9P031_RST_DISABLE);
197 if (ret < 0)
198 return ret;
199
200 return mt9p031_set_output_control(mt9p031, MT9P031_OUTPUT_CONTROL_CEN,
201 0);
202}
203
d6749258 204static int mt9p031_clk_setup(struct mt9p031 *mt9p031)
418d93ac 205{
08cd43cc
LP		 206 static const struct aptina_pll_limits limits = {
207 .ext_clock_min = 6000000,
208 .ext_clock_max = 27000000,
209 .int_clock_min = 2000000,
210 .int_clock_max = 13500000,
211 .out_clock_min = 180000000,
212 .out_clock_max = 360000000,
213 .pix_clock_max = 96000000,
214 .n_min = 1,
215 .n_max = 64,
216 .m_min = 16,
217 .m_max = 255,
218 .p1_min = 1,
219 .p1_max = 128,
220 };
221
418d93ac 222 struct i2c_client *client = v4l2_get_subdevdata(&mt9p031->subdev);
08cd43cc 223 struct mt9p031_platform_data *pdata = mt9p031->pdata;
418d93ac 224
d6749258
LP		 225 mt9p031->clk = devm_clk_get(&client->dev, NULL);
226 if (IS_ERR(mt9p031->clk))
227 return PTR_ERR(mt9p031->clk);
228
229 clk_set_rate(mt9p031->clk, pdata->ext_freq);
230
08cd43cc
LP		 231 mt9p031->pll.ext_clock = pdata->ext_freq;
232 mt9p031->pll.pix_clock = pdata->target_freq;
418d93ac 233
08cd43cc 234 return aptina_pll_calculate(&client->dev, &limits, &mt9p031->pll);
418d93ac
JM		 235}
236
237static int mt9p031_pll_enable(struct mt9p031 *mt9p031)
238{
239 struct i2c_client *client = v4l2_get_subdevdata(&mt9p031->subdev);
240 int ret;
241
242 ret = mt9p031_write(client, MT9P031_PLL_CONTROL,
243 MT9P031_PLL_CONTROL_PWRON);
244 if (ret < 0)
245 return ret;
246
247 ret = mt9p031_write(client, MT9P031_PLL_CONFIG_1,
08cd43cc 248 (mt9p031->pll.m << 8) | (mt9p031->pll.n - 1));
418d93ac
JM		 249 if (ret < 0)
250 return ret;
251
08cd43cc 252 ret = mt9p031_write(client, MT9P031_PLL_CONFIG_2, mt9p031->pll.p1 - 1);
418d93ac
JM		 253 if (ret < 0)
254 return ret;
255
256 usleep_range(1000, 2000);
257 ret = mt9p031_write(client, MT9P031_PLL_CONTROL,
258 MT9P031_PLL_CONTROL_PWRON |
259 MT9P031_PLL_CONTROL_USEPLL);
260 return ret;
261}
262
263static inline int mt9p031_pll_disable(struct mt9p031 *mt9p031)
264{
265 struct i2c_client *client = v4l2_get_subdevdata(&mt9p031->subdev);
266
267 return mt9p031_write(client, MT9P031_PLL_CONTROL,
268 MT9P031_PLL_CONTROL_PWROFF);
269}
270
271static int mt9p031_power_on(struct mt9p031 *mt9p031)
272{
7997196c
LP		 273 int ret;
274
418d93ac 275 /* Ensure RESET_BAR is low */
2660a22b 276 if (gpio_is_valid(mt9p031->reset)) {
15693b57 277 gpio_set_value(mt9p031->reset, 0);
418d93ac
JM		 278 usleep_range(1000, 2000);
279 }
280
97f21276 281 /* Bring up the supplies */
7997196c
LP		 282 ret = regulator_bulk_enable(ARRAY_SIZE(mt9p031->regulators),
283 mt9p031->regulators);
284 if (ret < 0)
285 return ret;
97f21276 286
418d93ac 287 /* Emable clock */
d6749258
LP		 288 if (mt9p031->clk)
289 clk_prepare_enable(mt9p031->clk);
418d93ac
JM		 290
291 /* Now RESET_BAR must be high */
2660a22b 292 if (gpio_is_valid(mt9p031->reset)) {
15693b57 293 gpio_set_value(mt9p031->reset, 1);
418d93ac
JM		 294 usleep_range(1000, 2000);
295 }
296
297 return 0;
298}
299
300static void mt9p031_power_off(struct mt9p031 *mt9p031)
301{
2660a22b 302 if (gpio_is_valid(mt9p031->reset)) {
15693b57 303 gpio_set_value(mt9p031->reset, 0);
418d93ac
JM		 304 usleep_range(1000, 2000);
305 }
306
7997196c
LP		 307 regulator_bulk_disable(ARRAY_SIZE(mt9p031->regulators),
308 mt9p031->regulators);
97f21276 309
d6749258
LP		 310 if (mt9p031->clk)
311 clk_disable_unprepare(mt9p031->clk);
418d93ac
JM		 312}
313
314static int __mt9p031_set_power(struct mt9p031 *mt9p031, bool on)
315{
316 struct i2c_client *client = v4l2_get_subdevdata(&mt9p031->subdev);
317 int ret;
318
319 if (!on) {
320 mt9p031_power_off(mt9p031);
321 return 0;
322 }
323
324 ret = mt9p031_power_on(mt9p031);
325 if (ret < 0)
326 return ret;
327
328 ret = mt9p031_reset(mt9p031);
329 if (ret < 0) {
330 dev_err(&client->dev, "Failed to reset the camera\n");
331 return ret;
332 }
333
334 return v4l2_ctrl_handler_setup(&mt9p031->ctrls);
335}
336
337/* -----------------------------------------------------------------------------
338 * V4L2 subdev video operations
339 */
340
341static int mt9p031_set_params(struct mt9p031 *mt9p031)
342{
343 struct i2c_client *client = v4l2_get_subdevdata(&mt9p031->subdev);
344 struct v4l2_mbus_framefmt *format = &mt9p031->format;
345 const struct v4l2_rect *crop = &mt9p031->crop;
346 unsigned int hblank;
347 unsigned int vblank;
348 unsigned int xskip;
349 unsigned int yskip;
350 unsigned int xbin;
351 unsigned int ybin;
352 int ret;
353
354 /* Windows position and size.
355 *
356 * TODO: Make sure the start coordinates and window size match the
357 * skipping, binning and mirroring (see description of registers 2 and 4
358 * in table 13, and Binning section on page 41).
359 */
360 ret = mt9p031_write(client, MT9P031_COLUMN_START, crop->left);
361 if (ret < 0)
362 return ret;
363 ret = mt9p031_write(client, MT9P031_ROW_START, crop->top);
364 if (ret < 0)
365 return ret;
366 ret = mt9p031_write(client, MT9P031_WINDOW_WIDTH, crop->width - 1);
367 if (ret < 0)
368 return ret;
369 ret = mt9p031_write(client, MT9P031_WINDOW_HEIGHT, crop->height - 1);
370 if (ret < 0)
371 return ret;
372
373 /* Row and column binning and skipping. Use the maximum binning value
374 * compatible with the skipping settings.
375 */
376 xskip = DIV_ROUND_CLOSEST(crop->width, format->width);
377 yskip = DIV_ROUND_CLOSEST(crop->height, format->height);
378 xbin = 1 << (ffs(xskip) - 1);
379 ybin = 1 << (ffs(yskip) - 1);
380
381 ret = mt9p031_write(client, MT9P031_COLUMN_ADDRESS_MODE,
382 ((xbin - 1) << 4) | (xskip - 1));
383 if (ret < 0)
384 return ret;
385 ret = mt9p031_write(client, MT9P031_ROW_ADDRESS_MODE,
386 ((ybin - 1) << 4) | (yskip - 1));
387 if (ret < 0)
388 return ret;
389
390 /* Blanking - use minimum value for horizontal blanking and default
391 * value for vertical blanking.
392 */
5266c98b 393 hblank = 346 * ybin + 64 + (80 >> min_t(unsigned int, xbin, 3));
418d93ac
JM		 394 vblank = MT9P031_VERTICAL_BLANK_DEF;
395
5266c98b 396 ret = mt9p031_write(client, MT9P031_HORIZONTAL_BLANK, hblank - 1);
418d93ac
JM		 397 if (ret < 0)
398 return ret;
5266c98b 399 ret = mt9p031_write(client, MT9P031_VERTICAL_BLANK, vblank - 1);
418d93ac
JM		 400 if (ret < 0)
401 return ret;
402
403 return ret;
404}
405
406static int mt9p031_s_stream(struct v4l2_subdev *subdev, int enable)
407{
408 struct mt9p031 *mt9p031 = to_mt9p031(subdev);
409 int ret;
410
411 if (!enable) {
412 /* Stop sensor readout */
413 ret = mt9p031_set_output_control(mt9p031,
414 MT9P031_OUTPUT_CONTROL_CEN, 0);
415 if (ret < 0)
416 return ret;
417
418 return mt9p031_pll_disable(mt9p031);
419 }
420
421 ret = mt9p031_set_params(mt9p031);
422 if (ret < 0)
423 return ret;
424
425 /* Switch to master "normal" mode */
426 ret = mt9p031_set_output_control(mt9p031, 0,
427 MT9P031_OUTPUT_CONTROL_CEN);
428 if (ret < 0)
429 return ret;
430
431 return mt9p031_pll_enable(mt9p031);
432}
433
434static int mt9p031_enum_mbus_code(struct v4l2_subdev *subdev,
435 struct v4l2_subdev_fh *fh,
436 struct v4l2_subdev_mbus_code_enum *code)
437{
438 struct mt9p031 *mt9p031 = to_mt9p031(subdev);
439
440 if (code->pad || code->index)
441 return -EINVAL;
442
443 code->code = mt9p031->format.code;
444 return 0;
445}
446
447static int mt9p031_enum_frame_size(struct v4l2_subdev *subdev,
448 struct v4l2_subdev_fh *fh,
449 struct v4l2_subdev_frame_size_enum *fse)
450{
451 struct mt9p031 *mt9p031 = to_mt9p031(subdev);
452
453 if (fse->index >= 8 || fse->code != mt9p031->format.code)
454 return -EINVAL;
455
456 fse->min_width = MT9P031_WINDOW_WIDTH_DEF
457 / min_t(unsigned int, 7, fse->index + 1);
458 fse->max_width = fse->min_width;
459 fse->min_height = MT9P031_WINDOW_HEIGHT_DEF / (fse->index + 1);
460 fse->max_height = fse->min_height;
461
462 return 0;
463}
464
465static struct v4l2_mbus_framefmt *
466__mt9p031_get_pad_format(struct mt9p031 *mt9p031, struct v4l2_subdev_fh *fh,
467 unsigned int pad, u32 which)
468{
469 switch (which) {
470 case V4L2_SUBDEV_FORMAT_TRY:
471 return v4l2_subdev_get_try_format(fh, pad);
472 case V4L2_SUBDEV_FORMAT_ACTIVE:
473 return &mt9p031->format;
474 default:
475 return NULL;
476 }
477}
478
479static struct v4l2_rect *
480__mt9p031_get_pad_crop(struct mt9p031 *mt9p031, struct v4l2_subdev_fh *fh,
481 unsigned int pad, u32 which)
482{
483 switch (which) {
484 case V4L2_SUBDEV_FORMAT_TRY:
485 return v4l2_subdev_get_try_crop(fh, pad);
486 case V4L2_SUBDEV_FORMAT_ACTIVE:
487 return &mt9p031->crop;
488 default:
489 return NULL;
490 }
491}
492
493static int mt9p031_get_format(struct v4l2_subdev *subdev,
494 struct v4l2_subdev_fh *fh,
495 struct v4l2_subdev_format *fmt)
496{
497 struct mt9p031 *mt9p031 = to_mt9p031(subdev);
498
499 fmt->format = *__mt9p031_get_pad_format(mt9p031, fh, fmt->pad,
500 fmt->which);
501 return 0;
502}
503
504static int mt9p031_set_format(struct v4l2_subdev *subdev,
505 struct v4l2_subdev_fh *fh,
506 struct v4l2_subdev_format *format)
507{
508 struct mt9p031 *mt9p031 = to_mt9p031(subdev);
509 struct v4l2_mbus_framefmt *__format;
510 struct v4l2_rect *__crop;
511 unsigned int width;
512 unsigned int height;
513 unsigned int hratio;
514 unsigned int vratio;
515
516 __crop = __mt9p031_get_pad_crop(mt9p031, fh, format->pad,
517 format->which);
518
519 /* Clamp the width and height to avoid dividing by zero. */
520 width = clamp_t(unsigned int, ALIGN(format->format.width, 2),
521 max(__crop->width / 7, MT9P031_WINDOW_WIDTH_MIN),
522 __crop->width);
523 height = clamp_t(unsigned int, ALIGN(format->format.height, 2),
524 max(__crop->height / 8, MT9P031_WINDOW_HEIGHT_MIN),
525 __crop->height);
526
527 hratio = DIV_ROUND_CLOSEST(__crop->width, width);
528 vratio = DIV_ROUND_CLOSEST(__crop->height, height);
529
530 __format = __mt9p031_get_pad_format(mt9p031, fh, format->pad,
531 format->which);
532 __format->width = __crop->width / hratio;
533 __format->height = __crop->height / vratio;
534
535 format->format = *__format;
536
537 return 0;
538}
539
540static int mt9p031_get_crop(struct v4l2_subdev *subdev,
541 struct v4l2_subdev_fh *fh,
542 struct v4l2_subdev_crop *crop)
543{
544 struct mt9p031 *mt9p031 = to_mt9p031(subdev);
545
546 crop->rect = *__mt9p031_get_pad_crop(mt9p031, fh, crop->pad,
547 crop->which);
548 return 0;
549}
550
551static int mt9p031_set_crop(struct v4l2_subdev *subdev,
552 struct v4l2_subdev_fh *fh,
553 struct v4l2_subdev_crop *crop)
554{
555 struct mt9p031 *mt9p031 = to_mt9p031(subdev);
556 struct v4l2_mbus_framefmt *__format;
557 struct v4l2_rect *__crop;
558 struct v4l2_rect rect;
559
560 /* Clamp the crop rectangle boundaries and align them to a multiple of 2
561 * pixels to ensure a GRBG Bayer pattern.
562 */
563 rect.left = clamp(ALIGN(crop->rect.left, 2), MT9P031_COLUMN_START_MIN,
564 MT9P031_COLUMN_START_MAX);
565 rect.top = clamp(ALIGN(crop->rect.top, 2), MT9P031_ROW_START_MIN,
566 MT9P031_ROW_START_MAX);
567 rect.width = clamp(ALIGN(crop->rect.width, 2),
568 MT9P031_WINDOW_WIDTH_MIN,
569 MT9P031_WINDOW_WIDTH_MAX);
570 rect.height = clamp(ALIGN(crop->rect.height, 2),
571 MT9P031_WINDOW_HEIGHT_MIN,
572 MT9P031_WINDOW_HEIGHT_MAX);
573
574 rect.width = min(rect.width, MT9P031_PIXEL_ARRAY_WIDTH - rect.left);
575 rect.height = min(rect.height, MT9P031_PIXEL_ARRAY_HEIGHT - rect.top);
576
577 __crop = __mt9p031_get_pad_crop(mt9p031, fh, crop->pad, crop->which);
578
579 if (rect.width != __crop->width || rect.height != __crop->height) {
580 /* Reset the output image size if the crop rectangle size has
581 * been modified.
582 */
583 __format = __mt9p031_get_pad_format(mt9p031, fh, crop->pad,
584 crop->which);
585 __format->width = rect.width;
586 __format->height = rect.height;
587 }
588
589 *__crop = rect;
590 crop->rect = rect;
591
592 return 0;
593}
594
595/* -----------------------------------------------------------------------------
596 * V4L2 subdev control operations
597 */
598
dfea0019
LP		 599#define V4L2_CID_BLC_AUTO (V4L2_CID_USER_BASE | 0x1002)
600#define V4L2_CID_BLC_TARGET_LEVEL (V4L2_CID_USER_BASE | 0x1003)
601#define V4L2_CID_BLC_ANALOG_OFFSET (V4L2_CID_USER_BASE | 0x1004)
602#define V4L2_CID_BLC_DIGITAL_OFFSET (V4L2_CID_USER_BASE | 0x1005)
418d93ac
JM		 603
604static int mt9p031_s_ctrl(struct v4l2_ctrl *ctrl)
605{
606 struct mt9p031 *mt9p031 =
607 container_of(ctrl->handler, struct mt9p031, ctrls);
608 struct i2c_client *client = v4l2_get_subdevdata(&mt9p031->subdev);
609 u16 data;
610 int ret;
611
612 switch (ctrl->id) {
613 case V4L2_CID_EXPOSURE:
614 ret = mt9p031_write(client, MT9P031_SHUTTER_WIDTH_UPPER,
615 (ctrl->val >> 16) & 0xffff);
616 if (ret < 0)
617 return ret;
618
619 return mt9p031_write(client, MT9P031_SHUTTER_WIDTH_LOWER,
620 ctrl->val & 0xffff);
621
622 case V4L2_CID_GAIN:
623 /* Gain is controlled by 2 analog stages and a digital stage.
624 * Valid values for the 3 stages are
625 *
626 * Stage Min Max Step
627 * ------------------------------------------
628 * First analog stage x1 x2 1
629 * Second analog stage x1 x4 0.125
630 * Digital stage x1 x16 0.125
631 *
632 * To minimize noise, the gain stages should be used in the
633 * second analog stage, first analog stage, digital stage order.
634 * Gain from a previous stage should be pushed to its maximum
635 * value before the next stage is used.
636 */
637 if (ctrl->val <= 32) {
638 data = ctrl->val;
639 } else if (ctrl->val <= 64) {
640 ctrl->val &= ~1;
641 data = (1 << 6) | (ctrl->val >> 1);
642 } else {
643 ctrl->val &= ~7;
644 data = ((ctrl->val - 64) << 5) | (1 << 6) | 32;
645 }
646
647 return mt9p031_write(client, MT9P031_GLOBAL_GAIN, data);
648
649 case V4L2_CID_HFLIP:
650 if (ctrl->val)
651 return mt9p031_set_mode2(mt9p031,
652 0, MT9P031_READ_MODE_2_COL_MIR);
653 else
654 return mt9p031_set_mode2(mt9p031,
655 MT9P031_READ_MODE_2_COL_MIR, 0);
656
657 case V4L2_CID_VFLIP:
658 if (ctrl->val)
659 return mt9p031_set_mode2(mt9p031,
660 0, MT9P031_READ_MODE_2_ROW_MIR);
661 else
662 return mt9p031_set_mode2(mt9p031,
663 MT9P031_READ_MODE_2_ROW_MIR, 0);
664
665 case V4L2_CID_TEST_PATTERN:
666 if (!ctrl->val) {
dfea0019
LP		 667 /* Restore the black level compensation settings. */
668 if (mt9p031->blc_auto->cur.val != 0) {
669 ret = mt9p031_s_ctrl(mt9p031->blc_auto);
670 if (ret < 0)
671 return ret;
672 }
673 if (mt9p031->blc_offset->cur.val != 0) {
674 ret = mt9p031_s_ctrl(mt9p031->blc_offset);
675 if (ret < 0)
676 return ret;
677 }
418d93ac
JM		 678 return mt9p031_write(client, MT9P031_TEST_PATTERN,
679 MT9P031_TEST_PATTERN_DISABLE);
680 }
681
682 ret = mt9p031_write(client, MT9P031_TEST_PATTERN_GREEN, 0x05a0);
683 if (ret < 0)
684 return ret;
685 ret = mt9p031_write(client, MT9P031_TEST_PATTERN_RED, 0x0a50);
686 if (ret < 0)
687 return ret;
688 ret = mt9p031_write(client, MT9P031_TEST_PATTERN_BLUE, 0x0aa0);
689 if (ret < 0)
690 return ret;
691
dfea0019
LP		 692 /* Disable digital black level compensation when using a test
693 * pattern.
694 */
418d93ac
JM		 695 ret = mt9p031_set_mode2(mt9p031, MT9P031_READ_MODE_2_ROW_BLC,
696 0);
697 if (ret < 0)
698 return ret;
dfea0019 699
418d93ac
JM		 700 ret = mt9p031_write(client, MT9P031_ROW_BLACK_DEF_OFFSET, 0);
701 if (ret < 0)
702 return ret;
703
704 return mt9p031_write(client, MT9P031_TEST_PATTERN,
705 ((ctrl->val - 1) << MT9P031_TEST_PATTERN_SHIFT)
706 | MT9P031_TEST_PATTERN_ENABLE);
dfea0019
LP		 707
708 case V4L2_CID_BLC_AUTO:
709 ret = mt9p031_set_mode2(mt9p031,
710 ctrl->val ? 0 : MT9P031_READ_MODE_2_ROW_BLC,
711 ctrl->val ? MT9P031_READ_MODE_2_ROW_BLC : 0);
712 if (ret < 0)
713 return ret;
714
715 return mt9p031_write(client, MT9P031_BLACK_LEVEL_CALIBRATION,
716 ctrl->val ? 0 : MT9P031_BLC_MANUAL_BLC);
717
718 case V4L2_CID_BLC_TARGET_LEVEL:
719 return mt9p031_write(client, MT9P031_ROW_BLACK_TARGET,
720 ctrl->val);
721
722 case V4L2_CID_BLC_ANALOG_OFFSET:
723 data = ctrl->val & ((1 << 9) - 1);
724
725 ret = mt9p031_write(client, MT9P031_GREEN1_OFFSET, data);
726 if (ret < 0)
727 return ret;
728 ret = mt9p031_write(client, MT9P031_GREEN2_OFFSET, data);
729 if (ret < 0)
730 return ret;
731 ret = mt9p031_write(client, MT9P031_RED_OFFSET, data);
732 if (ret < 0)
733 return ret;
734 return mt9p031_write(client, MT9P031_BLUE_OFFSET, data);
735
736 case V4L2_CID_BLC_DIGITAL_OFFSET:
737 return mt9p031_write(client, MT9P031_ROW_BLACK_DEF_OFFSET,
738 ctrl->val & ((1 << 12) - 1));
418d93ac 739 }
dfea0019 740
418d93ac
JM		 741 return 0;
742}
743
744static struct v4l2_ctrl_ops mt9p031_ctrl_ops = {
745 .s_ctrl = mt9p031_s_ctrl,
746};
747
748static const char * const mt9p031_test_pattern_menu[] = {
749 "Disabled",
750 "Color Field",
751 "Horizontal Gradient",
752 "Vertical Gradient",
753 "Diagonal Gradient",
754 "Classic Test Pattern",
755 "Walking 1s",
756 "Monochrome Horizontal Bars",
757 "Monochrome Vertical Bars",
758 "Vertical Color Bars",
759};
760
761static const struct v4l2_ctrl_config mt9p031_ctrls[] = {
762 {
dfea0019
LP		 763 .ops = &mt9p031_ctrl_ops,
764 .id = V4L2_CID_BLC_AUTO,
765 .type = V4L2_CTRL_TYPE_BOOLEAN,
766 .name = "BLC, Auto",
767 .min = 0,
768 .max = 1,
769 .step = 1,
770 .def = 1,
771 .flags = 0,
772 }, {
773 .ops = &mt9p031_ctrl_ops,
774 .id = V4L2_CID_BLC_TARGET_LEVEL,
775 .type = V4L2_CTRL_TYPE_INTEGER,
776 .name = "BLC Target Level",
777 .min = 0,
778 .max = 4095,
779 .step = 1,
780 .def = 168,
781 .flags = 0,
782 }, {
783 .ops = &mt9p031_ctrl_ops,
784 .id = V4L2_CID_BLC_ANALOG_OFFSET,
785 .type = V4L2_CTRL_TYPE_INTEGER,
786 .name = "BLC Analog Offset",
787 .min = -255,
788 .max = 255,
789 .step = 1,
790 .def = 32,
791 .flags = 0,
792 }, {
793 .ops = &mt9p031_ctrl_ops,
794 .id = V4L2_CID_BLC_DIGITAL_OFFSET,
795 .type = V4L2_CTRL_TYPE_INTEGER,
796 .name = "BLC Digital Offset",
797 .min = -2048,
798 .max = 2047,
799 .step = 1,
800 .def = 40,
801 .flags = 0,
418d93ac
JM		 802 }
803};
804
805/* -----------------------------------------------------------------------------
806 * V4L2 subdev core operations
807 */
808
809static int mt9p031_set_power(struct v4l2_subdev *subdev, int on)
810{
811 struct mt9p031 *mt9p031 = to_mt9p031(subdev);
812 int ret = 0;
813
814 mutex_lock(&mt9p031->power_lock);
815
816 /* If the power count is modified from 0 to != 0 or from != 0 to 0,
817 * update the power state.
818 */
819 if (mt9p031->power_count == !on) {
820 ret = __mt9p031_set_power(mt9p031, !!on);
821 if (ret < 0)
822 goto out;
823 }
824
825 /* Update the power count. */
826 mt9p031->power_count += on ? 1 : -1;
827 WARN_ON(mt9p031->power_count < 0);
828
829out:
830 mutex_unlock(&mt9p031->power_lock);
831 return ret;
832}
833
834/* -----------------------------------------------------------------------------
835 * V4L2 subdev internal operations
836 */
837
838static int mt9p031_registered(struct v4l2_subdev *subdev)
839{
840 struct i2c_client *client = v4l2_get_subdevdata(subdev);
841 struct mt9p031 *mt9p031 = to_mt9p031(subdev);
842 s32 data;
843 int ret;
844
845 ret = mt9p031_power_on(mt9p031);
846 if (ret < 0) {
847 dev_err(&client->dev, "MT9P031 power up failed\n");
848 return ret;
849 }
850
851 /* Read out the chip version register */
852 data = mt9p031_read(client, MT9P031_CHIP_VERSION);
bbcc9fa0
GL		 853 mt9p031_power_off(mt9p031);
854
418d93ac
JM		 855 if (data != MT9P031_CHIP_VERSION_VALUE) {
856 dev_err(&client->dev, "MT9P031 not detected, wrong version "
857 "0x%04x\n", data);
858 return -ENODEV;
859 }
860
418d93ac
JM		 861 dev_info(&client->dev, "MT9P031 detected at address 0x%02x\n",
862 client->addr);
863
bbcc9fa0 864 return 0;
418d93ac
JM		 865}
866
867static int mt9p031_open(struct v4l2_subdev *subdev, struct v4l2_subdev_fh *fh)
868{
869 struct mt9p031 *mt9p031 = to_mt9p031(subdev);
870 struct v4l2_mbus_framefmt *format;
871 struct v4l2_rect *crop;
872
873 crop = v4l2_subdev_get_try_crop(fh, 0);
874 crop->left = MT9P031_COLUMN_START_DEF;
875 crop->top = MT9P031_ROW_START_DEF;
876 crop->width = MT9P031_WINDOW_WIDTH_DEF;
877 crop->height = MT9P031_WINDOW_HEIGHT_DEF;
878
879 format = v4l2_subdev_get_try_format(fh, 0);
880
1c542ba8 881 if (mt9p031->model == MT9P031_MODEL_MONOCHROME)
418d93ac
JM		 882 format->code = V4L2_MBUS_FMT_Y12_1X12;
883 else
884 format->code = V4L2_MBUS_FMT_SGRBG12_1X12;
885
886 format->width = MT9P031_WINDOW_WIDTH_DEF;
887 format->height = MT9P031_WINDOW_HEIGHT_DEF;
888 format->field = V4L2_FIELD_NONE;
889 format->colorspace = V4L2_COLORSPACE_SRGB;
890
418d93ac
JM		 891 return mt9p031_set_power(subdev, 1);
892}
893
894static int mt9p031_close(struct v4l2_subdev *subdev, struct v4l2_subdev_fh *fh)
895{
896 return mt9p031_set_power(subdev, 0);
897}
898
899static struct v4l2_subdev_core_ops mt9p031_subdev_core_ops = {
900 .s_power = mt9p031_set_power,
901};
902
903static struct v4l2_subdev_video_ops mt9p031_subdev_video_ops = {
904 .s_stream = mt9p031_s_stream,
905};
906
907static struct v4l2_subdev_pad_ops mt9p031_subdev_pad_ops = {
908 .enum_mbus_code = mt9p031_enum_mbus_code,
909 .enum_frame_size = mt9p031_enum_frame_size,
910 .get_fmt = mt9p031_get_format,
911 .set_fmt = mt9p031_set_format,
912 .get_crop = mt9p031_get_crop,
913 .set_crop = mt9p031_set_crop,
914};
915
916static struct v4l2_subdev_ops mt9p031_subdev_ops = {
917 .core = &mt9p031_subdev_core_ops,
918 .video = &mt9p031_subdev_video_ops,
919 .pad = &mt9p031_subdev_pad_ops,
920};
921
922static const struct v4l2_subdev_internal_ops mt9p031_subdev_internal_ops = {
923 .registered = mt9p031_registered,
924 .open = mt9p031_open,
925 .close = mt9p031_close,
926};
927
928/* -----------------------------------------------------------------------------
929 * Driver initialization and probing
930 */
931
8d4da37c
LP		 932static struct mt9p031_platform_data *
933mt9p031_get_pdata(struct i2c_client *client)
934{
935 struct mt9p031_platform_data *pdata;
936 struct device_node *np;
937
938 if (!IS_ENABLED(CONFIG_OF) || !client->dev.of_node)
939 return client->dev.platform_data;
940
941 np = v4l2_of_get_next_endpoint(client->dev.of_node, NULL);
942 if (!np)
943 return NULL;
944
945 pdata = devm_kzalloc(&client->dev, sizeof(*pdata), GFP_KERNEL);
946 if (!pdata)
947 goto done;
948
949 pdata->reset = of_get_named_gpio(client->dev.of_node, "reset-gpios", 0);
950 of_property_read_u32(np, "input-clock-frequency", &pdata->ext_freq);
951 of_property_read_u32(np, "pixel-clock-frequency", &pdata->target_freq);
952
953done:
954 of_node_put(np);
955 return pdata;
956}
957
418d93ac
JM		 958static int mt9p031_probe(struct i2c_client *client,
959 const struct i2c_device_id *did)
960{
8d4da37c 961 struct mt9p031_platform_data *pdata = mt9p031_get_pdata(client);
418d93ac
JM		 962 struct i2c_adapter *adapter = to_i2c_adapter(client->dev.parent);
963 struct mt9p031 *mt9p031;
964 unsigned int i;
965 int ret;
966
967 if (pdata == NULL) {
968 dev_err(&client->dev, "No platform data\n");
969 return -EINVAL;
970 }
971
972 if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_WORD_DATA)) {
973 dev_warn(&client->dev,
974 "I2C-Adapter doesn't support I2C_FUNC_SMBUS_WORD\n");
975 return -EIO;
976 }
977
37b9f211 978 mt9p031 = devm_kzalloc(&client->dev, sizeof(*mt9p031), GFP_KERNEL);
418d93ac
JM		 979 if (mt9p031 == NULL)
980 return -ENOMEM;
981
982 mt9p031->pdata = pdata;
983 mt9p031->output_control = MT9P031_OUTPUT_CONTROL_DEF;
984 mt9p031->mode2 = MT9P031_READ_MODE_2_ROW_BLC;
1c542ba8 985 mt9p031->model = did->driver_data;
15693b57 986 mt9p031->reset = -1;
418d93ac 987
7997196c
LP		 988 mt9p031->regulators[0].supply = "vdd";
989 mt9p031->regulators[1].supply = "vdd_io";
990 mt9p031->regulators[2].supply = "vaa";
97f21276 991
7997196c
LP		 992 ret = devm_regulator_bulk_get(&client->dev, 3, mt9p031->regulators);
993 if (ret < 0) {
97f21276 994 dev_err(&client->dev, "Unable to get regulators\n");
7997196c 995 return ret;
97f21276
LP		 996 }
997
b28d7017 998 v4l2_ctrl_handler_init(&mt9p031->ctrls, ARRAY_SIZE(mt9p031_ctrls) + 6);
418d93ac
JM		 999
1000 v4l2_ctrl_new_std(&mt9p031->ctrls, &mt9p031_ctrl_ops,
1001 V4L2_CID_EXPOSURE, MT9P031_SHUTTER_WIDTH_MIN,
1002 MT9P031_SHUTTER_WIDTH_MAX, 1,
1003 MT9P031_SHUTTER_WIDTH_DEF);
1004 v4l2_ctrl_new_std(&mt9p031->ctrls, &mt9p031_ctrl_ops,
1005 V4L2_CID_GAIN, MT9P031_GLOBAL_GAIN_MIN,
1006 MT9P031_GLOBAL_GAIN_MAX, 1, MT9P031_GLOBAL_GAIN_DEF);
1007 v4l2_ctrl_new_std(&mt9p031->ctrls, &mt9p031_ctrl_ops,
1008 V4L2_CID_HFLIP, 0, 1, 1, 0);
1009 v4l2_ctrl_new_std(&mt9p031->ctrls, &mt9p031_ctrl_ops,
1010 V4L2_CID_VFLIP, 0, 1, 1, 0);
8d690c4a
LP		 1011 v4l2_ctrl_new_std(&mt9p031->ctrls, &mt9p031_ctrl_ops,
1012 V4L2_CID_PIXEL_RATE, pdata->target_freq,
1013 pdata->target_freq, 1, pdata->target_freq);
b28d7017
LP		 1014 v4l2_ctrl_new_std_menu_items(&mt9p031->ctrls, &mt9p031_ctrl_ops,
1015 V4L2_CID_TEST_PATTERN,
1016 ARRAY_SIZE(mt9p031_test_pattern_menu) - 1, 0,
1017 0, mt9p031_test_pattern_menu);
418d93ac
JM		 1018
1019 for (i = 0; i < ARRAY_SIZE(mt9p031_ctrls); ++i)
1020 v4l2_ctrl_new_custom(&mt9p031->ctrls, &mt9p031_ctrls[i], NULL);
1021
1022 mt9p031->subdev.ctrl_handler = &mt9p031->ctrls;
1023
dfea0019 1024 if (mt9p031->ctrls.error) {
418d93ac
JM		 1025 printk(KERN_INFO "%s: control initialization error %d\n",
1026 __func__, mt9p031->ctrls.error);
dfea0019
LP		 1027 ret = mt9p031->ctrls.error;
1028 goto done;
1029 }
1030
1031 mt9p031->blc_auto = v4l2_ctrl_find(&mt9p031->ctrls, V4L2_CID_BLC_AUTO);
1032 mt9p031->blc_offset = v4l2_ctrl_find(&mt9p031->ctrls,
1033 V4L2_CID_BLC_DIGITAL_OFFSET);
418d93ac
JM		 1034
1035 mutex_init(&mt9p031->power_lock);
1036 v4l2_i2c_subdev_init(&mt9p031->subdev, client, &mt9p031_subdev_ops);
1037 mt9p031->subdev.internal_ops = &mt9p031_subdev_internal_ops;
1038
1039 mt9p031->pad.flags = MEDIA_PAD_FL_SOURCE;
1040 ret = media_entity_init(&mt9p031->subdev.entity, 1, &mt9p031->pad, 0);
1041 if (ret < 0)
1042 goto done;
1043
1044 mt9p031->subdev.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1045
1046 mt9p031->crop.width = MT9P031_WINDOW_WIDTH_DEF;
1047 mt9p031->crop.height = MT9P031_WINDOW_HEIGHT_DEF;
1048 mt9p031->crop.left = MT9P031_COLUMN_START_DEF;
1049 mt9p031->crop.top = MT9P031_ROW_START_DEF;
1050
1c542ba8 1051 if (mt9p031->model == MT9P031_MODEL_MONOCHROME)
418d93ac
JM		 1052 mt9p031->format.code = V4L2_MBUS_FMT_Y12_1X12;
1053 else
1054 mt9p031->format.code = V4L2_MBUS_FMT_SGRBG12_1X12;
1055
1056 mt9p031->format.width = MT9P031_WINDOW_WIDTH_DEF;
1057 mt9p031->format.height = MT9P031_WINDOW_HEIGHT_DEF;
1058 mt9p031->format.field = V4L2_FIELD_NONE;
1059 mt9p031->format.colorspace = V4L2_COLORSPACE_SRGB;
1060
2660a22b 1061 if (gpio_is_valid(pdata->reset)) {
37b9f211
LP		 1062 ret = devm_gpio_request_one(&client->dev, pdata->reset,
1063 GPIOF_OUT_INIT_LOW, "mt9p031_rst");
15693b57
LP		 1064 if (ret < 0)
1065 goto done;
1066
1067 mt9p031->reset = pdata->reset;
1068 }
1069
d6749258 1070 ret = mt9p031_clk_setup(mt9p031);
418d93ac
JM		 1071
1072done:
1073 if (ret < 0) {
1074 v4l2_ctrl_handler_free(&mt9p031->ctrls);
1075 media_entity_cleanup(&mt9p031->subdev.entity);
418d93ac
JM		 1076 }
1077
1078 return ret;
1079}
1080
1081static int mt9p031_remove(struct i2c_client *client)
1082{
1083 struct v4l2_subdev *subdev = i2c_get_clientdata(client);
1084 struct mt9p031 *mt9p031 = to_mt9p031(subdev);
1085
1086 v4l2_ctrl_handler_free(&mt9p031->ctrls);
1087 v4l2_device_unregister_subdev(subdev);
1088 media_entity_cleanup(&subdev->entity);
418d93ac
JM		 1089
1090 return 0;
1091}
1092
1093static const struct i2c_device_id mt9p031_id[] = {
1c542ba8
LP		 1094 { "mt9p031", MT9P031_MODEL_COLOR },
1095 { "mt9p031m", MT9P031_MODEL_MONOCHROME },
418d93ac
JM		 1096 { }
1097};
1098MODULE_DEVICE_TABLE(i2c, mt9p031_id);
1099
8d4da37c
LP		 1100#if IS_ENABLED(CONFIG_OF)
1101static const struct of_device_id mt9p031_of_match[] = {
1102 { .compatible = "aptina,mt9p031", },
1103 { .compatible = "aptina,mt9p031m", },
1104 { /* sentinel */ },
1105};
1106MODULE_DEVICE_TABLE(of, mt9p031_of_match);
1107#endif
1108
418d93ac
JM		 1109static struct i2c_driver mt9p031_i2c_driver = {
1110 .driver = {
8d4da37c 1111 .of_match_table = of_match_ptr(mt9p031_of_match),
418d93ac
JM		 1112 .name = "mt9p031",
1113 },
1114 .probe = mt9p031_probe,
1115 .remove = mt9p031_remove,
1116 .id_table = mt9p031_id,
1117};
1118
c6e8d86f 1119module_i2c_driver(mt9p031_i2c_driver);
418d93ac
JM		 1120
1121MODULE_DESCRIPTION("Aptina MT9P031 Camera driver");
1122MODULE_AUTHOR("Bastian Hecht <hechtb@gmail.com>");
1123MODULE_LICENSE("GPL v2");
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