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0f2ce168 DC |
1 | /* |
2 | * Driver for MT9V032 CMOS Image Sensor from Micron | |
3 | * | |
4 | * Copyright (C) 2010, Laurent Pinchart <laurent.pinchart@ideasonboard.com> | |
5 | * | |
6 | * Based on the MT9M001 driver, | |
7 | * | |
8 | * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de> | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License version 2 as | |
12 | * published by the Free Software Foundation. | |
13 | */ | |
14 | ||
15 | #include <linux/delay.h> | |
16 | #include <linux/i2c.h> | |
17 | #include <linux/log2.h> | |
18 | #include <linux/mutex.h> | |
19 | #include <linux/slab.h> | |
20 | #include <linux/videodev2.h> | |
21 | #include <linux/v4l2-mediabus.h> | |
7a707b89 | 22 | #include <linux/module.h> |
0f2ce168 DC |
23 | |
24 | #include <media/mt9v032.h> | |
25 | #include <media/v4l2-ctrls.h> | |
26 | #include <media/v4l2-device.h> | |
27 | #include <media/v4l2-subdev.h> | |
28 | ||
29 | #define MT9V032_PIXEL_ARRAY_HEIGHT 492 | |
30 | #define MT9V032_PIXEL_ARRAY_WIDTH 782 | |
31 | ||
e9a50e4c LP |
32 | #define MT9V032_SYSCLK_FREQ_DEF 26600000 |
33 | ||
0f2ce168 DC |
34 | #define MT9V032_CHIP_VERSION 0x00 |
35 | #define MT9V032_CHIP_ID_REV1 0x1311 | |
36 | #define MT9V032_CHIP_ID_REV3 0x1313 | |
86cf786c | 37 | #define MT9V032_COLUMN_START 0x01 |
0f2ce168 | 38 | #define MT9V032_COLUMN_START_MIN 1 |
86cf786c | 39 | #define MT9V032_COLUMN_START_DEF 1 |
0f2ce168 | 40 | #define MT9V032_COLUMN_START_MAX 752 |
86cf786c LP |
41 | #define MT9V032_ROW_START 0x02 |
42 | #define MT9V032_ROW_START_MIN 4 | |
43 | #define MT9V032_ROW_START_DEF 5 | |
44 | #define MT9V032_ROW_START_MAX 482 | |
0f2ce168 DC |
45 | #define MT9V032_WINDOW_HEIGHT 0x03 |
46 | #define MT9V032_WINDOW_HEIGHT_MIN 1 | |
47 | #define MT9V032_WINDOW_HEIGHT_DEF 480 | |
48 | #define MT9V032_WINDOW_HEIGHT_MAX 480 | |
49 | #define MT9V032_WINDOW_WIDTH 0x04 | |
50 | #define MT9V032_WINDOW_WIDTH_MIN 1 | |
51 | #define MT9V032_WINDOW_WIDTH_DEF 752 | |
52 | #define MT9V032_WINDOW_WIDTH_MAX 752 | |
53 | #define MT9V032_HORIZONTAL_BLANKING 0x05 | |
54 | #define MT9V032_HORIZONTAL_BLANKING_MIN 43 | |
9ec670e2 | 55 | #define MT9V032_HORIZONTAL_BLANKING_DEF 94 |
0f2ce168 DC |
56 | #define MT9V032_HORIZONTAL_BLANKING_MAX 1023 |
57 | #define MT9V032_VERTICAL_BLANKING 0x06 | |
58 | #define MT9V032_VERTICAL_BLANKING_MIN 4 | |
9ec670e2 | 59 | #define MT9V032_VERTICAL_BLANKING_DEF 45 |
0f2ce168 DC |
60 | #define MT9V032_VERTICAL_BLANKING_MAX 3000 |
61 | #define MT9V032_CHIP_CONTROL 0x07 | |
62 | #define MT9V032_CHIP_CONTROL_MASTER_MODE (1 << 3) | |
63 | #define MT9V032_CHIP_CONTROL_DOUT_ENABLE (1 << 7) | |
64 | #define MT9V032_CHIP_CONTROL_SEQUENTIAL (1 << 8) | |
65 | #define MT9V032_SHUTTER_WIDTH1 0x08 | |
66 | #define MT9V032_SHUTTER_WIDTH2 0x09 | |
67 | #define MT9V032_SHUTTER_WIDTH_CONTROL 0x0a | |
68 | #define MT9V032_TOTAL_SHUTTER_WIDTH 0x0b | |
69 | #define MT9V032_TOTAL_SHUTTER_WIDTH_MIN 1 | |
70 | #define MT9V032_TOTAL_SHUTTER_WIDTH_DEF 480 | |
71 | #define MT9V032_TOTAL_SHUTTER_WIDTH_MAX 32767 | |
72 | #define MT9V032_RESET 0x0c | |
73 | #define MT9V032_READ_MODE 0x0d | |
74 | #define MT9V032_READ_MODE_ROW_BIN_MASK (3 << 0) | |
75 | #define MT9V032_READ_MODE_ROW_BIN_SHIFT 0 | |
76 | #define MT9V032_READ_MODE_COLUMN_BIN_MASK (3 << 2) | |
77 | #define MT9V032_READ_MODE_COLUMN_BIN_SHIFT 2 | |
78 | #define MT9V032_READ_MODE_ROW_FLIP (1 << 4) | |
79 | #define MT9V032_READ_MODE_COLUMN_FLIP (1 << 5) | |
80 | #define MT9V032_READ_MODE_DARK_COLUMNS (1 << 6) | |
81 | #define MT9V032_READ_MODE_DARK_ROWS (1 << 7) | |
82 | #define MT9V032_PIXEL_OPERATION_MODE 0x0f | |
83 | #define MT9V032_PIXEL_OPERATION_MODE_COLOR (1 << 2) | |
84 | #define MT9V032_PIXEL_OPERATION_MODE_HDR (1 << 6) | |
85 | #define MT9V032_ANALOG_GAIN 0x35 | |
86 | #define MT9V032_ANALOG_GAIN_MIN 16 | |
87 | #define MT9V032_ANALOG_GAIN_DEF 16 | |
88 | #define MT9V032_ANALOG_GAIN_MAX 64 | |
89 | #define MT9V032_MAX_ANALOG_GAIN 0x36 | |
90 | #define MT9V032_MAX_ANALOG_GAIN_MAX 127 | |
91 | #define MT9V032_FRAME_DARK_AVERAGE 0x42 | |
92 | #define MT9V032_DARK_AVG_THRESH 0x46 | |
93 | #define MT9V032_DARK_AVG_LOW_THRESH_MASK (255 << 0) | |
94 | #define MT9V032_DARK_AVG_LOW_THRESH_SHIFT 0 | |
95 | #define MT9V032_DARK_AVG_HIGH_THRESH_MASK (255 << 8) | |
96 | #define MT9V032_DARK_AVG_HIGH_THRESH_SHIFT 8 | |
97 | #define MT9V032_ROW_NOISE_CORR_CONTROL 0x70 | |
98 | #define MT9V032_ROW_NOISE_CORR_ENABLE (1 << 5) | |
99 | #define MT9V032_ROW_NOISE_CORR_USE_BLK_AVG (1 << 7) | |
100 | #define MT9V032_PIXEL_CLOCK 0x74 | |
101 | #define MT9V032_PIXEL_CLOCK_INV_LINE (1 << 0) | |
102 | #define MT9V032_PIXEL_CLOCK_INV_FRAME (1 << 1) | |
103 | #define MT9V032_PIXEL_CLOCK_XOR_LINE (1 << 2) | |
104 | #define MT9V032_PIXEL_CLOCK_CONT_LINE (1 << 3) | |
105 | #define MT9V032_PIXEL_CLOCK_INV_PXL_CLK (1 << 4) | |
106 | #define MT9V032_TEST_PATTERN 0x7f | |
107 | #define MT9V032_TEST_PATTERN_DATA_MASK (1023 << 0) | |
108 | #define MT9V032_TEST_PATTERN_DATA_SHIFT 0 | |
109 | #define MT9V032_TEST_PATTERN_USE_DATA (1 << 10) | |
110 | #define MT9V032_TEST_PATTERN_GRAY_MASK (3 << 11) | |
111 | #define MT9V032_TEST_PATTERN_GRAY_NONE (0 << 11) | |
112 | #define MT9V032_TEST_PATTERN_GRAY_VERTICAL (1 << 11) | |
113 | #define MT9V032_TEST_PATTERN_GRAY_HORIZONTAL (2 << 11) | |
114 | #define MT9V032_TEST_PATTERN_GRAY_DIAGONAL (3 << 11) | |
115 | #define MT9V032_TEST_PATTERN_ENABLE (1 << 13) | |
116 | #define MT9V032_TEST_PATTERN_FLIP (1 << 14) | |
117 | #define MT9V032_AEC_AGC_ENABLE 0xaf | |
118 | #define MT9V032_AEC_ENABLE (1 << 0) | |
119 | #define MT9V032_AGC_ENABLE (1 << 1) | |
120 | #define MT9V032_THERMAL_INFO 0xc1 | |
121 | ||
122 | struct mt9v032 { | |
123 | struct v4l2_subdev subdev; | |
124 | struct media_pad pad; | |
125 | ||
126 | struct v4l2_mbus_framefmt format; | |
127 | struct v4l2_rect crop; | |
128 | ||
129 | struct v4l2_ctrl_handler ctrls; | |
e9a50e4c LP |
130 | struct { |
131 | struct v4l2_ctrl *link_freq; | |
132 | struct v4l2_ctrl *pixel_rate; | |
133 | }; | |
0f2ce168 DC |
134 | |
135 | struct mutex power_lock; | |
136 | int power_count; | |
137 | ||
138 | struct mt9v032_platform_data *pdata; | |
e9a50e4c LP |
139 | |
140 | u32 sysclk; | |
0f2ce168 DC |
141 | u16 chip_control; |
142 | u16 aec_agc; | |
9ec670e2 | 143 | u16 hblank; |
0f2ce168 DC |
144 | }; |
145 | ||
146 | static struct mt9v032 *to_mt9v032(struct v4l2_subdev *sd) | |
147 | { | |
148 | return container_of(sd, struct mt9v032, subdev); | |
149 | } | |
150 | ||
151 | static int mt9v032_read(struct i2c_client *client, const u8 reg) | |
152 | { | |
3f877045 | 153 | s32 data = i2c_smbus_read_word_swapped(client, reg); |
0f2ce168 | 154 | dev_dbg(&client->dev, "%s: read 0x%04x from 0x%02x\n", __func__, |
3f877045 JC |
155 | data, reg); |
156 | return data; | |
0f2ce168 DC |
157 | } |
158 | ||
159 | static int mt9v032_write(struct i2c_client *client, const u8 reg, | |
160 | const u16 data) | |
161 | { | |
162 | dev_dbg(&client->dev, "%s: writing 0x%04x to 0x%02x\n", __func__, | |
163 | data, reg); | |
3f877045 | 164 | return i2c_smbus_write_word_swapped(client, reg, data); |
0f2ce168 DC |
165 | } |
166 | ||
167 | static int mt9v032_set_chip_control(struct mt9v032 *mt9v032, u16 clear, u16 set) | |
168 | { | |
169 | struct i2c_client *client = v4l2_get_subdevdata(&mt9v032->subdev); | |
170 | u16 value = (mt9v032->chip_control & ~clear) | set; | |
171 | int ret; | |
172 | ||
173 | ret = mt9v032_write(client, MT9V032_CHIP_CONTROL, value); | |
174 | if (ret < 0) | |
175 | return ret; | |
176 | ||
177 | mt9v032->chip_control = value; | |
178 | return 0; | |
179 | } | |
180 | ||
181 | static int | |
182 | mt9v032_update_aec_agc(struct mt9v032 *mt9v032, u16 which, int enable) | |
183 | { | |
184 | struct i2c_client *client = v4l2_get_subdevdata(&mt9v032->subdev); | |
185 | u16 value = mt9v032->aec_agc; | |
186 | int ret; | |
187 | ||
188 | if (enable) | |
189 | value |= which; | |
190 | else | |
191 | value &= ~which; | |
192 | ||
193 | ret = mt9v032_write(client, MT9V032_AEC_AGC_ENABLE, value); | |
194 | if (ret < 0) | |
195 | return ret; | |
196 | ||
197 | mt9v032->aec_agc = value; | |
198 | return 0; | |
199 | } | |
200 | ||
9ec670e2 LP |
201 | static int |
202 | mt9v032_update_hblank(struct mt9v032 *mt9v032) | |
203 | { | |
204 | struct i2c_client *client = v4l2_get_subdevdata(&mt9v032->subdev); | |
205 | struct v4l2_rect *crop = &mt9v032->crop; | |
206 | ||
207 | return mt9v032_write(client, MT9V032_HORIZONTAL_BLANKING, | |
208 | max_t(s32, mt9v032->hblank, 660 - crop->width)); | |
209 | } | |
210 | ||
41a33a00 SA |
211 | #define EXT_CLK 25000000 |
212 | ||
0f2ce168 DC |
213 | static int mt9v032_power_on(struct mt9v032 *mt9v032) |
214 | { | |
215 | struct i2c_client *client = v4l2_get_subdevdata(&mt9v032->subdev); | |
216 | int ret; | |
217 | ||
218 | if (mt9v032->pdata->set_clock) { | |
e9a50e4c | 219 | mt9v032->pdata->set_clock(&mt9v032->subdev, mt9v032->sysclk); |
0f2ce168 DC |
220 | udelay(1); |
221 | } | |
222 | ||
223 | /* Reset the chip and stop data read out */ | |
224 | ret = mt9v032_write(client, MT9V032_RESET, 1); | |
225 | if (ret < 0) | |
226 | return ret; | |
227 | ||
228 | ret = mt9v032_write(client, MT9V032_RESET, 0); | |
229 | if (ret < 0) | |
230 | return ret; | |
231 | ||
232 | return mt9v032_write(client, MT9V032_CHIP_CONTROL, 0); | |
233 | } | |
234 | ||
235 | static void mt9v032_power_off(struct mt9v032 *mt9v032) | |
236 | { | |
237 | if (mt9v032->pdata->set_clock) | |
238 | mt9v032->pdata->set_clock(&mt9v032->subdev, 0); | |
239 | } | |
240 | ||
241 | static int __mt9v032_set_power(struct mt9v032 *mt9v032, bool on) | |
242 | { | |
243 | struct i2c_client *client = v4l2_get_subdevdata(&mt9v032->subdev); | |
244 | int ret; | |
245 | ||
246 | if (!on) { | |
247 | mt9v032_power_off(mt9v032); | |
248 | return 0; | |
249 | } | |
250 | ||
251 | ret = mt9v032_power_on(mt9v032); | |
252 | if (ret < 0) | |
253 | return ret; | |
254 | ||
255 | /* Configure the pixel clock polarity */ | |
256 | if (mt9v032->pdata && mt9v032->pdata->clk_pol) { | |
257 | ret = mt9v032_write(client, MT9V032_PIXEL_CLOCK, | |
258 | MT9V032_PIXEL_CLOCK_INV_PXL_CLK); | |
259 | if (ret < 0) | |
260 | return ret; | |
261 | } | |
262 | ||
263 | /* Disable the noise correction algorithm and restore the controls. */ | |
264 | ret = mt9v032_write(client, MT9V032_ROW_NOISE_CORR_CONTROL, 0); | |
265 | if (ret < 0) | |
266 | return ret; | |
267 | ||
268 | return v4l2_ctrl_handler_setup(&mt9v032->ctrls); | |
269 | } | |
270 | ||
271 | /* ----------------------------------------------------------------------------- | |
272 | * V4L2 subdev video operations | |
273 | */ | |
274 | ||
275 | static struct v4l2_mbus_framefmt * | |
276 | __mt9v032_get_pad_format(struct mt9v032 *mt9v032, struct v4l2_subdev_fh *fh, | |
277 | unsigned int pad, enum v4l2_subdev_format_whence which) | |
278 | { | |
279 | switch (which) { | |
280 | case V4L2_SUBDEV_FORMAT_TRY: | |
281 | return v4l2_subdev_get_try_format(fh, pad); | |
282 | case V4L2_SUBDEV_FORMAT_ACTIVE: | |
283 | return &mt9v032->format; | |
284 | default: | |
285 | return NULL; | |
286 | } | |
287 | } | |
288 | ||
289 | static struct v4l2_rect * | |
290 | __mt9v032_get_pad_crop(struct mt9v032 *mt9v032, struct v4l2_subdev_fh *fh, | |
291 | unsigned int pad, enum v4l2_subdev_format_whence which) | |
292 | { | |
293 | switch (which) { | |
294 | case V4L2_SUBDEV_FORMAT_TRY: | |
295 | return v4l2_subdev_get_try_crop(fh, pad); | |
296 | case V4L2_SUBDEV_FORMAT_ACTIVE: | |
297 | return &mt9v032->crop; | |
298 | default: | |
299 | return NULL; | |
300 | } | |
301 | } | |
302 | ||
303 | static int mt9v032_s_stream(struct v4l2_subdev *subdev, int enable) | |
304 | { | |
305 | const u16 mode = MT9V032_CHIP_CONTROL_MASTER_MODE | |
306 | | MT9V032_CHIP_CONTROL_DOUT_ENABLE | |
307 | | MT9V032_CHIP_CONTROL_SEQUENTIAL; | |
308 | struct i2c_client *client = v4l2_get_subdevdata(subdev); | |
309 | struct mt9v032 *mt9v032 = to_mt9v032(subdev); | |
310 | struct v4l2_mbus_framefmt *format = &mt9v032->format; | |
311 | struct v4l2_rect *crop = &mt9v032->crop; | |
312 | unsigned int hratio; | |
313 | unsigned int vratio; | |
314 | int ret; | |
315 | ||
316 | if (!enable) | |
317 | return mt9v032_set_chip_control(mt9v032, mode, 0); | |
318 | ||
319 | /* Configure the window size and row/column bin */ | |
320 | hratio = DIV_ROUND_CLOSEST(crop->width, format->width); | |
321 | vratio = DIV_ROUND_CLOSEST(crop->height, format->height); | |
322 | ||
323 | ret = mt9v032_write(client, MT9V032_READ_MODE, | |
324 | (hratio - 1) << MT9V032_READ_MODE_ROW_BIN_SHIFT | | |
325 | (vratio - 1) << MT9V032_READ_MODE_COLUMN_BIN_SHIFT); | |
326 | if (ret < 0) | |
327 | return ret; | |
328 | ||
329 | ret = mt9v032_write(client, MT9V032_COLUMN_START, crop->left); | |
330 | if (ret < 0) | |
331 | return ret; | |
332 | ||
333 | ret = mt9v032_write(client, MT9V032_ROW_START, crop->top); | |
334 | if (ret < 0) | |
335 | return ret; | |
336 | ||
337 | ret = mt9v032_write(client, MT9V032_WINDOW_WIDTH, crop->width); | |
338 | if (ret < 0) | |
339 | return ret; | |
340 | ||
341 | ret = mt9v032_write(client, MT9V032_WINDOW_HEIGHT, crop->height); | |
342 | if (ret < 0) | |
343 | return ret; | |
344 | ||
9ec670e2 | 345 | ret = mt9v032_update_hblank(mt9v032); |
0f2ce168 DC |
346 | if (ret < 0) |
347 | return ret; | |
348 | ||
349 | /* Switch to master "normal" mode */ | |
350 | return mt9v032_set_chip_control(mt9v032, 0, mode); | |
351 | } | |
352 | ||
353 | static int mt9v032_enum_mbus_code(struct v4l2_subdev *subdev, | |
354 | struct v4l2_subdev_fh *fh, | |
355 | struct v4l2_subdev_mbus_code_enum *code) | |
356 | { | |
357 | if (code->index > 0) | |
358 | return -EINVAL; | |
359 | ||
360 | code->code = V4L2_MBUS_FMT_SGRBG10_1X10; | |
361 | return 0; | |
362 | } | |
363 | ||
364 | static int mt9v032_enum_frame_size(struct v4l2_subdev *subdev, | |
365 | struct v4l2_subdev_fh *fh, | |
366 | struct v4l2_subdev_frame_size_enum *fse) | |
367 | { | |
368 | if (fse->index >= 8 || fse->code != V4L2_MBUS_FMT_SGRBG10_1X10) | |
369 | return -EINVAL; | |
370 | ||
371 | fse->min_width = MT9V032_WINDOW_WIDTH_DEF / fse->index; | |
372 | fse->max_width = fse->min_width; | |
373 | fse->min_height = MT9V032_WINDOW_HEIGHT_DEF / fse->index; | |
374 | fse->max_height = fse->min_height; | |
375 | ||
376 | return 0; | |
377 | } | |
378 | ||
379 | static int mt9v032_get_format(struct v4l2_subdev *subdev, | |
380 | struct v4l2_subdev_fh *fh, | |
381 | struct v4l2_subdev_format *format) | |
382 | { | |
383 | struct mt9v032 *mt9v032 = to_mt9v032(subdev); | |
384 | ||
385 | format->format = *__mt9v032_get_pad_format(mt9v032, fh, format->pad, | |
386 | format->which); | |
387 | return 0; | |
388 | } | |
389 | ||
41a33a00 SA |
390 | static void mt9v032_configure_pixel_rate(struct mt9v032 *mt9v032, |
391 | unsigned int hratio) | |
392 | { | |
393 | struct i2c_client *client = v4l2_get_subdevdata(&mt9v032->subdev); | |
394 | int ret; | |
395 | ||
e9a50e4c LP |
396 | ret = v4l2_ctrl_s_ctrl_int64(mt9v032->pixel_rate, |
397 | mt9v032->sysclk / hratio); | |
41a33a00 SA |
398 | if (ret < 0) |
399 | dev_warn(&client->dev, "failed to set pixel rate (%d)\n", ret); | |
400 | } | |
401 | ||
0f2ce168 DC |
402 | static int mt9v032_set_format(struct v4l2_subdev *subdev, |
403 | struct v4l2_subdev_fh *fh, | |
404 | struct v4l2_subdev_format *format) | |
405 | { | |
406 | struct mt9v032 *mt9v032 = to_mt9v032(subdev); | |
407 | struct v4l2_mbus_framefmt *__format; | |
408 | struct v4l2_rect *__crop; | |
409 | unsigned int width; | |
410 | unsigned int height; | |
411 | unsigned int hratio; | |
412 | unsigned int vratio; | |
413 | ||
414 | __crop = __mt9v032_get_pad_crop(mt9v032, fh, format->pad, | |
415 | format->which); | |
416 | ||
417 | /* Clamp the width and height to avoid dividing by zero. */ | |
418 | width = clamp_t(unsigned int, ALIGN(format->format.width, 2), | |
419 | max(__crop->width / 8, MT9V032_WINDOW_WIDTH_MIN), | |
420 | __crop->width); | |
421 | height = clamp_t(unsigned int, ALIGN(format->format.height, 2), | |
422 | max(__crop->height / 8, MT9V032_WINDOW_HEIGHT_MIN), | |
423 | __crop->height); | |
424 | ||
425 | hratio = DIV_ROUND_CLOSEST(__crop->width, width); | |
426 | vratio = DIV_ROUND_CLOSEST(__crop->height, height); | |
427 | ||
428 | __format = __mt9v032_get_pad_format(mt9v032, fh, format->pad, | |
429 | format->which); | |
430 | __format->width = __crop->width / hratio; | |
431 | __format->height = __crop->height / vratio; | |
41a33a00 SA |
432 | if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE) |
433 | mt9v032_configure_pixel_rate(mt9v032, hratio); | |
0f2ce168 DC |
434 | |
435 | format->format = *__format; | |
436 | ||
437 | return 0; | |
438 | } | |
439 | ||
440 | static int mt9v032_get_crop(struct v4l2_subdev *subdev, | |
441 | struct v4l2_subdev_fh *fh, | |
442 | struct v4l2_subdev_crop *crop) | |
443 | { | |
444 | struct mt9v032 *mt9v032 = to_mt9v032(subdev); | |
445 | ||
446 | crop->rect = *__mt9v032_get_pad_crop(mt9v032, fh, crop->pad, | |
447 | crop->which); | |
448 | return 0; | |
449 | } | |
450 | ||
451 | static int mt9v032_set_crop(struct v4l2_subdev *subdev, | |
452 | struct v4l2_subdev_fh *fh, | |
453 | struct v4l2_subdev_crop *crop) | |
454 | { | |
455 | struct mt9v032 *mt9v032 = to_mt9v032(subdev); | |
456 | struct v4l2_mbus_framefmt *__format; | |
457 | struct v4l2_rect *__crop; | |
458 | struct v4l2_rect rect; | |
459 | ||
86cf786c LP |
460 | /* Clamp the crop rectangle boundaries and align them to a non multiple |
461 | * of 2 pixels to ensure a GRBG Bayer pattern. | |
0f2ce168 | 462 | */ |
86cf786c | 463 | rect.left = clamp(ALIGN(crop->rect.left + 1, 2) - 1, |
0f2ce168 DC |
464 | MT9V032_COLUMN_START_MIN, |
465 | MT9V032_COLUMN_START_MAX); | |
86cf786c | 466 | rect.top = clamp(ALIGN(crop->rect.top + 1, 2) - 1, |
0f2ce168 DC |
467 | MT9V032_ROW_START_MIN, |
468 | MT9V032_ROW_START_MAX); | |
469 | rect.width = clamp(ALIGN(crop->rect.width, 2), | |
470 | MT9V032_WINDOW_WIDTH_MIN, | |
471 | MT9V032_WINDOW_WIDTH_MAX); | |
472 | rect.height = clamp(ALIGN(crop->rect.height, 2), | |
473 | MT9V032_WINDOW_HEIGHT_MIN, | |
474 | MT9V032_WINDOW_HEIGHT_MAX); | |
475 | ||
476 | rect.width = min(rect.width, MT9V032_PIXEL_ARRAY_WIDTH - rect.left); | |
477 | rect.height = min(rect.height, MT9V032_PIXEL_ARRAY_HEIGHT - rect.top); | |
478 | ||
479 | __crop = __mt9v032_get_pad_crop(mt9v032, fh, crop->pad, crop->which); | |
480 | ||
481 | if (rect.width != __crop->width || rect.height != __crop->height) { | |
482 | /* Reset the output image size if the crop rectangle size has | |
483 | * been modified. | |
484 | */ | |
485 | __format = __mt9v032_get_pad_format(mt9v032, fh, crop->pad, | |
486 | crop->which); | |
487 | __format->width = rect.width; | |
488 | __format->height = rect.height; | |
41a33a00 SA |
489 | if (crop->which == V4L2_SUBDEV_FORMAT_ACTIVE) |
490 | mt9v032_configure_pixel_rate(mt9v032, 1); | |
0f2ce168 DC |
491 | } |
492 | ||
493 | *__crop = rect; | |
494 | crop->rect = rect; | |
495 | ||
496 | return 0; | |
497 | } | |
498 | ||
499 | /* ----------------------------------------------------------------------------- | |
500 | * V4L2 subdev control operations | |
501 | */ | |
502 | ||
503 | #define V4L2_CID_TEST_PATTERN (V4L2_CID_USER_BASE | 0x1001) | |
504 | ||
505 | static int mt9v032_s_ctrl(struct v4l2_ctrl *ctrl) | |
506 | { | |
507 | struct mt9v032 *mt9v032 = | |
508 | container_of(ctrl->handler, struct mt9v032, ctrls); | |
509 | struct i2c_client *client = v4l2_get_subdevdata(&mt9v032->subdev); | |
e9a50e4c | 510 | u32 freq; |
0f2ce168 DC |
511 | u16 data; |
512 | ||
513 | switch (ctrl->id) { | |
514 | case V4L2_CID_AUTOGAIN: | |
515 | return mt9v032_update_aec_agc(mt9v032, MT9V032_AGC_ENABLE, | |
516 | ctrl->val); | |
517 | ||
518 | case V4L2_CID_GAIN: | |
519 | return mt9v032_write(client, MT9V032_ANALOG_GAIN, ctrl->val); | |
520 | ||
521 | case V4L2_CID_EXPOSURE_AUTO: | |
522 | return mt9v032_update_aec_agc(mt9v032, MT9V032_AEC_ENABLE, | |
5c375981 | 523 | !ctrl->val); |
0f2ce168 DC |
524 | |
525 | case V4L2_CID_EXPOSURE: | |
526 | return mt9v032_write(client, MT9V032_TOTAL_SHUTTER_WIDTH, | |
527 | ctrl->val); | |
528 | ||
9ec670e2 LP |
529 | case V4L2_CID_HBLANK: |
530 | mt9v032->hblank = ctrl->val; | |
531 | return mt9v032_update_hblank(mt9v032); | |
532 | ||
533 | case V4L2_CID_VBLANK: | |
534 | return mt9v032_write(client, MT9V032_VERTICAL_BLANKING, | |
535 | ctrl->val); | |
536 | ||
e9a50e4c LP |
537 | case V4L2_CID_PIXEL_RATE: |
538 | case V4L2_CID_LINK_FREQ: | |
539 | if (mt9v032->link_freq == NULL) | |
540 | break; | |
541 | ||
542 | freq = mt9v032->pdata->link_freqs[mt9v032->link_freq->val]; | |
543 | mt9v032->pixel_rate->val64 = freq; | |
544 | mt9v032->sysclk = freq; | |
545 | break; | |
546 | ||
0f2ce168 DC |
547 | case V4L2_CID_TEST_PATTERN: |
548 | switch (ctrl->val) { | |
549 | case 0: | |
550 | data = 0; | |
551 | break; | |
552 | case 1: | |
553 | data = MT9V032_TEST_PATTERN_GRAY_VERTICAL | |
554 | | MT9V032_TEST_PATTERN_ENABLE; | |
555 | break; | |
556 | case 2: | |
557 | data = MT9V032_TEST_PATTERN_GRAY_HORIZONTAL | |
558 | | MT9V032_TEST_PATTERN_ENABLE; | |
559 | break; | |
560 | case 3: | |
561 | data = MT9V032_TEST_PATTERN_GRAY_DIAGONAL | |
562 | | MT9V032_TEST_PATTERN_ENABLE; | |
563 | break; | |
564 | default: | |
565 | data = (ctrl->val << MT9V032_TEST_PATTERN_DATA_SHIFT) | |
566 | | MT9V032_TEST_PATTERN_USE_DATA | |
567 | | MT9V032_TEST_PATTERN_ENABLE | |
568 | | MT9V032_TEST_PATTERN_FLIP; | |
569 | break; | |
570 | } | |
571 | ||
572 | return mt9v032_write(client, MT9V032_TEST_PATTERN, data); | |
573 | } | |
574 | ||
575 | return 0; | |
576 | } | |
577 | ||
578 | static struct v4l2_ctrl_ops mt9v032_ctrl_ops = { | |
579 | .s_ctrl = mt9v032_s_ctrl, | |
580 | }; | |
581 | ||
582 | static const struct v4l2_ctrl_config mt9v032_ctrls[] = { | |
583 | { | |
584 | .ops = &mt9v032_ctrl_ops, | |
585 | .id = V4L2_CID_TEST_PATTERN, | |
586 | .type = V4L2_CTRL_TYPE_INTEGER, | |
587 | .name = "Test pattern", | |
588 | .min = 0, | |
589 | .max = 1023, | |
590 | .step = 1, | |
591 | .def = 0, | |
592 | .flags = 0, | |
593 | } | |
594 | }; | |
595 | ||
596 | /* ----------------------------------------------------------------------------- | |
597 | * V4L2 subdev core operations | |
598 | */ | |
599 | ||
600 | static int mt9v032_set_power(struct v4l2_subdev *subdev, int on) | |
601 | { | |
602 | struct mt9v032 *mt9v032 = to_mt9v032(subdev); | |
603 | int ret = 0; | |
604 | ||
605 | mutex_lock(&mt9v032->power_lock); | |
606 | ||
607 | /* If the power count is modified from 0 to != 0 or from != 0 to 0, | |
608 | * update the power state. | |
609 | */ | |
610 | if (mt9v032->power_count == !on) { | |
611 | ret = __mt9v032_set_power(mt9v032, !!on); | |
612 | if (ret < 0) | |
613 | goto done; | |
614 | } | |
615 | ||
616 | /* Update the power count. */ | |
617 | mt9v032->power_count += on ? 1 : -1; | |
618 | WARN_ON(mt9v032->power_count < 0); | |
619 | ||
620 | done: | |
621 | mutex_unlock(&mt9v032->power_lock); | |
622 | return ret; | |
623 | } | |
624 | ||
625 | /* ----------------------------------------------------------------------------- | |
626 | * V4L2 subdev internal operations | |
627 | */ | |
628 | ||
629 | static int mt9v032_registered(struct v4l2_subdev *subdev) | |
630 | { | |
631 | struct i2c_client *client = v4l2_get_subdevdata(subdev); | |
632 | struct mt9v032 *mt9v032 = to_mt9v032(subdev); | |
633 | s32 data; | |
634 | int ret; | |
635 | ||
636 | dev_info(&client->dev, "Probing MT9V032 at address 0x%02x\n", | |
637 | client->addr); | |
638 | ||
639 | ret = mt9v032_power_on(mt9v032); | |
640 | if (ret < 0) { | |
641 | dev_err(&client->dev, "MT9V032 power up failed\n"); | |
642 | return ret; | |
643 | } | |
644 | ||
645 | /* Read and check the sensor version */ | |
646 | data = mt9v032_read(client, MT9V032_CHIP_VERSION); | |
647 | if (data != MT9V032_CHIP_ID_REV1 && data != MT9V032_CHIP_ID_REV3) { | |
648 | dev_err(&client->dev, "MT9V032 not detected, wrong version " | |
649 | "0x%04x\n", data); | |
650 | return -ENODEV; | |
651 | } | |
652 | ||
653 | mt9v032_power_off(mt9v032); | |
654 | ||
655 | dev_info(&client->dev, "MT9V032 detected at address 0x%02x\n", | |
656 | client->addr); | |
657 | ||
41a33a00 SA |
658 | mt9v032_configure_pixel_rate(mt9v032, 1); |
659 | ||
0f2ce168 DC |
660 | return ret; |
661 | } | |
662 | ||
663 | static int mt9v032_open(struct v4l2_subdev *subdev, struct v4l2_subdev_fh *fh) | |
664 | { | |
665 | struct v4l2_mbus_framefmt *format; | |
666 | struct v4l2_rect *crop; | |
667 | ||
668 | crop = v4l2_subdev_get_try_crop(fh, 0); | |
669 | crop->left = MT9V032_COLUMN_START_DEF; | |
670 | crop->top = MT9V032_ROW_START_DEF; | |
671 | crop->width = MT9V032_WINDOW_WIDTH_DEF; | |
672 | crop->height = MT9V032_WINDOW_HEIGHT_DEF; | |
673 | ||
674 | format = v4l2_subdev_get_try_format(fh, 0); | |
675 | format->code = V4L2_MBUS_FMT_SGRBG10_1X10; | |
676 | format->width = MT9V032_WINDOW_WIDTH_DEF; | |
677 | format->height = MT9V032_WINDOW_HEIGHT_DEF; | |
678 | format->field = V4L2_FIELD_NONE; | |
679 | format->colorspace = V4L2_COLORSPACE_SRGB; | |
680 | ||
681 | return mt9v032_set_power(subdev, 1); | |
682 | } | |
683 | ||
684 | static int mt9v032_close(struct v4l2_subdev *subdev, struct v4l2_subdev_fh *fh) | |
685 | { | |
686 | return mt9v032_set_power(subdev, 0); | |
687 | } | |
688 | ||
689 | static struct v4l2_subdev_core_ops mt9v032_subdev_core_ops = { | |
690 | .s_power = mt9v032_set_power, | |
691 | }; | |
692 | ||
693 | static struct v4l2_subdev_video_ops mt9v032_subdev_video_ops = { | |
694 | .s_stream = mt9v032_s_stream, | |
695 | }; | |
696 | ||
697 | static struct v4l2_subdev_pad_ops mt9v032_subdev_pad_ops = { | |
698 | .enum_mbus_code = mt9v032_enum_mbus_code, | |
699 | .enum_frame_size = mt9v032_enum_frame_size, | |
700 | .get_fmt = mt9v032_get_format, | |
701 | .set_fmt = mt9v032_set_format, | |
702 | .get_crop = mt9v032_get_crop, | |
703 | .set_crop = mt9v032_set_crop, | |
704 | }; | |
705 | ||
706 | static struct v4l2_subdev_ops mt9v032_subdev_ops = { | |
707 | .core = &mt9v032_subdev_core_ops, | |
708 | .video = &mt9v032_subdev_video_ops, | |
709 | .pad = &mt9v032_subdev_pad_ops, | |
710 | }; | |
711 | ||
712 | static const struct v4l2_subdev_internal_ops mt9v032_subdev_internal_ops = { | |
713 | .registered = mt9v032_registered, | |
714 | .open = mt9v032_open, | |
715 | .close = mt9v032_close, | |
716 | }; | |
717 | ||
718 | /* ----------------------------------------------------------------------------- | |
719 | * Driver initialization and probing | |
720 | */ | |
721 | ||
722 | static int mt9v032_probe(struct i2c_client *client, | |
723 | const struct i2c_device_id *did) | |
724 | { | |
e9a50e4c | 725 | struct mt9v032_platform_data *pdata = client->dev.platform_data; |
0f2ce168 DC |
726 | struct mt9v032 *mt9v032; |
727 | unsigned int i; | |
728 | int ret; | |
729 | ||
730 | if (!i2c_check_functionality(client->adapter, | |
731 | I2C_FUNC_SMBUS_WORD_DATA)) { | |
732 | dev_warn(&client->adapter->dev, | |
733 | "I2C-Adapter doesn't support I2C_FUNC_SMBUS_WORD\n"); | |
734 | return -EIO; | |
735 | } | |
736 | ||
737 | mt9v032 = kzalloc(sizeof(*mt9v032), GFP_KERNEL); | |
738 | if (!mt9v032) | |
739 | return -ENOMEM; | |
740 | ||
741 | mutex_init(&mt9v032->power_lock); | |
e9a50e4c | 742 | mt9v032->pdata = pdata; |
0f2ce168 | 743 | |
9ec670e2 | 744 | v4l2_ctrl_handler_init(&mt9v032->ctrls, ARRAY_SIZE(mt9v032_ctrls) + 8); |
0f2ce168 DC |
745 | |
746 | v4l2_ctrl_new_std(&mt9v032->ctrls, &mt9v032_ctrl_ops, | |
747 | V4L2_CID_AUTOGAIN, 0, 1, 1, 1); | |
748 | v4l2_ctrl_new_std(&mt9v032->ctrls, &mt9v032_ctrl_ops, | |
749 | V4L2_CID_GAIN, MT9V032_ANALOG_GAIN_MIN, | |
750 | MT9V032_ANALOG_GAIN_MAX, 1, MT9V032_ANALOG_GAIN_DEF); | |
751 | v4l2_ctrl_new_std_menu(&mt9v032->ctrls, &mt9v032_ctrl_ops, | |
752 | V4L2_CID_EXPOSURE_AUTO, V4L2_EXPOSURE_MANUAL, 0, | |
753 | V4L2_EXPOSURE_AUTO); | |
754 | v4l2_ctrl_new_std(&mt9v032->ctrls, &mt9v032_ctrl_ops, | |
755 | V4L2_CID_EXPOSURE, MT9V032_TOTAL_SHUTTER_WIDTH_MIN, | |
756 | MT9V032_TOTAL_SHUTTER_WIDTH_MAX, 1, | |
757 | MT9V032_TOTAL_SHUTTER_WIDTH_DEF); | |
9ec670e2 LP |
758 | v4l2_ctrl_new_std(&mt9v032->ctrls, &mt9v032_ctrl_ops, |
759 | V4L2_CID_HBLANK, MT9V032_HORIZONTAL_BLANKING_MIN, | |
760 | MT9V032_HORIZONTAL_BLANKING_MAX, 1, | |
761 | MT9V032_HORIZONTAL_BLANKING_DEF); | |
762 | v4l2_ctrl_new_std(&mt9v032->ctrls, &mt9v032_ctrl_ops, | |
763 | V4L2_CID_VBLANK, MT9V032_VERTICAL_BLANKING_MIN, | |
764 | MT9V032_VERTICAL_BLANKING_MAX, 1, | |
765 | MT9V032_VERTICAL_BLANKING_DEF); | |
e9a50e4c | 766 | |
41a33a00 SA |
767 | mt9v032->pixel_rate = |
768 | v4l2_ctrl_new_std(&mt9v032->ctrls, &mt9v032_ctrl_ops, | |
769 | V4L2_CID_PIXEL_RATE, 0, 0, 1, 0); | |
0f2ce168 | 770 | |
e9a50e4c LP |
771 | if (pdata && pdata->link_freqs) { |
772 | unsigned int def = 0; | |
773 | ||
774 | for (i = 0; pdata->link_freqs[i]; ++i) { | |
775 | if (pdata->link_freqs[i] == pdata->link_def_freq) | |
776 | def = i; | |
777 | } | |
778 | ||
779 | mt9v032->link_freq = | |
780 | v4l2_ctrl_new_int_menu(&mt9v032->ctrls, | |
781 | &mt9v032_ctrl_ops, | |
782 | V4L2_CID_LINK_FREQ, i - 1, def, | |
783 | pdata->link_freqs); | |
784 | v4l2_ctrl_cluster(2, &mt9v032->link_freq); | |
785 | } | |
786 | ||
0f2ce168 DC |
787 | for (i = 0; i < ARRAY_SIZE(mt9v032_ctrls); ++i) |
788 | v4l2_ctrl_new_custom(&mt9v032->ctrls, &mt9v032_ctrls[i], NULL); | |
789 | ||
790 | mt9v032->subdev.ctrl_handler = &mt9v032->ctrls; | |
791 | ||
792 | if (mt9v032->ctrls.error) | |
793 | printk(KERN_INFO "%s: control initialization error %d\n", | |
794 | __func__, mt9v032->ctrls.error); | |
795 | ||
796 | mt9v032->crop.left = MT9V032_COLUMN_START_DEF; | |
797 | mt9v032->crop.top = MT9V032_ROW_START_DEF; | |
798 | mt9v032->crop.width = MT9V032_WINDOW_WIDTH_DEF; | |
799 | mt9v032->crop.height = MT9V032_WINDOW_HEIGHT_DEF; | |
800 | ||
801 | mt9v032->format.code = V4L2_MBUS_FMT_SGRBG10_1X10; | |
802 | mt9v032->format.width = MT9V032_WINDOW_WIDTH_DEF; | |
803 | mt9v032->format.height = MT9V032_WINDOW_HEIGHT_DEF; | |
804 | mt9v032->format.field = V4L2_FIELD_NONE; | |
805 | mt9v032->format.colorspace = V4L2_COLORSPACE_SRGB; | |
806 | ||
807 | mt9v032->aec_agc = MT9V032_AEC_ENABLE | MT9V032_AGC_ENABLE; | |
9ec670e2 | 808 | mt9v032->hblank = MT9V032_HORIZONTAL_BLANKING_DEF; |
e9a50e4c | 809 | mt9v032->sysclk = MT9V032_SYSCLK_FREQ_DEF; |
0f2ce168 DC |
810 | |
811 | v4l2_i2c_subdev_init(&mt9v032->subdev, client, &mt9v032_subdev_ops); | |
812 | mt9v032->subdev.internal_ops = &mt9v032_subdev_internal_ops; | |
813 | mt9v032->subdev.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; | |
814 | ||
815 | mt9v032->pad.flags = MEDIA_PAD_FL_SOURCE; | |
816 | ret = media_entity_init(&mt9v032->subdev.entity, 1, &mt9v032->pad, 0); | |
817 | if (ret < 0) | |
818 | kfree(mt9v032); | |
819 | ||
820 | return ret; | |
821 | } | |
822 | ||
823 | static int mt9v032_remove(struct i2c_client *client) | |
824 | { | |
825 | struct v4l2_subdev *subdev = i2c_get_clientdata(client); | |
826 | struct mt9v032 *mt9v032 = to_mt9v032(subdev); | |
827 | ||
828 | v4l2_device_unregister_subdev(subdev); | |
829 | media_entity_cleanup(&subdev->entity); | |
830 | kfree(mt9v032); | |
831 | return 0; | |
832 | } | |
833 | ||
834 | static const struct i2c_device_id mt9v032_id[] = { | |
835 | { "mt9v032", 0 }, | |
836 | { } | |
837 | }; | |
838 | MODULE_DEVICE_TABLE(i2c, mt9v032_id); | |
839 | ||
840 | static struct i2c_driver mt9v032_driver = { | |
841 | .driver = { | |
842 | .name = "mt9v032", | |
843 | }, | |
844 | .probe = mt9v032_probe, | |
845 | .remove = mt9v032_remove, | |
846 | .id_table = mt9v032_id, | |
847 | }; | |
848 | ||
c6e8d86f | 849 | module_i2c_driver(mt9v032_driver); |
0f2ce168 DC |
850 | |
851 | MODULE_DESCRIPTION("Aptina MT9V032 Camera driver"); | |
852 | MODULE_AUTHOR("Laurent Pinchart <laurent.pinchart@ideasonboard.com>"); | |
853 | MODULE_LICENSE("GPL"); |