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[media] mt9v032: Remove unused macro
[mirror_ubuntu-artful-kernel.git] / drivers / media / i2c / mt9v032.c
CommitLineData
0f2ce168
DC		 1/*
2 * Driver for MT9V032 CMOS Image Sensor from Micron
3 *
4 * Copyright (C) 2010, Laurent Pinchart <laurent.pinchart@ideasonboard.com>
5 *
6 * Based on the MT9M001 driver,
7 *
8 * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
3300a8fd 15#include <linux/clk.h>
0f2ce168
DC		 16#include <linux/delay.h>
17#include <linux/i2c.h>
18#include <linux/log2.h>
19#include <linux/mutex.h>
20#include <linux/slab.h>
21#include <linux/videodev2.h>
22#include <linux/v4l2-mediabus.h>
7a707b89 23#include <linux/module.h>
0f2ce168
DC		 24
25#include <media/mt9v032.h>
26#include <media/v4l2-ctrls.h>
27#include <media/v4l2-device.h>
28#include <media/v4l2-subdev.h>
29
30#define MT9V032_PIXEL_ARRAY_HEIGHT 492
31#define MT9V032_PIXEL_ARRAY_WIDTH 782
32
e9a50e4c
LP		 33#define MT9V032_SYSCLK_FREQ_DEF 26600000
34
0f2ce168
DC		 35#define MT9V032_CHIP_VERSION 0x00
36#define MT9V032_CHIP_ID_REV1 0x1311
37#define MT9V032_CHIP_ID_REV3 0x1313
86cf786c 38#define MT9V032_COLUMN_START 0x01
0f2ce168 39#define MT9V032_COLUMN_START_MIN 1
86cf786c 40#define MT9V032_COLUMN_START_DEF 1
0f2ce168 41#define MT9V032_COLUMN_START_MAX 752
86cf786c
LP		 42#define MT9V032_ROW_START 0x02
43#define MT9V032_ROW_START_MIN 4
44#define MT9V032_ROW_START_DEF 5
45#define MT9V032_ROW_START_MAX 482
0f2ce168
DC		 46#define MT9V032_WINDOW_HEIGHT 0x03
47#define MT9V032_WINDOW_HEIGHT_MIN 1
48#define MT9V032_WINDOW_HEIGHT_DEF 480
49#define MT9V032_WINDOW_HEIGHT_MAX 480
50#define MT9V032_WINDOW_WIDTH 0x04
51#define MT9V032_WINDOW_WIDTH_MIN 1
52#define MT9V032_WINDOW_WIDTH_DEF 752
53#define MT9V032_WINDOW_WIDTH_MAX 752
54#define MT9V032_HORIZONTAL_BLANKING 0x05
55#define MT9V032_HORIZONTAL_BLANKING_MIN 43
9ec670e2 56#define MT9V032_HORIZONTAL_BLANKING_DEF 94
0f2ce168
DC		 57#define MT9V032_HORIZONTAL_BLANKING_MAX 1023
58#define MT9V032_VERTICAL_BLANKING 0x06
59#define MT9V032_VERTICAL_BLANKING_MIN 4
9ec670e2 60#define MT9V032_VERTICAL_BLANKING_DEF 45
0f2ce168
DC		 61#define MT9V032_VERTICAL_BLANKING_MAX 3000
62#define MT9V032_CHIP_CONTROL 0x07
63#define MT9V032_CHIP_CONTROL_MASTER_MODE (1 << 3)
64#define MT9V032_CHIP_CONTROL_DOUT_ENABLE (1 << 7)
65#define MT9V032_CHIP_CONTROL_SEQUENTIAL (1 << 8)
66#define MT9V032_SHUTTER_WIDTH1 0x08
67#define MT9V032_SHUTTER_WIDTH2 0x09
68#define MT9V032_SHUTTER_WIDTH_CONTROL 0x0a
69#define MT9V032_TOTAL_SHUTTER_WIDTH 0x0b
70#define MT9V032_TOTAL_SHUTTER_WIDTH_MIN 1
71#define MT9V032_TOTAL_SHUTTER_WIDTH_DEF 480
72#define MT9V032_TOTAL_SHUTTER_WIDTH_MAX 32767
73#define MT9V032_RESET 0x0c
74#define MT9V032_READ_MODE 0x0d
75#define MT9V032_READ_MODE_ROW_BIN_MASK (3 << 0)
76#define MT9V032_READ_MODE_ROW_BIN_SHIFT 0
77#define MT9V032_READ_MODE_COLUMN_BIN_MASK (3 << 2)
78#define MT9V032_READ_MODE_COLUMN_BIN_SHIFT 2
79#define MT9V032_READ_MODE_ROW_FLIP (1 << 4)
80#define MT9V032_READ_MODE_COLUMN_FLIP (1 << 5)
81#define MT9V032_READ_MODE_DARK_COLUMNS (1 << 6)
82#define MT9V032_READ_MODE_DARK_ROWS (1 << 7)
83#define MT9V032_PIXEL_OPERATION_MODE 0x0f
84#define MT9V032_PIXEL_OPERATION_MODE_COLOR (1 << 2)
85#define MT9V032_PIXEL_OPERATION_MODE_HDR (1 << 6)
86#define MT9V032_ANALOG_GAIN 0x35
87#define MT9V032_ANALOG_GAIN_MIN 16
88#define MT9V032_ANALOG_GAIN_DEF 16
89#define MT9V032_ANALOG_GAIN_MAX 64
90#define MT9V032_MAX_ANALOG_GAIN 0x36
91#define MT9V032_MAX_ANALOG_GAIN_MAX 127
92#define MT9V032_FRAME_DARK_AVERAGE 0x42
93#define MT9V032_DARK_AVG_THRESH 0x46
94#define MT9V032_DARK_AVG_LOW_THRESH_MASK (255 << 0)
95#define MT9V032_DARK_AVG_LOW_THRESH_SHIFT 0
96#define MT9V032_DARK_AVG_HIGH_THRESH_MASK (255 << 8)
97#define MT9V032_DARK_AVG_HIGH_THRESH_SHIFT 8
98#define MT9V032_ROW_NOISE_CORR_CONTROL 0x70
99#define MT9V032_ROW_NOISE_CORR_ENABLE (1 << 5)
100#define MT9V032_ROW_NOISE_CORR_USE_BLK_AVG (1 << 7)
101#define MT9V032_PIXEL_CLOCK 0x74
102#define MT9V032_PIXEL_CLOCK_INV_LINE (1 << 0)
103#define MT9V032_PIXEL_CLOCK_INV_FRAME (1 << 1)
104#define MT9V032_PIXEL_CLOCK_XOR_LINE (1 << 2)
105#define MT9V032_PIXEL_CLOCK_CONT_LINE (1 << 3)
106#define MT9V032_PIXEL_CLOCK_INV_PXL_CLK (1 << 4)
107#define MT9V032_TEST_PATTERN 0x7f
108#define MT9V032_TEST_PATTERN_DATA_MASK (1023 << 0)
109#define MT9V032_TEST_PATTERN_DATA_SHIFT 0
110#define MT9V032_TEST_PATTERN_USE_DATA (1 << 10)
111#define MT9V032_TEST_PATTERN_GRAY_MASK (3 << 11)
112#define MT9V032_TEST_PATTERN_GRAY_NONE (0 << 11)
113#define MT9V032_TEST_PATTERN_GRAY_VERTICAL (1 << 11)
114#define MT9V032_TEST_PATTERN_GRAY_HORIZONTAL (2 << 11)
115#define MT9V032_TEST_PATTERN_GRAY_DIAGONAL (3 << 11)
116#define MT9V032_TEST_PATTERN_ENABLE (1 << 13)
117#define MT9V032_TEST_PATTERN_FLIP (1 << 14)
118#define MT9V032_AEC_AGC_ENABLE 0xaf
119#define MT9V032_AEC_ENABLE (1 << 0)
120#define MT9V032_AGC_ENABLE (1 << 1)
121#define MT9V032_THERMAL_INFO 0xc1
122
123struct mt9v032 {
124 struct v4l2_subdev subdev;
125 struct media_pad pad;
126
127 struct v4l2_mbus_framefmt format;
128 struct v4l2_rect crop;
129
130 struct v4l2_ctrl_handler ctrls;
e9a50e4c
LP		 131 struct {
132 struct v4l2_ctrl *link_freq;
133 struct v4l2_ctrl *pixel_rate;
134 };
0f2ce168
DC		 135
136 struct mutex power_lock;
137 int power_count;
138
3300a8fd
LP		 139 struct clk *clk;
140
0f2ce168 141 struct mt9v032_platform_data *pdata;
e9a50e4c
LP		 142
143 u32 sysclk;
0f2ce168
DC		 144 u16 chip_control;
145 u16 aec_agc;
9ec670e2 146 u16 hblank;
b28d7017
LP		 147 struct {
148 struct v4l2_ctrl *test_pattern;
149 struct v4l2_ctrl *test_pattern_color;
150 };
0f2ce168
DC		 151};
152
153static struct mt9v032 *to_mt9v032(struct v4l2_subdev *sd)
154{
155 return container_of(sd, struct mt9v032, subdev);
156}
157
158static int mt9v032_read(struct i2c_client *client, const u8 reg)
159{
3f877045 160 s32 data = i2c_smbus_read_word_swapped(client, reg);
0f2ce168 161 dev_dbg(&client->dev, "%s: read 0x%04x from 0x%02x\n", __func__,
3f877045
JC		 162 data, reg);
163 return data;
0f2ce168
DC		 164}
165
166static int mt9v032_write(struct i2c_client *client, const u8 reg,
167 const u16 data)
168{
169 dev_dbg(&client->dev, "%s: writing 0x%04x to 0x%02x\n", __func__,
170 data, reg);
3f877045 171 return i2c_smbus_write_word_swapped(client, reg, data);
0f2ce168
DC		 172}
173
174static int mt9v032_set_chip_control(struct mt9v032 *mt9v032, u16 clear, u16 set)
175{
176 struct i2c_client *client = v4l2_get_subdevdata(&mt9v032->subdev);
177 u16 value = (mt9v032->chip_control & ~clear) | set;
178 int ret;
179
180 ret = mt9v032_write(client, MT9V032_CHIP_CONTROL, value);
181 if (ret < 0)
182 return ret;
183
184 mt9v032->chip_control = value;
185 return 0;
186}
187
188static int
189mt9v032_update_aec_agc(struct mt9v032 *mt9v032, u16 which, int enable)
190{
191 struct i2c_client *client = v4l2_get_subdevdata(&mt9v032->subdev);
192 u16 value = mt9v032->aec_agc;
193 int ret;
194
195 if (enable)
196 value |= which;
197 else
198 value &= ~which;
199
200 ret = mt9v032_write(client, MT9V032_AEC_AGC_ENABLE, value);
201 if (ret < 0)
202 return ret;
203
204 mt9v032->aec_agc = value;
205 return 0;
206}
207
9ec670e2
LP		 208static int
209mt9v032_update_hblank(struct mt9v032 *mt9v032)
210{
211 struct i2c_client *client = v4l2_get_subdevdata(&mt9v032->subdev);
212 struct v4l2_rect *crop = &mt9v032->crop;
213
214 return mt9v032_write(client, MT9V032_HORIZONTAL_BLANKING,
215 max_t(s32, mt9v032->hblank, 660 - crop->width));
216}
217
0f2ce168
DC		 218static int mt9v032_power_on(struct mt9v032 *mt9v032)
219{
220 struct i2c_client *client = v4l2_get_subdevdata(&mt9v032->subdev);
221 int ret;
222
3300a8fd
LP		 223 clk_set_rate(mt9v032->clk, mt9v032->sysclk);
224 clk_prepare_enable(mt9v032->clk);
225 udelay(1);
0f2ce168
DC		 226
227 /* Reset the chip and stop data read out */
228 ret = mt9v032_write(client, MT9V032_RESET, 1);
229 if (ret < 0)
230 return ret;
231
232 ret = mt9v032_write(client, MT9V032_RESET, 0);
233 if (ret < 0)
234 return ret;
235
236 return mt9v032_write(client, MT9V032_CHIP_CONTROL, 0);
237}
238
239static void mt9v032_power_off(struct mt9v032 *mt9v032)
240{
3300a8fd 241 clk_disable_unprepare(mt9v032->clk);
0f2ce168
DC		 242}
243
244static int __mt9v032_set_power(struct mt9v032 *mt9v032, bool on)
245{
246 struct i2c_client *client = v4l2_get_subdevdata(&mt9v032->subdev);
247 int ret;
248
249 if (!on) {
250 mt9v032_power_off(mt9v032);
251 return 0;
252 }
253
254 ret = mt9v032_power_on(mt9v032);
255 if (ret < 0)
256 return ret;
257
258 /* Configure the pixel clock polarity */
259 if (mt9v032->pdata && mt9v032->pdata->clk_pol) {
260 ret = mt9v032_write(client, MT9V032_PIXEL_CLOCK,
261 MT9V032_PIXEL_CLOCK_INV_PXL_CLK);
262 if (ret < 0)
263 return ret;
264 }
265
266 /* Disable the noise correction algorithm and restore the controls. */
267 ret = mt9v032_write(client, MT9V032_ROW_NOISE_CORR_CONTROL, 0);
268 if (ret < 0)
269 return ret;
270
271 return v4l2_ctrl_handler_setup(&mt9v032->ctrls);
272}
273
274/* -----------------------------------------------------------------------------
275 * V4L2 subdev video operations
276 */
277
278static struct v4l2_mbus_framefmt *
279__mt9v032_get_pad_format(struct mt9v032 *mt9v032, struct v4l2_subdev_fh *fh,
280 unsigned int pad, enum v4l2_subdev_format_whence which)
281{
282 switch (which) {
283 case V4L2_SUBDEV_FORMAT_TRY:
284 return v4l2_subdev_get_try_format(fh, pad);
285 case V4L2_SUBDEV_FORMAT_ACTIVE:
286 return &mt9v032->format;
287 default:
288 return NULL;
289 }
290}
291
292static struct v4l2_rect *
293__mt9v032_get_pad_crop(struct mt9v032 *mt9v032, struct v4l2_subdev_fh *fh,
294 unsigned int pad, enum v4l2_subdev_format_whence which)
295{
296 switch (which) {
297 case V4L2_SUBDEV_FORMAT_TRY:
298 return v4l2_subdev_get_try_crop(fh, pad);
299 case V4L2_SUBDEV_FORMAT_ACTIVE:
300 return &mt9v032->crop;
301 default:
302 return NULL;
303 }
304}
305
306static int mt9v032_s_stream(struct v4l2_subdev *subdev, int enable)
307{
308 const u16 mode = MT9V032_CHIP_CONTROL_MASTER_MODE
309 | MT9V032_CHIP_CONTROL_DOUT_ENABLE
310 | MT9V032_CHIP_CONTROL_SEQUENTIAL;
311 struct i2c_client *client = v4l2_get_subdevdata(subdev);
312 struct mt9v032 *mt9v032 = to_mt9v032(subdev);
313 struct v4l2_mbus_framefmt *format = &mt9v032->format;
314 struct v4l2_rect *crop = &mt9v032->crop;
315 unsigned int hratio;
316 unsigned int vratio;
317 int ret;
318
319 if (!enable)
320 return mt9v032_set_chip_control(mt9v032, mode, 0);
321
322 /* Configure the window size and row/column bin */
323 hratio = DIV_ROUND_CLOSEST(crop->width, format->width);
324 vratio = DIV_ROUND_CLOSEST(crop->height, format->height);
325
326 ret = mt9v032_write(client, MT9V032_READ_MODE,
327 (hratio - 1) << MT9V032_READ_MODE_ROW_BIN_SHIFT |
328 (vratio - 1) << MT9V032_READ_MODE_COLUMN_BIN_SHIFT);
329 if (ret < 0)
330 return ret;
331
332 ret = mt9v032_write(client, MT9V032_COLUMN_START, crop->left);
333 if (ret < 0)
334 return ret;
335
336 ret = mt9v032_write(client, MT9V032_ROW_START, crop->top);
337 if (ret < 0)
338 return ret;
339
340 ret = mt9v032_write(client, MT9V032_WINDOW_WIDTH, crop->width);
341 if (ret < 0)
342 return ret;
343
344 ret = mt9v032_write(client, MT9V032_WINDOW_HEIGHT, crop->height);
345 if (ret < 0)
346 return ret;
347
9ec670e2 348 ret = mt9v032_update_hblank(mt9v032);
0f2ce168
DC		 349 if (ret < 0)
350 return ret;
351
352 /* Switch to master "normal" mode */
353 return mt9v032_set_chip_control(mt9v032, 0, mode);
354}
355
356static int mt9v032_enum_mbus_code(struct v4l2_subdev *subdev,
357 struct v4l2_subdev_fh *fh,
358 struct v4l2_subdev_mbus_code_enum *code)
359{
360 if (code->index > 0)
361 return -EINVAL;
362
363 code->code = V4L2_MBUS_FMT_SGRBG10_1X10;
364 return 0;
365}
366
367static int mt9v032_enum_frame_size(struct v4l2_subdev *subdev,
368 struct v4l2_subdev_fh *fh,
369 struct v4l2_subdev_frame_size_enum *fse)
370{
371 if (fse->index >= 8 || fse->code != V4L2_MBUS_FMT_SGRBG10_1X10)
372 return -EINVAL;
373
374 fse->min_width = MT9V032_WINDOW_WIDTH_DEF / fse->index;
375 fse->max_width = fse->min_width;
376 fse->min_height = MT9V032_WINDOW_HEIGHT_DEF / fse->index;
377 fse->max_height = fse->min_height;
378
379 return 0;
380}
381
382static int mt9v032_get_format(struct v4l2_subdev *subdev,
383 struct v4l2_subdev_fh *fh,
384 struct v4l2_subdev_format *format)
385{
386 struct mt9v032 *mt9v032 = to_mt9v032(subdev);
387
388 format->format = *__mt9v032_get_pad_format(mt9v032, fh, format->pad,
389 format->which);
390 return 0;
391}
392
41a33a00
SA		 393static void mt9v032_configure_pixel_rate(struct mt9v032 *mt9v032,
394 unsigned int hratio)
395{
396 struct i2c_client *client = v4l2_get_subdevdata(&mt9v032->subdev);
397 int ret;
398
e9a50e4c
LP		 399 ret = v4l2_ctrl_s_ctrl_int64(mt9v032->pixel_rate,
400 mt9v032->sysclk / hratio);
41a33a00
SA		 401 if (ret < 0)
402 dev_warn(&client->dev, "failed to set pixel rate (%d)\n", ret);
403}
404
0f2ce168
DC		 405static int mt9v032_set_format(struct v4l2_subdev *subdev,
406 struct v4l2_subdev_fh *fh,
407 struct v4l2_subdev_format *format)
408{
409 struct mt9v032 *mt9v032 = to_mt9v032(subdev);
410 struct v4l2_mbus_framefmt *__format;
411 struct v4l2_rect *__crop;
412 unsigned int width;
413 unsigned int height;
414 unsigned int hratio;
415 unsigned int vratio;
416
417 __crop = __mt9v032_get_pad_crop(mt9v032, fh, format->pad,
418 format->which);
419
420 /* Clamp the width and height to avoid dividing by zero. */
421 width = clamp_t(unsigned int, ALIGN(format->format.width, 2),
422 max(__crop->width / 8, MT9V032_WINDOW_WIDTH_MIN),
423 __crop->width);
424 height = clamp_t(unsigned int, ALIGN(format->format.height, 2),
425 max(__crop->height / 8, MT9V032_WINDOW_HEIGHT_MIN),
426 __crop->height);
427
428 hratio = DIV_ROUND_CLOSEST(__crop->width, width);
429 vratio = DIV_ROUND_CLOSEST(__crop->height, height);
430
431 __format = __mt9v032_get_pad_format(mt9v032, fh, format->pad,
432 format->which);
433 __format->width = __crop->width / hratio;
434 __format->height = __crop->height / vratio;
41a33a00
SA		 435 if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE)
436 mt9v032_configure_pixel_rate(mt9v032, hratio);
0f2ce168
DC		 437
438 format->format = *__format;
439
440 return 0;
441}
442
443static int mt9v032_get_crop(struct v4l2_subdev *subdev,
444 struct v4l2_subdev_fh *fh,
445 struct v4l2_subdev_crop *crop)
446{
447 struct mt9v032 *mt9v032 = to_mt9v032(subdev);
448
449 crop->rect = *__mt9v032_get_pad_crop(mt9v032, fh, crop->pad,
450 crop->which);
451 return 0;
452}
453
454static int mt9v032_set_crop(struct v4l2_subdev *subdev,
455 struct v4l2_subdev_fh *fh,
456 struct v4l2_subdev_crop *crop)
457{
458 struct mt9v032 *mt9v032 = to_mt9v032(subdev);
459 struct v4l2_mbus_framefmt *__format;
460 struct v4l2_rect *__crop;
461 struct v4l2_rect rect;
462
86cf786c
LP		 463 /* Clamp the crop rectangle boundaries and align them to a non multiple
464 * of 2 pixels to ensure a GRBG Bayer pattern.
0f2ce168 465 */
86cf786c 466 rect.left = clamp(ALIGN(crop->rect.left + 1, 2) - 1,
0f2ce168
DC		 467 MT9V032_COLUMN_START_MIN,
468 MT9V032_COLUMN_START_MAX);
86cf786c 469 rect.top = clamp(ALIGN(crop->rect.top + 1, 2) - 1,
0f2ce168
DC		 470 MT9V032_ROW_START_MIN,
471 MT9V032_ROW_START_MAX);
472 rect.width = clamp(ALIGN(crop->rect.width, 2),
473 MT9V032_WINDOW_WIDTH_MIN,
474 MT9V032_WINDOW_WIDTH_MAX);
475 rect.height = clamp(ALIGN(crop->rect.height, 2),
476 MT9V032_WINDOW_HEIGHT_MIN,
477 MT9V032_WINDOW_HEIGHT_MAX);
478
479 rect.width = min(rect.width, MT9V032_PIXEL_ARRAY_WIDTH - rect.left);
480 rect.height = min(rect.height, MT9V032_PIXEL_ARRAY_HEIGHT - rect.top);
481
482 __crop = __mt9v032_get_pad_crop(mt9v032, fh, crop->pad, crop->which);
483
484 if (rect.width != __crop->width || rect.height != __crop->height) {
485 /* Reset the output image size if the crop rectangle size has
486 * been modified.
487 */
488 __format = __mt9v032_get_pad_format(mt9v032, fh, crop->pad,
489 crop->which);
490 __format->width = rect.width;
491 __format->height = rect.height;
41a33a00
SA		 492 if (crop->which == V4L2_SUBDEV_FORMAT_ACTIVE)
493 mt9v032_configure_pixel_rate(mt9v032, 1);
0f2ce168
DC		 494 }
495
496 *__crop = rect;
497 crop->rect = rect;
498
499 return 0;
500}
501
502/* -----------------------------------------------------------------------------
503 * V4L2 subdev control operations
504 */
505
b28d7017 506#define V4L2_CID_TEST_PATTERN_COLOR (V4L2_CID_USER_BASE | 0x1001)
0f2ce168
DC		 507
508static int mt9v032_s_ctrl(struct v4l2_ctrl *ctrl)
509{
510 struct mt9v032 *mt9v032 =
511 container_of(ctrl->handler, struct mt9v032, ctrls);
512 struct i2c_client *client = v4l2_get_subdevdata(&mt9v032->subdev);
e9a50e4c 513 u32 freq;
0f2ce168
DC		 514 u16 data;
515
516 switch (ctrl->id) {
517 case V4L2_CID_AUTOGAIN:
518 return mt9v032_update_aec_agc(mt9v032, MT9V032_AGC_ENABLE,
519 ctrl->val);
520
521 case V4L2_CID_GAIN:
522 return mt9v032_write(client, MT9V032_ANALOG_GAIN, ctrl->val);
523
524 case V4L2_CID_EXPOSURE_AUTO:
525 return mt9v032_update_aec_agc(mt9v032, MT9V032_AEC_ENABLE,
5c375981 526 !ctrl->val);
0f2ce168
DC		 527
528 case V4L2_CID_EXPOSURE:
529 return mt9v032_write(client, MT9V032_TOTAL_SHUTTER_WIDTH,
530 ctrl->val);
531
9ec670e2
LP		 532 case V4L2_CID_HBLANK:
533 mt9v032->hblank = ctrl->val;
534 return mt9v032_update_hblank(mt9v032);
535
536 case V4L2_CID_VBLANK:
537 return mt9v032_write(client, MT9V032_VERTICAL_BLANKING,
538 ctrl->val);
539
e9a50e4c
LP		 540 case V4L2_CID_PIXEL_RATE:
541 case V4L2_CID_LINK_FREQ:
542 if (mt9v032->link_freq == NULL)
543 break;
544
545 freq = mt9v032->pdata->link_freqs[mt9v032->link_freq->val];
546 mt9v032->pixel_rate->val64 = freq;
547 mt9v032->sysclk = freq;
548 break;
549
0f2ce168 550 case V4L2_CID_TEST_PATTERN:
b28d7017 551 switch (mt9v032->test_pattern->val) {
0f2ce168
DC		 552 case 0:
553 data = 0;
554 break;
555 case 1:
556 data = MT9V032_TEST_PATTERN_GRAY_VERTICAL
557 | MT9V032_TEST_PATTERN_ENABLE;
558 break;
559 case 2:
560 data = MT9V032_TEST_PATTERN_GRAY_HORIZONTAL
561 | MT9V032_TEST_PATTERN_ENABLE;
562 break;
563 case 3:
564 data = MT9V032_TEST_PATTERN_GRAY_DIAGONAL
565 | MT9V032_TEST_PATTERN_ENABLE;
566 break;
567 default:
b28d7017
LP		 568 data = (mt9v032->test_pattern_color->val <<
569 MT9V032_TEST_PATTERN_DATA_SHIFT)
0f2ce168
DC		 570 | MT9V032_TEST_PATTERN_USE_DATA
571 | MT9V032_TEST_PATTERN_ENABLE
572 | MT9V032_TEST_PATTERN_FLIP;
573 break;
574 }
0f2ce168
DC		 575 return mt9v032_write(client, MT9V032_TEST_PATTERN, data);
576 }
577
578 return 0;
579}
580
581static struct v4l2_ctrl_ops mt9v032_ctrl_ops = {
582 .s_ctrl = mt9v032_s_ctrl,
583};
584
b28d7017
LP		 585static const char * const mt9v032_test_pattern_menu[] = {
586 "Disabled",
587 "Gray Vertical Shade",
588 "Gray Horizontal Shade",
589 "Gray Diagonal Shade",
590 "Plain",
591};
592
593static const struct v4l2_ctrl_config mt9v032_test_pattern_color = {
594 .ops = &mt9v032_ctrl_ops,
595 .id = V4L2_CID_TEST_PATTERN_COLOR,
596 .type = V4L2_CTRL_TYPE_INTEGER,
597 .name = "Test Pattern Color",
598 .min = 0,
599 .max = 1023,
600 .step = 1,
601 .def = 0,
602 .flags = 0,
0f2ce168
DC		 603};
604
605/* -----------------------------------------------------------------------------
606 * V4L2 subdev core operations
607 */
608
609static int mt9v032_set_power(struct v4l2_subdev *subdev, int on)
610{
611 struct mt9v032 *mt9v032 = to_mt9v032(subdev);
612 int ret = 0;
613
614 mutex_lock(&mt9v032->power_lock);
615
616 /* If the power count is modified from 0 to != 0 or from != 0 to 0,
617 * update the power state.
618 */
619 if (mt9v032->power_count == !on) {
620 ret = __mt9v032_set_power(mt9v032, !!on);
621 if (ret < 0)
622 goto done;
623 }
624
625 /* Update the power count. */
626 mt9v032->power_count += on ? 1 : -1;
627 WARN_ON(mt9v032->power_count < 0);
628
629done:
630 mutex_unlock(&mt9v032->power_lock);
631 return ret;
632}
633
634/* -----------------------------------------------------------------------------
635 * V4L2 subdev internal operations
636 */
637
638static int mt9v032_registered(struct v4l2_subdev *subdev)
639{
640 struct i2c_client *client = v4l2_get_subdevdata(subdev);
641 struct mt9v032 *mt9v032 = to_mt9v032(subdev);
642 s32 data;
643 int ret;
644
645 dev_info(&client->dev, "Probing MT9V032 at address 0x%02x\n",
646 client->addr);
647
648 ret = mt9v032_power_on(mt9v032);
649 if (ret < 0) {
650 dev_err(&client->dev, "MT9V032 power up failed\n");
651 return ret;
652 }
653
654 /* Read and check the sensor version */
655 data = mt9v032_read(client, MT9V032_CHIP_VERSION);
656 if (data != MT9V032_CHIP_ID_REV1 && data != MT9V032_CHIP_ID_REV3) {
657 dev_err(&client->dev, "MT9V032 not detected, wrong version "
658 "0x%04x\n", data);
659 return -ENODEV;
660 }
661
662 mt9v032_power_off(mt9v032);
663
664 dev_info(&client->dev, "MT9V032 detected at address 0x%02x\n",
665 client->addr);
666
41a33a00
SA		 667 mt9v032_configure_pixel_rate(mt9v032, 1);
668
0f2ce168
DC		 669 return ret;
670}
671
672static int mt9v032_open(struct v4l2_subdev *subdev, struct v4l2_subdev_fh *fh)
673{
674 struct v4l2_mbus_framefmt *format;
675 struct v4l2_rect *crop;
676
677 crop = v4l2_subdev_get_try_crop(fh, 0);
678 crop->left = MT9V032_COLUMN_START_DEF;
679 crop->top = MT9V032_ROW_START_DEF;
680 crop->width = MT9V032_WINDOW_WIDTH_DEF;
681 crop->height = MT9V032_WINDOW_HEIGHT_DEF;
682
683 format = v4l2_subdev_get_try_format(fh, 0);
684 format->code = V4L2_MBUS_FMT_SGRBG10_1X10;
685 format->width = MT9V032_WINDOW_WIDTH_DEF;
686 format->height = MT9V032_WINDOW_HEIGHT_DEF;
687 format->field = V4L2_FIELD_NONE;
688 format->colorspace = V4L2_COLORSPACE_SRGB;
689
690 return mt9v032_set_power(subdev, 1);
691}
692
693static int mt9v032_close(struct v4l2_subdev *subdev, struct v4l2_subdev_fh *fh)
694{
695 return mt9v032_set_power(subdev, 0);
696}
697
698static struct v4l2_subdev_core_ops mt9v032_subdev_core_ops = {
699 .s_power = mt9v032_set_power,
700};
701
702static struct v4l2_subdev_video_ops mt9v032_subdev_video_ops = {
703 .s_stream = mt9v032_s_stream,
704};
705
706static struct v4l2_subdev_pad_ops mt9v032_subdev_pad_ops = {
707 .enum_mbus_code = mt9v032_enum_mbus_code,
708 .enum_frame_size = mt9v032_enum_frame_size,
709 .get_fmt = mt9v032_get_format,
710 .set_fmt = mt9v032_set_format,
711 .get_crop = mt9v032_get_crop,
712 .set_crop = mt9v032_set_crop,
713};
714
715static struct v4l2_subdev_ops mt9v032_subdev_ops = {
716 .core = &mt9v032_subdev_core_ops,
717 .video = &mt9v032_subdev_video_ops,
718 .pad = &mt9v032_subdev_pad_ops,
719};
720
721static const struct v4l2_subdev_internal_ops mt9v032_subdev_internal_ops = {
722 .registered = mt9v032_registered,
723 .open = mt9v032_open,
724 .close = mt9v032_close,
725};
726
727/* -----------------------------------------------------------------------------
728 * Driver initialization and probing
729 */
730
731static int mt9v032_probe(struct i2c_client *client,
732 const struct i2c_device_id *did)
733{
e9a50e4c 734 struct mt9v032_platform_data *pdata = client->dev.platform_data;
0f2ce168
DC		 735 struct mt9v032 *mt9v032;
736 unsigned int i;
737 int ret;
738
739 if (!i2c_check_functionality(client->adapter,
740 I2C_FUNC_SMBUS_WORD_DATA)) {
741 dev_warn(&client->adapter->dev,
742 "I2C-Adapter doesn't support I2C_FUNC_SMBUS_WORD\n");
743 return -EIO;
744 }
745
c02b211d 746 mt9v032 = devm_kzalloc(&client->dev, sizeof(*mt9v032), GFP_KERNEL);
0f2ce168
DC		 747 if (!mt9v032)
748 return -ENOMEM;
749
3300a8fd
LP		 750 mt9v032->clk = devm_clk_get(&client->dev, NULL);
751 if (IS_ERR(mt9v032->clk))
752 return PTR_ERR(mt9v032->clk);
753
0f2ce168 754 mutex_init(&mt9v032->power_lock);
e9a50e4c 755 mt9v032->pdata = pdata;
0f2ce168 756
b28d7017 757 v4l2_ctrl_handler_init(&mt9v032->ctrls, 10);
0f2ce168
DC		 758
759 v4l2_ctrl_new_std(&mt9v032->ctrls, &mt9v032_ctrl_ops,
760 V4L2_CID_AUTOGAIN, 0, 1, 1, 1);
761 v4l2_ctrl_new_std(&mt9v032->ctrls, &mt9v032_ctrl_ops,
762 V4L2_CID_GAIN, MT9V032_ANALOG_GAIN_MIN,
763 MT9V032_ANALOG_GAIN_MAX, 1, MT9V032_ANALOG_GAIN_DEF);
764 v4l2_ctrl_new_std_menu(&mt9v032->ctrls, &mt9v032_ctrl_ops,
765 V4L2_CID_EXPOSURE_AUTO, V4L2_EXPOSURE_MANUAL, 0,
766 V4L2_EXPOSURE_AUTO);
767 v4l2_ctrl_new_std(&mt9v032->ctrls, &mt9v032_ctrl_ops,
768 V4L2_CID_EXPOSURE, MT9V032_TOTAL_SHUTTER_WIDTH_MIN,
769 MT9V032_TOTAL_SHUTTER_WIDTH_MAX, 1,
770 MT9V032_TOTAL_SHUTTER_WIDTH_DEF);
9ec670e2
LP		 771 v4l2_ctrl_new_std(&mt9v032->ctrls, &mt9v032_ctrl_ops,
772 V4L2_CID_HBLANK, MT9V032_HORIZONTAL_BLANKING_MIN,
773 MT9V032_HORIZONTAL_BLANKING_MAX, 1,
774 MT9V032_HORIZONTAL_BLANKING_DEF);
775 v4l2_ctrl_new_std(&mt9v032->ctrls, &mt9v032_ctrl_ops,
776 V4L2_CID_VBLANK, MT9V032_VERTICAL_BLANKING_MIN,
777 MT9V032_VERTICAL_BLANKING_MAX, 1,
778 MT9V032_VERTICAL_BLANKING_DEF);
b28d7017
LP		 779 mt9v032->test_pattern = v4l2_ctrl_new_std_menu_items(&mt9v032->ctrls,
780 &mt9v032_ctrl_ops, V4L2_CID_TEST_PATTERN,
781 ARRAY_SIZE(mt9v032_test_pattern_menu) - 1, 0, 0,
782 mt9v032_test_pattern_menu);
783 mt9v032->test_pattern_color = v4l2_ctrl_new_custom(&mt9v032->ctrls,
784 &mt9v032_test_pattern_color, NULL);
785
786 v4l2_ctrl_cluster(2, &mt9v032->test_pattern);
e9a50e4c 787
41a33a00
SA		 788 mt9v032->pixel_rate =
789 v4l2_ctrl_new_std(&mt9v032->ctrls, &mt9v032_ctrl_ops,
790 V4L2_CID_PIXEL_RATE, 0, 0, 1, 0);
0f2ce168 791
e9a50e4c
LP		 792 if (pdata && pdata->link_freqs) {
793 unsigned int def = 0;
794
795 for (i = 0; pdata->link_freqs[i]; ++i) {
796 if (pdata->link_freqs[i] == pdata->link_def_freq)
797 def = i;
798 }
799
800 mt9v032->link_freq =
801 v4l2_ctrl_new_int_menu(&mt9v032->ctrls,
802 &mt9v032_ctrl_ops,
803 V4L2_CID_LINK_FREQ, i - 1, def,
804 pdata->link_freqs);
805 v4l2_ctrl_cluster(2, &mt9v032->link_freq);
806 }
807
0f2ce168
DC		 808
809 mt9v032->subdev.ctrl_handler = &mt9v032->ctrls;
810
811 if (mt9v032->ctrls.error)
812 printk(KERN_INFO "%s: control initialization error %d\n",
813 __func__, mt9v032->ctrls.error);
814
815 mt9v032->crop.left = MT9V032_COLUMN_START_DEF;
816 mt9v032->crop.top = MT9V032_ROW_START_DEF;
817 mt9v032->crop.width = MT9V032_WINDOW_WIDTH_DEF;
818 mt9v032->crop.height = MT9V032_WINDOW_HEIGHT_DEF;
819
820 mt9v032->format.code = V4L2_MBUS_FMT_SGRBG10_1X10;
821 mt9v032->format.width = MT9V032_WINDOW_WIDTH_DEF;
822 mt9v032->format.height = MT9V032_WINDOW_HEIGHT_DEF;
823 mt9v032->format.field = V4L2_FIELD_NONE;
824 mt9v032->format.colorspace = V4L2_COLORSPACE_SRGB;
825
826 mt9v032->aec_agc = MT9V032_AEC_ENABLE | MT9V032_AGC_ENABLE;
9ec670e2 827 mt9v032->hblank = MT9V032_HORIZONTAL_BLANKING_DEF;
e9a50e4c 828 mt9v032->sysclk = MT9V032_SYSCLK_FREQ_DEF;
0f2ce168
DC		 829
830 v4l2_i2c_subdev_init(&mt9v032->subdev, client, &mt9v032_subdev_ops);
831 mt9v032->subdev.internal_ops = &mt9v032_subdev_internal_ops;
832 mt9v032->subdev.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
833
834 mt9v032->pad.flags = MEDIA_PAD_FL_SOURCE;
835 ret = media_entity_init(&mt9v032->subdev.entity, 1, &mt9v032->pad, 0);
9462550f 836
c02b211d 837 if (ret < 0)
9462550f 838 v4l2_ctrl_handler_free(&mt9v032->ctrls);
0f2ce168
DC		 839
840 return ret;
841}
842
843static int mt9v032_remove(struct i2c_client *client)
844{
845 struct v4l2_subdev *subdev = i2c_get_clientdata(client);
846 struct mt9v032 *mt9v032 = to_mt9v032(subdev);
847
9462550f 848 v4l2_ctrl_handler_free(&mt9v032->ctrls);
0f2ce168
DC		 849 v4l2_device_unregister_subdev(subdev);
850 media_entity_cleanup(&subdev->entity);
9462550f 851
0f2ce168
DC		 852 return 0;
853}
854
855static const struct i2c_device_id mt9v032_id[] = {
856 { "mt9v032", 0 },
857 { }
858};
859MODULE_DEVICE_TABLE(i2c, mt9v032_id);
860
861static struct i2c_driver mt9v032_driver = {
862 .driver = {
863 .name = "mt9v032",
864 },
865 .probe = mt9v032_probe,
866 .remove = mt9v032_remove,
867 .id_table = mt9v032_id,
868};
869
c6e8d86f 870module_i2c_driver(mt9v032_driver);
0f2ce168
DC		 871
872MODULE_DESCRIPTION("Aptina MT9V032 Camera driver");
873MODULE_AUTHOR("Laurent Pinchart <laurent.pinchart@ideasonboard.com>");
874MODULE_LICENSE("GPL");
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