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0f2ce168 DC |
1 | /* |
2 | * Driver for MT9V032 CMOS Image Sensor from Micron | |
3 | * | |
4 | * Copyright (C) 2010, Laurent Pinchart <laurent.pinchart@ideasonboard.com> | |
5 | * | |
6 | * Based on the MT9M001 driver, | |
7 | * | |
8 | * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de> | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License version 2 as | |
12 | * published by the Free Software Foundation. | |
13 | */ | |
14 | ||
3300a8fd | 15 | #include <linux/clk.h> |
0f2ce168 DC |
16 | #include <linux/delay.h> |
17 | #include <linux/i2c.h> | |
18 | #include <linux/log2.h> | |
19 | #include <linux/mutex.h> | |
20 | #include <linux/slab.h> | |
21 | #include <linux/videodev2.h> | |
22 | #include <linux/v4l2-mediabus.h> | |
7a707b89 | 23 | #include <linux/module.h> |
0f2ce168 DC |
24 | |
25 | #include <media/mt9v032.h> | |
26 | #include <media/v4l2-ctrls.h> | |
27 | #include <media/v4l2-device.h> | |
28 | #include <media/v4l2-subdev.h> | |
29 | ||
2b9e9f77 LP |
30 | /* The first four rows are black rows. The active area spans 753x481 pixels. */ |
31 | #define MT9V032_PIXEL_ARRAY_HEIGHT 485 | |
32 | #define MT9V032_PIXEL_ARRAY_WIDTH 753 | |
0f2ce168 | 33 | |
e9a50e4c LP |
34 | #define MT9V032_SYSCLK_FREQ_DEF 26600000 |
35 | ||
0f2ce168 DC |
36 | #define MT9V032_CHIP_VERSION 0x00 |
37 | #define MT9V032_CHIP_ID_REV1 0x1311 | |
38 | #define MT9V032_CHIP_ID_REV3 0x1313 | |
daecfebc | 39 | #define MT9V034_CHIP_ID_REV1 0X1324 |
86cf786c | 40 | #define MT9V032_COLUMN_START 0x01 |
0f2ce168 | 41 | #define MT9V032_COLUMN_START_MIN 1 |
86cf786c | 42 | #define MT9V032_COLUMN_START_DEF 1 |
0f2ce168 | 43 | #define MT9V032_COLUMN_START_MAX 752 |
86cf786c LP |
44 | #define MT9V032_ROW_START 0x02 |
45 | #define MT9V032_ROW_START_MIN 4 | |
46 | #define MT9V032_ROW_START_DEF 5 | |
47 | #define MT9V032_ROW_START_MAX 482 | |
0f2ce168 DC |
48 | #define MT9V032_WINDOW_HEIGHT 0x03 |
49 | #define MT9V032_WINDOW_HEIGHT_MIN 1 | |
50 | #define MT9V032_WINDOW_HEIGHT_DEF 480 | |
51 | #define MT9V032_WINDOW_HEIGHT_MAX 480 | |
52 | #define MT9V032_WINDOW_WIDTH 0x04 | |
53 | #define MT9V032_WINDOW_WIDTH_MIN 1 | |
54 | #define MT9V032_WINDOW_WIDTH_DEF 752 | |
55 | #define MT9V032_WINDOW_WIDTH_MAX 752 | |
56 | #define MT9V032_HORIZONTAL_BLANKING 0x05 | |
57 | #define MT9V032_HORIZONTAL_BLANKING_MIN 43 | |
daecfebc | 58 | #define MT9V034_HORIZONTAL_BLANKING_MIN 61 |
9ec670e2 | 59 | #define MT9V032_HORIZONTAL_BLANKING_DEF 94 |
0f2ce168 DC |
60 | #define MT9V032_HORIZONTAL_BLANKING_MAX 1023 |
61 | #define MT9V032_VERTICAL_BLANKING 0x06 | |
62 | #define MT9V032_VERTICAL_BLANKING_MIN 4 | |
daecfebc | 63 | #define MT9V034_VERTICAL_BLANKING_MIN 2 |
9ec670e2 | 64 | #define MT9V032_VERTICAL_BLANKING_DEF 45 |
0f2ce168 | 65 | #define MT9V032_VERTICAL_BLANKING_MAX 3000 |
daecfebc | 66 | #define MT9V034_VERTICAL_BLANKING_MAX 32288 |
0f2ce168 DC |
67 | #define MT9V032_CHIP_CONTROL 0x07 |
68 | #define MT9V032_CHIP_CONTROL_MASTER_MODE (1 << 3) | |
69 | #define MT9V032_CHIP_CONTROL_DOUT_ENABLE (1 << 7) | |
70 | #define MT9V032_CHIP_CONTROL_SEQUENTIAL (1 << 8) | |
71 | #define MT9V032_SHUTTER_WIDTH1 0x08 | |
72 | #define MT9V032_SHUTTER_WIDTH2 0x09 | |
73 | #define MT9V032_SHUTTER_WIDTH_CONTROL 0x0a | |
74 | #define MT9V032_TOTAL_SHUTTER_WIDTH 0x0b | |
75 | #define MT9V032_TOTAL_SHUTTER_WIDTH_MIN 1 | |
daecfebc | 76 | #define MT9V034_TOTAL_SHUTTER_WIDTH_MIN 0 |
0f2ce168 DC |
77 | #define MT9V032_TOTAL_SHUTTER_WIDTH_DEF 480 |
78 | #define MT9V032_TOTAL_SHUTTER_WIDTH_MAX 32767 | |
daecfebc | 79 | #define MT9V034_TOTAL_SHUTTER_WIDTH_MAX 32765 |
0f2ce168 DC |
80 | #define MT9V032_RESET 0x0c |
81 | #define MT9V032_READ_MODE 0x0d | |
82 | #define MT9V032_READ_MODE_ROW_BIN_MASK (3 << 0) | |
83 | #define MT9V032_READ_MODE_ROW_BIN_SHIFT 0 | |
84 | #define MT9V032_READ_MODE_COLUMN_BIN_MASK (3 << 2) | |
85 | #define MT9V032_READ_MODE_COLUMN_BIN_SHIFT 2 | |
86 | #define MT9V032_READ_MODE_ROW_FLIP (1 << 4) | |
87 | #define MT9V032_READ_MODE_COLUMN_FLIP (1 << 5) | |
88 | #define MT9V032_READ_MODE_DARK_COLUMNS (1 << 6) | |
89 | #define MT9V032_READ_MODE_DARK_ROWS (1 << 7) | |
90 | #define MT9V032_PIXEL_OPERATION_MODE 0x0f | |
daecfebc LP |
91 | #define MT9V034_PIXEL_OPERATION_MODE_HDR (1 << 0) |
92 | #define MT9V034_PIXEL_OPERATION_MODE_COLOR (1 << 1) | |
0f2ce168 DC |
93 | #define MT9V032_PIXEL_OPERATION_MODE_COLOR (1 << 2) |
94 | #define MT9V032_PIXEL_OPERATION_MODE_HDR (1 << 6) | |
95 | #define MT9V032_ANALOG_GAIN 0x35 | |
96 | #define MT9V032_ANALOG_GAIN_MIN 16 | |
97 | #define MT9V032_ANALOG_GAIN_DEF 16 | |
98 | #define MT9V032_ANALOG_GAIN_MAX 64 | |
99 | #define MT9V032_MAX_ANALOG_GAIN 0x36 | |
100 | #define MT9V032_MAX_ANALOG_GAIN_MAX 127 | |
101 | #define MT9V032_FRAME_DARK_AVERAGE 0x42 | |
102 | #define MT9V032_DARK_AVG_THRESH 0x46 | |
103 | #define MT9V032_DARK_AVG_LOW_THRESH_MASK (255 << 0) | |
104 | #define MT9V032_DARK_AVG_LOW_THRESH_SHIFT 0 | |
105 | #define MT9V032_DARK_AVG_HIGH_THRESH_MASK (255 << 8) | |
106 | #define MT9V032_DARK_AVG_HIGH_THRESH_SHIFT 8 | |
107 | #define MT9V032_ROW_NOISE_CORR_CONTROL 0x70 | |
daecfebc LP |
108 | #define MT9V034_ROW_NOISE_CORR_ENABLE (1 << 0) |
109 | #define MT9V034_ROW_NOISE_CORR_USE_BLK_AVG (1 << 1) | |
0f2ce168 DC |
110 | #define MT9V032_ROW_NOISE_CORR_ENABLE (1 << 5) |
111 | #define MT9V032_ROW_NOISE_CORR_USE_BLK_AVG (1 << 7) | |
112 | #define MT9V032_PIXEL_CLOCK 0x74 | |
daecfebc | 113 | #define MT9V034_PIXEL_CLOCK 0x72 |
0f2ce168 DC |
114 | #define MT9V032_PIXEL_CLOCK_INV_LINE (1 << 0) |
115 | #define MT9V032_PIXEL_CLOCK_INV_FRAME (1 << 1) | |
116 | #define MT9V032_PIXEL_CLOCK_XOR_LINE (1 << 2) | |
117 | #define MT9V032_PIXEL_CLOCK_CONT_LINE (1 << 3) | |
118 | #define MT9V032_PIXEL_CLOCK_INV_PXL_CLK (1 << 4) | |
119 | #define MT9V032_TEST_PATTERN 0x7f | |
120 | #define MT9V032_TEST_PATTERN_DATA_MASK (1023 << 0) | |
121 | #define MT9V032_TEST_PATTERN_DATA_SHIFT 0 | |
122 | #define MT9V032_TEST_PATTERN_USE_DATA (1 << 10) | |
123 | #define MT9V032_TEST_PATTERN_GRAY_MASK (3 << 11) | |
124 | #define MT9V032_TEST_PATTERN_GRAY_NONE (0 << 11) | |
125 | #define MT9V032_TEST_PATTERN_GRAY_VERTICAL (1 << 11) | |
126 | #define MT9V032_TEST_PATTERN_GRAY_HORIZONTAL (2 << 11) | |
127 | #define MT9V032_TEST_PATTERN_GRAY_DIAGONAL (3 << 11) | |
128 | #define MT9V032_TEST_PATTERN_ENABLE (1 << 13) | |
129 | #define MT9V032_TEST_PATTERN_FLIP (1 << 14) | |
130 | #define MT9V032_AEC_AGC_ENABLE 0xaf | |
131 | #define MT9V032_AEC_ENABLE (1 << 0) | |
132 | #define MT9V032_AGC_ENABLE (1 << 1) | |
133 | #define MT9V032_THERMAL_INFO 0xc1 | |
134 | ||
220ddc7f | 135 | enum mt9v032_model { |
daecfebc LP |
136 | MT9V032_MODEL_V032_COLOR, |
137 | MT9V032_MODEL_V032_MONO, | |
138 | MT9V032_MODEL_V034_COLOR, | |
139 | MT9V032_MODEL_V034_MONO, | |
220ddc7f LP |
140 | }; |
141 | ||
0a466b60 LP |
142 | struct mt9v032_model_version { |
143 | unsigned int version; | |
144 | const char *name; | |
145 | }; | |
146 | ||
147 | struct mt9v032_model_data { | |
148 | unsigned int min_row_time; | |
149 | unsigned int min_hblank; | |
150 | unsigned int min_vblank; | |
151 | unsigned int max_vblank; | |
152 | unsigned int min_shutter; | |
153 | unsigned int max_shutter; | |
154 | unsigned int pclk_reg; | |
155 | }; | |
156 | ||
220ddc7f | 157 | struct mt9v032_model_info { |
0a466b60 | 158 | const struct mt9v032_model_data *data; |
220ddc7f LP |
159 | bool color; |
160 | }; | |
161 | ||
0a466b60 LP |
162 | static const struct mt9v032_model_version mt9v032_versions[] = { |
163 | { MT9V032_CHIP_ID_REV1, "MT9V032 rev1/2" }, | |
164 | { MT9V032_CHIP_ID_REV3, "MT9V032 rev3" }, | |
daecfebc | 165 | { MT9V034_CHIP_ID_REV1, "MT9V034 rev1" }, |
0a466b60 LP |
166 | }; |
167 | ||
168 | static const struct mt9v032_model_data mt9v032_model_data[] = { | |
169 | { | |
170 | /* MT9V032 revisions 1/2/3 */ | |
171 | .min_row_time = 660, | |
172 | .min_hblank = MT9V032_HORIZONTAL_BLANKING_MIN, | |
173 | .min_vblank = MT9V032_VERTICAL_BLANKING_MIN, | |
174 | .max_vblank = MT9V032_VERTICAL_BLANKING_MAX, | |
175 | .min_shutter = MT9V032_TOTAL_SHUTTER_WIDTH_MIN, | |
176 | .max_shutter = MT9V032_TOTAL_SHUTTER_WIDTH_MAX, | |
177 | .pclk_reg = MT9V032_PIXEL_CLOCK, | |
daecfebc LP |
178 | }, { |
179 | /* MT9V034 */ | |
180 | .min_row_time = 690, | |
181 | .min_hblank = MT9V034_HORIZONTAL_BLANKING_MIN, | |
182 | .min_vblank = MT9V034_VERTICAL_BLANKING_MIN, | |
183 | .max_vblank = MT9V034_VERTICAL_BLANKING_MAX, | |
184 | .min_shutter = MT9V034_TOTAL_SHUTTER_WIDTH_MIN, | |
185 | .max_shutter = MT9V034_TOTAL_SHUTTER_WIDTH_MAX, | |
186 | .pclk_reg = MT9V034_PIXEL_CLOCK, | |
0a466b60 LP |
187 | }, |
188 | }; | |
189 | ||
220ddc7f | 190 | static const struct mt9v032_model_info mt9v032_models[] = { |
daecfebc | 191 | [MT9V032_MODEL_V032_COLOR] = { |
0a466b60 | 192 | .data = &mt9v032_model_data[0], |
220ddc7f LP |
193 | .color = true, |
194 | }, | |
daecfebc | 195 | [MT9V032_MODEL_V032_MONO] = { |
0a466b60 | 196 | .data = &mt9v032_model_data[0], |
220ddc7f LP |
197 | .color = false, |
198 | }, | |
daecfebc LP |
199 | [MT9V032_MODEL_V034_COLOR] = { |
200 | .data = &mt9v032_model_data[1], | |
201 | .color = true, | |
202 | }, | |
203 | [MT9V032_MODEL_V034_MONO] = { | |
204 | .data = &mt9v032_model_data[1], | |
205 | .color = false, | |
206 | }, | |
220ddc7f LP |
207 | }; |
208 | ||
0f2ce168 DC |
209 | struct mt9v032 { |
210 | struct v4l2_subdev subdev; | |
211 | struct media_pad pad; | |
212 | ||
213 | struct v4l2_mbus_framefmt format; | |
214 | struct v4l2_rect crop; | |
637f005e LP |
215 | unsigned int hratio; |
216 | unsigned int vratio; | |
0f2ce168 DC |
217 | |
218 | struct v4l2_ctrl_handler ctrls; | |
e9a50e4c LP |
219 | struct { |
220 | struct v4l2_ctrl *link_freq; | |
221 | struct v4l2_ctrl *pixel_rate; | |
222 | }; | |
0f2ce168 DC |
223 | |
224 | struct mutex power_lock; | |
225 | int power_count; | |
226 | ||
3300a8fd LP |
227 | struct clk *clk; |
228 | ||
0f2ce168 | 229 | struct mt9v032_platform_data *pdata; |
220ddc7f | 230 | const struct mt9v032_model_info *model; |
0a466b60 | 231 | const struct mt9v032_model_version *version; |
e9a50e4c LP |
232 | |
233 | u32 sysclk; | |
0f2ce168 DC |
234 | u16 chip_control; |
235 | u16 aec_agc; | |
9ec670e2 | 236 | u16 hblank; |
b28d7017 LP |
237 | struct { |
238 | struct v4l2_ctrl *test_pattern; | |
239 | struct v4l2_ctrl *test_pattern_color; | |
240 | }; | |
0f2ce168 DC |
241 | }; |
242 | ||
243 | static struct mt9v032 *to_mt9v032(struct v4l2_subdev *sd) | |
244 | { | |
245 | return container_of(sd, struct mt9v032, subdev); | |
246 | } | |
247 | ||
248 | static int mt9v032_read(struct i2c_client *client, const u8 reg) | |
249 | { | |
3f877045 | 250 | s32 data = i2c_smbus_read_word_swapped(client, reg); |
0f2ce168 | 251 | dev_dbg(&client->dev, "%s: read 0x%04x from 0x%02x\n", __func__, |
3f877045 JC |
252 | data, reg); |
253 | return data; | |
0f2ce168 DC |
254 | } |
255 | ||
256 | static int mt9v032_write(struct i2c_client *client, const u8 reg, | |
257 | const u16 data) | |
258 | { | |
259 | dev_dbg(&client->dev, "%s: writing 0x%04x to 0x%02x\n", __func__, | |
260 | data, reg); | |
3f877045 | 261 | return i2c_smbus_write_word_swapped(client, reg, data); |
0f2ce168 DC |
262 | } |
263 | ||
264 | static int mt9v032_set_chip_control(struct mt9v032 *mt9v032, u16 clear, u16 set) | |
265 | { | |
266 | struct i2c_client *client = v4l2_get_subdevdata(&mt9v032->subdev); | |
267 | u16 value = (mt9v032->chip_control & ~clear) | set; | |
268 | int ret; | |
269 | ||
270 | ret = mt9v032_write(client, MT9V032_CHIP_CONTROL, value); | |
271 | if (ret < 0) | |
272 | return ret; | |
273 | ||
274 | mt9v032->chip_control = value; | |
275 | return 0; | |
276 | } | |
277 | ||
278 | static int | |
279 | mt9v032_update_aec_agc(struct mt9v032 *mt9v032, u16 which, int enable) | |
280 | { | |
281 | struct i2c_client *client = v4l2_get_subdevdata(&mt9v032->subdev); | |
282 | u16 value = mt9v032->aec_agc; | |
283 | int ret; | |
284 | ||
285 | if (enable) | |
286 | value |= which; | |
287 | else | |
288 | value &= ~which; | |
289 | ||
290 | ret = mt9v032_write(client, MT9V032_AEC_AGC_ENABLE, value); | |
291 | if (ret < 0) | |
292 | return ret; | |
293 | ||
294 | mt9v032->aec_agc = value; | |
295 | return 0; | |
296 | } | |
297 | ||
9ec670e2 LP |
298 | static int |
299 | mt9v032_update_hblank(struct mt9v032 *mt9v032) | |
300 | { | |
301 | struct i2c_client *client = v4l2_get_subdevdata(&mt9v032->subdev); | |
302 | struct v4l2_rect *crop = &mt9v032->crop; | |
daecfebc | 303 | unsigned int min_hblank = mt9v032->model->data->min_hblank; |
0a466b60 | 304 | unsigned int hblank; |
9ec670e2 | 305 | |
daecfebc LP |
306 | if (mt9v032->version->version == MT9V034_CHIP_ID_REV1) |
307 | min_hblank += (mt9v032->hratio - 1) * 10; | |
f90580ca RRD |
308 | min_hblank = max_t(unsigned int, (int)mt9v032->model->data->min_row_time - crop->width, |
309 | (int)min_hblank); | |
daecfebc LP |
310 | hblank = max_t(unsigned int, mt9v032->hblank, min_hblank); |
311 | ||
0a466b60 | 312 | return mt9v032_write(client, MT9V032_HORIZONTAL_BLANKING, hblank); |
9ec670e2 LP |
313 | } |
314 | ||
0f2ce168 DC |
315 | static int mt9v032_power_on(struct mt9v032 *mt9v032) |
316 | { | |
317 | struct i2c_client *client = v4l2_get_subdevdata(&mt9v032->subdev); | |
318 | int ret; | |
319 | ||
79019190 LP |
320 | ret = clk_set_rate(mt9v032->clk, mt9v032->sysclk); |
321 | if (ret < 0) | |
322 | return ret; | |
323 | ||
324 | ret = clk_prepare_enable(mt9v032->clk); | |
325 | if (ret) | |
326 | return ret; | |
327 | ||
3300a8fd | 328 | udelay(1); |
0f2ce168 DC |
329 | |
330 | /* Reset the chip and stop data read out */ | |
331 | ret = mt9v032_write(client, MT9V032_RESET, 1); | |
332 | if (ret < 0) | |
333 | return ret; | |
334 | ||
335 | ret = mt9v032_write(client, MT9V032_RESET, 0); | |
336 | if (ret < 0) | |
337 | return ret; | |
338 | ||
339 | return mt9v032_write(client, MT9V032_CHIP_CONTROL, 0); | |
340 | } | |
341 | ||
342 | static void mt9v032_power_off(struct mt9v032 *mt9v032) | |
343 | { | |
3300a8fd | 344 | clk_disable_unprepare(mt9v032->clk); |
0f2ce168 DC |
345 | } |
346 | ||
347 | static int __mt9v032_set_power(struct mt9v032 *mt9v032, bool on) | |
348 | { | |
349 | struct i2c_client *client = v4l2_get_subdevdata(&mt9v032->subdev); | |
350 | int ret; | |
351 | ||
352 | if (!on) { | |
353 | mt9v032_power_off(mt9v032); | |
354 | return 0; | |
355 | } | |
356 | ||
357 | ret = mt9v032_power_on(mt9v032); | |
358 | if (ret < 0) | |
359 | return ret; | |
360 | ||
361 | /* Configure the pixel clock polarity */ | |
362 | if (mt9v032->pdata && mt9v032->pdata->clk_pol) { | |
0a466b60 | 363 | ret = mt9v032_write(client, mt9v032->model->data->pclk_reg, |
0f2ce168 DC |
364 | MT9V032_PIXEL_CLOCK_INV_PXL_CLK); |
365 | if (ret < 0) | |
366 | return ret; | |
367 | } | |
368 | ||
369 | /* Disable the noise correction algorithm and restore the controls. */ | |
370 | ret = mt9v032_write(client, MT9V032_ROW_NOISE_CORR_CONTROL, 0); | |
371 | if (ret < 0) | |
372 | return ret; | |
373 | ||
374 | return v4l2_ctrl_handler_setup(&mt9v032->ctrls); | |
375 | } | |
376 | ||
377 | /* ----------------------------------------------------------------------------- | |
378 | * V4L2 subdev video operations | |
379 | */ | |
380 | ||
381 | static struct v4l2_mbus_framefmt * | |
382 | __mt9v032_get_pad_format(struct mt9v032 *mt9v032, struct v4l2_subdev_fh *fh, | |
383 | unsigned int pad, enum v4l2_subdev_format_whence which) | |
384 | { | |
385 | switch (which) { | |
386 | case V4L2_SUBDEV_FORMAT_TRY: | |
387 | return v4l2_subdev_get_try_format(fh, pad); | |
388 | case V4L2_SUBDEV_FORMAT_ACTIVE: | |
389 | return &mt9v032->format; | |
390 | default: | |
391 | return NULL; | |
392 | } | |
393 | } | |
394 | ||
395 | static struct v4l2_rect * | |
396 | __mt9v032_get_pad_crop(struct mt9v032 *mt9v032, struct v4l2_subdev_fh *fh, | |
397 | unsigned int pad, enum v4l2_subdev_format_whence which) | |
398 | { | |
399 | switch (which) { | |
400 | case V4L2_SUBDEV_FORMAT_TRY: | |
401 | return v4l2_subdev_get_try_crop(fh, pad); | |
402 | case V4L2_SUBDEV_FORMAT_ACTIVE: | |
403 | return &mt9v032->crop; | |
404 | default: | |
405 | return NULL; | |
406 | } | |
407 | } | |
408 | ||
409 | static int mt9v032_s_stream(struct v4l2_subdev *subdev, int enable) | |
410 | { | |
411 | const u16 mode = MT9V032_CHIP_CONTROL_MASTER_MODE | |
412 | | MT9V032_CHIP_CONTROL_DOUT_ENABLE | |
413 | | MT9V032_CHIP_CONTROL_SEQUENTIAL; | |
414 | struct i2c_client *client = v4l2_get_subdevdata(subdev); | |
415 | struct mt9v032 *mt9v032 = to_mt9v032(subdev); | |
0f2ce168 | 416 | struct v4l2_rect *crop = &mt9v032->crop; |
637f005e LP |
417 | unsigned int hbin; |
418 | unsigned int vbin; | |
0f2ce168 DC |
419 | int ret; |
420 | ||
421 | if (!enable) | |
422 | return mt9v032_set_chip_control(mt9v032, mode, 0); | |
423 | ||
424 | /* Configure the window size and row/column bin */ | |
637f005e LP |
425 | hbin = fls(mt9v032->hratio) - 1; |
426 | vbin = fls(mt9v032->vratio) - 1; | |
0f2ce168 | 427 | ret = mt9v032_write(client, MT9V032_READ_MODE, |
637f005e LP |
428 | hbin << MT9V032_READ_MODE_COLUMN_BIN_SHIFT | |
429 | vbin << MT9V032_READ_MODE_ROW_BIN_SHIFT); | |
0f2ce168 DC |
430 | if (ret < 0) |
431 | return ret; | |
432 | ||
433 | ret = mt9v032_write(client, MT9V032_COLUMN_START, crop->left); | |
434 | if (ret < 0) | |
435 | return ret; | |
436 | ||
437 | ret = mt9v032_write(client, MT9V032_ROW_START, crop->top); | |
438 | if (ret < 0) | |
439 | return ret; | |
440 | ||
441 | ret = mt9v032_write(client, MT9V032_WINDOW_WIDTH, crop->width); | |
442 | if (ret < 0) | |
443 | return ret; | |
444 | ||
445 | ret = mt9v032_write(client, MT9V032_WINDOW_HEIGHT, crop->height); | |
446 | if (ret < 0) | |
447 | return ret; | |
448 | ||
9ec670e2 | 449 | ret = mt9v032_update_hblank(mt9v032); |
0f2ce168 DC |
450 | if (ret < 0) |
451 | return ret; | |
452 | ||
453 | /* Switch to master "normal" mode */ | |
454 | return mt9v032_set_chip_control(mt9v032, 0, mode); | |
455 | } | |
456 | ||
457 | static int mt9v032_enum_mbus_code(struct v4l2_subdev *subdev, | |
458 | struct v4l2_subdev_fh *fh, | |
459 | struct v4l2_subdev_mbus_code_enum *code) | |
460 | { | |
461 | if (code->index > 0) | |
462 | return -EINVAL; | |
463 | ||
464 | code->code = V4L2_MBUS_FMT_SGRBG10_1X10; | |
465 | return 0; | |
466 | } | |
467 | ||
468 | static int mt9v032_enum_frame_size(struct v4l2_subdev *subdev, | |
469 | struct v4l2_subdev_fh *fh, | |
470 | struct v4l2_subdev_frame_size_enum *fse) | |
471 | { | |
637f005e | 472 | if (fse->index >= 3 || fse->code != V4L2_MBUS_FMT_SGRBG10_1X10) |
0f2ce168 DC |
473 | return -EINVAL; |
474 | ||
637f005e | 475 | fse->min_width = MT9V032_WINDOW_WIDTH_DEF / (1 << fse->index); |
0f2ce168 | 476 | fse->max_width = fse->min_width; |
637f005e | 477 | fse->min_height = MT9V032_WINDOW_HEIGHT_DEF / (1 << fse->index); |
0f2ce168 DC |
478 | fse->max_height = fse->min_height; |
479 | ||
480 | return 0; | |
481 | } | |
482 | ||
483 | static int mt9v032_get_format(struct v4l2_subdev *subdev, | |
484 | struct v4l2_subdev_fh *fh, | |
485 | struct v4l2_subdev_format *format) | |
486 | { | |
487 | struct mt9v032 *mt9v032 = to_mt9v032(subdev); | |
488 | ||
489 | format->format = *__mt9v032_get_pad_format(mt9v032, fh, format->pad, | |
490 | format->which); | |
491 | return 0; | |
492 | } | |
493 | ||
637f005e | 494 | static void mt9v032_configure_pixel_rate(struct mt9v032 *mt9v032) |
41a33a00 SA |
495 | { |
496 | struct i2c_client *client = v4l2_get_subdevdata(&mt9v032->subdev); | |
497 | int ret; | |
498 | ||
e9a50e4c | 499 | ret = v4l2_ctrl_s_ctrl_int64(mt9v032->pixel_rate, |
637f005e | 500 | mt9v032->sysclk / mt9v032->hratio); |
41a33a00 SA |
501 | if (ret < 0) |
502 | dev_warn(&client->dev, "failed to set pixel rate (%d)\n", ret); | |
503 | } | |
504 | ||
637f005e LP |
505 | static unsigned int mt9v032_calc_ratio(unsigned int input, unsigned int output) |
506 | { | |
507 | /* Compute the power-of-two binning factor closest to the input size to | |
508 | * output size ratio. Given that the output size is bounded by input/4 | |
509 | * and input, a generic implementation would be an ineffective luxury. | |
510 | */ | |
511 | if (output * 3 > input * 2) | |
512 | return 1; | |
513 | if (output * 3 > input) | |
514 | return 2; | |
515 | return 4; | |
516 | } | |
517 | ||
0f2ce168 DC |
518 | static int mt9v032_set_format(struct v4l2_subdev *subdev, |
519 | struct v4l2_subdev_fh *fh, | |
520 | struct v4l2_subdev_format *format) | |
521 | { | |
522 | struct mt9v032 *mt9v032 = to_mt9v032(subdev); | |
523 | struct v4l2_mbus_framefmt *__format; | |
524 | struct v4l2_rect *__crop; | |
525 | unsigned int width; | |
526 | unsigned int height; | |
527 | unsigned int hratio; | |
528 | unsigned int vratio; | |
529 | ||
530 | __crop = __mt9v032_get_pad_crop(mt9v032, fh, format->pad, | |
531 | format->which); | |
532 | ||
533 | /* Clamp the width and height to avoid dividing by zero. */ | |
f90580ca RRD |
534 | width = clamp(ALIGN(format->format.width, 2), |
535 | max_t(unsigned int, __crop->width / 4, | |
536 | MT9V032_WINDOW_WIDTH_MIN), | |
537 | __crop->width); | |
538 | height = clamp(ALIGN(format->format.height, 2), | |
539 | max_t(unsigned int, __crop->height / 4, | |
540 | MT9V032_WINDOW_HEIGHT_MIN), | |
541 | __crop->height); | |
0f2ce168 | 542 | |
637f005e LP |
543 | hratio = mt9v032_calc_ratio(__crop->width, width); |
544 | vratio = mt9v032_calc_ratio(__crop->height, height); | |
0f2ce168 DC |
545 | |
546 | __format = __mt9v032_get_pad_format(mt9v032, fh, format->pad, | |
547 | format->which); | |
548 | __format->width = __crop->width / hratio; | |
549 | __format->height = __crop->height / vratio; | |
637f005e LP |
550 | |
551 | if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE) { | |
552 | mt9v032->hratio = hratio; | |
553 | mt9v032->vratio = vratio; | |
554 | mt9v032_configure_pixel_rate(mt9v032); | |
555 | } | |
0f2ce168 DC |
556 | |
557 | format->format = *__format; | |
558 | ||
559 | return 0; | |
560 | } | |
561 | ||
562 | static int mt9v032_get_crop(struct v4l2_subdev *subdev, | |
563 | struct v4l2_subdev_fh *fh, | |
564 | struct v4l2_subdev_crop *crop) | |
565 | { | |
566 | struct mt9v032 *mt9v032 = to_mt9v032(subdev); | |
567 | ||
568 | crop->rect = *__mt9v032_get_pad_crop(mt9v032, fh, crop->pad, | |
569 | crop->which); | |
570 | return 0; | |
571 | } | |
572 | ||
573 | static int mt9v032_set_crop(struct v4l2_subdev *subdev, | |
574 | struct v4l2_subdev_fh *fh, | |
575 | struct v4l2_subdev_crop *crop) | |
576 | { | |
577 | struct mt9v032 *mt9v032 = to_mt9v032(subdev); | |
578 | struct v4l2_mbus_framefmt *__format; | |
579 | struct v4l2_rect *__crop; | |
580 | struct v4l2_rect rect; | |
581 | ||
86cf786c LP |
582 | /* Clamp the crop rectangle boundaries and align them to a non multiple |
583 | * of 2 pixels to ensure a GRBG Bayer pattern. | |
0f2ce168 | 584 | */ |
86cf786c | 585 | rect.left = clamp(ALIGN(crop->rect.left + 1, 2) - 1, |
0f2ce168 DC |
586 | MT9V032_COLUMN_START_MIN, |
587 | MT9V032_COLUMN_START_MAX); | |
86cf786c | 588 | rect.top = clamp(ALIGN(crop->rect.top + 1, 2) - 1, |
0f2ce168 DC |
589 | MT9V032_ROW_START_MIN, |
590 | MT9V032_ROW_START_MAX); | |
f90580ca RRD |
591 | rect.width = clamp_t(unsigned int, ALIGN(crop->rect.width, 2), |
592 | MT9V032_WINDOW_WIDTH_MIN, | |
593 | MT9V032_WINDOW_WIDTH_MAX); | |
594 | rect.height = clamp_t(unsigned int, ALIGN(crop->rect.height, 2), | |
595 | MT9V032_WINDOW_HEIGHT_MIN, | |
596 | MT9V032_WINDOW_HEIGHT_MAX); | |
597 | ||
598 | rect.width = min_t(unsigned int, | |
599 | rect.width, MT9V032_PIXEL_ARRAY_WIDTH - rect.left); | |
600 | rect.height = min_t(unsigned int, | |
601 | rect.height, MT9V032_PIXEL_ARRAY_HEIGHT - rect.top); | |
0f2ce168 DC |
602 | |
603 | __crop = __mt9v032_get_pad_crop(mt9v032, fh, crop->pad, crop->which); | |
604 | ||
605 | if (rect.width != __crop->width || rect.height != __crop->height) { | |
606 | /* Reset the output image size if the crop rectangle size has | |
607 | * been modified. | |
608 | */ | |
609 | __format = __mt9v032_get_pad_format(mt9v032, fh, crop->pad, | |
610 | crop->which); | |
611 | __format->width = rect.width; | |
612 | __format->height = rect.height; | |
637f005e LP |
613 | if (crop->which == V4L2_SUBDEV_FORMAT_ACTIVE) { |
614 | mt9v032->hratio = 1; | |
615 | mt9v032->vratio = 1; | |
616 | mt9v032_configure_pixel_rate(mt9v032); | |
617 | } | |
0f2ce168 DC |
618 | } |
619 | ||
620 | *__crop = rect; | |
621 | crop->rect = rect; | |
622 | ||
623 | return 0; | |
624 | } | |
625 | ||
626 | /* ----------------------------------------------------------------------------- | |
627 | * V4L2 subdev control operations | |
628 | */ | |
629 | ||
b28d7017 | 630 | #define V4L2_CID_TEST_PATTERN_COLOR (V4L2_CID_USER_BASE | 0x1001) |
0f2ce168 DC |
631 | |
632 | static int mt9v032_s_ctrl(struct v4l2_ctrl *ctrl) | |
633 | { | |
634 | struct mt9v032 *mt9v032 = | |
635 | container_of(ctrl->handler, struct mt9v032, ctrls); | |
636 | struct i2c_client *client = v4l2_get_subdevdata(&mt9v032->subdev); | |
e9a50e4c | 637 | u32 freq; |
0f2ce168 DC |
638 | u16 data; |
639 | ||
640 | switch (ctrl->id) { | |
641 | case V4L2_CID_AUTOGAIN: | |
642 | return mt9v032_update_aec_agc(mt9v032, MT9V032_AGC_ENABLE, | |
643 | ctrl->val); | |
644 | ||
645 | case V4L2_CID_GAIN: | |
646 | return mt9v032_write(client, MT9V032_ANALOG_GAIN, ctrl->val); | |
647 | ||
648 | case V4L2_CID_EXPOSURE_AUTO: | |
649 | return mt9v032_update_aec_agc(mt9v032, MT9V032_AEC_ENABLE, | |
5c375981 | 650 | !ctrl->val); |
0f2ce168 DC |
651 | |
652 | case V4L2_CID_EXPOSURE: | |
653 | return mt9v032_write(client, MT9V032_TOTAL_SHUTTER_WIDTH, | |
654 | ctrl->val); | |
655 | ||
9ec670e2 LP |
656 | case V4L2_CID_HBLANK: |
657 | mt9v032->hblank = ctrl->val; | |
658 | return mt9v032_update_hblank(mt9v032); | |
659 | ||
660 | case V4L2_CID_VBLANK: | |
661 | return mt9v032_write(client, MT9V032_VERTICAL_BLANKING, | |
662 | ctrl->val); | |
663 | ||
e9a50e4c LP |
664 | case V4L2_CID_PIXEL_RATE: |
665 | case V4L2_CID_LINK_FREQ: | |
666 | if (mt9v032->link_freq == NULL) | |
667 | break; | |
668 | ||
669 | freq = mt9v032->pdata->link_freqs[mt9v032->link_freq->val]; | |
670 | mt9v032->pixel_rate->val64 = freq; | |
671 | mt9v032->sysclk = freq; | |
672 | break; | |
673 | ||
0f2ce168 | 674 | case V4L2_CID_TEST_PATTERN: |
b28d7017 | 675 | switch (mt9v032->test_pattern->val) { |
0f2ce168 DC |
676 | case 0: |
677 | data = 0; | |
678 | break; | |
679 | case 1: | |
680 | data = MT9V032_TEST_PATTERN_GRAY_VERTICAL | |
681 | | MT9V032_TEST_PATTERN_ENABLE; | |
682 | break; | |
683 | case 2: | |
684 | data = MT9V032_TEST_PATTERN_GRAY_HORIZONTAL | |
685 | | MT9V032_TEST_PATTERN_ENABLE; | |
686 | break; | |
687 | case 3: | |
688 | data = MT9V032_TEST_PATTERN_GRAY_DIAGONAL | |
689 | | MT9V032_TEST_PATTERN_ENABLE; | |
690 | break; | |
691 | default: | |
b28d7017 LP |
692 | data = (mt9v032->test_pattern_color->val << |
693 | MT9V032_TEST_PATTERN_DATA_SHIFT) | |
0f2ce168 DC |
694 | | MT9V032_TEST_PATTERN_USE_DATA |
695 | | MT9V032_TEST_PATTERN_ENABLE | |
696 | | MT9V032_TEST_PATTERN_FLIP; | |
697 | break; | |
698 | } | |
0f2ce168 DC |
699 | return mt9v032_write(client, MT9V032_TEST_PATTERN, data); |
700 | } | |
701 | ||
702 | return 0; | |
703 | } | |
704 | ||
705 | static struct v4l2_ctrl_ops mt9v032_ctrl_ops = { | |
706 | .s_ctrl = mt9v032_s_ctrl, | |
707 | }; | |
708 | ||
b28d7017 LP |
709 | static const char * const mt9v032_test_pattern_menu[] = { |
710 | "Disabled", | |
711 | "Gray Vertical Shade", | |
712 | "Gray Horizontal Shade", | |
713 | "Gray Diagonal Shade", | |
714 | "Plain", | |
715 | }; | |
716 | ||
717 | static const struct v4l2_ctrl_config mt9v032_test_pattern_color = { | |
718 | .ops = &mt9v032_ctrl_ops, | |
719 | .id = V4L2_CID_TEST_PATTERN_COLOR, | |
720 | .type = V4L2_CTRL_TYPE_INTEGER, | |
721 | .name = "Test Pattern Color", | |
722 | .min = 0, | |
723 | .max = 1023, | |
724 | .step = 1, | |
725 | .def = 0, | |
726 | .flags = 0, | |
0f2ce168 DC |
727 | }; |
728 | ||
729 | /* ----------------------------------------------------------------------------- | |
730 | * V4L2 subdev core operations | |
731 | */ | |
732 | ||
733 | static int mt9v032_set_power(struct v4l2_subdev *subdev, int on) | |
734 | { | |
735 | struct mt9v032 *mt9v032 = to_mt9v032(subdev); | |
736 | int ret = 0; | |
737 | ||
738 | mutex_lock(&mt9v032->power_lock); | |
739 | ||
740 | /* If the power count is modified from 0 to != 0 or from != 0 to 0, | |
741 | * update the power state. | |
742 | */ | |
743 | if (mt9v032->power_count == !on) { | |
744 | ret = __mt9v032_set_power(mt9v032, !!on); | |
745 | if (ret < 0) | |
746 | goto done; | |
747 | } | |
748 | ||
749 | /* Update the power count. */ | |
750 | mt9v032->power_count += on ? 1 : -1; | |
751 | WARN_ON(mt9v032->power_count < 0); | |
752 | ||
753 | done: | |
754 | mutex_unlock(&mt9v032->power_lock); | |
755 | return ret; | |
756 | } | |
757 | ||
758 | /* ----------------------------------------------------------------------------- | |
759 | * V4L2 subdev internal operations | |
760 | */ | |
761 | ||
762 | static int mt9v032_registered(struct v4l2_subdev *subdev) | |
763 | { | |
764 | struct i2c_client *client = v4l2_get_subdevdata(subdev); | |
765 | struct mt9v032 *mt9v032 = to_mt9v032(subdev); | |
0a466b60 LP |
766 | unsigned int i; |
767 | s32 version; | |
0f2ce168 DC |
768 | int ret; |
769 | ||
770 | dev_info(&client->dev, "Probing MT9V032 at address 0x%02x\n", | |
771 | client->addr); | |
772 | ||
773 | ret = mt9v032_power_on(mt9v032); | |
774 | if (ret < 0) { | |
775 | dev_err(&client->dev, "MT9V032 power up failed\n"); | |
776 | return ret; | |
777 | } | |
778 | ||
779 | /* Read and check the sensor version */ | |
0a466b60 LP |
780 | version = mt9v032_read(client, MT9V032_CHIP_VERSION); |
781 | if (version < 0) { | |
782 | dev_err(&client->dev, "Failed reading chip version\n"); | |
783 | return version; | |
784 | } | |
785 | ||
786 | for (i = 0; i < ARRAY_SIZE(mt9v032_versions); ++i) { | |
787 | if (mt9v032_versions[i].version == version) { | |
788 | mt9v032->version = &mt9v032_versions[i]; | |
789 | break; | |
790 | } | |
791 | } | |
792 | ||
793 | if (mt9v032->version == NULL) { | |
794 | dev_err(&client->dev, "Unsupported chip version 0x%04x\n", | |
795 | version); | |
0f2ce168 DC |
796 | return -ENODEV; |
797 | } | |
798 | ||
799 | mt9v032_power_off(mt9v032); | |
800 | ||
0a466b60 LP |
801 | dev_info(&client->dev, "%s detected at address 0x%02x\n", |
802 | mt9v032->version->name, client->addr); | |
0f2ce168 | 803 | |
637f005e | 804 | mt9v032_configure_pixel_rate(mt9v032); |
41a33a00 | 805 | |
0f2ce168 DC |
806 | return ret; |
807 | } | |
808 | ||
809 | static int mt9v032_open(struct v4l2_subdev *subdev, struct v4l2_subdev_fh *fh) | |
810 | { | |
220ddc7f | 811 | struct mt9v032 *mt9v032 = to_mt9v032(subdev); |
0f2ce168 DC |
812 | struct v4l2_mbus_framefmt *format; |
813 | struct v4l2_rect *crop; | |
814 | ||
815 | crop = v4l2_subdev_get_try_crop(fh, 0); | |
816 | crop->left = MT9V032_COLUMN_START_DEF; | |
817 | crop->top = MT9V032_ROW_START_DEF; | |
818 | crop->width = MT9V032_WINDOW_WIDTH_DEF; | |
819 | crop->height = MT9V032_WINDOW_HEIGHT_DEF; | |
820 | ||
821 | format = v4l2_subdev_get_try_format(fh, 0); | |
220ddc7f LP |
822 | |
823 | if (mt9v032->model->color) | |
824 | format->code = V4L2_MBUS_FMT_SGRBG10_1X10; | |
825 | else | |
826 | format->code = V4L2_MBUS_FMT_Y10_1X10; | |
827 | ||
0f2ce168 DC |
828 | format->width = MT9V032_WINDOW_WIDTH_DEF; |
829 | format->height = MT9V032_WINDOW_HEIGHT_DEF; | |
830 | format->field = V4L2_FIELD_NONE; | |
831 | format->colorspace = V4L2_COLORSPACE_SRGB; | |
832 | ||
833 | return mt9v032_set_power(subdev, 1); | |
834 | } | |
835 | ||
836 | static int mt9v032_close(struct v4l2_subdev *subdev, struct v4l2_subdev_fh *fh) | |
837 | { | |
838 | return mt9v032_set_power(subdev, 0); | |
839 | } | |
840 | ||
841 | static struct v4l2_subdev_core_ops mt9v032_subdev_core_ops = { | |
842 | .s_power = mt9v032_set_power, | |
843 | }; | |
844 | ||
845 | static struct v4l2_subdev_video_ops mt9v032_subdev_video_ops = { | |
846 | .s_stream = mt9v032_s_stream, | |
847 | }; | |
848 | ||
849 | static struct v4l2_subdev_pad_ops mt9v032_subdev_pad_ops = { | |
850 | .enum_mbus_code = mt9v032_enum_mbus_code, | |
851 | .enum_frame_size = mt9v032_enum_frame_size, | |
852 | .get_fmt = mt9v032_get_format, | |
853 | .set_fmt = mt9v032_set_format, | |
854 | .get_crop = mt9v032_get_crop, | |
855 | .set_crop = mt9v032_set_crop, | |
856 | }; | |
857 | ||
858 | static struct v4l2_subdev_ops mt9v032_subdev_ops = { | |
859 | .core = &mt9v032_subdev_core_ops, | |
860 | .video = &mt9v032_subdev_video_ops, | |
861 | .pad = &mt9v032_subdev_pad_ops, | |
862 | }; | |
863 | ||
864 | static const struct v4l2_subdev_internal_ops mt9v032_subdev_internal_ops = { | |
865 | .registered = mt9v032_registered, | |
866 | .open = mt9v032_open, | |
867 | .close = mt9v032_close, | |
868 | }; | |
869 | ||
870 | /* ----------------------------------------------------------------------------- | |
871 | * Driver initialization and probing | |
872 | */ | |
873 | ||
874 | static int mt9v032_probe(struct i2c_client *client, | |
875 | const struct i2c_device_id *did) | |
876 | { | |
e9a50e4c | 877 | struct mt9v032_platform_data *pdata = client->dev.platform_data; |
0f2ce168 DC |
878 | struct mt9v032 *mt9v032; |
879 | unsigned int i; | |
880 | int ret; | |
881 | ||
882 | if (!i2c_check_functionality(client->adapter, | |
883 | I2C_FUNC_SMBUS_WORD_DATA)) { | |
884 | dev_warn(&client->adapter->dev, | |
885 | "I2C-Adapter doesn't support I2C_FUNC_SMBUS_WORD\n"); | |
886 | return -EIO; | |
887 | } | |
888 | ||
c02b211d | 889 | mt9v032 = devm_kzalloc(&client->dev, sizeof(*mt9v032), GFP_KERNEL); |
0f2ce168 DC |
890 | if (!mt9v032) |
891 | return -ENOMEM; | |
892 | ||
3300a8fd LP |
893 | mt9v032->clk = devm_clk_get(&client->dev, NULL); |
894 | if (IS_ERR(mt9v032->clk)) | |
895 | return PTR_ERR(mt9v032->clk); | |
896 | ||
0f2ce168 | 897 | mutex_init(&mt9v032->power_lock); |
e9a50e4c | 898 | mt9v032->pdata = pdata; |
220ddc7f | 899 | mt9v032->model = (const void *)did->driver_data; |
0f2ce168 | 900 | |
b28d7017 | 901 | v4l2_ctrl_handler_init(&mt9v032->ctrls, 10); |
0f2ce168 DC |
902 | |
903 | v4l2_ctrl_new_std(&mt9v032->ctrls, &mt9v032_ctrl_ops, | |
904 | V4L2_CID_AUTOGAIN, 0, 1, 1, 1); | |
905 | v4l2_ctrl_new_std(&mt9v032->ctrls, &mt9v032_ctrl_ops, | |
906 | V4L2_CID_GAIN, MT9V032_ANALOG_GAIN_MIN, | |
907 | MT9V032_ANALOG_GAIN_MAX, 1, MT9V032_ANALOG_GAIN_DEF); | |
908 | v4l2_ctrl_new_std_menu(&mt9v032->ctrls, &mt9v032_ctrl_ops, | |
909 | V4L2_CID_EXPOSURE_AUTO, V4L2_EXPOSURE_MANUAL, 0, | |
910 | V4L2_EXPOSURE_AUTO); | |
911 | v4l2_ctrl_new_std(&mt9v032->ctrls, &mt9v032_ctrl_ops, | |
0a466b60 LP |
912 | V4L2_CID_EXPOSURE, mt9v032->model->data->min_shutter, |
913 | mt9v032->model->data->max_shutter, 1, | |
0f2ce168 | 914 | MT9V032_TOTAL_SHUTTER_WIDTH_DEF); |
9ec670e2 | 915 | v4l2_ctrl_new_std(&mt9v032->ctrls, &mt9v032_ctrl_ops, |
0a466b60 | 916 | V4L2_CID_HBLANK, mt9v032->model->data->min_hblank, |
9ec670e2 LP |
917 | MT9V032_HORIZONTAL_BLANKING_MAX, 1, |
918 | MT9V032_HORIZONTAL_BLANKING_DEF); | |
919 | v4l2_ctrl_new_std(&mt9v032->ctrls, &mt9v032_ctrl_ops, | |
0a466b60 LP |
920 | V4L2_CID_VBLANK, mt9v032->model->data->min_vblank, |
921 | mt9v032->model->data->max_vblank, 1, | |
9ec670e2 | 922 | MT9V032_VERTICAL_BLANKING_DEF); |
b28d7017 LP |
923 | mt9v032->test_pattern = v4l2_ctrl_new_std_menu_items(&mt9v032->ctrls, |
924 | &mt9v032_ctrl_ops, V4L2_CID_TEST_PATTERN, | |
925 | ARRAY_SIZE(mt9v032_test_pattern_menu) - 1, 0, 0, | |
926 | mt9v032_test_pattern_menu); | |
927 | mt9v032->test_pattern_color = v4l2_ctrl_new_custom(&mt9v032->ctrls, | |
928 | &mt9v032_test_pattern_color, NULL); | |
929 | ||
930 | v4l2_ctrl_cluster(2, &mt9v032->test_pattern); | |
e9a50e4c | 931 | |
41a33a00 SA |
932 | mt9v032->pixel_rate = |
933 | v4l2_ctrl_new_std(&mt9v032->ctrls, &mt9v032_ctrl_ops, | |
934 | V4L2_CID_PIXEL_RATE, 0, 0, 1, 0); | |
0f2ce168 | 935 | |
e9a50e4c LP |
936 | if (pdata && pdata->link_freqs) { |
937 | unsigned int def = 0; | |
938 | ||
939 | for (i = 0; pdata->link_freqs[i]; ++i) { | |
940 | if (pdata->link_freqs[i] == pdata->link_def_freq) | |
941 | def = i; | |
942 | } | |
943 | ||
944 | mt9v032->link_freq = | |
945 | v4l2_ctrl_new_int_menu(&mt9v032->ctrls, | |
946 | &mt9v032_ctrl_ops, | |
947 | V4L2_CID_LINK_FREQ, i - 1, def, | |
948 | pdata->link_freqs); | |
949 | v4l2_ctrl_cluster(2, &mt9v032->link_freq); | |
950 | } | |
951 | ||
0f2ce168 DC |
952 | |
953 | mt9v032->subdev.ctrl_handler = &mt9v032->ctrls; | |
954 | ||
955 | if (mt9v032->ctrls.error) | |
956 | printk(KERN_INFO "%s: control initialization error %d\n", | |
957 | __func__, mt9v032->ctrls.error); | |
958 | ||
959 | mt9v032->crop.left = MT9V032_COLUMN_START_DEF; | |
960 | mt9v032->crop.top = MT9V032_ROW_START_DEF; | |
961 | mt9v032->crop.width = MT9V032_WINDOW_WIDTH_DEF; | |
962 | mt9v032->crop.height = MT9V032_WINDOW_HEIGHT_DEF; | |
963 | ||
220ddc7f LP |
964 | if (mt9v032->model->color) |
965 | mt9v032->format.code = V4L2_MBUS_FMT_SGRBG10_1X10; | |
966 | else | |
967 | mt9v032->format.code = V4L2_MBUS_FMT_Y10_1X10; | |
968 | ||
0f2ce168 DC |
969 | mt9v032->format.width = MT9V032_WINDOW_WIDTH_DEF; |
970 | mt9v032->format.height = MT9V032_WINDOW_HEIGHT_DEF; | |
971 | mt9v032->format.field = V4L2_FIELD_NONE; | |
972 | mt9v032->format.colorspace = V4L2_COLORSPACE_SRGB; | |
973 | ||
637f005e LP |
974 | mt9v032->hratio = 1; |
975 | mt9v032->vratio = 1; | |
976 | ||
0f2ce168 | 977 | mt9v032->aec_agc = MT9V032_AEC_ENABLE | MT9V032_AGC_ENABLE; |
9ec670e2 | 978 | mt9v032->hblank = MT9V032_HORIZONTAL_BLANKING_DEF; |
e9a50e4c | 979 | mt9v032->sysclk = MT9V032_SYSCLK_FREQ_DEF; |
0f2ce168 DC |
980 | |
981 | v4l2_i2c_subdev_init(&mt9v032->subdev, client, &mt9v032_subdev_ops); | |
982 | mt9v032->subdev.internal_ops = &mt9v032_subdev_internal_ops; | |
983 | mt9v032->subdev.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; | |
984 | ||
985 | mt9v032->pad.flags = MEDIA_PAD_FL_SOURCE; | |
986 | ret = media_entity_init(&mt9v032->subdev.entity, 1, &mt9v032->pad, 0); | |
9462550f | 987 | |
c02b211d | 988 | if (ret < 0) |
9462550f | 989 | v4l2_ctrl_handler_free(&mt9v032->ctrls); |
0f2ce168 DC |
990 | |
991 | return ret; | |
992 | } | |
993 | ||
994 | static int mt9v032_remove(struct i2c_client *client) | |
995 | { | |
996 | struct v4l2_subdev *subdev = i2c_get_clientdata(client); | |
997 | struct mt9v032 *mt9v032 = to_mt9v032(subdev); | |
998 | ||
9462550f | 999 | v4l2_ctrl_handler_free(&mt9v032->ctrls); |
0f2ce168 DC |
1000 | v4l2_device_unregister_subdev(subdev); |
1001 | media_entity_cleanup(&subdev->entity); | |
9462550f | 1002 | |
0f2ce168 DC |
1003 | return 0; |
1004 | } | |
1005 | ||
1006 | static const struct i2c_device_id mt9v032_id[] = { | |
daecfebc LP |
1007 | { "mt9v032", (kernel_ulong_t)&mt9v032_models[MT9V032_MODEL_V032_COLOR] }, |
1008 | { "mt9v032m", (kernel_ulong_t)&mt9v032_models[MT9V032_MODEL_V032_MONO] }, | |
1009 | { "mt9v034", (kernel_ulong_t)&mt9v032_models[MT9V032_MODEL_V034_COLOR] }, | |
1010 | { "mt9v034m", (kernel_ulong_t)&mt9v032_models[MT9V032_MODEL_V034_MONO] }, | |
0f2ce168 DC |
1011 | { } |
1012 | }; | |
1013 | MODULE_DEVICE_TABLE(i2c, mt9v032_id); | |
1014 | ||
1015 | static struct i2c_driver mt9v032_driver = { | |
1016 | .driver = { | |
1017 | .name = "mt9v032", | |
1018 | }, | |
1019 | .probe = mt9v032_probe, | |
1020 | .remove = mt9v032_remove, | |
1021 | .id_table = mt9v032_id, | |
1022 | }; | |
1023 | ||
c6e8d86f | 1024 | module_i2c_driver(mt9v032_driver); |
0f2ce168 DC |
1025 | |
1026 | MODULE_DESCRIPTION("Aptina MT9V032 Camera driver"); | |
1027 | MODULE_AUTHOR("Laurent Pinchart <laurent.pinchart@ideasonboard.com>"); | |
1028 | MODULE_LICENSE("GPL"); |