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UBUNTU: SAUCE: IPU6 driver release for kernel 5.14 on 2021-11-01
[mirror_ubuntu-jammy-kernel.git] / drivers / media / i2c / ov01a1s.c
CommitLineData
f2efa4ee 1// SPDX-License-Identifier: GPL-2.0
eaffc3a7 2// Copyright (c) 2020-2021 Intel Corporation.
f2efa4ee
WY		 3
4#include <asm/unaligned.h>
5#include <linux/acpi.h>
6#include <linux/delay.h>
7#include <linux/i2c.h>
8#include <linux/module.h>
9#include <linux/pm_runtime.h>
5a771b35 10#include <linux/version.h>
f2efa4ee
WY		 11#include <media/v4l2-ctrls.h>
12#include <media/v4l2-device.h>
13#include <media/v4l2-fwnode.h>
eaffc3a7 14#include "power_ctrl_logic.h"
5a771b35 15#include <linux/vsc.h>
f2efa4ee 16
3074d1c6 17#define OV01A1S_LINK_FREQ_400MHZ 400000000ULL
af60d6fc 18#define OV01A1S_SCLK 40000000LL
f2efa4ee
WY		 19#define OV01A1S_MCLK 19200000
20#define OV01A1S_DATA_LANES 1
21#define OV01A1S_RGB_DEPTH 10
22
23#define OV01A1S_REG_CHIP_ID 0x300a
24#define OV01A1S_CHIP_ID 0x560141
25
26#define OV01A1S_REG_MODE_SELECT 0x0100
27#define OV01A1S_MODE_STANDBY 0x00
28#define OV01A1S_MODE_STREAMING 0x01
29
30/* vertical-timings from sensor */
31#define OV01A1S_REG_VTS 0x380e
32#define OV01A1S_VTS_DEF 0x0380
33#define OV01A1S_VTS_MIN 0x0380
34#define OV01A1S_VTS_MAX 0xffff
35
f2efa4ee
WY		 36/* Exposure controls from sensor */
37#define OV01A1S_REG_EXPOSURE 0x3501
38#define OV01A1S_EXPOSURE_MIN 4
39#define OV01A1S_EXPOSURE_MAX_MARGIN 8
40#define OV01A1S_EXPOSURE_STEP 1
41
42/* Analog gain controls from sensor */
43#define OV01A1S_REG_ANALOG_GAIN 0x3508
44#define OV01A1S_ANAL_GAIN_MIN 0x100
3074d1c6 45#define OV01A1S_ANAL_GAIN_MAX 0xffff
f2efa4ee
WY		 46#define OV01A1S_ANAL_GAIN_STEP 1
47
48/* Digital gain controls from sensor */
3074d1c6
WY		 49#define OV01A1S_REG_DIGILAL_GAIN_B 0x350A
50#define OV01A1S_REG_DIGITAL_GAIN_GB 0x3510
51#define OV01A1S_REG_DIGITAL_GAIN_GR 0x3513
52#define OV01A1S_REG_DIGITAL_GAIN_R 0x3516
f2efa4ee 53#define OV01A1S_DGTL_GAIN_MIN 0
3074d1c6 54#define OV01A1S_DGTL_GAIN_MAX 0x3ffff
f2efa4ee
WY		 55#define OV01A1S_DGTL_GAIN_STEP 1
56#define OV01A1S_DGTL_GAIN_DEFAULT 1024
57
58/* Test Pattern Control */
59#define OV01A1S_REG_TEST_PATTERN 0x4503
60#define OV01A1S_TEST_PATTERN_ENABLE BIT(7)
61#define OV01A1S_TEST_PATTERN_BAR_SHIFT 0
62
63enum {
64 OV01A1S_LINK_FREQ_400MHZ_INDEX,
65};
66
67struct ov01a1s_reg {
68 u16 address;
69 u8 val;
70};
71
72struct ov01a1s_reg_list {
73 u32 num_of_regs;
74 const struct ov01a1s_reg *regs;
75};
76
77struct ov01a1s_link_freq_config {
78 const struct ov01a1s_reg_list reg_list;
79};
80
81struct ov01a1s_mode {
82 /* Frame width in pixels */
83 u32 width;
84
85 /* Frame height in pixels */
86 u32 height;
87
88 /* Horizontal timining size */
89 u32 hts;
90
91 /* Default vertical timining size */
92 u32 vts_def;
93
94 /* Min vertical timining size */
95 u32 vts_min;
96
97 /* Link frequency needed for this resolution */
98 u32 link_freq_index;
99
100 /* Sensor register settings for this resolution */
101 const struct ov01a1s_reg_list reg_list;
102};
103
104static const struct ov01a1s_reg mipi_data_rate_720mbps[] = {
105};
106
f2efa4ee
WY		 107static const struct ov01a1s_reg sensor_1296x800_setting[] = {
108 {0x0103, 0x01},
109 {0x0302, 0x00},
110 {0x0303, 0x06},
111 {0x0304, 0x01},
112 {0x0305, 0x90},
113 {0x0306, 0x00},
114 {0x0308, 0x01},
115 {0x0309, 0x00},
116 {0x030c, 0x01},
117 {0x0322, 0x01},
118 {0x0323, 0x06},
119 {0x0324, 0x01},
120 {0x0325, 0x68},
121 {0x3002, 0xa1},
122 {0x301e, 0xf0},
123 {0x3022, 0x01},
124 {0x3501, 0x03},
125 {0x3502, 0x78},
126 {0x3504, 0x0c},
127 {0x3508, 0x01},
128 {0x3509, 0x00},
129 {0x3601, 0xc0},
130 {0x3603, 0x71},
131 {0x3610, 0x68},
132 {0x3611, 0x86},
133 {0x3640, 0x10},
134 {0x3641, 0x80},
135 {0x3642, 0xdc},
136 {0x3646, 0x55},
137 {0x3647, 0x57},
138 {0x364b, 0x00},
139 {0x3653, 0x10},
140 {0x3655, 0x00},
141 {0x3656, 0x00},
142 {0x365f, 0x0f},
143 {0x3661, 0x45},
144 {0x3662, 0x24},
145 {0x3663, 0x11},
146 {0x3664, 0x07},
147 {0x3709, 0x34},
148 {0x370b, 0x6f},
149 {0x3714, 0x22},
150 {0x371b, 0x27},
151 {0x371c, 0x67},
152 {0x371d, 0xa7},
153 {0x371e, 0xe7},
154 {0x3730, 0x81},
155 {0x3733, 0x10},
156 {0x3734, 0x40},
157 {0x3737, 0x04},
158 {0x3739, 0x1c},
159 {0x3767, 0x00},
160 {0x376c, 0x81},
161 {0x3772, 0x14},
162 {0x37c2, 0x04},
163 {0x37d8, 0x03},
164 {0x37d9, 0x0c},
165 {0x37e0, 0x00},
166 {0x37e1, 0x08},
167 {0x37e2, 0x10},
168 {0x37e3, 0x04},
169 {0x37e4, 0x04},
170 {0x37e5, 0x03},
171 {0x37e6, 0x04},
172 {0x3800, 0x00},
173 {0x3801, 0x00},
174 {0x3802, 0x00},
175 {0x3803, 0x00},
176 {0x3804, 0x05},
177 {0x3805, 0x0f},
178 {0x3806, 0x03},
179 {0x3807, 0x2f},
180 {0x3808, 0x05},
181 {0x3809, 0x00},
182 {0x380a, 0x03},
3074d1c6
WY		 183 {0x380b, 0x1e},
184 {0x380c, 0x05},
185 {0x380d, 0xd0},
f2efa4ee
WY		 186 {0x380e, 0x03},
187 {0x380f, 0x80},
188 {0x3810, 0x00},
189 {0x3811, 0x09},
190 {0x3812, 0x00},
191 {0x3813, 0x08},
192 {0x3814, 0x01},
193 {0x3815, 0x01},
194 {0x3816, 0x01},
195 {0x3817, 0x01},
196 {0x3820, 0xa8},
197 {0x3822, 0x03},
198 {0x3832, 0x28},
199 {0x3833, 0x10},
200 {0x3b00, 0x00},
201 {0x3c80, 0x00},
202 {0x3c88, 0x02},
203 {0x3c8c, 0x07},
204 {0x3c8d, 0x40},
205 {0x3cc7, 0x80},
206 {0x4000, 0xc3},
207 {0x4001, 0xe0},
208 {0x4003, 0x40},
209 {0x4008, 0x02},
210 {0x4009, 0x19},
211 {0x400a, 0x01},
212 {0x400b, 0x6c},
213 {0x4011, 0x00},
214 {0x4041, 0x00},
215 {0x4300, 0xff},
216 {0x4301, 0x00},
217 {0x4302, 0x0f},
218 {0x4503, 0x00},
af60d6fc 219 {0x4601, 0x50},
f2efa4ee
WY		 220 {0x481f, 0x34},
221 {0x4825, 0x33},
af60d6fc 222 {0x4837, 0x14},
f2efa4ee
WY		 223 {0x4881, 0x40},
224 {0x4883, 0x01},
225 {0x4890, 0x00},
226 {0x4901, 0x00},
227 {0x4902, 0x00},
228 {0x4b00, 0x2a},
229 {0x4b0d, 0x00},
230 {0x450a, 0x04},
231 {0x450b, 0x00},
f2efa4ee
WY		 232 {0x5000, 0x65},
233 {0x5004, 0x00},
234 {0x5080, 0x40},
235 {0x5200, 0x18},
236 {0x4837, 0x14},
f2efa4ee 237 {0x0305, 0xf4},
af60d6fc 238 {0x0325, 0xc2},
f2efa4ee 239 {0x3808, 0x05},
af60d6fc
WY		 240 {0x3809, 0x10},
241 {0x380a, 0x03},
3074d1c6 242 {0x380b, 0x1e},
f2efa4ee 243 {0x3810, 0x00},
af60d6fc 244 {0x3811, 0x00},
f2efa4ee 245 {0x3812, 0x00},
af60d6fc 246 {0x3813, 0x09},
e36f1e60 247 {0x3820, 0x88},
f2efa4ee
WY		 248 {0x373d, 0x24},
249};
250
251static const char * const ov01a1s_test_pattern_menu[] = {
252 "Disabled",
253 "Color Bar",
254 "Top-Bottom Darker Color Bar",
255 "Right-Left Darker Color Bar",
af60d6fc 256 "Color Bar type 4",
f2efa4ee
WY		 257};
258
259static const s64 link_freq_menu_items[] = {
260 OV01A1S_LINK_FREQ_400MHZ,
261};
262
263static const struct ov01a1s_link_freq_config link_freq_configs[] = {
264 [OV01A1S_LINK_FREQ_400MHZ_INDEX] = {
265 .reg_list = {
266 .num_of_regs = ARRAY_SIZE(mipi_data_rate_720mbps),
267 .regs = mipi_data_rate_720mbps,
268 }
269 },
270};
271
272static const struct ov01a1s_mode supported_modes[] = {
273 {
274 .width = 1296,
3074d1c6
WY		 275 .height = 798,
276 .hts = 1488,
f2efa4ee
WY		 277 .vts_def = OV01A1S_VTS_DEF,
278 .vts_min = OV01A1S_VTS_MIN,
279 .reg_list = {
280 .num_of_regs = ARRAY_SIZE(sensor_1296x800_setting),
281 .regs = sensor_1296x800_setting,
282 },
283 .link_freq_index = OV01A1S_LINK_FREQ_400MHZ_INDEX,
284 },
285};
286
287struct ov01a1s {
288 struct v4l2_subdev sd;
289 struct media_pad pad;
290 struct v4l2_ctrl_handler ctrl_handler;
291
292 /* V4L2 Controls */
293 struct v4l2_ctrl *link_freq;
294 struct v4l2_ctrl *pixel_rate;
295 struct v4l2_ctrl *vblank;
296 struct v4l2_ctrl *hblank;
297 struct v4l2_ctrl *exposure;
298
299 /* Current mode */
300 const struct ov01a1s_mode *cur_mode;
301
302 /* To serialize asynchronus callbacks */
303 struct mutex mutex;
304
305 /* Streaming on/off */
306 bool streaming;
307};
308
309static inline struct ov01a1s *to_ov01a1s(struct v4l2_subdev *subdev)
310{
311 return container_of(subdev, struct ov01a1s, sd);
312}
313
f2efa4ee
WY		 314static int ov01a1s_read_reg(struct ov01a1s *ov01a1s, u16 reg, u16 len, u32 *val)
315{
316 struct i2c_client *client = v4l2_get_subdevdata(&ov01a1s->sd);
317 struct i2c_msg msgs[2];
318 u8 addr_buf[2];
319 u8 data_buf[4] = {0};
320 int ret = 0;
321
322 if (len > sizeof(data_buf))
323 return -EINVAL;
324
325 put_unaligned_be16(reg, addr_buf);
326 msgs[0].addr = client->addr;
327 msgs[0].flags = 0;
328 msgs[0].len = sizeof(addr_buf);
329 msgs[0].buf = addr_buf;
330 msgs[1].addr = client->addr;
331 msgs[1].flags = I2C_M_RD;
332 msgs[1].len = len;
333 msgs[1].buf = &data_buf[sizeof(data_buf) - len];
334
335 ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
336 if (ret != ARRAY_SIZE(msgs))
337 return ret < 0 ? ret : -EIO;
338
339 *val = get_unaligned_be32(data_buf);
340
341 return 0;
342}
343
344static int ov01a1s_write_reg(struct ov01a1s *ov01a1s, u16 reg, u16 len, u32 val)
345{
346 struct i2c_client *client = v4l2_get_subdevdata(&ov01a1s->sd);
347 u8 buf[6];
348 int ret = 0;
349
350 if (len > 4)
351 return -EINVAL;
352
353 put_unaligned_be16(reg, buf);
354 put_unaligned_be32(val << 8 * (4 - len), buf + 2);
355
356 ret = i2c_master_send(client, buf, len + 2);
357 if (ret != len + 2)
358 return ret < 0 ? ret : -EIO;
359
360 return 0;
361}
362
363static int ov01a1s_write_reg_list(struct ov01a1s *ov01a1s,
af60d6fc 364 const struct ov01a1s_reg_list *r_list)
f2efa4ee
WY		 365{
366 struct i2c_client *client = v4l2_get_subdevdata(&ov01a1s->sd);
367 unsigned int i;
368 int ret = 0;
369
370 for (i = 0; i < r_list->num_of_regs; i++) {
371 ret = ov01a1s_write_reg(ov01a1s, r_list->regs[i].address, 1,
af60d6fc 372 r_list->regs[i].val);
f2efa4ee
WY		 373 if (ret) {
374 dev_err_ratelimited(&client->dev,
375 "write reg 0x%4.4x return err = %d",
376 r_list->regs[i].address, ret);
377 return ret;
378 }
379 }
380
381 return 0;
382}
383
384static int ov01a1s_update_digital_gain(struct ov01a1s *ov01a1s, u32 d_gain)
385{
3074d1c6
WY		 386 struct i2c_client *client = v4l2_get_subdevdata(&ov01a1s->sd);
387 u32 real = d_gain << 6;
388 int ret = 0;
f2efa4ee 389
3074d1c6
WY		 390 ret = ov01a1s_write_reg(ov01a1s, OV01A1S_REG_DIGILAL_GAIN_B, 3, real);
391 if (ret) {
392 dev_err(&client->dev, "failed to set OV01A1S_REG_DIGITAL_GAIN_B");
393 return ret;
394 }
395 ret = ov01a1s_write_reg(ov01a1s, OV01A1S_REG_DIGITAL_GAIN_GB, 3, real);
396 if (ret) {
397 dev_err(&client->dev, "failed to set OV01A1S_REG_DIGITAL_GAIN_GB");
398 return ret;
399 }
400 ret = ov01a1s_write_reg(ov01a1s, OV01A1S_REG_DIGITAL_GAIN_GR, 3, real);
401 if (ret) {
402 dev_err(&client->dev, "failed to set OV01A1S_REG_DIGITAL_GAIN_GR");
403 return ret;
404 }
f2efa4ee 405
3074d1c6
WY		 406 ret = ov01a1s_write_reg(ov01a1s, OV01A1S_REG_DIGITAL_GAIN_R, 3, real);
407 if (ret) {
408 dev_err(&client->dev, "failed to set OV01A1S_REG_DIGITAL_GAIN_R");
409 return ret;
410 }
411 return ret;
f2efa4ee
WY		 412}
413
414static int ov01a1s_test_pattern(struct ov01a1s *ov01a1s, u32 pattern)
415{
416 if (pattern)
af60d6fc 417 pattern = (pattern - 1) << OV01A1S_TEST_PATTERN_BAR_SHIFT |
f2efa4ee
WY		 418 OV01A1S_TEST_PATTERN_ENABLE;
419
420 return ov01a1s_write_reg(ov01a1s, OV01A1S_REG_TEST_PATTERN, 1, pattern);
421}
422
423static int ov01a1s_set_ctrl(struct v4l2_ctrl *ctrl)
424{
425 struct ov01a1s *ov01a1s = container_of(ctrl->handler,
426 struct ov01a1s, ctrl_handler);
427 struct i2c_client *client = v4l2_get_subdevdata(&ov01a1s->sd);
428 s64 exposure_max;
429 int ret = 0;
430
431 /* Propagate change of current control to all related controls */
432 if (ctrl->id == V4L2_CID_VBLANK) {
433 /* Update max exposure while meeting expected vblanking */
434 exposure_max = ov01a1s->cur_mode->height + ctrl->val -
435 OV01A1S_EXPOSURE_MAX_MARGIN;
436 __v4l2_ctrl_modify_range(ov01a1s->exposure,
437 ov01a1s->exposure->minimum,
438 exposure_max, ov01a1s->exposure->step,
439 exposure_max);
440 }
441
442 /* V4L2 controls values will be applied only when power is already up */
443 if (!pm_runtime_get_if_in_use(&client->dev))
444 return 0;
445
446 switch (ctrl->id) {
447 case V4L2_CID_ANALOGUE_GAIN:
448 ret = ov01a1s_write_reg(ov01a1s, OV01A1S_REG_ANALOG_GAIN, 2,
3074d1c6 449 ctrl->val);
f2efa4ee
WY		 450 break;
451
452 case V4L2_CID_DIGITAL_GAIN:
453 ret = ov01a1s_update_digital_gain(ov01a1s, ctrl->val);
454 break;
455
456 case V4L2_CID_EXPOSURE:
457 ret = ov01a1s_write_reg(ov01a1s, OV01A1S_REG_EXPOSURE, 2,
af60d6fc 458 ctrl->val);
f2efa4ee
WY		 459 break;
460
461 case V4L2_CID_VBLANK:
462 ret = ov01a1s_write_reg(ov01a1s, OV01A1S_REG_VTS, 2,
af60d6fc 463 ov01a1s->cur_mode->height + ctrl->val);
f2efa4ee
WY		 464 break;
465
466 case V4L2_CID_TEST_PATTERN:
467 ret = ov01a1s_test_pattern(ov01a1s, ctrl->val);
468 break;
469
470 default:
471 ret = -EINVAL;
472 break;
473 }
474
475 pm_runtime_put(&client->dev);
476
477 return ret;
478}
479
480static const struct v4l2_ctrl_ops ov01a1s_ctrl_ops = {
481 .s_ctrl = ov01a1s_set_ctrl,
482};
483
484static int ov01a1s_init_controls(struct ov01a1s *ov01a1s)
485{
486 struct v4l2_ctrl_handler *ctrl_hdlr;
487 const struct ov01a1s_mode *cur_mode;
3074d1c6 488 s64 exposure_max, h_blank;
f2efa4ee
WY		 489 u32 vblank_min, vblank_max, vblank_default;
490 int size;
491 int ret = 0;
492
493 ctrl_hdlr = &ov01a1s->ctrl_handler;
494 ret = v4l2_ctrl_handler_init(ctrl_hdlr, 8);
495 if (ret)
496 return ret;
497
498 ctrl_hdlr->lock = &ov01a1s->mutex;
499 cur_mode = ov01a1s->cur_mode;
500 size = ARRAY_SIZE(link_freq_menu_items);
501
af60d6fc
WY		 502 ov01a1s->link_freq = v4l2_ctrl_new_int_menu(ctrl_hdlr,
503 &ov01a1s_ctrl_ops,
504 V4L2_CID_LINK_FREQ,
505 size - 1, 0,
506 link_freq_menu_items);
f2efa4ee
WY		 507 if (ov01a1s->link_freq)
508 ov01a1s->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY;
509
f2efa4ee 510 ov01a1s->pixel_rate = v4l2_ctrl_new_std(ctrl_hdlr, &ov01a1s_ctrl_ops,
af60d6fc 511 V4L2_CID_PIXEL_RATE, 0,
3074d1c6 512 OV01A1S_SCLK, 1, OV01A1S_SCLK);
f2efa4ee
WY		 513
514 vblank_min = cur_mode->vts_min - cur_mode->height;
515 vblank_max = OV01A1S_VTS_MAX - cur_mode->height;
516 vblank_default = cur_mode->vts_def - cur_mode->height;
517 ov01a1s->vblank = v4l2_ctrl_new_std(ctrl_hdlr, &ov01a1s_ctrl_ops,
af60d6fc
WY		 518 V4L2_CID_VBLANK, vblank_min,
519 vblank_max, 1, vblank_default);
f2efa4ee 520
3074d1c6 521 h_blank = cur_mode->hts - cur_mode->width;
f2efa4ee 522 ov01a1s->hblank = v4l2_ctrl_new_std(ctrl_hdlr, &ov01a1s_ctrl_ops,
af60d6fc
WY		 523 V4L2_CID_HBLANK, h_blank, h_blank,
524 1, h_blank);
f2efa4ee
WY		 525 if (ov01a1s->hblank)
526 ov01a1s->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
527
528 v4l2_ctrl_new_std(ctrl_hdlr, &ov01a1s_ctrl_ops, V4L2_CID_ANALOGUE_GAIN,
529 OV01A1S_ANAL_GAIN_MIN, OV01A1S_ANAL_GAIN_MAX,
530 OV01A1S_ANAL_GAIN_STEP, OV01A1S_ANAL_GAIN_MIN);
531 v4l2_ctrl_new_std(ctrl_hdlr, &ov01a1s_ctrl_ops, V4L2_CID_DIGITAL_GAIN,
532 OV01A1S_DGTL_GAIN_MIN, OV01A1S_DGTL_GAIN_MAX,
533 OV01A1S_DGTL_GAIN_STEP, OV01A1S_DGTL_GAIN_DEFAULT);
534 exposure_max = cur_mode->vts_def - OV01A1S_EXPOSURE_MAX_MARGIN;
535 ov01a1s->exposure = v4l2_ctrl_new_std(ctrl_hdlr, &ov01a1s_ctrl_ops,
af60d6fc
WY		 536 V4L2_CID_EXPOSURE,
537 OV01A1S_EXPOSURE_MIN,
538 exposure_max,
539 OV01A1S_EXPOSURE_STEP,
540 exposure_max);
f2efa4ee
WY		 541 v4l2_ctrl_new_std_menu_items(ctrl_hdlr, &ov01a1s_ctrl_ops,
542 V4L2_CID_TEST_PATTERN,
543 ARRAY_SIZE(ov01a1s_test_pattern_menu) - 1,
544 0, 0, ov01a1s_test_pattern_menu);
545 if (ctrl_hdlr->error)
546 return ctrl_hdlr->error;
547
548 ov01a1s->sd.ctrl_handler = ctrl_hdlr;
549
550 return 0;
551}
552
553static void ov01a1s_update_pad_format(const struct ov01a1s_mode *mode,
af60d6fc 554 struct v4l2_mbus_framefmt *fmt)
f2efa4ee
WY		 555{
556 fmt->width = mode->width;
557 fmt->height = mode->height;
558 fmt->code = MEDIA_BUS_FMT_SGRBG10_1X10;
559 fmt->field = V4L2_FIELD_NONE;
560}
561
562static int ov01a1s_start_streaming(struct ov01a1s *ov01a1s)
563{
564 struct i2c_client *client = v4l2_get_subdevdata(&ov01a1s->sd);
565 const struct ov01a1s_reg_list *reg_list;
566 int link_freq_index;
567 int ret = 0;
568
eaffc3a7 569 power_ctrl_logic_set_power(1);
f2efa4ee
WY		 570 link_freq_index = ov01a1s->cur_mode->link_freq_index;
571 reg_list = &link_freq_configs[link_freq_index].reg_list;
572 ret = ov01a1s_write_reg_list(ov01a1s, reg_list);
573 if (ret) {
574 dev_err(&client->dev, "failed to set plls");
575 return ret;
576 }
577
578 reg_list = &ov01a1s->cur_mode->reg_list;
579 ret = ov01a1s_write_reg_list(ov01a1s, reg_list);
580 if (ret) {
581 dev_err(&client->dev, "failed to set mode");
582 return ret;
583 }
584
585 ret = __v4l2_ctrl_handler_setup(ov01a1s->sd.ctrl_handler);
586 if (ret)
587 return ret;
588
589 ret = ov01a1s_write_reg(ov01a1s, OV01A1S_REG_MODE_SELECT, 1,
af60d6fc 590 OV01A1S_MODE_STREAMING);
f2efa4ee
WY		 591 if (ret)
592 dev_err(&client->dev, "failed to start streaming");
593
594 return ret;
595}
596
597static void ov01a1s_stop_streaming(struct ov01a1s *ov01a1s)
598{
599 struct i2c_client *client = v4l2_get_subdevdata(&ov01a1s->sd);
af60d6fc 600 int ret = 0;
f2efa4ee 601
af60d6fc
WY		 602 ret = ov01a1s_write_reg(ov01a1s, OV01A1S_REG_MODE_SELECT, 1,
603 OV01A1S_MODE_STANDBY);
604 if (ret)
f2efa4ee 605 dev_err(&client->dev, "failed to stop streaming");
eaffc3a7 606 power_ctrl_logic_set_power(0);
f2efa4ee
WY		 607}
608
609static int ov01a1s_set_stream(struct v4l2_subdev *sd, int enable)
610{
611 struct ov01a1s *ov01a1s = to_ov01a1s(sd);
612 struct i2c_client *client = v4l2_get_subdevdata(sd);
613 int ret = 0;
614
615 if (ov01a1s->streaming == enable)
616 return 0;
617
618 mutex_lock(&ov01a1s->mutex);
619 if (enable) {
620 ret = pm_runtime_get_sync(&client->dev);
621 if (ret < 0) {
622 pm_runtime_put_noidle(&client->dev);
623 mutex_unlock(&ov01a1s->mutex);
624 return ret;
625 }
626
627 ret = ov01a1s_start_streaming(ov01a1s);
628 if (ret) {
629 enable = 0;
630 ov01a1s_stop_streaming(ov01a1s);
631 pm_runtime_put(&client->dev);
632 }
633 } else {
634 ov01a1s_stop_streaming(ov01a1s);
635 pm_runtime_put(&client->dev);
636 }
637
638 ov01a1s->streaming = enable;
639 mutex_unlock(&ov01a1s->mutex);
640
641 return ret;
642}
643
644static int __maybe_unused ov01a1s_suspend(struct device *dev)
645{
646 struct i2c_client *client = to_i2c_client(dev);
647 struct v4l2_subdev *sd = i2c_get_clientdata(client);
648 struct ov01a1s *ov01a1s = to_ov01a1s(sd);
649
650 mutex_lock(&ov01a1s->mutex);
651 if (ov01a1s->streaming)
652 ov01a1s_stop_streaming(ov01a1s);
653
654 mutex_unlock(&ov01a1s->mutex);
655
656 return 0;
657}
658
659static int __maybe_unused ov01a1s_resume(struct device *dev)
660{
661 struct i2c_client *client = to_i2c_client(dev);
662 struct v4l2_subdev *sd = i2c_get_clientdata(client);
663 struct ov01a1s *ov01a1s = to_ov01a1s(sd);
664 int ret = 0;
665
666 mutex_lock(&ov01a1s->mutex);
667 if (!ov01a1s->streaming)
668 goto exit;
669
670 ret = ov01a1s_start_streaming(ov01a1s);
671 if (ret) {
672 ov01a1s->streaming = false;
673 ov01a1s_stop_streaming(ov01a1s);
674 }
675
676exit:
677 mutex_unlock(&ov01a1s->mutex);
678 return ret;
679}
680
681static int ov01a1s_set_format(struct v4l2_subdev *sd,
5a771b35 682 struct v4l2_subdev_state *sd_state,
af60d6fc 683 struct v4l2_subdev_format *fmt)
f2efa4ee
WY		 684{
685 struct ov01a1s *ov01a1s = to_ov01a1s(sd);
686 const struct ov01a1s_mode *mode;
687 s32 vblank_def, h_blank;
688
689 mode = v4l2_find_nearest_size(supported_modes,
690 ARRAY_SIZE(supported_modes), width,
691 height, fmt->format.width,
692 fmt->format.height);
693
694 mutex_lock(&ov01a1s->mutex);
695 ov01a1s_update_pad_format(mode, &fmt->format);
696 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
5a771b35 697 *v4l2_subdev_get_try_format(sd, sd_state, fmt->pad) = fmt->format;
f2efa4ee
WY		 698 } else {
699 ov01a1s->cur_mode = mode;
700 __v4l2_ctrl_s_ctrl(ov01a1s->link_freq, mode->link_freq_index);
3074d1c6 701 __v4l2_ctrl_s_ctrl_int64(ov01a1s->pixel_rate, OV01A1S_SCLK);
f2efa4ee
WY		 702
703 /* Update limits and set FPS to default */
704 vblank_def = mode->vts_def - mode->height;
705 __v4l2_ctrl_modify_range(ov01a1s->vblank,
706 mode->vts_min - mode->height,
707 OV01A1S_VTS_MAX - mode->height, 1,
708 vblank_def);
709 __v4l2_ctrl_s_ctrl(ov01a1s->vblank, vblank_def);
3074d1c6 710 h_blank = mode->hts - mode->width;
f2efa4ee
WY		 711 __v4l2_ctrl_modify_range(ov01a1s->hblank, h_blank, h_blank, 1,
712 h_blank);
713 }
714 mutex_unlock(&ov01a1s->mutex);
715
716 return 0;
717}
718
719static int ov01a1s_get_format(struct v4l2_subdev *sd,
5a771b35 720 struct v4l2_subdev_state *sd_state,
af60d6fc 721 struct v4l2_subdev_format *fmt)
f2efa4ee
WY		 722{
723 struct ov01a1s *ov01a1s = to_ov01a1s(sd);
724
725 mutex_lock(&ov01a1s->mutex);
726 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY)
5a771b35
HY		 727 fmt->format = *v4l2_subdev_get_try_format(&ov01a1s->sd,
728 sd_state, fmt->pad);
f2efa4ee
WY		 729 else
730 ov01a1s_update_pad_format(ov01a1s->cur_mode, &fmt->format);
731
732 mutex_unlock(&ov01a1s->mutex);
733
734 return 0;
735}
736
737static int ov01a1s_enum_mbus_code(struct v4l2_subdev *sd,
5a771b35 738 struct v4l2_subdev_state *sd_state,
af60d6fc 739 struct v4l2_subdev_mbus_code_enum *code)
f2efa4ee
WY		 740{
741 if (code->index > 0)
742 return -EINVAL;
743
744 code->code = MEDIA_BUS_FMT_SGRBG10_1X10;
745
746 return 0;
747}
748
749static int ov01a1s_enum_frame_size(struct v4l2_subdev *sd,
5a771b35 750 struct v4l2_subdev_state *sd_state,
af60d6fc 751 struct v4l2_subdev_frame_size_enum *fse)
f2efa4ee
WY		 752{
753 if (fse->index >= ARRAY_SIZE(supported_modes))
754 return -EINVAL;
755
756 if (fse->code != MEDIA_BUS_FMT_SGRBG10_1X10)
757 return -EINVAL;
758
759 fse->min_width = supported_modes[fse->index].width;
760 fse->max_width = fse->min_width;
761 fse->min_height = supported_modes[fse->index].height;
762 fse->max_height = fse->min_height;
763
764 return 0;
765}
766
767static int ov01a1s_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
768{
769 struct ov01a1s *ov01a1s = to_ov01a1s(sd);
770
771 mutex_lock(&ov01a1s->mutex);
772 ov01a1s_update_pad_format(&supported_modes[0],
5a771b35 773 v4l2_subdev_get_try_format(sd, fh->state, 0));
f2efa4ee
WY		 774 mutex_unlock(&ov01a1s->mutex);
775
776 return 0;
777}
778
779static const struct v4l2_subdev_video_ops ov01a1s_video_ops = {
780 .s_stream = ov01a1s_set_stream,
781};
782
783static const struct v4l2_subdev_pad_ops ov01a1s_pad_ops = {
784 .set_fmt = ov01a1s_set_format,
785 .get_fmt = ov01a1s_get_format,
786 .enum_mbus_code = ov01a1s_enum_mbus_code,
787 .enum_frame_size = ov01a1s_enum_frame_size,
788};
789
790static const struct v4l2_subdev_ops ov01a1s_subdev_ops = {
791 .video = &ov01a1s_video_ops,
792 .pad = &ov01a1s_pad_ops,
793};
794
795static const struct media_entity_operations ov01a1s_subdev_entity_ops = {
796 .link_validate = v4l2_subdev_link_validate,
797};
798
799static const struct v4l2_subdev_internal_ops ov01a1s_internal_ops = {
800 .open = ov01a1s_open,
801};
802
803static int ov01a1s_identify_module(struct ov01a1s *ov01a1s)
804{
805 struct i2c_client *client = v4l2_get_subdevdata(&ov01a1s->sd);
806 int ret;
807 u32 val;
808
809 ret = ov01a1s_read_reg(ov01a1s, OV01A1S_REG_CHIP_ID, 3, &val);
810 if (ret)
811 return ret;
812
813 if (val != OV01A1S_CHIP_ID) {
814 dev_err(&client->dev, "chip id mismatch: %x!=%x",
815 OV01A1S_CHIP_ID, val);
816 return -ENXIO;
817 }
818
819 return 0;
820}
821
822static int ov01a1s_remove(struct i2c_client *client)
823{
824 struct v4l2_subdev *sd = i2c_get_clientdata(client);
825 struct ov01a1s *ov01a1s = to_ov01a1s(sd);
826
827 v4l2_async_unregister_subdev(sd);
828 media_entity_cleanup(&sd->entity);
829 v4l2_ctrl_handler_free(sd->ctrl_handler);
830 pm_runtime_disable(&client->dev);
831 mutex_destroy(&ov01a1s->mutex);
832
833 return 0;
834}
835
836static int ov01a1s_probe(struct i2c_client *client)
837{
838 struct ov01a1s *ov01a1s;
839 int ret = 0;
5a771b35
HY		 840 struct vsc_mipi_config conf;
841 struct vsc_camera_status status;
842 s64 link_freq;
843
844 conf.lane_num = OV01A1S_DATA_LANES;
845 /* frequency unit 100k */
846 conf.freq = OV01A1S_LINK_FREQ_400MHZ / 100000;
847 ret = vsc_acquire_camera_sensor(&conf, NULL, NULL, &status);
848 if (ret == -EAGAIN)
849 ret = power_ctrl_logic_set_power(1);
850 if (ret == -EAGAIN)
85301793 851 return -EPROBE_DEFER;
5a771b35
HY		 852 else if (ret)
853 return ret;
f2efa4ee 854 ov01a1s = devm_kzalloc(&client->dev, sizeof(*ov01a1s), GFP_KERNEL);
85301793
WY		 855 if (!ov01a1s) {
856 ret = -ENOMEM;
857 goto probe_error_ret;
858 }
f2efa4ee
WY		 859
860 v4l2_i2c_subdev_init(&ov01a1s->sd, client, &ov01a1s_subdev_ops);
861 ret = ov01a1s_identify_module(ov01a1s);
862 if (ret) {
863 dev_err(&client->dev, "failed to find sensor: %d", ret);
85301793 864 goto probe_error_ret;
f2efa4ee
WY		 865 }
866
867 mutex_init(&ov01a1s->mutex);
868 ov01a1s->cur_mode = &supported_modes[0];
869 ret = ov01a1s_init_controls(ov01a1s);
870 if (ret) {
871 dev_err(&client->dev, "failed to init controls: %d", ret);
872 goto probe_error_v4l2_ctrl_handler_free;
873 }
874
875 ov01a1s->sd.internal_ops = &ov01a1s_internal_ops;
876 ov01a1s->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
877 ov01a1s->sd.entity.ops = &ov01a1s_subdev_entity_ops;
878 ov01a1s->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
879 ov01a1s->pad.flags = MEDIA_PAD_FL_SOURCE;
880 ret = media_entity_pads_init(&ov01a1s->sd.entity, 1, &ov01a1s->pad);
881 if (ret) {
882 dev_err(&client->dev, "failed to init entity pads: %d", ret);
883 goto probe_error_v4l2_ctrl_handler_free;
884 }
885
1223f6d5 886 ret = v4l2_async_register_subdev_sensor(&ov01a1s->sd);
f2efa4ee
WY		 887 if (ret < 0) {
888 dev_err(&client->dev, "failed to register V4L2 subdev: %d",
889 ret);
890 goto probe_error_media_entity_cleanup;
891 }
892
5a771b35 893 vsc_release_camera_sensor(&status);
f2efa4ee
WY		 894 /*
895 * Device is already turned on by i2c-core with ACPI domain PM.
896 * Enable runtime PM and turn off the device.
897 */
898 pm_runtime_set_active(&client->dev);
899 pm_runtime_enable(&client->dev);
900 pm_runtime_idle(&client->dev);
901
eaffc3a7 902 power_ctrl_logic_set_power(0);
f2efa4ee
WY		 903 return 0;
904
905probe_error_media_entity_cleanup:
906 media_entity_cleanup(&ov01a1s->sd.entity);
907
908probe_error_v4l2_ctrl_handler_free:
909 v4l2_ctrl_handler_free(ov01a1s->sd.ctrl_handler);
910 mutex_destroy(&ov01a1s->mutex);
911
85301793
WY		 912probe_error_ret:
913 power_ctrl_logic_set_power(0);
5a771b35 914 vsc_release_camera_sensor(&status);
f2efa4ee
WY		 915 return ret;
916}
917
918static const struct dev_pm_ops ov01a1s_pm_ops = {
919 SET_SYSTEM_SLEEP_PM_OPS(ov01a1s_suspend, ov01a1s_resume)
920};
921
922#ifdef CONFIG_ACPI
923static const struct acpi_device_id ov01a1s_acpi_ids[] = {
3ebd4441 924 { "OVTI01AS" },
f2efa4ee
WY		 925 {}
926};
927
928MODULE_DEVICE_TABLE(acpi, ov01a1s_acpi_ids);
929#endif
930
931static struct i2c_driver ov01a1s_i2c_driver = {
932 .driver = {
af60d6fc 933 .name = "ov01a1s",
f2efa4ee
WY		 934 .pm = &ov01a1s_pm_ops,
935 .acpi_match_table = ACPI_PTR(ov01a1s_acpi_ids),
936 },
937 .probe_new = ov01a1s_probe,
938 .remove = ov01a1s_remove,
939};
940
941module_i2c_driver(ov01a1s_i2c_driver);
942
af60d6fc 943MODULE_AUTHOR("Xu, Chongyang <chongyang.xu@intel.com>");
f2efa4ee
WY		 944MODULE_AUTHOR("Lai, Jim <jim.lai@intel.com>");
945MODULE_AUTHOR("Qiu, Tianshu <tian.shu.qiu@intel.com>");
946MODULE_AUTHOR("Shawn Tu <shawnx.tu@intel.com>");
947MODULE_AUTHOR("Bingbu Cao <bingbu.cao@intel.com>");
948MODULE_DESCRIPTION("OmniVision OV01A1S sensor driver");
949MODULE_LICENSE("GPL v2");
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