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2f6e2404 | 1 | /* |
23a52386 | 2 | * V4L2 subdevice driver for OmniVision OV6650 Camera Sensor |
2f6e2404 JK |
3 | * |
4 | * Copyright (C) 2010 Janusz Krzysztofik <jkrzyszt@tis.icnet.pl> | |
5 | * | |
6 | * Based on OmniVision OV96xx Camera Driver | |
7 | * Copyright (C) 2009 Marek Vasut <marek.vasut@gmail.com> | |
8 | * | |
9 | * Based on ov772x camera driver: | |
10 | * Copyright (C) 2008 Renesas Solutions Corp. | |
11 | * Kuninori Morimoto <morimoto.kuninori@renesas.com> | |
12 | * | |
13 | * Based on ov7670 and soc_camera_platform driver, | |
14 | * Copyright 2006-7 Jonathan Corbet <corbet@lwn.net> | |
15 | * Copyright (C) 2008 Magnus Damm | |
16 | * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de> | |
17 | * | |
18 | * Hardware specific bits initialy based on former work by Matt Callow | |
19 | * drivers/media/video/omap/sensor_ov6650.c | |
20 | * Copyright (C) 2006 Matt Callow | |
21 | * | |
22 | * This program is free software; you can redistribute it and/or modify | |
23 | * it under the terms of the GNU General Public License version 2 as | |
24 | * published by the Free Software Foundation. | |
25 | */ | |
26 | ||
27 | #include <linux/bitops.h> | |
28 | #include <linux/delay.h> | |
29 | #include <linux/i2c.h> | |
30 | #include <linux/slab.h> | |
95d20109 | 31 | #include <linux/v4l2-mediabus.h> |
7a707b89 | 32 | #include <linux/module.h> |
2f6e2404 | 33 | |
9aea470b | 34 | #include <media/v4l2-clk.h> |
afd9690c | 35 | #include <media/v4l2-ctrls.h> |
23a52386 | 36 | #include <media/v4l2-device.h> |
2f6e2404 | 37 | |
2f6e2404 JK |
38 | /* Register definitions */ |
39 | #define REG_GAIN 0x00 /* range 00 - 3F */ | |
40 | #define REG_BLUE 0x01 | |
41 | #define REG_RED 0x02 | |
42 | #define REG_SAT 0x03 /* [7:4] saturation [0:3] reserved */ | |
43 | #define REG_HUE 0x04 /* [7:6] rsrvd [5] hue en [4:0] hue */ | |
44 | ||
45 | #define REG_BRT 0x06 | |
46 | ||
47 | #define REG_PIDH 0x0a | |
48 | #define REG_PIDL 0x0b | |
49 | ||
50 | #define REG_AECH 0x10 | |
51 | #define REG_CLKRC 0x11 /* Data Format and Internal Clock */ | |
52 | /* [7:6] Input system clock (MHz)*/ | |
53 | /* 00=8, 01=12, 10=16, 11=24 */ | |
54 | /* [5:0]: Internal Clock Pre-Scaler */ | |
55 | #define REG_COMA 0x12 /* [7] Reset */ | |
56 | #define REG_COMB 0x13 | |
57 | #define REG_COMC 0x14 | |
58 | #define REG_COMD 0x15 | |
59 | #define REG_COML 0x16 | |
60 | #define REG_HSTRT 0x17 | |
61 | #define REG_HSTOP 0x18 | |
62 | #define REG_VSTRT 0x19 | |
63 | #define REG_VSTOP 0x1a | |
64 | #define REG_PSHFT 0x1b | |
65 | #define REG_MIDH 0x1c | |
66 | #define REG_MIDL 0x1d | |
67 | #define REG_HSYNS 0x1e | |
68 | #define REG_HSYNE 0x1f | |
69 | #define REG_COME 0x20 | |
70 | #define REG_YOFF 0x21 | |
71 | #define REG_UOFF 0x22 | |
72 | #define REG_VOFF 0x23 | |
73 | #define REG_AEW 0x24 | |
74 | #define REG_AEB 0x25 | |
75 | #define REG_COMF 0x26 | |
76 | #define REG_COMG 0x27 | |
77 | #define REG_COMH 0x28 | |
78 | #define REG_COMI 0x29 | |
79 | ||
80 | #define REG_FRARL 0x2b | |
81 | #define REG_COMJ 0x2c | |
82 | #define REG_COMK 0x2d | |
83 | #define REG_AVGY 0x2e | |
84 | #define REG_REF0 0x2f | |
85 | #define REG_REF1 0x30 | |
86 | #define REG_REF2 0x31 | |
87 | #define REG_FRAJH 0x32 | |
88 | #define REG_FRAJL 0x33 | |
89 | #define REG_FACT 0x34 | |
90 | #define REG_L1AEC 0x35 | |
91 | #define REG_AVGU 0x36 | |
92 | #define REG_AVGV 0x37 | |
93 | ||
94 | #define REG_SPCB 0x60 | |
95 | #define REG_SPCC 0x61 | |
96 | #define REG_GAM1 0x62 | |
97 | #define REG_GAM2 0x63 | |
98 | #define REG_GAM3 0x64 | |
99 | #define REG_SPCD 0x65 | |
100 | ||
101 | #define REG_SPCE 0x68 | |
102 | #define REG_ADCL 0x69 | |
103 | ||
104 | #define REG_RMCO 0x6c | |
105 | #define REG_GMCO 0x6d | |
106 | #define REG_BMCO 0x6e | |
107 | ||
108 | ||
109 | /* Register bits, values, etc. */ | |
110 | #define OV6650_PIDH 0x66 /* high byte of product ID number */ | |
111 | #define OV6650_PIDL 0x50 /* low byte of product ID number */ | |
112 | #define OV6650_MIDH 0x7F /* high byte of mfg ID */ | |
113 | #define OV6650_MIDL 0xA2 /* low byte of mfg ID */ | |
114 | ||
115 | #define DEF_GAIN 0x00 | |
116 | #define DEF_BLUE 0x80 | |
117 | #define DEF_RED 0x80 | |
118 | ||
119 | #define SAT_SHIFT 4 | |
120 | #define SAT_MASK (0xf << SAT_SHIFT) | |
121 | #define SET_SAT(x) (((x) << SAT_SHIFT) & SAT_MASK) | |
122 | ||
123 | #define HUE_EN BIT(5) | |
124 | #define HUE_MASK 0x1f | |
125 | #define DEF_HUE 0x10 | |
126 | #define SET_HUE(x) (HUE_EN | ((x) & HUE_MASK)) | |
127 | ||
128 | #define DEF_AECH 0x4D | |
129 | ||
130 | #define CLKRC_6MHz 0x00 | |
131 | #define CLKRC_12MHz 0x40 | |
132 | #define CLKRC_16MHz 0x80 | |
133 | #define CLKRC_24MHz 0xc0 | |
134 | #define CLKRC_DIV_MASK 0x3f | |
135 | #define GET_CLKRC_DIV(x) (((x) & CLKRC_DIV_MASK) + 1) | |
136 | ||
137 | #define COMA_RESET BIT(7) | |
138 | #define COMA_QCIF BIT(5) | |
139 | #define COMA_RAW_RGB BIT(4) | |
140 | #define COMA_RGB BIT(3) | |
141 | #define COMA_BW BIT(2) | |
142 | #define COMA_WORD_SWAP BIT(1) | |
143 | #define COMA_BYTE_SWAP BIT(0) | |
144 | #define DEF_COMA 0x00 | |
145 | ||
146 | #define COMB_FLIP_V BIT(7) | |
147 | #define COMB_FLIP_H BIT(5) | |
148 | #define COMB_BAND_FILTER BIT(4) | |
149 | #define COMB_AWB BIT(2) | |
150 | #define COMB_AGC BIT(1) | |
151 | #define COMB_AEC BIT(0) | |
152 | #define DEF_COMB 0x5f | |
153 | ||
154 | #define COML_ONE_CHANNEL BIT(7) | |
155 | ||
156 | #define DEF_HSTRT 0x24 | |
157 | #define DEF_HSTOP 0xd4 | |
158 | #define DEF_VSTRT 0x04 | |
159 | #define DEF_VSTOP 0x94 | |
160 | ||
161 | #define COMF_HREF_LOW BIT(4) | |
162 | ||
163 | #define COMJ_PCLK_RISING BIT(4) | |
164 | #define COMJ_VSYNC_HIGH BIT(0) | |
165 | ||
166 | /* supported resolutions */ | |
167 | #define W_QCIF (DEF_HSTOP - DEF_HSTRT) | |
168 | #define W_CIF (W_QCIF << 1) | |
169 | #define H_QCIF (DEF_VSTOP - DEF_VSTRT) | |
170 | #define H_CIF (H_QCIF << 1) | |
171 | ||
172 | #define FRAME_RATE_MAX 30 | |
173 | ||
174 | ||
175 | struct ov6650_reg { | |
176 | u8 reg; | |
177 | u8 val; | |
178 | }; | |
179 | ||
180 | struct ov6650 { | |
181 | struct v4l2_subdev subdev; | |
afd9690c HV |
182 | struct v4l2_ctrl_handler hdl; |
183 | struct { | |
184 | /* exposure/autoexposure cluster */ | |
185 | struct v4l2_ctrl *autoexposure; | |
186 | struct v4l2_ctrl *exposure; | |
187 | }; | |
188 | struct { | |
189 | /* gain/autogain cluster */ | |
190 | struct v4l2_ctrl *autogain; | |
191 | struct v4l2_ctrl *gain; | |
192 | }; | |
193 | struct { | |
194 | /* blue/red/autowhitebalance cluster */ | |
195 | struct v4l2_ctrl *autowb; | |
196 | struct v4l2_ctrl *blue; | |
197 | struct v4l2_ctrl *red; | |
198 | }; | |
9aea470b | 199 | struct v4l2_clk *clk; |
2f6e2404 JK |
200 | bool half_scale; /* scale down output by 2 */ |
201 | struct v4l2_rect rect; /* sensor cropping window */ | |
202 | unsigned long pclk_limit; /* from host */ | |
203 | unsigned long pclk_max; /* from resolution and format */ | |
204 | struct v4l2_fract tpf; /* as requested with s_parm */ | |
f5fe58fd | 205 | u32 code; |
2f6e2404 JK |
206 | }; |
207 | ||
208 | ||
f5fe58fd BB |
209 | static u32 ov6650_codes[] = { |
210 | MEDIA_BUS_FMT_YUYV8_2X8, | |
211 | MEDIA_BUS_FMT_UYVY8_2X8, | |
212 | MEDIA_BUS_FMT_YVYU8_2X8, | |
213 | MEDIA_BUS_FMT_VYUY8_2X8, | |
214 | MEDIA_BUS_FMT_SBGGR8_1X8, | |
215 | MEDIA_BUS_FMT_Y8_1X8, | |
2f6e2404 JK |
216 | }; |
217 | ||
191ac914 JK |
218 | static const struct v4l2_mbus_framefmt ov6650_def_fmt = { |
219 | .width = W_CIF, | |
220 | .height = H_CIF, | |
221 | .code = MEDIA_BUS_FMT_SBGGR8_1X8, | |
222 | .colorspace = V4L2_COLORSPACE_SRGB, | |
223 | .field = V4L2_FIELD_NONE, | |
224 | .ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT, | |
225 | .quantization = V4L2_QUANTIZATION_DEFAULT, | |
226 | .xfer_func = V4L2_XFER_FUNC_DEFAULT, | |
227 | }; | |
228 | ||
2f6e2404 JK |
229 | /* read a register */ |
230 | static int ov6650_reg_read(struct i2c_client *client, u8 reg, u8 *val) | |
231 | { | |
232 | int ret; | |
233 | u8 data = reg; | |
234 | struct i2c_msg msg = { | |
235 | .addr = client->addr, | |
236 | .flags = 0, | |
237 | .len = 1, | |
238 | .buf = &data, | |
239 | }; | |
240 | ||
241 | ret = i2c_transfer(client->adapter, &msg, 1); | |
242 | if (ret < 0) | |
243 | goto err; | |
244 | ||
245 | msg.flags = I2C_M_RD; | |
246 | ret = i2c_transfer(client->adapter, &msg, 1); | |
247 | if (ret < 0) | |
248 | goto err; | |
249 | ||
250 | *val = data; | |
251 | return 0; | |
252 | ||
253 | err: | |
254 | dev_err(&client->dev, "Failed reading register 0x%02x!\n", reg); | |
255 | return ret; | |
256 | } | |
257 | ||
258 | /* write a register */ | |
259 | static int ov6650_reg_write(struct i2c_client *client, u8 reg, u8 val) | |
260 | { | |
261 | int ret; | |
262 | unsigned char data[2] = { reg, val }; | |
263 | struct i2c_msg msg = { | |
264 | .addr = client->addr, | |
265 | .flags = 0, | |
266 | .len = 2, | |
267 | .buf = data, | |
268 | }; | |
269 | ||
270 | ret = i2c_transfer(client->adapter, &msg, 1); | |
271 | udelay(100); | |
272 | ||
273 | if (ret < 0) { | |
274 | dev_err(&client->dev, "Failed writing register 0x%02x!\n", reg); | |
275 | return ret; | |
276 | } | |
277 | return 0; | |
278 | } | |
279 | ||
280 | ||
281 | /* Read a register, alter its bits, write it back */ | |
282 | static int ov6650_reg_rmw(struct i2c_client *client, u8 reg, u8 set, u8 mask) | |
283 | { | |
284 | u8 val; | |
285 | int ret; | |
286 | ||
287 | ret = ov6650_reg_read(client, reg, &val); | |
288 | if (ret) { | |
289 | dev_err(&client->dev, | |
290 | "[Read]-Modify-Write of register 0x%02x failed!\n", | |
291 | reg); | |
292 | return ret; | |
293 | } | |
294 | ||
295 | val &= ~mask; | |
296 | val |= set; | |
297 | ||
298 | ret = ov6650_reg_write(client, reg, val); | |
299 | if (ret) | |
300 | dev_err(&client->dev, | |
301 | "Read-Modify-[Write] of register 0x%02x failed!\n", | |
302 | reg); | |
303 | ||
304 | return ret; | |
305 | } | |
306 | ||
307 | static struct ov6650 *to_ov6650(const struct i2c_client *client) | |
308 | { | |
309 | return container_of(i2c_get_clientdata(client), struct ov6650, subdev); | |
310 | } | |
311 | ||
312 | /* Start/Stop streaming from the device */ | |
313 | static int ov6650_s_stream(struct v4l2_subdev *sd, int enable) | |
314 | { | |
315 | return 0; | |
316 | } | |
317 | ||
2f6e2404 | 318 | /* Get status of additional camera capabilities */ |
afd9690c | 319 | static int ov6550_g_volatile_ctrl(struct v4l2_ctrl *ctrl) |
2f6e2404 | 320 | { |
afd9690c HV |
321 | struct ov6650 *priv = container_of(ctrl->handler, struct ov6650, hdl); |
322 | struct v4l2_subdev *sd = &priv->subdev; | |
2f6e2404 | 323 | struct i2c_client *client = v4l2_get_subdevdata(sd); |
afd9690c | 324 | uint8_t reg, reg2; |
2e56d933 | 325 | int ret; |
2f6e2404 JK |
326 | |
327 | switch (ctrl->id) { | |
328 | case V4L2_CID_AUTOGAIN: | |
afd9690c HV |
329 | ret = ov6650_reg_read(client, REG_GAIN, ®); |
330 | if (!ret) | |
331 | priv->gain->val = reg; | |
332 | return ret; | |
2f6e2404 | 333 | case V4L2_CID_AUTO_WHITE_BALANCE: |
afd9690c HV |
334 | ret = ov6650_reg_read(client, REG_BLUE, ®); |
335 | if (!ret) | |
336 | ret = ov6650_reg_read(client, REG_RED, ®2); | |
337 | if (!ret) { | |
338 | priv->blue->val = reg; | |
339 | priv->red->val = reg2; | |
2f6e2404 | 340 | } |
afd9690c | 341 | return ret; |
2f6e2404 | 342 | case V4L2_CID_EXPOSURE_AUTO: |
afd9690c HV |
343 | ret = ov6650_reg_read(client, REG_AECH, ®); |
344 | if (!ret) | |
345 | priv->exposure->val = reg; | |
346 | return ret; | |
2f6e2404 | 347 | } |
afd9690c | 348 | return -EINVAL; |
2f6e2404 JK |
349 | } |
350 | ||
351 | /* Set status of additional camera capabilities */ | |
afd9690c | 352 | static int ov6550_s_ctrl(struct v4l2_ctrl *ctrl) |
2f6e2404 | 353 | { |
afd9690c HV |
354 | struct ov6650 *priv = container_of(ctrl->handler, struct ov6650, hdl); |
355 | struct v4l2_subdev *sd = &priv->subdev; | |
2f6e2404 | 356 | struct i2c_client *client = v4l2_get_subdevdata(sd); |
2e56d933 | 357 | int ret; |
2f6e2404 JK |
358 | |
359 | switch (ctrl->id) { | |
360 | case V4L2_CID_AUTOGAIN: | |
361 | ret = ov6650_reg_rmw(client, REG_COMB, | |
afd9690c HV |
362 | ctrl->val ? COMB_AGC : 0, COMB_AGC); |
363 | if (!ret && !ctrl->val) | |
364 | ret = ov6650_reg_write(client, REG_GAIN, priv->gain->val); | |
365 | return ret; | |
2f6e2404 JK |
366 | case V4L2_CID_AUTO_WHITE_BALANCE: |
367 | ret = ov6650_reg_rmw(client, REG_COMB, | |
afd9690c HV |
368 | ctrl->val ? COMB_AWB : 0, COMB_AWB); |
369 | if (!ret && !ctrl->val) { | |
370 | ret = ov6650_reg_write(client, REG_BLUE, priv->blue->val); | |
371 | if (!ret) | |
372 | ret = ov6650_reg_write(client, REG_RED, | |
373 | priv->red->val); | |
374 | } | |
375 | return ret; | |
2f6e2404 | 376 | case V4L2_CID_SATURATION: |
afd9690c | 377 | return ov6650_reg_rmw(client, REG_SAT, SET_SAT(ctrl->val), |
2f6e2404 | 378 | SAT_MASK); |
2f6e2404 | 379 | case V4L2_CID_HUE: |
afd9690c | 380 | return ov6650_reg_rmw(client, REG_HUE, SET_HUE(ctrl->val), |
2f6e2404 | 381 | HUE_MASK); |
2f6e2404 | 382 | case V4L2_CID_BRIGHTNESS: |
afd9690c | 383 | return ov6650_reg_write(client, REG_BRT, ctrl->val); |
2f6e2404 | 384 | case V4L2_CID_EXPOSURE_AUTO: |
2e56d933 JK |
385 | ret = ov6650_reg_rmw(client, REG_COMB, ctrl->val == |
386 | V4L2_EXPOSURE_AUTO ? COMB_AEC : 0, COMB_AEC); | |
afd9690c HV |
387 | if (!ret && ctrl->val == V4L2_EXPOSURE_MANUAL) |
388 | ret = ov6650_reg_write(client, REG_AECH, | |
389 | priv->exposure->val); | |
390 | return ret; | |
2f6e2404 | 391 | case V4L2_CID_GAMMA: |
afd9690c | 392 | return ov6650_reg_write(client, REG_GAM1, ctrl->val); |
2f6e2404 | 393 | case V4L2_CID_VFLIP: |
afd9690c HV |
394 | return ov6650_reg_rmw(client, REG_COMB, |
395 | ctrl->val ? COMB_FLIP_V : 0, COMB_FLIP_V); | |
2f6e2404 | 396 | case V4L2_CID_HFLIP: |
afd9690c HV |
397 | return ov6650_reg_rmw(client, REG_COMB, |
398 | ctrl->val ? COMB_FLIP_H : 0, COMB_FLIP_H); | |
2f6e2404 JK |
399 | } |
400 | ||
afd9690c | 401 | return -EINVAL; |
2f6e2404 JK |
402 | } |
403 | ||
2f6e2404 JK |
404 | #ifdef CONFIG_VIDEO_ADV_DEBUG |
405 | static int ov6650_get_register(struct v4l2_subdev *sd, | |
406 | struct v4l2_dbg_register *reg) | |
407 | { | |
408 | struct i2c_client *client = v4l2_get_subdevdata(sd); | |
409 | int ret; | |
410 | u8 val; | |
411 | ||
412 | if (reg->reg & ~0xff) | |
413 | return -EINVAL; | |
414 | ||
415 | reg->size = 1; | |
416 | ||
417 | ret = ov6650_reg_read(client, reg->reg, &val); | |
418 | if (!ret) | |
419 | reg->val = (__u64)val; | |
420 | ||
421 | return ret; | |
422 | } | |
423 | ||
424 | static int ov6650_set_register(struct v4l2_subdev *sd, | |
977ba3b1 | 425 | const struct v4l2_dbg_register *reg) |
2f6e2404 JK |
426 | { |
427 | struct i2c_client *client = v4l2_get_subdevdata(sd); | |
428 | ||
429 | if (reg->reg & ~0xff || reg->val & ~0xff) | |
430 | return -EINVAL; | |
431 | ||
432 | return ov6650_reg_write(client, reg->reg, reg->val); | |
433 | } | |
434 | #endif | |
435 | ||
4ec10bac LP |
436 | static int ov6650_s_power(struct v4l2_subdev *sd, int on) |
437 | { | |
438 | struct i2c_client *client = v4l2_get_subdevdata(sd); | |
9aea470b | 439 | struct ov6650 *priv = to_ov6650(client); |
23a52386 | 440 | int ret = 0; |
4ec10bac | 441 | |
23a52386 JK |
442 | if (on) |
443 | ret = v4l2_clk_enable(priv->clk); | |
444 | else | |
445 | v4l2_clk_disable(priv->clk); | |
446 | ||
447 | return ret; | |
4ec10bac LP |
448 | } |
449 | ||
10d5509c HV |
450 | static int ov6650_get_selection(struct v4l2_subdev *sd, |
451 | struct v4l2_subdev_pad_config *cfg, | |
452 | struct v4l2_subdev_selection *sel) | |
2f6e2404 JK |
453 | { |
454 | struct i2c_client *client = v4l2_get_subdevdata(sd); | |
455 | struct ov6650 *priv = to_ov6650(client); | |
456 | ||
10d5509c HV |
457 | if (sel->which != V4L2_SUBDEV_FORMAT_ACTIVE) |
458 | return -EINVAL; | |
2f6e2404 | 459 | |
10d5509c HV |
460 | switch (sel->target) { |
461 | case V4L2_SEL_TGT_CROP_BOUNDS: | |
462 | case V4L2_SEL_TGT_CROP_DEFAULT: | |
463 | sel->r.left = DEF_HSTRT << 1; | |
464 | sel->r.top = DEF_VSTRT << 1; | |
465 | sel->r.width = W_CIF; | |
466 | sel->r.height = H_CIF; | |
467 | return 0; | |
468 | case V4L2_SEL_TGT_CROP: | |
469 | sel->r = priv->rect; | |
470 | return 0; | |
471 | default: | |
472 | return -EINVAL; | |
473 | } | |
2f6e2404 JK |
474 | } |
475 | ||
10d5509c HV |
476 | static int ov6650_set_selection(struct v4l2_subdev *sd, |
477 | struct v4l2_subdev_pad_config *cfg, | |
478 | struct v4l2_subdev_selection *sel) | |
2f6e2404 JK |
479 | { |
480 | struct i2c_client *client = v4l2_get_subdevdata(sd); | |
481 | struct ov6650 *priv = to_ov6650(client); | |
2f6e2404 JK |
482 | int ret; |
483 | ||
10d5509c HV |
484 | if (sel->which != V4L2_SUBDEV_FORMAT_ACTIVE || |
485 | sel->target != V4L2_SEL_TGT_CROP) | |
2f6e2404 JK |
486 | return -EINVAL; |
487 | ||
883595f2 JK |
488 | v4l_bound_align_image(&sel->r.width, 2, W_CIF, 1, |
489 | &sel->r.height, 2, H_CIF, 1, 0); | |
490 | v4l_bound_align_image(&sel->r.left, DEF_HSTRT << 1, | |
491 | (DEF_HSTRT << 1) + W_CIF - (__s32)sel->r.width, 1, | |
492 | &sel->r.top, DEF_VSTRT << 1, | |
493 | (DEF_VSTRT << 1) + H_CIF - (__s32)sel->r.height, | |
494 | 1, 0); | |
2f6e2404 | 495 | |
883595f2 | 496 | ret = ov6650_reg_write(client, REG_HSTRT, sel->r.left >> 1); |
2f6e2404 | 497 | if (!ret) { |
4cc21b49 | 498 | priv->rect.width += priv->rect.left - sel->r.left; |
883595f2 | 499 | priv->rect.left = sel->r.left; |
2f6e2404 | 500 | ret = ov6650_reg_write(client, REG_HSTOP, |
883595f2 | 501 | (sel->r.left + sel->r.width) >> 1); |
2f6e2404 JK |
502 | } |
503 | if (!ret) { | |
883595f2 JK |
504 | priv->rect.width = sel->r.width; |
505 | ret = ov6650_reg_write(client, REG_VSTRT, sel->r.top >> 1); | |
2f6e2404 JK |
506 | } |
507 | if (!ret) { | |
4cc21b49 | 508 | priv->rect.height += priv->rect.top - sel->r.top; |
883595f2 | 509 | priv->rect.top = sel->r.top; |
2f6e2404 | 510 | ret = ov6650_reg_write(client, REG_VSTOP, |
883595f2 | 511 | (sel->r.top + sel->r.height) >> 1); |
2f6e2404 JK |
512 | } |
513 | if (!ret) | |
883595f2 | 514 | priv->rect.height = sel->r.height; |
2f6e2404 JK |
515 | |
516 | return ret; | |
517 | } | |
518 | ||
da298c6d HV |
519 | static int ov6650_get_fmt(struct v4l2_subdev *sd, |
520 | struct v4l2_subdev_pad_config *cfg, | |
521 | struct v4l2_subdev_format *format) | |
2f6e2404 | 522 | { |
da298c6d | 523 | struct v4l2_mbus_framefmt *mf = &format->format; |
2f6e2404 JK |
524 | struct i2c_client *client = v4l2_get_subdevdata(sd); |
525 | struct ov6650 *priv = to_ov6650(client); | |
526 | ||
da298c6d HV |
527 | if (format->pad) |
528 | return -EINVAL; | |
529 | ||
191ac914 JK |
530 | /* initialize response with default media bus frame format */ |
531 | *mf = ov6650_def_fmt; | |
532 | ||
533 | /* update media bus format code and frame size */ | |
2f6e2404 JK |
534 | mf->width = priv->rect.width >> priv->half_scale; |
535 | mf->height = priv->rect.height >> priv->half_scale; | |
536 | mf->code = priv->code; | |
2f6e2404 JK |
537 | |
538 | return 0; | |
539 | } | |
540 | ||
541 | static bool is_unscaled_ok(int width, int height, struct v4l2_rect *rect) | |
542 | { | |
d889eb1e | 543 | return width > rect->width >> 1 || height > rect->height >> 1; |
2f6e2404 JK |
544 | } |
545 | ||
546 | static u8 to_clkrc(struct v4l2_fract *timeperframe, | |
547 | unsigned long pclk_limit, unsigned long pclk_max) | |
548 | { | |
549 | unsigned long pclk; | |
550 | ||
551 | if (timeperframe->numerator && timeperframe->denominator) | |
552 | pclk = pclk_max * timeperframe->denominator / | |
553 | (FRAME_RATE_MAX * timeperframe->numerator); | |
554 | else | |
555 | pclk = pclk_max; | |
556 | ||
557 | if (pclk_limit && pclk_limit < pclk) | |
558 | pclk = pclk_limit; | |
559 | ||
560 | return (pclk_max - 1) / pclk; | |
561 | } | |
562 | ||
563 | /* set the format we will capture in */ | |
564 | static int ov6650_s_fmt(struct v4l2_subdev *sd, struct v4l2_mbus_framefmt *mf) | |
565 | { | |
566 | struct i2c_client *client = v4l2_get_subdevdata(sd); | |
2f6e2404 JK |
567 | struct ov6650 *priv = to_ov6650(client); |
568 | bool half_scale = !is_unscaled_ok(mf->width, mf->height, &priv->rect); | |
10d5509c HV |
569 | struct v4l2_subdev_selection sel = { |
570 | .which = V4L2_SUBDEV_FORMAT_ACTIVE, | |
571 | .target = V4L2_SEL_TGT_CROP, | |
572 | .r.left = priv->rect.left + (priv->rect.width >> 1) - | |
573 | (mf->width >> (1 - half_scale)), | |
574 | .r.top = priv->rect.top + (priv->rect.height >> 1) - | |
575 | (mf->height >> (1 - half_scale)), | |
576 | .r.width = mf->width << half_scale, | |
577 | .r.height = mf->height << half_scale, | |
2f6e2404 | 578 | }; |
f5fe58fd | 579 | u32 code = mf->code; |
2f6e2404 JK |
580 | unsigned long mclk, pclk; |
581 | u8 coma_set = 0, coma_mask = 0, coml_set, coml_mask, clkrc; | |
582 | int ret; | |
583 | ||
584 | /* select color matrix configuration for given color encoding */ | |
585 | switch (code) { | |
f5fe58fd | 586 | case MEDIA_BUS_FMT_Y8_1X8: |
2f6e2404 JK |
587 | dev_dbg(&client->dev, "pixel format GREY8_1X8\n"); |
588 | coma_mask |= COMA_RGB | COMA_WORD_SWAP | COMA_BYTE_SWAP; | |
589 | coma_set |= COMA_BW; | |
590 | break; | |
f5fe58fd | 591 | case MEDIA_BUS_FMT_YUYV8_2X8: |
2f6e2404 JK |
592 | dev_dbg(&client->dev, "pixel format YUYV8_2X8_LE\n"); |
593 | coma_mask |= COMA_RGB | COMA_BW | COMA_BYTE_SWAP; | |
594 | coma_set |= COMA_WORD_SWAP; | |
595 | break; | |
f5fe58fd | 596 | case MEDIA_BUS_FMT_YVYU8_2X8: |
2f6e2404 JK |
597 | dev_dbg(&client->dev, "pixel format YVYU8_2X8_LE (untested)\n"); |
598 | coma_mask |= COMA_RGB | COMA_BW | COMA_WORD_SWAP | | |
599 | COMA_BYTE_SWAP; | |
600 | break; | |
f5fe58fd | 601 | case MEDIA_BUS_FMT_UYVY8_2X8: |
2f6e2404 JK |
602 | dev_dbg(&client->dev, "pixel format YUYV8_2X8_BE\n"); |
603 | if (half_scale) { | |
604 | coma_mask |= COMA_RGB | COMA_BW | COMA_WORD_SWAP; | |
605 | coma_set |= COMA_BYTE_SWAP; | |
606 | } else { | |
607 | coma_mask |= COMA_RGB | COMA_BW; | |
608 | coma_set |= COMA_BYTE_SWAP | COMA_WORD_SWAP; | |
609 | } | |
610 | break; | |
f5fe58fd | 611 | case MEDIA_BUS_FMT_VYUY8_2X8: |
2f6e2404 JK |
612 | dev_dbg(&client->dev, "pixel format YVYU8_2X8_BE (untested)\n"); |
613 | if (half_scale) { | |
614 | coma_mask |= COMA_RGB | COMA_BW; | |
615 | coma_set |= COMA_BYTE_SWAP | COMA_WORD_SWAP; | |
616 | } else { | |
617 | coma_mask |= COMA_RGB | COMA_BW | COMA_WORD_SWAP; | |
618 | coma_set |= COMA_BYTE_SWAP; | |
619 | } | |
620 | break; | |
f5fe58fd | 621 | case MEDIA_BUS_FMT_SBGGR8_1X8: |
2f6e2404 JK |
622 | dev_dbg(&client->dev, "pixel format SBGGR8_1X8 (untested)\n"); |
623 | coma_mask |= COMA_BW | COMA_BYTE_SWAP | COMA_WORD_SWAP; | |
624 | coma_set |= COMA_RAW_RGB | COMA_RGB; | |
625 | break; | |
2f6e2404 JK |
626 | default: |
627 | dev_err(&client->dev, "Pixel format not handled: 0x%x\n", code); | |
628 | return -EINVAL; | |
629 | } | |
2f6e2404 | 630 | |
f5fe58fd BB |
631 | if (code == MEDIA_BUS_FMT_Y8_1X8 || |
632 | code == MEDIA_BUS_FMT_SBGGR8_1X8) { | |
2f6e2404 JK |
633 | coml_mask = COML_ONE_CHANNEL; |
634 | coml_set = 0; | |
635 | priv->pclk_max = 4000000; | |
636 | } else { | |
637 | coml_mask = 0; | |
638 | coml_set = COML_ONE_CHANNEL; | |
639 | priv->pclk_max = 8000000; | |
640 | } | |
641 | ||
2f6e2404 JK |
642 | if (half_scale) { |
643 | dev_dbg(&client->dev, "max resolution: QCIF\n"); | |
644 | coma_set |= COMA_QCIF; | |
645 | priv->pclk_max /= 2; | |
646 | } else { | |
647 | dev_dbg(&client->dev, "max resolution: CIF\n"); | |
648 | coma_mask |= COMA_QCIF; | |
649 | } | |
2f6e2404 | 650 | |
23a52386 JK |
651 | clkrc = CLKRC_12MHz; |
652 | mclk = 12000000; | |
653 | priv->pclk_limit = 1334000; | |
654 | dev_dbg(&client->dev, "using 12MHz input clock\n"); | |
2f6e2404 JK |
655 | |
656 | clkrc |= to_clkrc(&priv->tpf, priv->pclk_limit, priv->pclk_max); | |
657 | ||
658 | pclk = priv->pclk_max / GET_CLKRC_DIV(clkrc); | |
659 | dev_dbg(&client->dev, "pixel clock divider: %ld.%ld\n", | |
660 | mclk / pclk, 10 * mclk % pclk / pclk); | |
661 | ||
10d5509c | 662 | ret = ov6650_set_selection(sd, NULL, &sel); |
2f6e2404 JK |
663 | if (!ret) |
664 | ret = ov6650_reg_rmw(client, REG_COMA, coma_set, coma_mask); | |
665 | if (!ret) | |
666 | ret = ov6650_reg_write(client, REG_CLKRC, clkrc); | |
34efe312 JK |
667 | if (!ret) { |
668 | priv->half_scale = half_scale; | |
669 | ||
2f6e2404 | 670 | ret = ov6650_reg_rmw(client, REG_COML, coml_set, coml_mask); |
34efe312 JK |
671 | } |
672 | if (!ret) | |
673 | priv->code = code; | |
2f6e2404 | 674 | |
2f6e2404 JK |
675 | return ret; |
676 | } | |
677 | ||
717fd5b4 HV |
678 | static int ov6650_set_fmt(struct v4l2_subdev *sd, |
679 | struct v4l2_subdev_pad_config *cfg, | |
680 | struct v4l2_subdev_format *format) | |
2f6e2404 | 681 | { |
717fd5b4 | 682 | struct v4l2_mbus_framefmt *mf = &format->format; |
2f6e2404 JK |
683 | struct i2c_client *client = v4l2_get_subdevdata(sd); |
684 | struct ov6650 *priv = to_ov6650(client); | |
685 | ||
717fd5b4 HV |
686 | if (format->pad) |
687 | return -EINVAL; | |
688 | ||
2f6e2404 JK |
689 | if (is_unscaled_ok(mf->width, mf->height, &priv->rect)) |
690 | v4l_bound_align_image(&mf->width, 2, W_CIF, 1, | |
691 | &mf->height, 2, H_CIF, 1, 0); | |
692 | ||
2f6e2404 | 693 | switch (mf->code) { |
f5fe58fd BB |
694 | case MEDIA_BUS_FMT_Y10_1X10: |
695 | mf->code = MEDIA_BUS_FMT_Y8_1X8; | |
06eeefe8 | 696 | /* fall through */ |
f5fe58fd BB |
697 | case MEDIA_BUS_FMT_Y8_1X8: |
698 | case MEDIA_BUS_FMT_YVYU8_2X8: | |
699 | case MEDIA_BUS_FMT_YUYV8_2X8: | |
700 | case MEDIA_BUS_FMT_VYUY8_2X8: | |
701 | case MEDIA_BUS_FMT_UYVY8_2X8: | |
2f6e2404 JK |
702 | break; |
703 | default: | |
f5fe58fd | 704 | mf->code = MEDIA_BUS_FMT_SBGGR8_1X8; |
06eeefe8 | 705 | /* fall through */ |
f5fe58fd | 706 | case MEDIA_BUS_FMT_SBGGR8_1X8: |
2f6e2404 JK |
707 | break; |
708 | } | |
709 | ||
191ac914 JK |
710 | if (format->which == V4L2_SUBDEV_FORMAT_TRY) { |
711 | /* store media bus format code and frame size in pad config */ | |
712 | cfg->try_fmt.width = mf->width; | |
713 | cfg->try_fmt.height = mf->height; | |
714 | cfg->try_fmt.code = mf->code; | |
717fd5b4 | 715 | |
191ac914 JK |
716 | /* return default mbus frame format updated with pad config */ |
717 | *mf = ov6650_def_fmt; | |
718 | mf->width = cfg->try_fmt.width; | |
719 | mf->height = cfg->try_fmt.height; | |
720 | mf->code = cfg->try_fmt.code; | |
721 | ||
722 | } else { | |
723 | /* apply new media bus format code and frame size */ | |
724 | int ret = ov6650_s_fmt(sd, mf); | |
725 | ||
726 | if (ret) | |
727 | return ret; | |
728 | ||
729 | /* return default format updated with active size and code */ | |
730 | *mf = ov6650_def_fmt; | |
731 | mf->width = priv->rect.width >> priv->half_scale; | |
732 | mf->height = priv->rect.height >> priv->half_scale; | |
733 | mf->code = priv->code; | |
734 | } | |
2f6e2404 JK |
735 | return 0; |
736 | } | |
737 | ||
ebcff5fc HV |
738 | static int ov6650_enum_mbus_code(struct v4l2_subdev *sd, |
739 | struct v4l2_subdev_pad_config *cfg, | |
740 | struct v4l2_subdev_mbus_code_enum *code) | |
2f6e2404 | 741 | { |
ebcff5fc | 742 | if (code->pad || code->index >= ARRAY_SIZE(ov6650_codes)) |
2f6e2404 JK |
743 | return -EINVAL; |
744 | ||
ebcff5fc | 745 | code->code = ov6650_codes[code->index]; |
2f6e2404 JK |
746 | return 0; |
747 | } | |
748 | ||
749 | static int ov6650_g_parm(struct v4l2_subdev *sd, struct v4l2_streamparm *parms) | |
750 | { | |
751 | struct i2c_client *client = v4l2_get_subdevdata(sd); | |
752 | struct ov6650 *priv = to_ov6650(client); | |
753 | struct v4l2_captureparm *cp = &parms->parm.capture; | |
754 | ||
755 | if (parms->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) | |
756 | return -EINVAL; | |
757 | ||
758 | memset(cp, 0, sizeof(*cp)); | |
759 | cp->capability = V4L2_CAP_TIMEPERFRAME; | |
760 | cp->timeperframe.numerator = GET_CLKRC_DIV(to_clkrc(&priv->tpf, | |
761 | priv->pclk_limit, priv->pclk_max)); | |
762 | cp->timeperframe.denominator = FRAME_RATE_MAX; | |
763 | ||
764 | dev_dbg(&client->dev, "Frame interval: %u/%u s\n", | |
765 | cp->timeperframe.numerator, cp->timeperframe.denominator); | |
766 | ||
767 | return 0; | |
768 | } | |
769 | ||
770 | static int ov6650_s_parm(struct v4l2_subdev *sd, struct v4l2_streamparm *parms) | |
771 | { | |
772 | struct i2c_client *client = v4l2_get_subdevdata(sd); | |
773 | struct ov6650 *priv = to_ov6650(client); | |
774 | struct v4l2_captureparm *cp = &parms->parm.capture; | |
775 | struct v4l2_fract *tpf = &cp->timeperframe; | |
776 | int div, ret; | |
777 | u8 clkrc; | |
778 | ||
779 | if (parms->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) | |
780 | return -EINVAL; | |
781 | ||
782 | if (cp->extendedmode != 0) | |
783 | return -EINVAL; | |
784 | ||
785 | if (tpf->numerator == 0 || tpf->denominator == 0) | |
786 | div = 1; /* Reset to full rate */ | |
787 | else | |
788 | div = (tpf->numerator * FRAME_RATE_MAX) / tpf->denominator; | |
789 | ||
790 | if (div == 0) | |
791 | div = 1; | |
792 | else if (div > GET_CLKRC_DIV(CLKRC_DIV_MASK)) | |
793 | div = GET_CLKRC_DIV(CLKRC_DIV_MASK); | |
794 | ||
795 | /* | |
796 | * Keep result to be used as tpf limit | |
797 | * for subseqent clock divider calculations | |
798 | */ | |
799 | priv->tpf.numerator = div; | |
800 | priv->tpf.denominator = FRAME_RATE_MAX; | |
801 | ||
802 | clkrc = to_clkrc(&priv->tpf, priv->pclk_limit, priv->pclk_max); | |
803 | ||
804 | ret = ov6650_reg_rmw(client, REG_CLKRC, clkrc, CLKRC_DIV_MASK); | |
805 | if (!ret) { | |
806 | tpf->numerator = GET_CLKRC_DIV(clkrc); | |
807 | tpf->denominator = FRAME_RATE_MAX; | |
808 | } | |
809 | ||
810 | return ret; | |
811 | } | |
812 | ||
813 | /* Soft reset the camera. This has nothing to do with the RESET pin! */ | |
814 | static int ov6650_reset(struct i2c_client *client) | |
815 | { | |
816 | int ret; | |
817 | ||
818 | dev_dbg(&client->dev, "reset\n"); | |
819 | ||
820 | ret = ov6650_reg_rmw(client, REG_COMA, COMA_RESET, 0); | |
821 | if (ret) | |
822 | dev_err(&client->dev, | |
25985edc | 823 | "An error occurred while entering soft reset!\n"); |
2f6e2404 JK |
824 | |
825 | return ret; | |
826 | } | |
827 | ||
828 | /* program default register values */ | |
829 | static int ov6650_prog_dflt(struct i2c_client *client) | |
830 | { | |
831 | int ret; | |
832 | ||
833 | dev_dbg(&client->dev, "initializing\n"); | |
834 | ||
835 | ret = ov6650_reg_write(client, REG_COMA, 0); /* ~COMA_RESET */ | |
836 | if (!ret) | |
837 | ret = ov6650_reg_rmw(client, REG_COMB, 0, COMB_BAND_FILTER); | |
838 | ||
839 | return ret; | |
840 | } | |
841 | ||
14178aa5 | 842 | static int ov6650_video_probe(struct i2c_client *client) |
2f6e2404 | 843 | { |
4bbc6d52 | 844 | struct ov6650 *priv = to_ov6650(client); |
2f6e2404 | 845 | u8 pidh, pidl, midh, midl; |
4bbc6d52 LP |
846 | int ret; |
847 | ||
13c4ad86 JK |
848 | priv->clk = v4l2_clk_get(&client->dev, NULL); |
849 | if (IS_ERR(priv->clk)) { | |
850 | ret = PTR_ERR(priv->clk); | |
851 | dev_err(&client->dev, "v4l2_clk request err: %d\n", ret); | |
852 | return ret; | |
853 | } | |
854 | ||
4bbc6d52 LP |
855 | ret = ov6650_s_power(&priv->subdev, 1); |
856 | if (ret < 0) | |
13c4ad86 | 857 | goto eclkput; |
2f6e2404 | 858 | |
3b0d727b JK |
859 | msleep(20); |
860 | ||
2f6e2404 JK |
861 | /* |
862 | * check and show product ID and manufacturer ID | |
863 | */ | |
864 | ret = ov6650_reg_read(client, REG_PIDH, &pidh); | |
865 | if (!ret) | |
866 | ret = ov6650_reg_read(client, REG_PIDL, &pidl); | |
867 | if (!ret) | |
868 | ret = ov6650_reg_read(client, REG_MIDH, &midh); | |
869 | if (!ret) | |
870 | ret = ov6650_reg_read(client, REG_MIDL, &midl); | |
871 | ||
872 | if (ret) | |
4bbc6d52 | 873 | goto done; |
2f6e2404 JK |
874 | |
875 | if ((pidh != OV6650_PIDH) || (pidl != OV6650_PIDL)) { | |
876 | dev_err(&client->dev, "Product ID error 0x%02x:0x%02x\n", | |
877 | pidh, pidl); | |
4bbc6d52 LP |
878 | ret = -ENODEV; |
879 | goto done; | |
2f6e2404 JK |
880 | } |
881 | ||
882 | dev_info(&client->dev, | |
883 | "ov6650 Product ID 0x%02x:0x%02x Manufacturer ID 0x%02x:0x%02x\n", | |
884 | pidh, pidl, midh, midl); | |
885 | ||
886 | ret = ov6650_reset(client); | |
887 | if (!ret) | |
888 | ret = ov6650_prog_dflt(client); | |
4bbc6d52 LP |
889 | if (!ret) |
890 | ret = v4l2_ctrl_handler_setup(&priv->hdl); | |
2f6e2404 | 891 | |
4bbc6d52 LP |
892 | done: |
893 | ov6650_s_power(&priv->subdev, 0); | |
13c4ad86 JK |
894 | if (!ret) |
895 | return 0; | |
896 | eclkput: | |
897 | v4l2_clk_put(priv->clk); | |
898 | ||
2f6e2404 JK |
899 | return ret; |
900 | } | |
901 | ||
afd9690c HV |
902 | static const struct v4l2_ctrl_ops ov6550_ctrl_ops = { |
903 | .g_volatile_ctrl = ov6550_g_volatile_ctrl, | |
904 | .s_ctrl = ov6550_s_ctrl, | |
2f6e2404 JK |
905 | }; |
906 | ||
6713c88f | 907 | static const struct v4l2_subdev_core_ops ov6650_core_ops = { |
2f6e2404 JK |
908 | #ifdef CONFIG_VIDEO_ADV_DEBUG |
909 | .g_register = ov6650_get_register, | |
910 | .s_register = ov6650_set_register, | |
911 | #endif | |
4ec10bac | 912 | .s_power = ov6650_s_power, |
2f6e2404 JK |
913 | }; |
914 | ||
db669e79 | 915 | /* Request bus settings on camera side */ |
59ca25b7 GL |
916 | static int ov6650_g_mbus_config(struct v4l2_subdev *sd, |
917 | struct v4l2_mbus_config *cfg) | |
918 | { | |
59ca25b7 GL |
919 | |
920 | cfg->flags = V4L2_MBUS_MASTER | | |
921 | V4L2_MBUS_PCLK_SAMPLE_RISING | V4L2_MBUS_PCLK_SAMPLE_FALLING | | |
922 | V4L2_MBUS_HSYNC_ACTIVE_HIGH | V4L2_MBUS_HSYNC_ACTIVE_LOW | | |
923 | V4L2_MBUS_VSYNC_ACTIVE_HIGH | V4L2_MBUS_VSYNC_ACTIVE_LOW | | |
924 | V4L2_MBUS_DATA_ACTIVE_HIGH; | |
925 | cfg->type = V4L2_MBUS_PARALLEL; | |
59ca25b7 GL |
926 | |
927 | return 0; | |
928 | } | |
929 | ||
db669e79 | 930 | /* Alter bus settings on camera side */ |
59ca25b7 GL |
931 | static int ov6650_s_mbus_config(struct v4l2_subdev *sd, |
932 | const struct v4l2_mbus_config *cfg) | |
933 | { | |
934 | struct i2c_client *client = v4l2_get_subdevdata(sd); | |
59ca25b7 GL |
935 | int ret; |
936 | ||
23a52386 | 937 | if (cfg->flags & V4L2_MBUS_PCLK_SAMPLE_RISING) |
59ca25b7 GL |
938 | ret = ov6650_reg_rmw(client, REG_COMJ, COMJ_PCLK_RISING, 0); |
939 | else | |
940 | ret = ov6650_reg_rmw(client, REG_COMJ, 0, COMJ_PCLK_RISING); | |
941 | if (ret) | |
942 | return ret; | |
943 | ||
23a52386 | 944 | if (cfg->flags & V4L2_MBUS_HSYNC_ACTIVE_LOW) |
59ca25b7 GL |
945 | ret = ov6650_reg_rmw(client, REG_COMF, COMF_HREF_LOW, 0); |
946 | else | |
947 | ret = ov6650_reg_rmw(client, REG_COMF, 0, COMF_HREF_LOW); | |
948 | if (ret) | |
949 | return ret; | |
950 | ||
23a52386 | 951 | if (cfg->flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH) |
59ca25b7 GL |
952 | ret = ov6650_reg_rmw(client, REG_COMJ, COMJ_VSYNC_HIGH, 0); |
953 | else | |
954 | ret = ov6650_reg_rmw(client, REG_COMJ, 0, COMJ_VSYNC_HIGH); | |
955 | ||
956 | return ret; | |
957 | } | |
958 | ||
6713c88f | 959 | static const struct v4l2_subdev_video_ops ov6650_video_ops = { |
2f6e2404 | 960 | .s_stream = ov6650_s_stream, |
2f6e2404 JK |
961 | .g_parm = ov6650_g_parm, |
962 | .s_parm = ov6650_s_parm, | |
59ca25b7 GL |
963 | .g_mbus_config = ov6650_g_mbus_config, |
964 | .s_mbus_config = ov6650_s_mbus_config, | |
2f6e2404 JK |
965 | }; |
966 | ||
ebcff5fc HV |
967 | static const struct v4l2_subdev_pad_ops ov6650_pad_ops = { |
968 | .enum_mbus_code = ov6650_enum_mbus_code, | |
10d5509c HV |
969 | .get_selection = ov6650_get_selection, |
970 | .set_selection = ov6650_set_selection, | |
da298c6d | 971 | .get_fmt = ov6650_get_fmt, |
717fd5b4 | 972 | .set_fmt = ov6650_set_fmt, |
ebcff5fc HV |
973 | }; |
974 | ||
6713c88f | 975 | static const struct v4l2_subdev_ops ov6650_subdev_ops = { |
2f6e2404 JK |
976 | .core = &ov6650_core_ops, |
977 | .video = &ov6650_video_ops, | |
ebcff5fc | 978 | .pad = &ov6650_pad_ops, |
2f6e2404 JK |
979 | }; |
980 | ||
981 | /* | |
982 | * i2c_driver function | |
983 | */ | |
984 | static int ov6650_probe(struct i2c_client *client, | |
985 | const struct i2c_device_id *did) | |
986 | { | |
987 | struct ov6650 *priv; | |
2f6e2404 JK |
988 | int ret; |
989 | ||
70e176a5 | 990 | priv = devm_kzalloc(&client->dev, sizeof(*priv), GFP_KERNEL); |
0fd58435 | 991 | if (!priv) |
2f6e2404 | 992 | return -ENOMEM; |
2f6e2404 JK |
993 | |
994 | v4l2_i2c_subdev_init(&priv->subdev, client, &ov6650_subdev_ops); | |
afd9690c HV |
995 | v4l2_ctrl_handler_init(&priv->hdl, 13); |
996 | v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops, | |
997 | V4L2_CID_VFLIP, 0, 1, 1, 0); | |
998 | v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops, | |
999 | V4L2_CID_HFLIP, 0, 1, 1, 0); | |
1000 | priv->autogain = v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops, | |
1001 | V4L2_CID_AUTOGAIN, 0, 1, 1, 1); | |
1002 | priv->gain = v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops, | |
1003 | V4L2_CID_GAIN, 0, 0x3f, 1, DEF_GAIN); | |
1004 | priv->autowb = v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops, | |
1005 | V4L2_CID_AUTO_WHITE_BALANCE, 0, 1, 1, 1); | |
1006 | priv->blue = v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops, | |
1007 | V4L2_CID_BLUE_BALANCE, 0, 0xff, 1, DEF_BLUE); | |
1008 | priv->red = v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops, | |
1009 | V4L2_CID_RED_BALANCE, 0, 0xff, 1, DEF_RED); | |
1010 | v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops, | |
1011 | V4L2_CID_SATURATION, 0, 0xf, 1, 0x8); | |
1012 | v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops, | |
1013 | V4L2_CID_HUE, 0, HUE_MASK, 1, DEF_HUE); | |
1014 | v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops, | |
1015 | V4L2_CID_BRIGHTNESS, 0, 0xff, 1, 0x80); | |
1016 | priv->autoexposure = v4l2_ctrl_new_std_menu(&priv->hdl, | |
2e56d933 JK |
1017 | &ov6550_ctrl_ops, V4L2_CID_EXPOSURE_AUTO, |
1018 | V4L2_EXPOSURE_MANUAL, 0, V4L2_EXPOSURE_AUTO); | |
afd9690c HV |
1019 | priv->exposure = v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops, |
1020 | V4L2_CID_EXPOSURE, 0, 0xff, 1, DEF_AECH); | |
1021 | v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops, | |
1022 | V4L2_CID_GAMMA, 0, 0xff, 1, 0x12); | |
1023 | ||
1024 | priv->subdev.ctrl_handler = &priv->hdl; | |
70e176a5 GL |
1025 | if (priv->hdl.error) |
1026 | return priv->hdl.error; | |
2f6e2404 | 1027 | |
afd9690c HV |
1028 | v4l2_ctrl_auto_cluster(2, &priv->autogain, 0, true); |
1029 | v4l2_ctrl_auto_cluster(3, &priv->autowb, 0, true); | |
1030 | v4l2_ctrl_auto_cluster(2, &priv->autoexposure, | |
1031 | V4L2_EXPOSURE_MANUAL, true); | |
2f6e2404 JK |
1032 | |
1033 | priv->rect.left = DEF_HSTRT << 1; | |
1034 | priv->rect.top = DEF_VSTRT << 1; | |
1035 | priv->rect.width = W_CIF; | |
1036 | priv->rect.height = H_CIF; | |
1037 | priv->half_scale = false; | |
f5fe58fd | 1038 | priv->code = MEDIA_BUS_FMT_YUYV8_2X8; |
2f6e2404 | 1039 | |
14178aa5 | 1040 | ret = ov6650_video_probe(client); |
13c4ad86 | 1041 | if (ret) |
afd9690c | 1042 | v4l2_ctrl_handler_free(&priv->hdl); |
2f6e2404 JK |
1043 | |
1044 | return ret; | |
1045 | } | |
1046 | ||
1047 | static int ov6650_remove(struct i2c_client *client) | |
1048 | { | |
1049 | struct ov6650 *priv = to_ov6650(client); | |
1050 | ||
9aea470b | 1051 | v4l2_clk_put(priv->clk); |
afd9690c HV |
1052 | v4l2_device_unregister_subdev(&priv->subdev); |
1053 | v4l2_ctrl_handler_free(&priv->hdl); | |
2f6e2404 JK |
1054 | return 0; |
1055 | } | |
1056 | ||
1057 | static const struct i2c_device_id ov6650_id[] = { | |
1058 | { "ov6650", 0 }, | |
1059 | { } | |
1060 | }; | |
1061 | MODULE_DEVICE_TABLE(i2c, ov6650_id); | |
1062 | ||
1063 | static struct i2c_driver ov6650_i2c_driver = { | |
1064 | .driver = { | |
1065 | .name = "ov6650", | |
1066 | }, | |
1067 | .probe = ov6650_probe, | |
1068 | .remove = ov6650_remove, | |
1069 | .id_table = ov6650_id, | |
1070 | }; | |
1071 | ||
c6e8d86f | 1072 | module_i2c_driver(ov6650_i2c_driver); |
2f6e2404 JK |
1073 | |
1074 | MODULE_DESCRIPTION("SoC Camera driver for OmniVision OV6650"); | |
1075 | MODULE_AUTHOR("Janusz Krzysztofik <jkrzyszt@tis.icnet.pl>"); | |
1076 | MODULE_LICENSE("GPL v2"); |