]> git.proxmox.com Git - mirror_ubuntu-jammy-kernel.git/blame - drivers/media/i2c/ov7670.c
projects / mirror_ubuntu-jammy-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Merge tag 'firewire-update' of git://git.kernel.org/pub/scm/linux/kernel/git/ieee1394...
[mirror_ubuntu-jammy-kernel.git] / drivers / media / i2c / ov7670.c
CommitLineData
12237550 1// SPDX-License-Identifier: GPL-2.0-only
111f3356
JC		 2/*
3 * A V4L2 driver for OmniVision OV7670 cameras.
4 *
5 * Copyright 2006 One Laptop Per Child Association, Inc. Written
6 * by Jonathan Corbet with substantial inspiration from Mark
7 * McClelland's ovcamchip code.
8 *
77d5140f 9 * Copyright 2006-7 Jonathan Corbet <corbet@lwn.net>
111f3356 10 */
0a024d63 11#include <linux/clk.h>
111f3356
JC		 12#include <linux/init.h>
13#include <linux/module.h>
5a0e3ad6 14#include <linux/slab.h>
14386c2b 15#include <linux/i2c.h>
111f3356 16#include <linux/delay.h>
7e0a16f6 17#include <linux/videodev2.h>
a0c4164e
HV		 18#include <linux/gpio.h>
19#include <linux/gpio/consumer.h>
14386c2b 20#include <media/v4l2-device.h>
7852adf8 21#include <media/v4l2-event.h>
492959c7 22#include <media/v4l2-ctrls.h>
01b84448 23#include <media/v4l2-fwnode.h>
959f3bda 24#include <media/v4l2-mediabus.h>
4721b3eb 25#include <media/v4l2-image-sizes.h>
b5dcee22 26#include <media/i2c/ov7670.h>
111f3356 27
5e614475 28MODULE_AUTHOR("Jonathan Corbet <corbet@lwn.net>");
111f3356
JC		 29MODULE_DESCRIPTION("A low-level driver for OmniVision ov7670 sensors");
30MODULE_LICENSE("GPL");
31
90ab5ee9 32static bool debug;
14386c2b
HV		 33module_param(debug, bool, 0644);
34MODULE_PARM_DESC(debug, "Debug level (0-1)");
35
111f3356
JC		 36/*
37 * The 7670 sits on i2c with ID 0x42
38 */
39#define OV7670_I2C_ADDR 0x42
40
f6dd927f
JM		 41#define PLL_FACTOR 4
42
111f3356
JC		 43/* Registers */
44#define REG_GAIN 0x00 /* Gain lower 8 bits (rest in vref) */
45#define REG_BLUE 0x01 /* blue gain */
46#define REG_RED 0x02 /* red gain */
47#define REG_VREF 0x03 /* Pieces of GAIN, VSTART, VSTOP */
48#define REG_COM1 0x04 /* Control 1 */
49#define COM1_CCIR656 0x40 /* CCIR656 enable */
50#define REG_BAVE 0x05 /* U/B Average level */
51#define REG_GbAVE 0x06 /* Y/Gb Average level */
52#define REG_AECHH 0x07 /* AEC MS 5 bits */
53#define REG_RAVE 0x08 /* V/R Average level */
54#define REG_COM2 0x09 /* Control 2 */
55#define COM2_SSLEEP 0x10 /* Soft sleep mode */
56#define REG_PID 0x0a /* Product ID MSB */
57#define REG_VER 0x0b /* Product ID LSB */
58#define REG_COM3 0x0c /* Control 3 */
59#define COM3_SWAP 0x40 /* Byte swap */
60#define COM3_SCALEEN 0x08 /* Enable scaling */
61#define COM3_DCWEN 0x04 /* Enable downsamp/crop/window */
62#define REG_COM4 0x0d /* Control 4 */
63#define REG_COM5 0x0e /* All "reserved" */
64#define REG_COM6 0x0f /* Control 6 */
65#define REG_AECH 0x10 /* More bits of AEC value */
66#define REG_CLKRC 0x11 /* Clocl control */
67#define CLK_EXT 0x40 /* Use external clock directly */
68#define CLK_SCALE 0x3f /* Mask for internal clock scale */
69#define REG_COM7 0x12 /* Control 7 */
70#define COM7_RESET 0x80 /* Register reset */
71#define COM7_FMT_MASK 0x38
72#define COM7_FMT_VGA 0x00
73#define COM7_FMT_CIF 0x20 /* CIF format */
74#define COM7_FMT_QVGA 0x10 /* QVGA format */
75#define COM7_FMT_QCIF 0x08 /* QCIF format */
76#define COM7_RGB 0x04 /* bits 0 and 2 - RGB format */
77#define COM7_YUV 0x00 /* YUV */
78#define COM7_BAYER 0x01 /* Bayer format */
79#define COM7_PBAYER 0x05 /* "Processed bayer" */
80#define REG_COM8 0x13 /* Control 8 */
81#define COM8_FASTAEC 0x80 /* Enable fast AGC/AEC */
82#define COM8_AECSTEP 0x40 /* Unlimited AEC step size */
83#define COM8_BFILT 0x20 /* Band filter enable */
84#define COM8_AGC 0x04 /* Auto gain enable */
85#define COM8_AWB 0x02 /* White balance enable */
86#define COM8_AEC 0x01 /* Auto exposure enable */
87#define REG_COM9 0x14 /* Control 9 - gain ceiling */
88#define REG_COM10 0x15 /* Control 10 */
89#define COM10_HSYNC 0x40 /* HSYNC instead of HREF */
90#define COM10_PCLK_HB 0x20 /* Suppress PCLK on horiz blank */
91#define COM10_HREF_REV 0x08 /* Reverse HREF */
92#define COM10_VS_LEAD 0x04 /* VSYNC on clock leading edge */
93#define COM10_VS_NEG 0x02 /* VSYNC negative */
94#define COM10_HS_NEG 0x01 /* HSYNC negative */
95#define REG_HSTART 0x17 /* Horiz start high bits */
96#define REG_HSTOP 0x18 /* Horiz stop high bits */
97#define REG_VSTART 0x19 /* Vert start high bits */
98#define REG_VSTOP 0x1a /* Vert stop high bits */
99#define REG_PSHFT 0x1b /* Pixel delay after HREF */
100#define REG_MIDH 0x1c /* Manuf. ID high */
101#define REG_MIDL 0x1d /* Manuf. ID low */
102#define REG_MVFP 0x1e /* Mirror / vflip */
103#define MVFP_MIRROR 0x20 /* Mirror image */
104#define MVFP_FLIP 0x10 /* Vertical flip */
105
106#define REG_AEW 0x24 /* AGC upper limit */
107#define REG_AEB 0x25 /* AGC lower limit */
108#define REG_VPT 0x26 /* AGC/AEC fast mode op region */
109#define REG_HSYST 0x30 /* HSYNC rising edge delay */
110#define REG_HSYEN 0x31 /* HSYNC falling edge delay */
111#define REG_HREF 0x32 /* HREF pieces */
112#define REG_TSLB 0x3a /* lots of stuff */
113#define TSLB_YLAST 0x04 /* UYVY or VYUY - see com13 */
114#define REG_COM11 0x3b /* Control 11 */
115#define COM11_NIGHT 0x80 /* NIght mode enable */
116#define COM11_NMFR 0x60 /* Two bit NM frame rate */
117#define COM11_HZAUTO 0x10 /* Auto detect 50/60 Hz */
118#define COM11_50HZ 0x08 /* Manual 50Hz select */
119#define COM11_EXP 0x02
120#define REG_COM12 0x3c /* Control 12 */
121#define COM12_HREF 0x80 /* HREF always */
122#define REG_COM13 0x3d /* Control 13 */
123#define COM13_GAMMA 0x80 /* Gamma enable */
124#define COM13_UVSAT 0x40 /* UV saturation auto adjustment */
125#define COM13_UVSWAP 0x01 /* V before U - w/TSLB */
126#define REG_COM14 0x3e /* Control 14 */
127#define COM14_DCWEN 0x10 /* DCW/PCLK-scale enable */
128#define REG_EDGE 0x3f /* Edge enhancement factor */
129#define REG_COM15 0x40 /* Control 15 */
130#define COM15_R10F0 0x00 /* Data range 10 to F0 */
131#define COM15_R01FE 0x80 /* 01 to FE */
132#define COM15_R00FF 0xc0 /* 00 to FF */
133#define COM15_RGB565 0x10 /* RGB565 output */
134#define COM15_RGB555 0x30 /* RGB555 output */
135#define REG_COM16 0x41 /* Control 16 */
136#define COM16_AWBGAIN 0x08 /* AWB gain enable */
137#define REG_COM17 0x42 /* Control 17 */
138#define COM17_AECWIN 0xc0 /* AEC window - must match COM4 */
139#define COM17_CBAR 0x08 /* DSP Color bar */
140
f9a76156
JC		 141/*
142 * This matrix defines how the colors are generated, must be
143 * tweaked to adjust hue and saturation.
144 *
145 * Order: v-red, v-green, v-blue, u-red, u-green, u-blue
146 *
147 * They are nine-bit signed quantities, with the sign bit
148 * stored in 0x58. Sign for v-red is bit 0, and up from there.
149 */
150#define REG_CMATRIX_BASE 0x4f
151#define CMATRIX_LEN 6
152#define REG_CMATRIX_SIGN 0x58
153
154
111f3356
JC		 155#define REG_BRIGHT 0x55 /* Brightness */
156#define REG_CONTRAS 0x56 /* Contrast control */
157
158#define REG_GFIX 0x69 /* Fix gain control */
159
f6dd927f 160#define REG_DBLV 0x6b /* PLL control an debugging */
61da76be
JM		 161#define DBLV_BYPASS 0x0a /* Bypass PLL */
162#define DBLV_X4 0x4a /* clock x4 */
163#define DBLV_X6 0x8a /* clock x6 */
164#define DBLV_X8 0xca /* clock x8 */
f6dd927f 165
b48d908d
AM		 166#define REG_SCALING_XSC 0x70 /* Test pattern and horizontal scale factor */
167#define TEST_PATTTERN_0 0x80
168#define REG_SCALING_YSC 0x71 /* Test pattern and vertical scale factor */
169#define TEST_PATTTERN_1 0x80
170
585553ec
JC		 171#define REG_REG76 0x76 /* OV's name */
172#define R76_BLKPCOR 0x80 /* Black pixel correction enable */
173#define R76_WHTPCOR 0x40 /* White pixel correction enable */
174
111f3356
JC		 175#define REG_RGB444 0x8c /* RGB 444 control */
176#define R444_ENABLE 0x02 /* Turn on RGB444, overrides 5x5 */
177#define R444_RGBX 0x01 /* Empty nibble at end */
178
179#define REG_HAECC1 0x9f /* Hist AEC/AGC control 1 */
180#define REG_HAECC2 0xa0 /* Hist AEC/AGC control 2 */
181
182#define REG_BD50MAX 0xa5 /* 50hz banding step limit */
183#define REG_HAECC3 0xa6 /* Hist AEC/AGC control 3 */
184#define REG_HAECC4 0xa7 /* Hist AEC/AGC control 4 */
185#define REG_HAECC5 0xa8 /* Hist AEC/AGC control 5 */
186#define REG_HAECC6 0xa9 /* Hist AEC/AGC control 6 */
187#define REG_HAECC7 0xaa /* Hist AEC/AGC control 7 */
188#define REG_BD60MAX 0xab /* 60hz banding step limit */
189
d058e237
JM		 190enum ov7670_model {
191 MODEL_OV7670 = 0,
192 MODEL_OV7675,
193};
194
195struct ov7670_win_size {
196 int width;
197 int height;
198 unsigned char com7_bit;
199 int hstart; /* Start/stop values for the camera. Note */
200 int hstop; /* that they do not always make complete */
201 int vstart; /* sense to humans, but evidently the sensor */
202 int vstop; /* will do the right thing... */
203 struct regval_list *regs; /* Regs to tweak */
204};
205
206struct ov7670_devtype {
207 /* formats supported for each model */
208 struct ov7670_win_size *win_sizes;
209 unsigned int n_win_sizes;
f6dd927f
JM		 210 /* callbacks for frame rate control */
211 int (*set_framerate)(struct v4l2_subdev *, struct v4l2_fract *);
212 void (*get_framerate)(struct v4l2_subdev *, struct v4l2_fract *);
d058e237 213};
111f3356 214
f9a76156
JC		 215/*
216 * Information we maintain about a known sensor.
217 */
218struct ov7670_format_struct; /* coming later */
219struct ov7670_info {
14386c2b 220 struct v4l2_subdev sd;
d94a26f0
WY		 221#if defined(CONFIG_MEDIA_CONTROLLER)
222 struct media_pad pad;
223#endif
492959c7
JM		 224 struct v4l2_ctrl_handler hdl;
225 struct {
226 /* gain cluster */
227 struct v4l2_ctrl *auto_gain;
228 struct v4l2_ctrl *gain;
229 };
230 struct {
231 /* exposure cluster */
232 struct v4l2_ctrl *auto_exposure;
233 struct v4l2_ctrl *exposure;
234 };
235 struct {
236 /* saturation/hue cluster */
237 struct v4l2_ctrl *saturation;
238 struct v4l2_ctrl *hue;
239 };
c0662dd4 240 struct v4l2_mbus_framefmt format;
f9a76156 241 struct ov7670_format_struct *fmt; /* Current format */
5556ab2a 242 struct ov7670_win_size *wsize;
0a024d63 243 struct clk *clk;
3d6a8fe2 244 int on;
a0c4164e
HV		 245 struct gpio_desc *resetb_gpio;
246 struct gpio_desc *pwdn_gpio;
01b84448 247 unsigned int mbus_config; /* Media bus configuration flags */
75e2bdad
DD		 248 int min_width; /* Filter out smaller sizes */
249 int min_height; /* Filter out smaller sizes */
250 int clock_speed; /* External clock speed (MHz) */
d8d20155 251 u8 clkrc; /* Clock divider value */
75e2bdad 252 bool use_smbus; /* Use smbus I/O instead of I2C */
04ee6d92 253 bool pll_bypass;
ee95258e 254 bool pclk_hb_disable;
d058e237 255 const struct ov7670_devtype *devtype; /* Device specifics */
f9a76156
JC		 256};
257
14386c2b
HV		 258static inline struct ov7670_info *to_state(struct v4l2_subdev *sd)
259{
260 return container_of(sd, struct ov7670_info, sd);
261}
f9a76156 262
492959c7
JM		 263static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
264{
265 return &container_of(ctrl->handler, struct ov7670_info, hdl)->sd;
266}
267
f9a76156
JC		 268
269
111f3356
JC		 270/*
271 * The default register settings, as obtained from OmniVision. There
272 * is really no making sense of most of these - lots of "reserved" values
273 * and such.
274 *
275 * These settings give VGA YUYV.
276 */
277
278struct regval_list {
279 unsigned char reg_num;
280 unsigned char value;
281};
282
283static struct regval_list ov7670_default_regs[] = {
284 { REG_COM7, COM7_RESET },
285/*
286 * Clock scale: 3 = 15fps
287 * 2 = 20fps
288 * 1 = 30fps
289 */
f9a76156 290 { REG_CLKRC, 0x1 }, /* OV: clock scale (30 fps) */
111f3356
JC		 291 { REG_TSLB, 0x04 }, /* OV */
292 { REG_COM7, 0 }, /* VGA */
293 /*
294 * Set the hardware window. These values from OV don't entirely
295 * make sense - hstop is less than hstart. But they work...
296 */
297 { REG_HSTART, 0x13 }, { REG_HSTOP, 0x01 },
298 { REG_HREF, 0xb6 }, { REG_VSTART, 0x02 },
299 { REG_VSTOP, 0x7a }, { REG_VREF, 0x0a },
300
301 { REG_COM3, 0 }, { REG_COM14, 0 },
302 /* Mystery scaling numbers */
b48d908d
AM		 303 { REG_SCALING_XSC, 0x3a },
304 { REG_SCALING_YSC, 0x35 },
111f3356
JC		 305 { 0x72, 0x11 }, { 0x73, 0xf0 },
306 { 0xa2, 0x02 }, { REG_COM10, 0x0 },
307
308 /* Gamma curve values */
309 { 0x7a, 0x20 }, { 0x7b, 0x10 },
310 { 0x7c, 0x1e }, { 0x7d, 0x35 },
311 { 0x7e, 0x5a }, { 0x7f, 0x69 },
312 { 0x80, 0x76 }, { 0x81, 0x80 },
313 { 0x82, 0x88 }, { 0x83, 0x8f },
314 { 0x84, 0x96 }, { 0x85, 0xa3 },
315 { 0x86, 0xaf }, { 0x87, 0xc4 },
316 { 0x88, 0xd7 }, { 0x89, 0xe8 },
317
318 /* AGC and AEC parameters. Note we start by disabling those features,
319 then turn them only after tweaking the values. */
320 { REG_COM8, COM8_FASTAEC | COM8_AECSTEP | COM8_BFILT },
321 { REG_GAIN, 0 }, { REG_AECH, 0 },
322 { REG_COM4, 0x40 }, /* magic reserved bit */
323 { REG_COM9, 0x18 }, /* 4x gain + magic rsvd bit */
324 { REG_BD50MAX, 0x05 }, { REG_BD60MAX, 0x07 },
325 { REG_AEW, 0x95 }, { REG_AEB, 0x33 },
326 { REG_VPT, 0xe3 }, { REG_HAECC1, 0x78 },
327 { REG_HAECC2, 0x68 }, { 0xa1, 0x03 }, /* magic */
328 { REG_HAECC3, 0xd8 }, { REG_HAECC4, 0xd8 },
329 { REG_HAECC5, 0xf0 }, { REG_HAECC6, 0x90 },
330 { REG_HAECC7, 0x94 },
331 { REG_COM8, COM8_FASTAEC|COM8_AECSTEP|COM8_BFILT|COM8_AGC|COM8_AEC },
332
333 /* Almost all of these are magic "reserved" values. */
334 { REG_COM5, 0x61 }, { REG_COM6, 0x4b },
7f7b12f0 335 { 0x16, 0x02 }, { REG_MVFP, 0x07 },
111f3356
JC		 336 { 0x21, 0x02 }, { 0x22, 0x91 },
337 { 0x29, 0x07 }, { 0x33, 0x0b },
338 { 0x35, 0x0b }, { 0x37, 0x1d },
339 { 0x38, 0x71 }, { 0x39, 0x2a },
340 { REG_COM12, 0x78 }, { 0x4d, 0x40 },
341 { 0x4e, 0x20 }, { REG_GFIX, 0 },
342 { 0x6b, 0x4a }, { 0x74, 0x10 },
343 { 0x8d, 0x4f }, { 0x8e, 0 },
344 { 0x8f, 0 }, { 0x90, 0 },
345 { 0x91, 0 }, { 0x96, 0 },
346 { 0x9a, 0 }, { 0xb0, 0x84 },
347 { 0xb1, 0x0c }, { 0xb2, 0x0e },
348 { 0xb3, 0x82 }, { 0xb8, 0x0a },
349
350 /* More reserved magic, some of which tweaks white balance */
351 { 0x43, 0x0a }, { 0x44, 0xf0 },
352 { 0x45, 0x34 }, { 0x46, 0x58 },
353 { 0x47, 0x28 }, { 0x48, 0x3a },
354 { 0x59, 0x88 }, { 0x5a, 0x88 },
355 { 0x5b, 0x44 }, { 0x5c, 0x67 },
356 { 0x5d, 0x49 }, { 0x5e, 0x0e },
357 { 0x6c, 0x0a }, { 0x6d, 0x55 },
358 { 0x6e, 0x11 }, { 0x6f, 0x9f }, /* "9e for advance AWB" */
359 { 0x6a, 0x40 }, { REG_BLUE, 0x40 },
360 { REG_RED, 0x60 },
361 { REG_COM8, COM8_FASTAEC|COM8_AECSTEP|COM8_BFILT|COM8_AGC|COM8_AEC|COM8_AWB },
362
363 /* Matrix coefficients */
364 { 0x4f, 0x80 }, { 0x50, 0x80 },
365 { 0x51, 0 }, { 0x52, 0x22 },
366 { 0x53, 0x5e }, { 0x54, 0x80 },
367 { 0x58, 0x9e },
368
369 { REG_COM16, COM16_AWBGAIN }, { REG_EDGE, 0 },
370 { 0x75, 0x05 }, { 0x76, 0xe1 },
371 { 0x4c, 0 }, { 0x77, 0x01 },
372 { REG_COM13, 0xc3 }, { 0x4b, 0x09 },
373 { 0xc9, 0x60 }, { REG_COM16, 0x38 },
374 { 0x56, 0x40 },
375
c8f5b2f5 376 { 0x34, 0x11 }, { REG_COM11, COM11_EXP|COM11_HZAUTO },
111f3356
JC		 377 { 0xa4, 0x88 }, { 0x96, 0 },
378 { 0x97, 0x30 }, { 0x98, 0x20 },
379 { 0x99, 0x30 }, { 0x9a, 0x84 },
380 { 0x9b, 0x29 }, { 0x9c, 0x03 },
381 { 0x9d, 0x4c }, { 0x9e, 0x3f },
382 { 0x78, 0x04 },
383
384 /* Extra-weird stuff. Some sort of multiplexor register */
385 { 0x79, 0x01 }, { 0xc8, 0xf0 },
386 { 0x79, 0x0f }, { 0xc8, 0x00 },
387 { 0x79, 0x10 }, { 0xc8, 0x7e },
388 { 0x79, 0x0a }, { 0xc8, 0x80 },
389 { 0x79, 0x0b }, { 0xc8, 0x01 },
390 { 0x79, 0x0c }, { 0xc8, 0x0f },
391 { 0x79, 0x0d }, { 0xc8, 0x20 },
392 { 0x79, 0x09 }, { 0xc8, 0x80 },
393 { 0x79, 0x02 }, { 0xc8, 0xc0 },
394 { 0x79, 0x03 }, { 0xc8, 0x40 },
395 { 0x79, 0x05 }, { 0xc8, 0x30 },
396 { 0x79, 0x26 },
397
111f3356
JC		 398 { 0xff, 0xff }, /* END MARKER */
399};
400
401
402/*
403 * Here we'll try to encapsulate the changes for just the output
404 * video format.
405 *
406 * RGB656 and YUV422 come from OV; RGB444 is homebrewed.
407 *
408 * IMPORTANT RULE: the first entry must be for COM7, see ov7670_s_fmt for why.
409 */
410
411
412static struct regval_list ov7670_fmt_yuv422[] = {
413 { REG_COM7, 0x0 }, /* Selects YUV mode */
414 { REG_RGB444, 0 }, /* No RGB444 please */
97693f91 415 { REG_COM1, 0 }, /* CCIR601 */
111f3356 416 { REG_COM15, COM15_R00FF },
c01b7429 417 { REG_COM9, 0x48 }, /* 32x gain ceiling; 0x8 is reserved bit */
6e6a8b5a
MCC		 418 { 0x4f, 0x80 }, /* "matrix coefficient 1" */
419 { 0x50, 0x80 }, /* "matrix coefficient 2" */
f9a76156 420 { 0x51, 0 }, /* vb */
6e6a8b5a
MCC		 421 { 0x52, 0x22 }, /* "matrix coefficient 4" */
422 { 0x53, 0x5e }, /* "matrix coefficient 5" */
423 { 0x54, 0x80 }, /* "matrix coefficient 6" */
111f3356
JC		 424 { REG_COM13, COM13_GAMMA|COM13_UVSAT },
425 { 0xff, 0xff },
426};
427
428static struct regval_list ov7670_fmt_rgb565[] = {
429 { REG_COM7, COM7_RGB }, /* Selects RGB mode */
430 { REG_RGB444, 0 }, /* No RGB444 please */
97693f91 431 { REG_COM1, 0x0 }, /* CCIR601 */
111f3356 432 { REG_COM15, COM15_RGB565 },
6e6a8b5a
MCC		 433 { REG_COM9, 0x38 }, /* 16x gain ceiling; 0x8 is reserved bit */
434 { 0x4f, 0xb3 }, /* "matrix coefficient 1" */
435 { 0x50, 0xb3 }, /* "matrix coefficient 2" */
f9a76156 436 { 0x51, 0 }, /* vb */
6e6a8b5a
MCC		 437 { 0x52, 0x3d }, /* "matrix coefficient 4" */
438 { 0x53, 0xa7 }, /* "matrix coefficient 5" */
439 { 0x54, 0xe4 }, /* "matrix coefficient 6" */
111f3356
JC		 440 { REG_COM13, COM13_GAMMA|COM13_UVSAT },
441 { 0xff, 0xff },
442};
443
444static struct regval_list ov7670_fmt_rgb444[] = {
445 { REG_COM7, COM7_RGB }, /* Selects RGB mode */
446 { REG_RGB444, R444_ENABLE }, /* Enable xxxxrrrr ggggbbbb */
97693f91 447 { REG_COM1, 0x0 }, /* CCIR601 */
111f3356 448 { REG_COM15, COM15_R01FE|COM15_RGB565 }, /* Data range needed? */
6e6a8b5a
MCC		 449 { REG_COM9, 0x38 }, /* 16x gain ceiling; 0x8 is reserved bit */
450 { 0x4f, 0xb3 }, /* "matrix coefficient 1" */
451 { 0x50, 0xb3 }, /* "matrix coefficient 2" */
f9a76156 452 { 0x51, 0 }, /* vb */
6e6a8b5a
MCC		 453 { 0x52, 0x3d }, /* "matrix coefficient 4" */
454 { 0x53, 0xa7 }, /* "matrix coefficient 5" */
455 { 0x54, 0xe4 }, /* "matrix coefficient 6" */
111f3356
JC		 456 { REG_COM13, COM13_GAMMA|COM13_UVSAT|0x2 }, /* Magic rsvd bit */
457 { 0xff, 0xff },
458};
459
585553ec
JC		 460static struct regval_list ov7670_fmt_raw[] = {
461 { REG_COM7, COM7_BAYER },
462 { REG_COM13, 0x08 }, /* No gamma, magic rsvd bit */
463 { REG_COM16, 0x3d }, /* Edge enhancement, denoise */
464 { REG_REG76, 0xe1 }, /* Pix correction, magic rsvd */
465 { 0xff, 0xff },
466};
111f3356
JC		 467
468
469
470/*
471 * Low-level register I/O.
46714209
JC		 472 *
473 * Note that there are two versions of these. On the XO 1, the
474 * i2c controller only does SMBUS, so that's what we use. The
475 * ov7670 is not really an SMBUS device, though, so the communication
476 * is not always entirely reliable.
477 */
75e2bdad 478static int ov7670_read_smbus(struct v4l2_subdev *sd, unsigned char reg,
46714209
JC		 479 unsigned char *value)
480{
481 struct i2c_client *client = v4l2_get_subdevdata(sd);
482 int ret;
483
484 ret = i2c_smbus_read_byte_data(client, reg);
485 if (ret >= 0) {
486 *value = (unsigned char)ret;
487 ret = 0;
488 }
489 return ret;
490}
491
492
75e2bdad 493static int ov7670_write_smbus(struct v4l2_subdev *sd, unsigned char reg,
46714209
JC		 494 unsigned char value)
495{
496 struct i2c_client *client = v4l2_get_subdevdata(sd);
497 int ret = i2c_smbus_write_byte_data(client, reg, value);
498
499 if (reg == REG_COM7 && (value & COM7_RESET))
500 msleep(5); /* Wait for reset to run */
501 return ret;
502}
503
46714209
JC		 504/*
505 * On most platforms, we'd rather do straight i2c I/O.
111f3356 506 */
75e2bdad 507static int ov7670_read_i2c(struct v4l2_subdev *sd, unsigned char reg,
111f3356
JC		 508 unsigned char *value)
509{
14386c2b 510 struct i2c_client *client = v4l2_get_subdevdata(sd);
2bf7de48
JC		 511 u8 data = reg;
512 struct i2c_msg msg;
111f3356
JC		 513 int ret;
514
2bf7de48
JC		 515 /*
516 * Send out the register address...
517 */
518 msg.addr = client->addr;
519 msg.flags = 0;
520 msg.len = 1;
521 msg.buf = &data;
522 ret = i2c_transfer(client->adapter, &msg, 1);
523 if (ret < 0) {
524 printk(KERN_ERR "Error %d on register write\n", ret);
525 return ret;
526 }
527 /*
528 * ...then read back the result.
529 */
530 msg.flags = I2C_M_RD;
531 ret = i2c_transfer(client->adapter, &msg, 1);
bca5c2c5 532 if (ret >= 0) {
2bf7de48 533 *value = data;
bca5c2c5
AS		 534 ret = 0;
535 }
111f3356
JC		 536 return ret;
537}
538
539
75e2bdad 540static int ov7670_write_i2c(struct v4l2_subdev *sd, unsigned char reg,
111f3356
JC		 541 unsigned char value)
542{
14386c2b 543 struct i2c_client *client = v4l2_get_subdevdata(sd);
2bf7de48
JC		 544 struct i2c_msg msg;
545 unsigned char data[2] = { reg, value };
546 int ret;
14386c2b 547
2bf7de48
JC		 548 msg.addr = client->addr;
549 msg.flags = 0;
550 msg.len = 2;
551 msg.buf = data;
552 ret = i2c_transfer(client->adapter, &msg, 1);
553 if (ret > 0)
554 ret = 0;
6d77444a 555 if (reg == REG_COM7 && (value & COM7_RESET))
97693f91 556 msleep(5); /* Wait for reset to run */
6d77444a 557 return ret;
111f3356
JC		 558}
559
75e2bdad
DD		 560static int ov7670_read(struct v4l2_subdev *sd, unsigned char reg,
561 unsigned char *value)
562{
563 struct ov7670_info *info = to_state(sd);
3abafaf4 564
75e2bdad
DD		 565 if (info->use_smbus)
566 return ov7670_read_smbus(sd, reg, value);
567 else
568 return ov7670_read_i2c(sd, reg, value);
569}
570
571static int ov7670_write(struct v4l2_subdev *sd, unsigned char reg,
572 unsigned char value)
573{
574 struct ov7670_info *info = to_state(sd);
3abafaf4 575
75e2bdad
DD		 576 if (info->use_smbus)
577 return ov7670_write_smbus(sd, reg, value);
578 else
579 return ov7670_write_i2c(sd, reg, value);
580}
111f3356 581
b48d908d
AM		 582static int ov7670_update_bits(struct v4l2_subdev *sd, unsigned char reg,
583 unsigned char mask, unsigned char value)
584{
585 unsigned char orig;
586 int ret;
587
588 ret = ov7670_read(sd, reg, &orig);
589 if (ret)
590 return ret;
591
592 return ov7670_write(sd, reg, (orig & ~mask) | (value & mask));
593}
594
111f3356
JC		 595/*
596 * Write a list of register settings; ff/ff stops the process.
597 */
14386c2b 598static int ov7670_write_array(struct v4l2_subdev *sd, struct regval_list *vals)
111f3356
JC		 599{
600 while (vals->reg_num != 0xff || vals->value != 0xff) {
14386c2b 601 int ret = ov7670_write(sd, vals->reg_num, vals->value);
3abafaf4 602
111f3356
JC		 603 if (ret < 0)
604 return ret;
605 vals++;
606 }
607 return 0;
608}
609
610
611/*
612 * Stuff that knows about the sensor.
613 */
14386c2b 614static int ov7670_reset(struct v4l2_subdev *sd, u32 val)
111f3356 615{
14386c2b 616 ov7670_write(sd, REG_COM7, COM7_RESET);
111f3356 617 msleep(1);
14386c2b 618 return 0;
111f3356
JC		 619}
620
621
14386c2b 622static int ov7670_init(struct v4l2_subdev *sd, u32 val)
111f3356 623{
14386c2b 624 return ov7670_write_array(sd, ov7670_default_regs);
111f3356
JC		 625}
626
14386c2b 627static int ov7670_detect(struct v4l2_subdev *sd)
111f3356
JC		 628{
629 unsigned char v;
630 int ret;
631
14386c2b 632 ret = ov7670_init(sd, 0);
111f3356
JC		 633 if (ret < 0)
634 return ret;
14386c2b 635 ret = ov7670_read(sd, REG_MIDH, &v);
111f3356
JC		 636 if (ret < 0)
637 return ret;
638 if (v != 0x7f) /* OV manuf. id. */
639 return -ENODEV;
14386c2b 640 ret = ov7670_read(sd, REG_MIDL, &v);
111f3356
JC		 641 if (ret < 0)
642 return ret;
643 if (v != 0xa2)
644 return -ENODEV;
645 /*
646 * OK, we know we have an OmniVision chip...but which one?
647 */
14386c2b 648 ret = ov7670_read(sd, REG_PID, &v);
111f3356
JC		 649 if (ret < 0)
650 return ret;
651 if (v != 0x76) /* PID + VER = 0x76 / 0x73 */
652 return -ENODEV;
14386c2b 653 ret = ov7670_read(sd, REG_VER, &v);
111f3356
JC		 654 if (ret < 0)
655 return ret;
656 if (v != 0x73) /* PID + VER = 0x76 / 0x73 */
657 return -ENODEV;
658 return 0;
659}
660
661
f9a76156
JC		 662/*
663 * Store information about the video data format. The color matrix
664 * is deeply tied into the format, so keep the relevant values here.
959f3bda 665 * The magic matrix numbers come from OmniVision.
f9a76156 666 */
111f3356 667static struct ov7670_format_struct {
f5fe58fd 668 u32 mbus_code;
959f3bda 669 enum v4l2_colorspace colorspace;
111f3356 670 struct regval_list *regs;
f9a76156 671 int cmatrix[CMATRIX_LEN];
111f3356
JC		 672} ov7670_formats[] = {
673 {
f5fe58fd 674 .mbus_code = MEDIA_BUS_FMT_YUYV8_2X8,
75eb9847 675 .colorspace = V4L2_COLORSPACE_SRGB,
6e6a8b5a 676 .regs = ov7670_fmt_yuv422,
f9a76156 677 .cmatrix = { 128, -128, 0, -34, -94, 128 },
111f3356
JC		 678 },
679 {
f5fe58fd 680 .mbus_code = MEDIA_BUS_FMT_RGB444_2X8_PADHI_LE,
959f3bda 681 .colorspace = V4L2_COLORSPACE_SRGB,
111f3356 682 .regs = ov7670_fmt_rgb444,
f9a76156 683 .cmatrix = { 179, -179, 0, -61, -176, 228 },
111f3356
JC		 684 },
685 {
f5fe58fd 686 .mbus_code = MEDIA_BUS_FMT_RGB565_2X8_LE,
959f3bda 687 .colorspace = V4L2_COLORSPACE_SRGB,
111f3356 688 .regs = ov7670_fmt_rgb565,
f9a76156 689 .cmatrix = { 179, -179, 0, -61, -176, 228 },
585553ec
JC		 690 },
691 {
f5fe58fd 692 .mbus_code = MEDIA_BUS_FMT_SBGGR8_1X8,
959f3bda 693 .colorspace = V4L2_COLORSPACE_SRGB,
6e6a8b5a 694 .regs = ov7670_fmt_raw,
585553ec 695 .cmatrix = { 0, 0, 0, 0, 0, 0 },
111f3356 696 },
111f3356 697};
585553ec 698#define N_OV7670_FMTS ARRAY_SIZE(ov7670_formats)
111f3356 699
111f3356
JC		 700
701/*
702 * Then there is the issue of window sizes. Try to capture the info here.
703 */
f9a76156
JC		 704
705/*
706 * QCIF mode is done (by OV) in a very strange way - it actually looks like
707 * VGA with weird scaling options - they do *not* use the canned QCIF mode
708 * which is allegedly provided by the sensor. So here's the weird register
709 * settings.
710 */
711static struct regval_list ov7670_qcif_regs[] = {
712 { REG_COM3, COM3_SCALEEN|COM3_DCWEN },
713 { REG_COM3, COM3_DCWEN },
714 { REG_COM14, COM14_DCWEN | 0x01},
715 { 0x73, 0xf1 },
716 { 0xa2, 0x52 },
717 { 0x7b, 0x1c },
718 { 0x7c, 0x28 },
719 { 0x7d, 0x3c },
720 { 0x7f, 0x69 },
721 { REG_COM9, 0x38 },
722 { 0xa1, 0x0b },
723 { 0x74, 0x19 },
724 { 0x9a, 0x80 },
725 { 0x43, 0x14 },
726 { REG_COM13, 0xc0 },
727 { 0xff, 0xff },
728};
729
d058e237 730static struct ov7670_win_size ov7670_win_sizes[] = {
111f3356
JC		 731 /* VGA */
732 {
733 .width = VGA_WIDTH,
734 .height = VGA_HEIGHT,
735 .com7_bit = COM7_FMT_VGA,
d058e237
JM		 736 .hstart = 158, /* These values from */
737 .hstop = 14, /* Omnivision */
111f3356
JC		 738 .vstart = 10,
739 .vstop = 490,
d058e237 740 .regs = NULL,
111f3356
JC		 741 },
742 /* CIF */
743 {
744 .width = CIF_WIDTH,
745 .height = CIF_HEIGHT,
746 .com7_bit = COM7_FMT_CIF,
d058e237 747 .hstart = 170, /* Empirically determined */
111f3356
JC		 748 .hstop = 90,
749 .vstart = 14,
750 .vstop = 494,
d058e237 751 .regs = NULL,
111f3356
JC		 752 },
753 /* QVGA */
754 {
755 .width = QVGA_WIDTH,
756 .height = QVGA_HEIGHT,
757 .com7_bit = COM7_FMT_QVGA,
d058e237 758 .hstart = 168, /* Empirically determined */
dc4589c8
DD		 759 .hstop = 24,
760 .vstart = 12,
761 .vstop = 492,
d058e237 762 .regs = NULL,
f9a76156
JC		 763 },
764 /* QCIF */
765 {
766 .width = QCIF_WIDTH,
767 .height = QCIF_HEIGHT,
768 .com7_bit = COM7_FMT_VGA, /* see comment above */
d058e237 769 .hstart = 456, /* Empirically determined */
f9a76156
JC		 770 .hstop = 24,
771 .vstart = 14,
772 .vstop = 494,
d058e237
JM		 773 .regs = ov7670_qcif_regs,
774 }
111f3356
JC		 775};
776
d058e237
JM		 777static struct ov7670_win_size ov7675_win_sizes[] = {
778 /*
779 * Currently, only VGA is supported. Theoretically it could be possible
780 * to support CIF, QVGA and QCIF too. Taking values for ov7670 as a
781 * base and tweak them empirically could be required.
782 */
783 {
784 .width = VGA_WIDTH,
785 .height = VGA_HEIGHT,
786 .com7_bit = COM7_FMT_VGA,
787 .hstart = 158, /* These values from */
788 .hstop = 14, /* Omnivision */
789 .vstart = 14, /* Empirically determined */
790 .vstop = 494,
791 .regs = NULL,
792 }
793};
111f3356 794
f6dd927f
JM		 795static void ov7675_get_framerate(struct v4l2_subdev *sd,
796 struct v4l2_fract *tpf)
797{
798 struct ov7670_info *info = to_state(sd);
799 u32 clkrc = info->clkrc;
04ee6d92
JM		 800 int pll_factor;
801
802 if (info->pll_bypass)
803 pll_factor = 1;
804 else
805 pll_factor = PLL_FACTOR;
f6dd927f
JM		 806
807 clkrc++;
f5fe58fd 808 if (info->fmt->mbus_code == MEDIA_BUS_FMT_SBGGR8_1X8)
f6dd927f
JM		 809 clkrc = (clkrc >> 1);
810
811 tpf->numerator = 1;
812 tpf->denominator = (5 * pll_factor * info->clock_speed) /
813 (4 * clkrc);
814}
815
40012cd5
LR		 816static int ov7675_apply_framerate(struct v4l2_subdev *sd)
817{
818 struct ov7670_info *info = to_state(sd);
819 int ret;
820
821 ret = ov7670_write(sd, REG_CLKRC, info->clkrc);
822 if (ret < 0)
823 return ret;
824
825 return ov7670_write(sd, REG_DBLV,
826 info->pll_bypass ? DBLV_BYPASS : DBLV_X4);
827}
828
f6dd927f
JM		 829static int ov7675_set_framerate(struct v4l2_subdev *sd,
830 struct v4l2_fract *tpf)
831{
832 struct ov7670_info *info = to_state(sd);
833 u32 clkrc;
04ee6d92 834 int pll_factor;
f6dd927f
JM		 835
836 /*
837 * The formula is fps = 5/4*pixclk for YUV/RGB and
838 * fps = 5/2*pixclk for RAW.
839 *
840 * pixclk = clock_speed / (clkrc + 1) * PLLfactor
841 *
842 */
843 if (tpf->numerator == 0 || tpf->denominator == 0) {
844 clkrc = 0;
845 } else {
40012cd5 846 pll_factor = info->pll_bypass ? 1 : PLL_FACTOR;
f6dd927f
JM		 847 clkrc = (5 * pll_factor * info->clock_speed * tpf->numerator) /
848 (4 * tpf->denominator);
f5fe58fd 849 if (info->fmt->mbus_code == MEDIA_BUS_FMT_SBGGR8_1X8)
f6dd927f
JM		 850 clkrc = (clkrc << 1);
851 clkrc--;
852 }
853
854 /*
855 * The datasheet claims that clkrc = 0 will divide the input clock by 1
856 * but we've checked with an oscilloscope that it divides by 2 instead.
857 * So, if clkrc = 0 just bypass the divider.
858 */
859 if (clkrc <= 0)
860 clkrc = CLK_EXT;
861 else if (clkrc > CLK_SCALE)
862 clkrc = CLK_SCALE;
863 info->clkrc = clkrc;
864
865 /* Recalculate frame rate */
866 ov7675_get_framerate(sd, tpf);
867
12f6153d
AM		 868 /*
869 * If the device is not powered up by the host driver do
870 * not apply any changes to H/W at this time. Instead
871 * the framerate will be restored right after power-up.
872 */
873 if (info->on)
874 return ov7675_apply_framerate(sd);
875
876 return 0;
f6dd927f
JM		 877}
878
879static void ov7670_get_framerate_legacy(struct v4l2_subdev *sd,
880 struct v4l2_fract *tpf)
881{
882 struct ov7670_info *info = to_state(sd);
883
884 tpf->numerator = 1;
885 tpf->denominator = info->clock_speed;
886 if ((info->clkrc & CLK_EXT) == 0 && (info->clkrc & CLK_SCALE) > 1)
887 tpf->denominator /= (info->clkrc & CLK_SCALE);
888}
889
890static int ov7670_set_framerate_legacy(struct v4l2_subdev *sd,
891 struct v4l2_fract *tpf)
892{
893 struct ov7670_info *info = to_state(sd);
894 int div;
895
896 if (tpf->numerator == 0 || tpf->denominator == 0)
897 div = 1; /* Reset to full rate */
898 else
899 div = (tpf->numerator * info->clock_speed) / tpf->denominator;
900 if (div == 0)
901 div = 1;
902 else if (div > CLK_SCALE)
903 div = CLK_SCALE;
904 info->clkrc = (info->clkrc & 0x80) | div;
905 tpf->numerator = 1;
906 tpf->denominator = info->clock_speed / div;
12f6153d
AM		 907
908 /*
909 * If the device is not powered up by the host driver do
910 * not apply any changes to H/W at this time. Instead
911 * the framerate will be restored right after power-up.
912 */
913 if (info->on)
914 return ov7670_write(sd, REG_CLKRC, info->clkrc);
915
916 return 0;
f6dd927f
JM		 917}
918
111f3356
JC		 919/*
920 * Store a set of start/stop values into the camera.
921 */
14386c2b 922static int ov7670_set_hw(struct v4l2_subdev *sd, int hstart, int hstop,
111f3356
JC		 923 int vstart, int vstop)
924{
925 int ret;
926 unsigned char v;
3abafaf4
TR		 927 /*
928 * Horizontal: 11 bits, top 8 live in hstart and hstop. Bottom 3 of
929 * hstart are in href[2:0], bottom 3 of hstop in href[5:3]. There is
930 * a mystery "edge offset" value in the top two bits of href.
931 */
932 ret = ov7670_write(sd, REG_HSTART, (hstart >> 3) & 0xff);
933 if (ret)
934 return ret;
935 ret = ov7670_write(sd, REG_HSTOP, (hstop >> 3) & 0xff);
936 if (ret)
937 return ret;
938 ret = ov7670_read(sd, REG_HREF, &v);
939 if (ret)
940 return ret;
111f3356
JC		 941 v = (v & 0xc0) | ((hstop & 0x7) << 3) | (hstart & 0x7);
942 msleep(10);
3abafaf4
TR		 943 ret = ov7670_write(sd, REG_HREF, v);
944 if (ret)
945 return ret;
946 /* Vertical: similar arrangement, but only 10 bits. */
947 ret = ov7670_write(sd, REG_VSTART, (vstart >> 2) & 0xff);
948 if (ret)
949 return ret;
950 ret = ov7670_write(sd, REG_VSTOP, (vstop >> 2) & 0xff);
951 if (ret)
952 return ret;
953 ret = ov7670_read(sd, REG_VREF, &v);
954 if (ret)
955 return ret;
111f3356
JC		 956 v = (v & 0xf0) | ((vstop & 0x3) << 2) | (vstart & 0x3);
957 msleep(10);
3abafaf4 958 return ov7670_write(sd, REG_VREF, v);
111f3356
JC		 959}
960
961
ebcff5fc 962static int ov7670_enum_mbus_code(struct v4l2_subdev *sd,
0d346d2a 963 struct v4l2_subdev_state *sd_state,
ebcff5fc 964 struct v4l2_subdev_mbus_code_enum *code)
959f3bda 965{
ebcff5fc 966 if (code->pad || code->index >= N_OV7670_FMTS)
959f3bda
HV		 967 return -EINVAL;
968
ebcff5fc 969 code->code = ov7670_formats[code->index].mbus_code;
959f3bda
HV		 970 return 0;
971}
111f3356 972
14386c2b 973static int ov7670_try_fmt_internal(struct v4l2_subdev *sd,
959f3bda 974 struct v4l2_mbus_framefmt *fmt,
111f3356
JC		 975 struct ov7670_format_struct **ret_fmt,
976 struct ov7670_win_size **ret_wsize)
977{
f748cd3e 978 int index, i;
111f3356 979 struct ov7670_win_size *wsize;
d058e237
JM		 980 struct ov7670_info *info = to_state(sd);
981 unsigned int n_win_sizes = info->devtype->n_win_sizes;
f748cd3e 982 unsigned int win_sizes_limit = n_win_sizes;
111f3356
JC		 983
984 for (index = 0; index < N_OV7670_FMTS; index++)
959f3bda 985 if (ov7670_formats[index].mbus_code == fmt->code)
111f3356 986 break;
cd257a6f
DD		 987 if (index >= N_OV7670_FMTS) {
988 /* default to first format */
989 index = 0;
959f3bda 990 fmt->code = ov7670_formats[0].mbus_code;
cd257a6f 991 }
111f3356
JC		 992 if (ret_fmt != NULL)
993 *ret_fmt = ov7670_formats + index;
994 /*
995 * Fields: the OV devices claim to be progressive.
996 */
959f3bda 997 fmt->field = V4L2_FIELD_NONE;
f748cd3e
JM		 998
999 /*
1000 * Don't consider values that don't match min_height and min_width
1001 * constraints.
1002 */
1003 if (info->min_width || info->min_height)
1004 for (i = 0; i < n_win_sizes; i++) {
1005 wsize = info->devtype->win_sizes + i;
1006
1007 if (wsize->width < info->min_width ||
1008 wsize->height < info->min_height) {
1009 win_sizes_limit = i;
1010 break;
1011 }
1012 }
111f3356
JC		 1013 /*
1014 * Round requested image size down to the nearest
1015 * we support, but not below the smallest.
1016 */
d058e237 1017 for (wsize = info->devtype->win_sizes;
f748cd3e 1018 wsize < info->devtype->win_sizes + win_sizes_limit; wsize++)
959f3bda 1019 if (fmt->width >= wsize->width && fmt->height >= wsize->height)
111f3356 1020 break;
f748cd3e 1021 if (wsize >= info->devtype->win_sizes + win_sizes_limit)
111f3356
JC		 1022 wsize--; /* Take the smallest one */
1023 if (ret_wsize != NULL)
1024 *ret_wsize = wsize;
1025 /*
1026 * Note the size we'll actually handle.
1027 */
959f3bda
HV		 1028 fmt->width = wsize->width;
1029 fmt->height = wsize->height;
1030 fmt->colorspace = ov7670_formats[index].colorspace;
c0662dd4
WY		 1031
1032 info->format = *fmt;
1033
111f3356 1034 return 0;
111f3356
JC		 1035}
1036
5556ab2a 1037static int ov7670_apply_fmt(struct v4l2_subdev *sd)
111f3356 1038{
14386c2b 1039 struct ov7670_info *info = to_state(sd);
5556ab2a 1040 struct ov7670_win_size *wsize = info->wsize;
01b84448 1041 unsigned char com7, com10 = 0;
959f3bda 1042 int ret;
111f3356 1043
111f3356
JC		 1044 /*
1045 * COM7 is a pain in the ass, it doesn't like to be read then
1046 * quickly written afterward. But we have everything we need
1047 * to set it absolutely here, as long as the format-specific
1048 * register sets list it first.
1049 */
5556ab2a 1050 com7 = info->fmt->regs[0].value;
111f3356 1051 com7 |= wsize->com7_bit;
01b84448
JM		 1052 ret = ov7670_write(sd, REG_COM7, com7);
1053 if (ret)
1054 return ret;
1055
1056 /*
1057 * Configure the media bus through COM10 register
1058 */
1059 if (info->mbus_config & V4L2_MBUS_VSYNC_ACTIVE_LOW)
1060 com10 |= COM10_VS_NEG;
1061 if (info->mbus_config & V4L2_MBUS_HSYNC_ACTIVE_LOW)
1062 com10 |= COM10_HREF_REV;
1063 if (info->pclk_hb_disable)
1064 com10 |= COM10_PCLK_HB;
1065 ret = ov7670_write(sd, REG_COM10, com10);
1066 if (ret)
1067 return ret;
1068
111f3356
JC		 1069 /*
1070 * Now write the rest of the array. Also store start/stops
1071 */
5556ab2a 1072 ret = ov7670_write_array(sd, info->fmt->regs + 1);
01b84448
JM		 1073 if (ret)
1074 return ret;
1075
1076 ret = ov7670_set_hw(sd, wsize->hstart, wsize->hstop, wsize->vstart,
1077 wsize->vstop);
1078 if (ret)
1079 return ret;
1080
1081 if (wsize->regs) {
14386c2b 1082 ret = ov7670_write_array(sd, wsize->regs);
01b84448
JM		 1083 if (ret)
1084 return ret;
1085 }
1086
d8d20155
JC		 1087 /*
1088 * If we're running RGB565, we must rewrite clkrc after setting
1089 * the other parameters or the image looks poor. If we're *not*
1090 * doing RGB565, we must not rewrite clkrc or the image looks
1091 * *really* poor.
a8e68c37
JC		 1092 *
1093 * (Update) Now that we retain clkrc state, we should be able
1094 * to write it unconditionally, and that will make the frame
1095 * rate persistent too.
d8d20155 1096 */
01b84448
JM		 1097 ret = ov7670_write(sd, REG_CLKRC, info->clkrc);
1098 if (ret)
1099 return ret;
1100
959f3bda
HV		 1101 return 0;
1102}
1103
5556ab2a
LR		 1104/*
1105 * Set a format.
1106 */
1107static int ov7670_set_fmt(struct v4l2_subdev *sd,
0d346d2a 1108 struct v4l2_subdev_state *sd_state,
5556ab2a
LR		 1109 struct v4l2_subdev_format *format)
1110{
1111 struct ov7670_info *info = to_state(sd);
1112#ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1113 struct v4l2_mbus_framefmt *mbus_fmt;
1114#endif
1115 int ret;
1116
1117 if (format->pad)
1118 return -EINVAL;
1119
1120 if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
1121 ret = ov7670_try_fmt_internal(sd, &format->format, NULL, NULL);
1122 if (ret)
1123 return ret;
1124#ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
0d346d2a
TV		 1125 mbus_fmt = v4l2_subdev_get_try_format(sd, sd_state,
1126 format->pad);
5556ab2a 1127 *mbus_fmt = format->format;
5556ab2a 1128#endif
fa564e90 1129 return 0;
5556ab2a
LR		 1130 }
1131
1132 ret = ov7670_try_fmt_internal(sd, &format->format, &info->fmt, &info->wsize);
1133 if (ret)
1134 return ret;
1135
12f6153d
AM		 1136 /*
1137 * If the device is not powered up by the host driver do
1138 * not apply any changes to H/W at this time. Instead
1139 * the frame format will be restored right after power-up.
1140 */
1141 if (info->on)
1142 return ov7670_apply_fmt(sd);
5556ab2a
LR		 1143
1144 return 0;
1145}
1146
c0662dd4 1147static int ov7670_get_fmt(struct v4l2_subdev *sd,
0d346d2a 1148 struct v4l2_subdev_state *sd_state,
c0662dd4
WY		 1149 struct v4l2_subdev_format *format)
1150{
1151 struct ov7670_info *info = to_state(sd);
1152#ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1153 struct v4l2_mbus_framefmt *mbus_fmt;
1154#endif
1155
1156 if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
1157#ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
0d346d2a 1158 mbus_fmt = v4l2_subdev_get_try_format(sd, sd_state, 0);
c0662dd4
WY		 1159 format->format = *mbus_fmt;
1160 return 0;
1161#else
fa564e90 1162 return -EINVAL;
c0662dd4
WY		 1163#endif
1164 } else {
1165 format->format = info->format;
1166 }
1167
1168 return 0;
1169}
1170
c8f5b2f5
JC		 1171/*
1172 * Implement G/S_PARM. There is a "high quality" mode we could try
1173 * to do someday; for now, we just do the frame rate tweak.
1174 */
4471109e
HV		 1175static int ov7670_g_frame_interval(struct v4l2_subdev *sd,
1176 struct v4l2_subdev_frame_interval *ival)
c8f5b2f5 1177{
d8d20155 1178 struct ov7670_info *info = to_state(sd);
c8f5b2f5 1179
d8d20155 1180
4471109e 1181 info->devtype->get_framerate(sd, &ival->interval);
f6dd927f 1182
c8f5b2f5
JC		 1183 return 0;
1184}
1185
4471109e
HV		 1186static int ov7670_s_frame_interval(struct v4l2_subdev *sd,
1187 struct v4l2_subdev_frame_interval *ival)
c8f5b2f5 1188{
4471109e 1189 struct v4l2_fract *tpf = &ival->interval;
d8d20155 1190 struct ov7670_info *info = to_state(sd);
c8f5b2f5 1191
d8d20155 1192
f6dd927f 1193 return info->devtype->set_framerate(sd, tpf);
c8f5b2f5
JC		 1194}
1195
1196
111f3356 1197/*
e99dfcf7
JC		 1198 * Frame intervals. Since frame rates are controlled with the clock
1199 * divider, we can only do 30/n for integer n values. So no continuous
1200 * or stepwise options. Here we just pick a handful of logical values.
111f3356
JC		 1201 */
1202
e99dfcf7 1203static int ov7670_frame_rates[] = { 30, 15, 10, 5, 1 };
f9a76156 1204
17bef885 1205static int ov7670_enum_frame_interval(struct v4l2_subdev *sd,
0d346d2a 1206 struct v4l2_subdev_state *sd_state,
17bef885 1207 struct v4l2_subdev_frame_interval_enum *fie)
e99dfcf7 1208{
b8cc79fd
HV		 1209 struct ov7670_info *info = to_state(sd);
1210 unsigned int n_win_sizes = info->devtype->n_win_sizes;
1211 int i;
1212
17bef885 1213 if (fie->pad)
e99dfcf7 1214 return -EINVAL;
17bef885
HV		 1215 if (fie->index >= ARRAY_SIZE(ov7670_frame_rates))
1216 return -EINVAL;
b8cc79fd
HV		 1217
1218 /*
1219 * Check if the width/height is valid.
1220 *
1221 * If a minimum width/height was requested, filter out the capture
1222 * windows that fall outside that.
1223 */
1224 for (i = 0; i < n_win_sizes; i++) {
1225 struct ov7670_win_size *win = &info->devtype->win_sizes[i];
1226
1227 if (info->min_width && win->width < info->min_width)
1228 continue;
1229 if (info->min_height && win->height < info->min_height)
1230 continue;
1231 if (fie->width == win->width && fie->height == win->height)
1232 break;
1233 }
1234 if (i == n_win_sizes)
1235 return -EINVAL;
17bef885
HV		 1236 fie->interval.numerator = 1;
1237 fie->interval.denominator = ov7670_frame_rates[fie->index];
e99dfcf7
JC		 1238 return 0;
1239}
f9a76156 1240
b0326b7f
DD		 1241/*
1242 * Frame size enumeration
1243 */
17bef885 1244static int ov7670_enum_frame_size(struct v4l2_subdev *sd,
0d346d2a 1245 struct v4l2_subdev_state *sd_state,
17bef885 1246 struct v4l2_subdev_frame_size_enum *fse)
b0326b7f 1247{
75e2bdad
DD		 1248 struct ov7670_info *info = to_state(sd);
1249 int i;
1250 int num_valid = -1;
17bef885 1251 __u32 index = fse->index;
d058e237 1252 unsigned int n_win_sizes = info->devtype->n_win_sizes;
b0326b7f 1253
17bef885
HV		 1254 if (fse->pad)
1255 return -EINVAL;
1256
75e2bdad
DD		 1257 /*
1258 * If a minimum width/height was requested, filter out the capture
1259 * windows that fall outside that.
1260 */
d058e237 1261 for (i = 0; i < n_win_sizes; i++) {
322e6d19 1262 struct ov7670_win_size *win = &info->devtype->win_sizes[i];
3abafaf4 1263
75e2bdad
DD		 1264 if (info->min_width && win->width < info->min_width)
1265 continue;
1266 if (info->min_height && win->height < info->min_height)
1267 continue;
1268 if (index == ++num_valid) {
17bef885
HV		 1269 fse->min_width = fse->max_width = win->width;
1270 fse->min_height = fse->max_height = win->height;
75e2bdad
DD		 1271 return 0;
1272 }
1273 }
1274
1275 return -EINVAL;
b0326b7f
DD		 1276}
1277
e99dfcf7
JC		 1278/*
1279 * Code for dealing with controls.
1280 */
f9a76156 1281
14386c2b 1282static int ov7670_store_cmatrix(struct v4l2_subdev *sd,
f9a76156
JC		 1283 int matrix[CMATRIX_LEN])
1284{
1285 int i, ret;
e3bf20de 1286 unsigned char signbits = 0;
f9a76156
JC		 1287
1288 /*
1289 * Weird crap seems to exist in the upper part of
1290 * the sign bits register, so let's preserve it.
1291 */
14386c2b 1292 ret = ov7670_read(sd, REG_CMATRIX_SIGN, &signbits);
f9a76156
JC		 1293 signbits &= 0xc0;
1294
1295 for (i = 0; i < CMATRIX_LEN; i++) {
1296 unsigned char raw;
1297
1298 if (matrix[i] < 0) {
1299 signbits |= (1 << i);
1300 if (matrix[i] < -255)
1301 raw = 0xff;
1302 else
1303 raw = (-1 * matrix[i]) & 0xff;
3abafaf4 1304 } else {
f9a76156
JC		 1305 if (matrix[i] > 255)
1306 raw = 0xff;
1307 else
1308 raw = matrix[i] & 0xff;
1309 }
3abafaf4
TR		 1310 ret = ov7670_write(sd, REG_CMATRIX_BASE + i, raw);
1311 if (ret)
1312 return ret;
f9a76156 1313 }
3abafaf4 1314 return ov7670_write(sd, REG_CMATRIX_SIGN, signbits);
f9a76156
JC		 1315}
1316
1317
1318/*
1319 * Hue also requires messing with the color matrix. It also requires
1320 * trig functions, which tend not to be well supported in the kernel.
1321 * So here is a simple table of sine values, 0-90 degrees, in steps
1322 * of five degrees. Values are multiplied by 1000.
1323 *
1324 * The following naive approximate trig functions require an argument
1325 * carefully limited to -180 <= theta <= 180.
1326 */
1327#define SIN_STEP 5
1328static const int ov7670_sin_table[] = {
1329 0, 87, 173, 258, 342, 422,
1330 499, 573, 642, 707, 766, 819,
1331 866, 906, 939, 965, 984, 996,
1332 1000
1333};
1334
1335static int ov7670_sine(int theta)
1336{
1337 int chs = 1;
1338 int sine;
1339
1340 if (theta < 0) {
1341 theta = -theta;
1342 chs = -1;
1343 }
1344 if (theta <= 90)
1345 sine = ov7670_sin_table[theta/SIN_STEP];
1346 else {
1347 theta -= 90;
1348 sine = 1000 - ov7670_sin_table[theta/SIN_STEP];
1349 }
1350 return sine*chs;
1351}
1352
1353static int ov7670_cosine(int theta)
1354{
1355 theta = 90 - theta;
1356 if (theta > 180)
1357 theta -= 360;
1358 else if (theta < -180)
1359 theta += 360;
1360 return ov7670_sine(theta);
1361}
1362
1363
1364
1365
1366static void ov7670_calc_cmatrix(struct ov7670_info *info,
492959c7 1367 int matrix[CMATRIX_LEN], int sat, int hue)
f9a76156
JC		 1368{
1369 int i;
1370 /*
1371 * Apply the current saturation setting first.
1372 */
1373 for (i = 0; i < CMATRIX_LEN; i++)
492959c7 1374 matrix[i] = (info->fmt->cmatrix[i] * sat) >> 7;
f9a76156
JC		 1375 /*
1376 * Then, if need be, rotate the hue value.
1377 */
492959c7 1378 if (hue != 0) {
f9a76156
JC		 1379 int sinth, costh, tmpmatrix[CMATRIX_LEN];
1380
1381 memcpy(tmpmatrix, matrix, CMATRIX_LEN*sizeof(int));
492959c7
JM		 1382 sinth = ov7670_sine(hue);
1383 costh = ov7670_cosine(hue);
f9a76156
JC		 1384
1385 matrix[0] = (matrix[3]*sinth + matrix[0]*costh)/1000;
1386 matrix[1] = (matrix[4]*sinth + matrix[1]*costh)/1000;
1387 matrix[2] = (matrix[5]*sinth + matrix[2]*costh)/1000;
1388 matrix[3] = (matrix[3]*costh - matrix[0]*sinth)/1000;
1389 matrix[4] = (matrix[4]*costh - matrix[1]*sinth)/1000;
1390 matrix[5] = (matrix[5]*costh - matrix[2]*sinth)/1000;
1391 }
1392}
1393
1394
1395
492959c7 1396static int ov7670_s_sat_hue(struct v4l2_subdev *sd, int sat, int hue)
f9a76156 1397{
14386c2b 1398 struct ov7670_info *info = to_state(sd);
f9a76156 1399 int matrix[CMATRIX_LEN];
f9a76156 1400
492959c7 1401 ov7670_calc_cmatrix(info, matrix, sat, hue);
3abafaf4 1402 return ov7670_store_cmatrix(sd, matrix);
f9a76156
JC		 1403}
1404
f9a76156 1405
111f3356
JC		 1406/*
1407 * Some weird registers seem to store values in a sign/magnitude format!
1408 */
111f3356
JC		 1409
1410static unsigned char ov7670_abs_to_sm(unsigned char v)
1411{
1412 if (v > 127)
1413 return v & 0x7f;
14386c2b 1414 return (128 - v) | 0x80;
111f3356
JC		 1415}
1416
ca07561a 1417static int ov7670_s_brightness(struct v4l2_subdev *sd, int value)
111f3356 1418{
e3bf20de 1419 unsigned char com8 = 0, v;
111f3356 1420
14386c2b 1421 ov7670_read(sd, REG_COM8, &com8);
111f3356 1422 com8 &= ~COM8_AEC;
14386c2b 1423 ov7670_write(sd, REG_COM8, com8);
f9a76156 1424 v = ov7670_abs_to_sm(value);
3abafaf4 1425 return ov7670_write(sd, REG_BRIGHT, v);
111f3356
JC		 1426}
1427
ca07561a 1428static int ov7670_s_contrast(struct v4l2_subdev *sd, int value)
111f3356 1429{
14386c2b 1430 return ov7670_write(sd, REG_CONTRAS, (unsigned char) value);
111f3356
JC		 1431}
1432
ca07561a 1433static int ov7670_s_hflip(struct v4l2_subdev *sd, int value)
111f3356 1434{
e3bf20de 1435 unsigned char v = 0;
111f3356
JC		 1436 int ret;
1437
14386c2b 1438 ret = ov7670_read(sd, REG_MVFP, &v);
3abafaf4
TR		 1439 if (ret)
1440 return ret;
111f3356
JC		 1441 if (value)
1442 v |= MVFP_MIRROR;
1443 else
1444 v &= ~MVFP_MIRROR;
1445 msleep(10); /* FIXME */
3abafaf4 1446 return ov7670_write(sd, REG_MVFP, v);
111f3356
JC		 1447}
1448
ca07561a 1449static int ov7670_s_vflip(struct v4l2_subdev *sd, int value)
111f3356 1450{
e3bf20de 1451 unsigned char v = 0;
111f3356
JC		 1452 int ret;
1453
14386c2b 1454 ret = ov7670_read(sd, REG_MVFP, &v);
3abafaf4
TR		 1455 if (ret)
1456 return ret;
111f3356
JC		 1457 if (value)
1458 v |= MVFP_FLIP;
1459 else
1460 v &= ~MVFP_FLIP;
1461 msleep(10); /* FIXME */
3abafaf4 1462 return ov7670_write(sd, REG_MVFP, v);
111f3356
JC		 1463}
1464
81898671
JC		 1465/*
1466 * GAIN is split between REG_GAIN and REG_VREF[7:6]. If one believes
1467 * the data sheet, the VREF parts should be the most significant, but
1468 * experience shows otherwise. There seems to be little value in
1469 * messing with the VREF bits, so we leave them alone.
1470 */
1471static int ov7670_g_gain(struct v4l2_subdev *sd, __s32 *value)
1472{
1473 int ret;
1474 unsigned char gain;
1475
1476 ret = ov7670_read(sd, REG_GAIN, &gain);
3abafaf4
TR		 1477 if (ret)
1478 return ret;
81898671 1479 *value = gain;
3abafaf4 1480 return 0;
81898671
JC		 1481}
1482
1483static int ov7670_s_gain(struct v4l2_subdev *sd, int value)
1484{
1485 int ret;
1486 unsigned char com8;
1487
1488 ret = ov7670_write(sd, REG_GAIN, value & 0xff);
3abafaf4
TR		 1489 if (ret)
1490 return ret;
81898671 1491 /* Have to turn off AGC as well */
3abafaf4
TR		 1492 ret = ov7670_read(sd, REG_COM8, &com8);
1493 if (ret)
1494 return ret;
1495 return ov7670_write(sd, REG_COM8, com8 & ~COM8_AGC);
81898671
JC		 1496}
1497
1498/*
1499 * Tweak autogain.
1500 */
81898671
JC		 1501static int ov7670_s_autogain(struct v4l2_subdev *sd, int value)
1502{
1503 int ret;
1504 unsigned char com8;
1505
1506 ret = ov7670_read(sd, REG_COM8, &com8);
1507 if (ret == 0) {
1508 if (value)
1509 com8 |= COM8_AGC;
1510 else
1511 com8 &= ~COM8_AGC;
1512 ret = ov7670_write(sd, REG_COM8, com8);
1513 }
1514 return ret;
1515}
1516
364e9337
JC		 1517static int ov7670_s_exp(struct v4l2_subdev *sd, int value)
1518{
1519 int ret;
1520 unsigned char com1, com8, aech, aechh;
1521
1522 ret = ov7670_read(sd, REG_COM1, &com1) +
d487df9e 1523 ov7670_read(sd, REG_COM8, &com8) +
364e9337
JC		 1524 ov7670_read(sd, REG_AECHH, &aechh);
1525 if (ret)
1526 return ret;
1527
1528 com1 = (com1 & 0xfc) | (value & 0x03);
1529 aech = (value >> 2) & 0xff;
1530 aechh = (aechh & 0xc0) | ((value >> 10) & 0x3f);
1531 ret = ov7670_write(sd, REG_COM1, com1) +
1532 ov7670_write(sd, REG_AECH, aech) +
1533 ov7670_write(sd, REG_AECHH, aechh);
1534 /* Have to turn off AEC as well */
1535 if (ret == 0)
1536 ret = ov7670_write(sd, REG_COM8, com8 & ~COM8_AEC);
1537 return ret;
1538}
1539
1540/*
1541 * Tweak autoexposure.
1542 */
364e9337
JC		 1543static int ov7670_s_autoexp(struct v4l2_subdev *sd,
1544 enum v4l2_exposure_auto_type value)
1545{
1546 int ret;
1547 unsigned char com8;
1548
1549 ret = ov7670_read(sd, REG_COM8, &com8);
1550 if (ret == 0) {
1551 if (value == V4L2_EXPOSURE_AUTO)
1552 com8 |= COM8_AEC;
1553 else
1554 com8 &= ~COM8_AEC;
1555 ret = ov7670_write(sd, REG_COM8, com8);
1556 }
1557 return ret;
1558}
1559
b48d908d
AM		 1560static const char * const ov7670_test_pattern_menu[] = {
1561 "No test output",
1562 "Shifting \"1\"",
1563 "8-bar color bar",
1564 "Fade to gray color bar",
1565};
1566
1567static int ov7670_s_test_pattern(struct v4l2_subdev *sd, int value)
1568{
1569 int ret;
1570
1571 ret = ov7670_update_bits(sd, REG_SCALING_XSC, TEST_PATTTERN_0,
1572 value & BIT(0) ? TEST_PATTTERN_0 : 0);
1573 if (ret)
1574 return ret;
1575
1576 return ov7670_update_bits(sd, REG_SCALING_YSC, TEST_PATTTERN_1,
1577 value & BIT(1) ? TEST_PATTTERN_1 : 0);
1578}
81898671 1579
492959c7 1580static int ov7670_g_volatile_ctrl(struct v4l2_ctrl *ctrl)
111f3356 1581{
492959c7
JM		 1582 struct v4l2_subdev *sd = to_sd(ctrl);
1583 struct ov7670_info *info = to_state(sd);
111f3356 1584
ca07561a 1585 switch (ctrl->id) {
81898671 1586 case V4L2_CID_AUTOGAIN:
492959c7 1587 return ov7670_g_gain(sd, &info->gain->val);
ca07561a
HV		 1588 }
1589 return -EINVAL;
111f3356
JC		 1590}
1591
492959c7 1592static int ov7670_s_ctrl(struct v4l2_ctrl *ctrl)
111f3356 1593{
492959c7
JM		 1594 struct v4l2_subdev *sd = to_sd(ctrl);
1595 struct ov7670_info *info = to_state(sd);
1596
ca07561a
HV		 1597 switch (ctrl->id) {
1598 case V4L2_CID_BRIGHTNESS:
492959c7 1599 return ov7670_s_brightness(sd, ctrl->val);
ca07561a 1600 case V4L2_CID_CONTRAST:
492959c7 1601 return ov7670_s_contrast(sd, ctrl->val);
ca07561a 1602 case V4L2_CID_SATURATION:
492959c7
JM		 1603 return ov7670_s_sat_hue(sd,
1604 info->saturation->val, info->hue->val);
ca07561a 1605 case V4L2_CID_VFLIP:
492959c7 1606 return ov7670_s_vflip(sd, ctrl->val);
ca07561a 1607 case V4L2_CID_HFLIP:
492959c7 1608 return ov7670_s_hflip(sd, ctrl->val);
81898671 1609 case V4L2_CID_AUTOGAIN:
492959c7
JM		 1610 /* Only set manual gain if auto gain is not explicitly
1611 turned on. */
1612 if (!ctrl->val) {
1613 /* ov7670_s_gain turns off auto gain */
1614 return ov7670_s_gain(sd, info->gain->val);
1615 }
1616 return ov7670_s_autogain(sd, ctrl->val);
364e9337 1617 case V4L2_CID_EXPOSURE_AUTO:
492959c7
JM		 1618 /* Only set manual exposure if auto exposure is not explicitly
1619 turned on. */
1620 if (ctrl->val == V4L2_EXPOSURE_MANUAL) {
1621 /* ov7670_s_exp turns off auto exposure */
1622 return ov7670_s_exp(sd, info->exposure->val);
1623 }
1624 return ov7670_s_autoexp(sd, ctrl->val);
b48d908d
AM		 1625 case V4L2_CID_TEST_PATTERN:
1626 return ov7670_s_test_pattern(sd, ctrl->val);
ca07561a
HV		 1627 }
1628 return -EINVAL;
111f3356
JC		 1629}
1630
492959c7
JM		 1631static const struct v4l2_ctrl_ops ov7670_ctrl_ops = {
1632 .s_ctrl = ov7670_s_ctrl,
1633 .g_volatile_ctrl = ov7670_g_volatile_ctrl,
1634};
1635
b794aabf
HV		 1636#ifdef CONFIG_VIDEO_ADV_DEBUG
1637static int ov7670_g_register(struct v4l2_subdev *sd, struct v4l2_dbg_register *reg)
1638{
b794aabf
HV		 1639 unsigned char val = 0;
1640 int ret;
1641
b794aabf
HV		 1642 ret = ov7670_read(sd, reg->reg & 0xff, &val);
1643 reg->val = val;
1644 reg->size = 1;
1645 return ret;
1646}
1647
977ba3b1 1648static int ov7670_s_register(struct v4l2_subdev *sd, const struct v4l2_dbg_register *reg)
b794aabf 1649{
b794aabf
HV		 1650 ov7670_write(sd, reg->reg & 0xff, reg->val & 0xff);
1651 return 0;
1652}
1653#endif
1654
3d6a8fe2 1655static void ov7670_power_on(struct v4l2_subdev *sd)
71862f63
WY		 1656{
1657 struct ov7670_info *info = to_state(sd);
1658
3d6a8fe2
LR		 1659 if (info->on)
1660 return;
1661
030f9f68
LR		 1662 clk_prepare_enable(info->clk);
1663
71862f63 1664 if (info->pwdn_gpio)
3d6a8fe2
LR		 1665 gpiod_set_value(info->pwdn_gpio, 0);
1666 if (info->resetb_gpio) {
71862f63
WY		 1667 gpiod_set_value(info->resetb_gpio, 1);
1668 usleep_range(500, 1000);
1669 gpiod_set_value(info->resetb_gpio, 0);
71862f63 1670 }
030f9f68
LR		 1671 if (info->pwdn_gpio || info->resetb_gpio || info->clk)
1672 usleep_range(3000, 5000);
71862f63 1673
3d6a8fe2
LR		 1674 info->on = true;
1675}
1676
1677static void ov7670_power_off(struct v4l2_subdev *sd)
1678{
1679 struct ov7670_info *info = to_state(sd);
1680
1681 if (!info->on)
1682 return;
1683
030f9f68
LR		 1684 clk_disable_unprepare(info->clk);
1685
3d6a8fe2
LR		 1686 if (info->pwdn_gpio)
1687 gpiod_set_value(info->pwdn_gpio, 1);
1688
1689 info->on = false;
1690}
1691
1692static int ov7670_s_power(struct v4l2_subdev *sd, int on)
1693{
1694 struct ov7670_info *info = to_state(sd);
1695
1696 if (info->on == on)
1697 return 0;
1698
1699 if (on) {
3abafaf4 1700 ov7670_power_on(sd);
32ab688b 1701 ov7670_init(sd, 0);
3d6a8fe2
LR		 1702 ov7670_apply_fmt(sd);
1703 ov7675_apply_framerate(sd);
1704 v4l2_ctrl_handler_setup(&info->hdl);
1705 } else {
3abafaf4 1706 ov7670_power_off(sd);
3d6a8fe2
LR		 1707 }
1708
71862f63
WY		 1709 return 0;
1710}
1711
c0662dd4
WY		 1712static void ov7670_get_default_format(struct v4l2_subdev *sd,
1713 struct v4l2_mbus_framefmt *format)
1714{
1715 struct ov7670_info *info = to_state(sd);
1716
1717 format->width = info->devtype->win_sizes[0].width;
1718 format->height = info->devtype->win_sizes[0].height;
1719 format->colorspace = info->fmt->colorspace;
1720 format->code = info->fmt->mbus_code;
1721 format->field = V4L2_FIELD_NONE;
1722}
1723
1724#ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1725static int ov7670_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
1726{
1727 struct v4l2_mbus_framefmt *format =
0d346d2a 1728 v4l2_subdev_get_try_format(sd, fh->state, 0);
c0662dd4
WY		 1729
1730 ov7670_get_default_format(sd, format);
1731
1732 return 0;
1733}
1734#endif
1735
14386c2b 1736/* ----------------------------------------------------------------------- */
111f3356 1737
14386c2b 1738static const struct v4l2_subdev_core_ops ov7670_core_ops = {
14386c2b
HV		 1739 .reset = ov7670_reset,
1740 .init = ov7670_init,
3d6a8fe2 1741 .s_power = ov7670_s_power,
7852adf8
AM		 1742 .log_status = v4l2_ctrl_subdev_log_status,
1743 .subscribe_event = v4l2_ctrl_subdev_subscribe_event,
1744 .unsubscribe_event = v4l2_event_subdev_unsubscribe,
b794aabf
HV		 1745#ifdef CONFIG_VIDEO_ADV_DEBUG
1746 .g_register = ov7670_g_register,
1747 .s_register = ov7670_s_register,
1748#endif
14386c2b 1749};
111f3356 1750
14386c2b 1751static const struct v4l2_subdev_video_ops ov7670_video_ops = {
4471109e
HV		 1752 .s_frame_interval = ov7670_s_frame_interval,
1753 .g_frame_interval = ov7670_g_frame_interval,
17bef885
HV		 1754};
1755
1756static const struct v4l2_subdev_pad_ops ov7670_pad_ops = {
1757 .enum_frame_interval = ov7670_enum_frame_interval,
1758 .enum_frame_size = ov7670_enum_frame_size,
ebcff5fc 1759 .enum_mbus_code = ov7670_enum_mbus_code,
c0662dd4 1760 .get_fmt = ov7670_get_fmt,
717fd5b4 1761 .set_fmt = ov7670_set_fmt,
14386c2b 1762};
111f3356 1763
14386c2b
HV		 1764static const struct v4l2_subdev_ops ov7670_ops = {
1765 .core = &ov7670_core_ops,
1766 .video = &ov7670_video_ops,
17bef885 1767 .pad = &ov7670_pad_ops,
14386c2b 1768};
111f3356 1769
c0662dd4
WY		 1770#ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1771static const struct v4l2_subdev_internal_ops ov7670_subdev_internal_ops = {
1772 .open = ov7670_open,
1773};
1774#endif
1775
14386c2b 1776/* ----------------------------------------------------------------------- */
111f3356 1777
d058e237
JM		 1778static const struct ov7670_devtype ov7670_devdata[] = {
1779 [MODEL_OV7670] = {
1780 .win_sizes = ov7670_win_sizes,
1781 .n_win_sizes = ARRAY_SIZE(ov7670_win_sizes),
f6dd927f
JM		 1782 .set_framerate = ov7670_set_framerate_legacy,
1783 .get_framerate = ov7670_get_framerate_legacy,
d058e237
JM		 1784 },
1785 [MODEL_OV7675] = {
1786 .win_sizes = ov7675_win_sizes,
1787 .n_win_sizes = ARRAY_SIZE(ov7675_win_sizes),
f6dd927f
JM		 1788 .set_framerate = ov7675_set_framerate,
1789 .get_framerate = ov7675_get_framerate,
d058e237
JM		 1790 },
1791};
1792
a0c4164e
HV		 1793static int ov7670_init_gpio(struct i2c_client *client, struct ov7670_info *info)
1794{
1795 info->pwdn_gpio = devm_gpiod_get_optional(&client->dev, "powerdown",
1796 GPIOD_OUT_LOW);
1797 if (IS_ERR(info->pwdn_gpio)) {
1798 dev_info(&client->dev, "can't get %s GPIO\n", "powerdown");
1799 return PTR_ERR(info->pwdn_gpio);
1800 }
1801
1802 info->resetb_gpio = devm_gpiod_get_optional(&client->dev, "reset",
1803 GPIOD_OUT_LOW);
1804 if (IS_ERR(info->resetb_gpio)) {
1805 dev_info(&client->dev, "can't get %s GPIO\n", "reset");
1806 return PTR_ERR(info->resetb_gpio);
1807 }
1808
1809 usleep_range(3000, 5000);
1810
1811 return 0;
1812}
1813
01b84448
JM		 1814/*
1815 * ov7670_parse_dt() - Parse device tree to collect mbus configuration
1816 * properties
1817 */
1818static int ov7670_parse_dt(struct device *dev,
1819 struct ov7670_info *info)
1820{
1821 struct fwnode_handle *fwnode = dev_fwnode(dev);
60359a28 1822 struct v4l2_fwnode_endpoint bus_cfg = { .bus_type = 0 };
01b84448
JM		 1823 struct fwnode_handle *ep;
1824 int ret;
1825
1826 if (!fwnode)
1827 return -EINVAL;
1828
1829 info->pclk_hb_disable = false;
1830 if (fwnode_property_present(fwnode, "ov7670,pclk-hb-disable"))
1831 info->pclk_hb_disable = true;
1832
1833 ep = fwnode_graph_get_next_endpoint(fwnode, NULL);
1834 if (!ep)
1835 return -EINVAL;
1836
1837 ret = v4l2_fwnode_endpoint_parse(ep, &bus_cfg);
09a48f74
JM		 1838 fwnode_handle_put(ep);
1839 if (ret)
01b84448 1840 return ret;
01b84448
JM		 1841
1842 if (bus_cfg.bus_type != V4L2_MBUS_PARALLEL) {
1843 dev_err(dev, "Unsupported media bus type\n");
01b84448
JM		 1844 return ret;
1845 }
1846 info->mbus_config = bus_cfg.bus.parallel.flags;
1847
1848 return 0;
1849}
1850
14386c2b
HV		 1851static int ov7670_probe(struct i2c_client *client,
1852 const struct i2c_device_id *id)
111f3356 1853{
f6dd927f 1854 struct v4l2_fract tpf;
14386c2b 1855 struct v4l2_subdev *sd;
f9a76156 1856 struct ov7670_info *info;
3c7c9370 1857 int ret;
111f3356 1858
c02b211d 1859 info = devm_kzalloc(&client->dev, sizeof(*info), GFP_KERNEL);
14386c2b 1860 if (info == NULL)
111f3356 1861 return -ENOMEM;
14386c2b
HV		 1862 sd = &info->sd;
1863 v4l2_i2c_subdev_init(sd, client, &ov7670_ops);
1864
c0662dd4
WY		 1865#ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1866 sd->internal_ops = &ov7670_subdev_internal_ops;
7852adf8 1867 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS;
c0662dd4
WY		 1868#endif
1869
3c7c9370 1870 info->clock_speed = 30; /* default: a guess */
01b84448
JM		 1871
1872 if (dev_fwnode(&client->dev)) {
1873 ret = ov7670_parse_dt(&client->dev, info);
1874 if (ret)
1875 return ret;
1876
1877 } else if (client->dev.platform_data) {
3c7c9370
HV		 1878 struct ov7670_config *config = client->dev.platform_data;
1879
1880 /*
1881 * Must apply configuration before initializing device, because it
1882 * selects I/O method.
1883 */
1884 info->min_width = config->min_width;
1885 info->min_height = config->min_height;
1886 info->use_smbus = config->use_smbus;
1887
1888 if (config->clock_speed)
1889 info->clock_speed = config->clock_speed;
04ee6d92 1890
61da76be 1891 if (config->pll_bypass)
04ee6d92 1892 info->pll_bypass = true;
ee95258e
JM		 1893
1894 if (config->pclk_hb_disable)
1895 info->pclk_hb_disable = true;
3c7c9370
HV		 1896 }
1897
786fa584
LR		 1898 info->clk = devm_clk_get(&client->dev, "xclk"); /* optional */
1899 if (IS_ERR(info->clk)) {
1900 ret = PTR_ERR(info->clk);
1901 if (ret == -ENOENT)
1902 info->clk = NULL;
1903 else
1904 return ret;
1905 }
3d6a8fe2 1906
030f9f68
LR		 1907 ret = ov7670_init_gpio(client, info);
1908 if (ret)
1909 return ret;
0a024d63 1910
030f9f68
LR		 1911 ov7670_power_on(sd);
1912
1913 if (info->clk) {
786fa584
LR		 1914 info->clock_speed = clk_get_rate(info->clk) / 1000000;
1915 if (info->clock_speed < 10 || info->clock_speed > 48) {
1916 ret = -EINVAL;
030f9f68 1917 goto power_off;
786fa584 1918 }
0a024d63
HV		 1919 }
1920
3c7c9370
HV		 1921 /* Make sure it's an ov7670 */
1922 ret = ov7670_detect(sd);
1923 if (ret) {
1924 v4l_dbg(1, debug, client,
1925 "chip found @ 0x%x (%s) is not an ov7670 chip.\n",
1926 client->addr << 1, client->adapter->name);
71862f63 1927 goto power_off;
3c7c9370
HV		 1928 }
1929 v4l_info(client, "chip found @ 0x%02x (%s)\n",
1930 client->addr << 1, client->adapter->name);
1931
d058e237 1932 info->devtype = &ov7670_devdata[id->driver_data];
3c7c9370 1933 info->fmt = &ov7670_formats[0];
5556ab2a 1934 info->wsize = &info->devtype->win_sizes[0];
c0662dd4
WY		 1935
1936 ov7670_get_default_format(sd, &info->format);
1937
f6dd927f
JM		 1938 info->clkrc = 0;
1939
1940 /* Set default frame rate to 30 fps */
1941 tpf.numerator = 1;
1942 tpf.denominator = 30;
1943 info->devtype->set_framerate(sd, &tpf);
1944
492959c7
JM		 1945 v4l2_ctrl_handler_init(&info->hdl, 10);
1946 v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops,
1947 V4L2_CID_BRIGHTNESS, 0, 255, 1, 128);
1948 v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops,
1949 V4L2_CID_CONTRAST, 0, 127, 1, 64);
1950 v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops,
1951 V4L2_CID_VFLIP, 0, 1, 1, 0);
1952 v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops,
1953 V4L2_CID_HFLIP, 0, 1, 1, 0);
1954 info->saturation = v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops,
1955 V4L2_CID_SATURATION, 0, 256, 1, 128);
1956 info->hue = v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops,
1957 V4L2_CID_HUE, -180, 180, 5, 0);
1958 info->gain = v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops,
1959 V4L2_CID_GAIN, 0, 255, 1, 128);
1960 info->auto_gain = v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops,
1961 V4L2_CID_AUTOGAIN, 0, 1, 1, 1);
1962 info->exposure = v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops,
1963 V4L2_CID_EXPOSURE, 0, 65535, 1, 500);
1964 info->auto_exposure = v4l2_ctrl_new_std_menu(&info->hdl, &ov7670_ctrl_ops,
1965 V4L2_CID_EXPOSURE_AUTO, V4L2_EXPOSURE_MANUAL, 0,
1966 V4L2_EXPOSURE_AUTO);
b48d908d
AM		 1967 v4l2_ctrl_new_std_menu_items(&info->hdl, &ov7670_ctrl_ops,
1968 V4L2_CID_TEST_PATTERN,
1969 ARRAY_SIZE(ov7670_test_pattern_menu) - 1, 0, 0,
1970 ov7670_test_pattern_menu);
492959c7
JM		 1971 sd->ctrl_handler = &info->hdl;
1972 if (info->hdl.error) {
7d1b8619 1973 ret = info->hdl.error;
492959c7 1974
7d1b8619 1975 goto hdl_free;
492959c7
JM		 1976 }
1977 /*
1978 * We have checked empirically that hw allows to read back the gain
1979 * value chosen by auto gain but that's not the case for auto exposure.
1980 */
1981 v4l2_ctrl_auto_cluster(2, &info->auto_gain, 0, true);
1982 v4l2_ctrl_auto_cluster(2, &info->auto_exposure,
1983 V4L2_EXPOSURE_MANUAL, false);
1984 v4l2_ctrl_cluster(2, &info->saturation);
d94a26f0
WY		 1985
1986#if defined(CONFIG_MEDIA_CONTROLLER)
1987 info->pad.flags = MEDIA_PAD_FL_SOURCE;
1988 info->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
1989 ret = media_entity_pads_init(&info->sd.entity, 1, &info->pad);
1990 if (ret < 0)
1991 goto hdl_free;
1992#endif
1993
492959c7
JM		 1994 v4l2_ctrl_handler_setup(&info->hdl);
1995
7d1b8619
HV		 1996 ret = v4l2_async_register_subdev(&info->sd);
1997 if (ret < 0)
d94a26f0 1998 goto entity_cleanup;
7d1b8619 1999
030f9f68 2000 ov7670_power_off(sd);
111f3356 2001 return 0;
7d1b8619 2002
d94a26f0 2003entity_cleanup:
d94a26f0 2004 media_entity_cleanup(&info->sd.entity);
7d1b8619
HV		 2005hdl_free:
2006 v4l2_ctrl_handler_free(&info->hdl);
71862f63 2007power_off:
3d6a8fe2 2008 ov7670_power_off(sd);
7d1b8619 2009 return ret;
111f3356
JC		 2010}
2011
14386c2b 2012static int ov7670_remove(struct i2c_client *client)
111f3356 2013{
14386c2b 2014 struct v4l2_subdev *sd = i2c_get_clientdata(client);
492959c7 2015 struct ov7670_info *info = to_state(sd);
111f3356 2016
344aa836 2017 v4l2_async_unregister_subdev(sd);
492959c7 2018 v4l2_ctrl_handler_free(&info->hdl);
d94a26f0 2019 media_entity_cleanup(&info->sd.entity);
3d6a8fe2 2020 ov7670_power_off(sd);
14386c2b 2021 return 0;
111f3356
JC		 2022}
2023
14386c2b 2024static const struct i2c_device_id ov7670_id[] = {
d058e237
JM		 2025 { "ov7670", MODEL_OV7670 },
2026 { "ov7675", MODEL_OV7675 },
14386c2b
HV		 2027 { }
2028};
2029MODULE_DEVICE_TABLE(i2c, ov7670_id);
2030
a0c4164e
HV		 2031#if IS_ENABLED(CONFIG_OF)
2032static const struct of_device_id ov7670_of_match[] = {
2033 { .compatible = "ovti,ov7670", },
2034 { /* sentinel */ },
2035};
2036MODULE_DEVICE_TABLE(of, ov7670_of_match);
2037#endif
2038
ef2ac770
HV		 2039static struct i2c_driver ov7670_driver = {
2040 .driver = {
ef2ac770 2041 .name = "ov7670",
a0c4164e 2042 .of_match_table = of_match_ptr(ov7670_of_match),
ef2ac770
HV		 2043 },
2044 .probe = ov7670_probe,
2045 .remove = ov7670_remove,
2046 .id_table = ov7670_id,
111f3356 2047};
ef2ac770 2048
c6e8d86f 2049module_i2c_driver(ov7670_driver);
Ubuntu Jammy Linux kernel mirror