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Commit | Line | Data |
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111f3356 JC |
1 | /* |
2 | * A V4L2 driver for OmniVision OV7670 cameras. | |
3 | * | |
4 | * Copyright 2006 One Laptop Per Child Association, Inc. Written | |
5 | * by Jonathan Corbet with substantial inspiration from Mark | |
6 | * McClelland's ovcamchip code. | |
7 | * | |
77d5140f JC |
8 | * Copyright 2006-7 Jonathan Corbet <corbet@lwn.net> |
9 | * | |
111f3356 JC |
10 | * This file may be distributed under the terms of the GNU General |
11 | * Public License, version 2. | |
12 | */ | |
0a024d63 | 13 | #include <linux/clk.h> |
111f3356 JC |
14 | #include <linux/init.h> |
15 | #include <linux/module.h> | |
5a0e3ad6 | 16 | #include <linux/slab.h> |
14386c2b | 17 | #include <linux/i2c.h> |
111f3356 | 18 | #include <linux/delay.h> |
7e0a16f6 | 19 | #include <linux/videodev2.h> |
a0c4164e HV |
20 | #include <linux/gpio.h> |
21 | #include <linux/gpio/consumer.h> | |
14386c2b | 22 | #include <media/v4l2-device.h> |
7852adf8 | 23 | #include <media/v4l2-event.h> |
492959c7 | 24 | #include <media/v4l2-ctrls.h> |
01b84448 | 25 | #include <media/v4l2-fwnode.h> |
959f3bda | 26 | #include <media/v4l2-mediabus.h> |
4721b3eb | 27 | #include <media/v4l2-image-sizes.h> |
b5dcee22 | 28 | #include <media/i2c/ov7670.h> |
111f3356 | 29 | |
5e614475 | 30 | MODULE_AUTHOR("Jonathan Corbet <corbet@lwn.net>"); |
111f3356 JC |
31 | MODULE_DESCRIPTION("A low-level driver for OmniVision ov7670 sensors"); |
32 | MODULE_LICENSE("GPL"); | |
33 | ||
90ab5ee9 | 34 | static bool debug; |
14386c2b HV |
35 | module_param(debug, bool, 0644); |
36 | MODULE_PARM_DESC(debug, "Debug level (0-1)"); | |
37 | ||
111f3356 JC |
38 | /* |
39 | * The 7670 sits on i2c with ID 0x42 | |
40 | */ | |
41 | #define OV7670_I2C_ADDR 0x42 | |
42 | ||
f6dd927f JM |
43 | #define PLL_FACTOR 4 |
44 | ||
111f3356 JC |
45 | /* Registers */ |
46 | #define REG_GAIN 0x00 /* Gain lower 8 bits (rest in vref) */ | |
47 | #define REG_BLUE 0x01 /* blue gain */ | |
48 | #define REG_RED 0x02 /* red gain */ | |
49 | #define REG_VREF 0x03 /* Pieces of GAIN, VSTART, VSTOP */ | |
50 | #define REG_COM1 0x04 /* Control 1 */ | |
51 | #define COM1_CCIR656 0x40 /* CCIR656 enable */ | |
52 | #define REG_BAVE 0x05 /* U/B Average level */ | |
53 | #define REG_GbAVE 0x06 /* Y/Gb Average level */ | |
54 | #define REG_AECHH 0x07 /* AEC MS 5 bits */ | |
55 | #define REG_RAVE 0x08 /* V/R Average level */ | |
56 | #define REG_COM2 0x09 /* Control 2 */ | |
57 | #define COM2_SSLEEP 0x10 /* Soft sleep mode */ | |
58 | #define REG_PID 0x0a /* Product ID MSB */ | |
59 | #define REG_VER 0x0b /* Product ID LSB */ | |
60 | #define REG_COM3 0x0c /* Control 3 */ | |
61 | #define COM3_SWAP 0x40 /* Byte swap */ | |
62 | #define COM3_SCALEEN 0x08 /* Enable scaling */ | |
63 | #define COM3_DCWEN 0x04 /* Enable downsamp/crop/window */ | |
64 | #define REG_COM4 0x0d /* Control 4 */ | |
65 | #define REG_COM5 0x0e /* All "reserved" */ | |
66 | #define REG_COM6 0x0f /* Control 6 */ | |
67 | #define REG_AECH 0x10 /* More bits of AEC value */ | |
68 | #define REG_CLKRC 0x11 /* Clocl control */ | |
69 | #define CLK_EXT 0x40 /* Use external clock directly */ | |
70 | #define CLK_SCALE 0x3f /* Mask for internal clock scale */ | |
71 | #define REG_COM7 0x12 /* Control 7 */ | |
72 | #define COM7_RESET 0x80 /* Register reset */ | |
73 | #define COM7_FMT_MASK 0x38 | |
74 | #define COM7_FMT_VGA 0x00 | |
75 | #define COM7_FMT_CIF 0x20 /* CIF format */ | |
76 | #define COM7_FMT_QVGA 0x10 /* QVGA format */ | |
77 | #define COM7_FMT_QCIF 0x08 /* QCIF format */ | |
78 | #define COM7_RGB 0x04 /* bits 0 and 2 - RGB format */ | |
79 | #define COM7_YUV 0x00 /* YUV */ | |
80 | #define COM7_BAYER 0x01 /* Bayer format */ | |
81 | #define COM7_PBAYER 0x05 /* "Processed bayer" */ | |
82 | #define REG_COM8 0x13 /* Control 8 */ | |
83 | #define COM8_FASTAEC 0x80 /* Enable fast AGC/AEC */ | |
84 | #define COM8_AECSTEP 0x40 /* Unlimited AEC step size */ | |
85 | #define COM8_BFILT 0x20 /* Band filter enable */ | |
86 | #define COM8_AGC 0x04 /* Auto gain enable */ | |
87 | #define COM8_AWB 0x02 /* White balance enable */ | |
88 | #define COM8_AEC 0x01 /* Auto exposure enable */ | |
89 | #define REG_COM9 0x14 /* Control 9 - gain ceiling */ | |
90 | #define REG_COM10 0x15 /* Control 10 */ | |
91 | #define COM10_HSYNC 0x40 /* HSYNC instead of HREF */ | |
92 | #define COM10_PCLK_HB 0x20 /* Suppress PCLK on horiz blank */ | |
93 | #define COM10_HREF_REV 0x08 /* Reverse HREF */ | |
94 | #define COM10_VS_LEAD 0x04 /* VSYNC on clock leading edge */ | |
95 | #define COM10_VS_NEG 0x02 /* VSYNC negative */ | |
96 | #define COM10_HS_NEG 0x01 /* HSYNC negative */ | |
97 | #define REG_HSTART 0x17 /* Horiz start high bits */ | |
98 | #define REG_HSTOP 0x18 /* Horiz stop high bits */ | |
99 | #define REG_VSTART 0x19 /* Vert start high bits */ | |
100 | #define REG_VSTOP 0x1a /* Vert stop high bits */ | |
101 | #define REG_PSHFT 0x1b /* Pixel delay after HREF */ | |
102 | #define REG_MIDH 0x1c /* Manuf. ID high */ | |
103 | #define REG_MIDL 0x1d /* Manuf. ID low */ | |
104 | #define REG_MVFP 0x1e /* Mirror / vflip */ | |
105 | #define MVFP_MIRROR 0x20 /* Mirror image */ | |
106 | #define MVFP_FLIP 0x10 /* Vertical flip */ | |
107 | ||
108 | #define REG_AEW 0x24 /* AGC upper limit */ | |
109 | #define REG_AEB 0x25 /* AGC lower limit */ | |
110 | #define REG_VPT 0x26 /* AGC/AEC fast mode op region */ | |
111 | #define REG_HSYST 0x30 /* HSYNC rising edge delay */ | |
112 | #define REG_HSYEN 0x31 /* HSYNC falling edge delay */ | |
113 | #define REG_HREF 0x32 /* HREF pieces */ | |
114 | #define REG_TSLB 0x3a /* lots of stuff */ | |
115 | #define TSLB_YLAST 0x04 /* UYVY or VYUY - see com13 */ | |
116 | #define REG_COM11 0x3b /* Control 11 */ | |
117 | #define COM11_NIGHT 0x80 /* NIght mode enable */ | |
118 | #define COM11_NMFR 0x60 /* Two bit NM frame rate */ | |
119 | #define COM11_HZAUTO 0x10 /* Auto detect 50/60 Hz */ | |
120 | #define COM11_50HZ 0x08 /* Manual 50Hz select */ | |
121 | #define COM11_EXP 0x02 | |
122 | #define REG_COM12 0x3c /* Control 12 */ | |
123 | #define COM12_HREF 0x80 /* HREF always */ | |
124 | #define REG_COM13 0x3d /* Control 13 */ | |
125 | #define COM13_GAMMA 0x80 /* Gamma enable */ | |
126 | #define COM13_UVSAT 0x40 /* UV saturation auto adjustment */ | |
127 | #define COM13_UVSWAP 0x01 /* V before U - w/TSLB */ | |
128 | #define REG_COM14 0x3e /* Control 14 */ | |
129 | #define COM14_DCWEN 0x10 /* DCW/PCLK-scale enable */ | |
130 | #define REG_EDGE 0x3f /* Edge enhancement factor */ | |
131 | #define REG_COM15 0x40 /* Control 15 */ | |
132 | #define COM15_R10F0 0x00 /* Data range 10 to F0 */ | |
133 | #define COM15_R01FE 0x80 /* 01 to FE */ | |
134 | #define COM15_R00FF 0xc0 /* 00 to FF */ | |
135 | #define COM15_RGB565 0x10 /* RGB565 output */ | |
136 | #define COM15_RGB555 0x30 /* RGB555 output */ | |
137 | #define REG_COM16 0x41 /* Control 16 */ | |
138 | #define COM16_AWBGAIN 0x08 /* AWB gain enable */ | |
139 | #define REG_COM17 0x42 /* Control 17 */ | |
140 | #define COM17_AECWIN 0xc0 /* AEC window - must match COM4 */ | |
141 | #define COM17_CBAR 0x08 /* DSP Color bar */ | |
142 | ||
f9a76156 JC |
143 | /* |
144 | * This matrix defines how the colors are generated, must be | |
145 | * tweaked to adjust hue and saturation. | |
146 | * | |
147 | * Order: v-red, v-green, v-blue, u-red, u-green, u-blue | |
148 | * | |
149 | * They are nine-bit signed quantities, with the sign bit | |
150 | * stored in 0x58. Sign for v-red is bit 0, and up from there. | |
151 | */ | |
152 | #define REG_CMATRIX_BASE 0x4f | |
153 | #define CMATRIX_LEN 6 | |
154 | #define REG_CMATRIX_SIGN 0x58 | |
155 | ||
156 | ||
111f3356 JC |
157 | #define REG_BRIGHT 0x55 /* Brightness */ |
158 | #define REG_CONTRAS 0x56 /* Contrast control */ | |
159 | ||
160 | #define REG_GFIX 0x69 /* Fix gain control */ | |
161 | ||
f6dd927f | 162 | #define REG_DBLV 0x6b /* PLL control an debugging */ |
61da76be JM |
163 | #define DBLV_BYPASS 0x0a /* Bypass PLL */ |
164 | #define DBLV_X4 0x4a /* clock x4 */ | |
165 | #define DBLV_X6 0x8a /* clock x6 */ | |
166 | #define DBLV_X8 0xca /* clock x8 */ | |
f6dd927f | 167 | |
b48d908d AM |
168 | #define REG_SCALING_XSC 0x70 /* Test pattern and horizontal scale factor */ |
169 | #define TEST_PATTTERN_0 0x80 | |
170 | #define REG_SCALING_YSC 0x71 /* Test pattern and vertical scale factor */ | |
171 | #define TEST_PATTTERN_1 0x80 | |
172 | ||
585553ec JC |
173 | #define REG_REG76 0x76 /* OV's name */ |
174 | #define R76_BLKPCOR 0x80 /* Black pixel correction enable */ | |
175 | #define R76_WHTPCOR 0x40 /* White pixel correction enable */ | |
176 | ||
111f3356 JC |
177 | #define REG_RGB444 0x8c /* RGB 444 control */ |
178 | #define R444_ENABLE 0x02 /* Turn on RGB444, overrides 5x5 */ | |
179 | #define R444_RGBX 0x01 /* Empty nibble at end */ | |
180 | ||
181 | #define REG_HAECC1 0x9f /* Hist AEC/AGC control 1 */ | |
182 | #define REG_HAECC2 0xa0 /* Hist AEC/AGC control 2 */ | |
183 | ||
184 | #define REG_BD50MAX 0xa5 /* 50hz banding step limit */ | |
185 | #define REG_HAECC3 0xa6 /* Hist AEC/AGC control 3 */ | |
186 | #define REG_HAECC4 0xa7 /* Hist AEC/AGC control 4 */ | |
187 | #define REG_HAECC5 0xa8 /* Hist AEC/AGC control 5 */ | |
188 | #define REG_HAECC6 0xa9 /* Hist AEC/AGC control 6 */ | |
189 | #define REG_HAECC7 0xaa /* Hist AEC/AGC control 7 */ | |
190 | #define REG_BD60MAX 0xab /* 60hz banding step limit */ | |
191 | ||
d058e237 JM |
192 | enum ov7670_model { |
193 | MODEL_OV7670 = 0, | |
194 | MODEL_OV7675, | |
195 | }; | |
196 | ||
197 | struct ov7670_win_size { | |
198 | int width; | |
199 | int height; | |
200 | unsigned char com7_bit; | |
201 | int hstart; /* Start/stop values for the camera. Note */ | |
202 | int hstop; /* that they do not always make complete */ | |
203 | int vstart; /* sense to humans, but evidently the sensor */ | |
204 | int vstop; /* will do the right thing... */ | |
205 | struct regval_list *regs; /* Regs to tweak */ | |
206 | }; | |
207 | ||
208 | struct ov7670_devtype { | |
209 | /* formats supported for each model */ | |
210 | struct ov7670_win_size *win_sizes; | |
211 | unsigned int n_win_sizes; | |
f6dd927f JM |
212 | /* callbacks for frame rate control */ |
213 | int (*set_framerate)(struct v4l2_subdev *, struct v4l2_fract *); | |
214 | void (*get_framerate)(struct v4l2_subdev *, struct v4l2_fract *); | |
d058e237 | 215 | }; |
111f3356 | 216 | |
f9a76156 JC |
217 | /* |
218 | * Information we maintain about a known sensor. | |
219 | */ | |
220 | struct ov7670_format_struct; /* coming later */ | |
221 | struct ov7670_info { | |
14386c2b | 222 | struct v4l2_subdev sd; |
d94a26f0 WY |
223 | #if defined(CONFIG_MEDIA_CONTROLLER) |
224 | struct media_pad pad; | |
225 | #endif | |
492959c7 JM |
226 | struct v4l2_ctrl_handler hdl; |
227 | struct { | |
228 | /* gain cluster */ | |
229 | struct v4l2_ctrl *auto_gain; | |
230 | struct v4l2_ctrl *gain; | |
231 | }; | |
232 | struct { | |
233 | /* exposure cluster */ | |
234 | struct v4l2_ctrl *auto_exposure; | |
235 | struct v4l2_ctrl *exposure; | |
236 | }; | |
237 | struct { | |
238 | /* saturation/hue cluster */ | |
239 | struct v4l2_ctrl *saturation; | |
240 | struct v4l2_ctrl *hue; | |
241 | }; | |
c0662dd4 | 242 | struct v4l2_mbus_framefmt format; |
f9a76156 | 243 | struct ov7670_format_struct *fmt; /* Current format */ |
5556ab2a | 244 | struct ov7670_win_size *wsize; |
0a024d63 | 245 | struct clk *clk; |
3d6a8fe2 | 246 | int on; |
a0c4164e HV |
247 | struct gpio_desc *resetb_gpio; |
248 | struct gpio_desc *pwdn_gpio; | |
01b84448 | 249 | unsigned int mbus_config; /* Media bus configuration flags */ |
75e2bdad DD |
250 | int min_width; /* Filter out smaller sizes */ |
251 | int min_height; /* Filter out smaller sizes */ | |
252 | int clock_speed; /* External clock speed (MHz) */ | |
d8d20155 | 253 | u8 clkrc; /* Clock divider value */ |
75e2bdad | 254 | bool use_smbus; /* Use smbus I/O instead of I2C */ |
04ee6d92 | 255 | bool pll_bypass; |
ee95258e | 256 | bool pclk_hb_disable; |
d058e237 | 257 | const struct ov7670_devtype *devtype; /* Device specifics */ |
f9a76156 JC |
258 | }; |
259 | ||
14386c2b HV |
260 | static inline struct ov7670_info *to_state(struct v4l2_subdev *sd) |
261 | { | |
262 | return container_of(sd, struct ov7670_info, sd); | |
263 | } | |
f9a76156 | 264 | |
492959c7 JM |
265 | static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl) |
266 | { | |
267 | return &container_of(ctrl->handler, struct ov7670_info, hdl)->sd; | |
268 | } | |
269 | ||
f9a76156 JC |
270 | |
271 | ||
111f3356 JC |
272 | /* |
273 | * The default register settings, as obtained from OmniVision. There | |
274 | * is really no making sense of most of these - lots of "reserved" values | |
275 | * and such. | |
276 | * | |
277 | * These settings give VGA YUYV. | |
278 | */ | |
279 | ||
280 | struct regval_list { | |
281 | unsigned char reg_num; | |
282 | unsigned char value; | |
283 | }; | |
284 | ||
285 | static struct regval_list ov7670_default_regs[] = { | |
286 | { REG_COM7, COM7_RESET }, | |
287 | /* | |
288 | * Clock scale: 3 = 15fps | |
289 | * 2 = 20fps | |
290 | * 1 = 30fps | |
291 | */ | |
f9a76156 | 292 | { REG_CLKRC, 0x1 }, /* OV: clock scale (30 fps) */ |
111f3356 JC |
293 | { REG_TSLB, 0x04 }, /* OV */ |
294 | { REG_COM7, 0 }, /* VGA */ | |
295 | /* | |
296 | * Set the hardware window. These values from OV don't entirely | |
297 | * make sense - hstop is less than hstart. But they work... | |
298 | */ | |
299 | { REG_HSTART, 0x13 }, { REG_HSTOP, 0x01 }, | |
300 | { REG_HREF, 0xb6 }, { REG_VSTART, 0x02 }, | |
301 | { REG_VSTOP, 0x7a }, { REG_VREF, 0x0a }, | |
302 | ||
303 | { REG_COM3, 0 }, { REG_COM14, 0 }, | |
304 | /* Mystery scaling numbers */ | |
b48d908d AM |
305 | { REG_SCALING_XSC, 0x3a }, |
306 | { REG_SCALING_YSC, 0x35 }, | |
111f3356 JC |
307 | { 0x72, 0x11 }, { 0x73, 0xf0 }, |
308 | { 0xa2, 0x02 }, { REG_COM10, 0x0 }, | |
309 | ||
310 | /* Gamma curve values */ | |
311 | { 0x7a, 0x20 }, { 0x7b, 0x10 }, | |
312 | { 0x7c, 0x1e }, { 0x7d, 0x35 }, | |
313 | { 0x7e, 0x5a }, { 0x7f, 0x69 }, | |
314 | { 0x80, 0x76 }, { 0x81, 0x80 }, | |
315 | { 0x82, 0x88 }, { 0x83, 0x8f }, | |
316 | { 0x84, 0x96 }, { 0x85, 0xa3 }, | |
317 | { 0x86, 0xaf }, { 0x87, 0xc4 }, | |
318 | { 0x88, 0xd7 }, { 0x89, 0xe8 }, | |
319 | ||
320 | /* AGC and AEC parameters. Note we start by disabling those features, | |
321 | then turn them only after tweaking the values. */ | |
322 | { REG_COM8, COM8_FASTAEC | COM8_AECSTEP | COM8_BFILT }, | |
323 | { REG_GAIN, 0 }, { REG_AECH, 0 }, | |
324 | { REG_COM4, 0x40 }, /* magic reserved bit */ | |
325 | { REG_COM9, 0x18 }, /* 4x gain + magic rsvd bit */ | |
326 | { REG_BD50MAX, 0x05 }, { REG_BD60MAX, 0x07 }, | |
327 | { REG_AEW, 0x95 }, { REG_AEB, 0x33 }, | |
328 | { REG_VPT, 0xe3 }, { REG_HAECC1, 0x78 }, | |
329 | { REG_HAECC2, 0x68 }, { 0xa1, 0x03 }, /* magic */ | |
330 | { REG_HAECC3, 0xd8 }, { REG_HAECC4, 0xd8 }, | |
331 | { REG_HAECC5, 0xf0 }, { REG_HAECC6, 0x90 }, | |
332 | { REG_HAECC7, 0x94 }, | |
333 | { REG_COM8, COM8_FASTAEC|COM8_AECSTEP|COM8_BFILT|COM8_AGC|COM8_AEC }, | |
334 | ||
335 | /* Almost all of these are magic "reserved" values. */ | |
336 | { REG_COM5, 0x61 }, { REG_COM6, 0x4b }, | |
7f7b12f0 | 337 | { 0x16, 0x02 }, { REG_MVFP, 0x07 }, |
111f3356 JC |
338 | { 0x21, 0x02 }, { 0x22, 0x91 }, |
339 | { 0x29, 0x07 }, { 0x33, 0x0b }, | |
340 | { 0x35, 0x0b }, { 0x37, 0x1d }, | |
341 | { 0x38, 0x71 }, { 0x39, 0x2a }, | |
342 | { REG_COM12, 0x78 }, { 0x4d, 0x40 }, | |
343 | { 0x4e, 0x20 }, { REG_GFIX, 0 }, | |
344 | { 0x6b, 0x4a }, { 0x74, 0x10 }, | |
345 | { 0x8d, 0x4f }, { 0x8e, 0 }, | |
346 | { 0x8f, 0 }, { 0x90, 0 }, | |
347 | { 0x91, 0 }, { 0x96, 0 }, | |
348 | { 0x9a, 0 }, { 0xb0, 0x84 }, | |
349 | { 0xb1, 0x0c }, { 0xb2, 0x0e }, | |
350 | { 0xb3, 0x82 }, { 0xb8, 0x0a }, | |
351 | ||
352 | /* More reserved magic, some of which tweaks white balance */ | |
353 | { 0x43, 0x0a }, { 0x44, 0xf0 }, | |
354 | { 0x45, 0x34 }, { 0x46, 0x58 }, | |
355 | { 0x47, 0x28 }, { 0x48, 0x3a }, | |
356 | { 0x59, 0x88 }, { 0x5a, 0x88 }, | |
357 | { 0x5b, 0x44 }, { 0x5c, 0x67 }, | |
358 | { 0x5d, 0x49 }, { 0x5e, 0x0e }, | |
359 | { 0x6c, 0x0a }, { 0x6d, 0x55 }, | |
360 | { 0x6e, 0x11 }, { 0x6f, 0x9f }, /* "9e for advance AWB" */ | |
361 | { 0x6a, 0x40 }, { REG_BLUE, 0x40 }, | |
362 | { REG_RED, 0x60 }, | |
363 | { REG_COM8, COM8_FASTAEC|COM8_AECSTEP|COM8_BFILT|COM8_AGC|COM8_AEC|COM8_AWB }, | |
364 | ||
365 | /* Matrix coefficients */ | |
366 | { 0x4f, 0x80 }, { 0x50, 0x80 }, | |
367 | { 0x51, 0 }, { 0x52, 0x22 }, | |
368 | { 0x53, 0x5e }, { 0x54, 0x80 }, | |
369 | { 0x58, 0x9e }, | |
370 | ||
371 | { REG_COM16, COM16_AWBGAIN }, { REG_EDGE, 0 }, | |
372 | { 0x75, 0x05 }, { 0x76, 0xe1 }, | |
373 | { 0x4c, 0 }, { 0x77, 0x01 }, | |
374 | { REG_COM13, 0xc3 }, { 0x4b, 0x09 }, | |
375 | { 0xc9, 0x60 }, { REG_COM16, 0x38 }, | |
376 | { 0x56, 0x40 }, | |
377 | ||
c8f5b2f5 | 378 | { 0x34, 0x11 }, { REG_COM11, COM11_EXP|COM11_HZAUTO }, |
111f3356 JC |
379 | { 0xa4, 0x88 }, { 0x96, 0 }, |
380 | { 0x97, 0x30 }, { 0x98, 0x20 }, | |
381 | { 0x99, 0x30 }, { 0x9a, 0x84 }, | |
382 | { 0x9b, 0x29 }, { 0x9c, 0x03 }, | |
383 | { 0x9d, 0x4c }, { 0x9e, 0x3f }, | |
384 | { 0x78, 0x04 }, | |
385 | ||
386 | /* Extra-weird stuff. Some sort of multiplexor register */ | |
387 | { 0x79, 0x01 }, { 0xc8, 0xf0 }, | |
388 | { 0x79, 0x0f }, { 0xc8, 0x00 }, | |
389 | { 0x79, 0x10 }, { 0xc8, 0x7e }, | |
390 | { 0x79, 0x0a }, { 0xc8, 0x80 }, | |
391 | { 0x79, 0x0b }, { 0xc8, 0x01 }, | |
392 | { 0x79, 0x0c }, { 0xc8, 0x0f }, | |
393 | { 0x79, 0x0d }, { 0xc8, 0x20 }, | |
394 | { 0x79, 0x09 }, { 0xc8, 0x80 }, | |
395 | { 0x79, 0x02 }, { 0xc8, 0xc0 }, | |
396 | { 0x79, 0x03 }, { 0xc8, 0x40 }, | |
397 | { 0x79, 0x05 }, { 0xc8, 0x30 }, | |
398 | { 0x79, 0x26 }, | |
399 | ||
111f3356 JC |
400 | { 0xff, 0xff }, /* END MARKER */ |
401 | }; | |
402 | ||
403 | ||
404 | /* | |
405 | * Here we'll try to encapsulate the changes for just the output | |
406 | * video format. | |
407 | * | |
408 | * RGB656 and YUV422 come from OV; RGB444 is homebrewed. | |
409 | * | |
410 | * IMPORTANT RULE: the first entry must be for COM7, see ov7670_s_fmt for why. | |
411 | */ | |
412 | ||
413 | ||
414 | static struct regval_list ov7670_fmt_yuv422[] = { | |
415 | { REG_COM7, 0x0 }, /* Selects YUV mode */ | |
416 | { REG_RGB444, 0 }, /* No RGB444 please */ | |
97693f91 | 417 | { REG_COM1, 0 }, /* CCIR601 */ |
111f3356 | 418 | { REG_COM15, COM15_R00FF }, |
c01b7429 | 419 | { REG_COM9, 0x48 }, /* 32x gain ceiling; 0x8 is reserved bit */ |
6e6a8b5a MCC |
420 | { 0x4f, 0x80 }, /* "matrix coefficient 1" */ |
421 | { 0x50, 0x80 }, /* "matrix coefficient 2" */ | |
f9a76156 | 422 | { 0x51, 0 }, /* vb */ |
6e6a8b5a MCC |
423 | { 0x52, 0x22 }, /* "matrix coefficient 4" */ |
424 | { 0x53, 0x5e }, /* "matrix coefficient 5" */ | |
425 | { 0x54, 0x80 }, /* "matrix coefficient 6" */ | |
111f3356 JC |
426 | { REG_COM13, COM13_GAMMA|COM13_UVSAT }, |
427 | { 0xff, 0xff }, | |
428 | }; | |
429 | ||
430 | static struct regval_list ov7670_fmt_rgb565[] = { | |
431 | { REG_COM7, COM7_RGB }, /* Selects RGB mode */ | |
432 | { REG_RGB444, 0 }, /* No RGB444 please */ | |
97693f91 | 433 | { REG_COM1, 0x0 }, /* CCIR601 */ |
111f3356 | 434 | { REG_COM15, COM15_RGB565 }, |
6e6a8b5a MCC |
435 | { REG_COM9, 0x38 }, /* 16x gain ceiling; 0x8 is reserved bit */ |
436 | { 0x4f, 0xb3 }, /* "matrix coefficient 1" */ | |
437 | { 0x50, 0xb3 }, /* "matrix coefficient 2" */ | |
f9a76156 | 438 | { 0x51, 0 }, /* vb */ |
6e6a8b5a MCC |
439 | { 0x52, 0x3d }, /* "matrix coefficient 4" */ |
440 | { 0x53, 0xa7 }, /* "matrix coefficient 5" */ | |
441 | { 0x54, 0xe4 }, /* "matrix coefficient 6" */ | |
111f3356 JC |
442 | { REG_COM13, COM13_GAMMA|COM13_UVSAT }, |
443 | { 0xff, 0xff }, | |
444 | }; | |
445 | ||
446 | static struct regval_list ov7670_fmt_rgb444[] = { | |
447 | { REG_COM7, COM7_RGB }, /* Selects RGB mode */ | |
448 | { REG_RGB444, R444_ENABLE }, /* Enable xxxxrrrr ggggbbbb */ | |
97693f91 | 449 | { REG_COM1, 0x0 }, /* CCIR601 */ |
111f3356 | 450 | { REG_COM15, COM15_R01FE|COM15_RGB565 }, /* Data range needed? */ |
6e6a8b5a MCC |
451 | { REG_COM9, 0x38 }, /* 16x gain ceiling; 0x8 is reserved bit */ |
452 | { 0x4f, 0xb3 }, /* "matrix coefficient 1" */ | |
453 | { 0x50, 0xb3 }, /* "matrix coefficient 2" */ | |
f9a76156 | 454 | { 0x51, 0 }, /* vb */ |
6e6a8b5a MCC |
455 | { 0x52, 0x3d }, /* "matrix coefficient 4" */ |
456 | { 0x53, 0xa7 }, /* "matrix coefficient 5" */ | |
457 | { 0x54, 0xe4 }, /* "matrix coefficient 6" */ | |
111f3356 JC |
458 | { REG_COM13, COM13_GAMMA|COM13_UVSAT|0x2 }, /* Magic rsvd bit */ |
459 | { 0xff, 0xff }, | |
460 | }; | |
461 | ||
585553ec JC |
462 | static struct regval_list ov7670_fmt_raw[] = { |
463 | { REG_COM7, COM7_BAYER }, | |
464 | { REG_COM13, 0x08 }, /* No gamma, magic rsvd bit */ | |
465 | { REG_COM16, 0x3d }, /* Edge enhancement, denoise */ | |
466 | { REG_REG76, 0xe1 }, /* Pix correction, magic rsvd */ | |
467 | { 0xff, 0xff }, | |
468 | }; | |
111f3356 JC |
469 | |
470 | ||
471 | ||
472 | /* | |
473 | * Low-level register I/O. | |
46714209 JC |
474 | * |
475 | * Note that there are two versions of these. On the XO 1, the | |
476 | * i2c controller only does SMBUS, so that's what we use. The | |
477 | * ov7670 is not really an SMBUS device, though, so the communication | |
478 | * is not always entirely reliable. | |
479 | */ | |
75e2bdad | 480 | static int ov7670_read_smbus(struct v4l2_subdev *sd, unsigned char reg, |
46714209 JC |
481 | unsigned char *value) |
482 | { | |
483 | struct i2c_client *client = v4l2_get_subdevdata(sd); | |
484 | int ret; | |
485 | ||
486 | ret = i2c_smbus_read_byte_data(client, reg); | |
487 | if (ret >= 0) { | |
488 | *value = (unsigned char)ret; | |
489 | ret = 0; | |
490 | } | |
491 | return ret; | |
492 | } | |
493 | ||
494 | ||
75e2bdad | 495 | static int ov7670_write_smbus(struct v4l2_subdev *sd, unsigned char reg, |
46714209 JC |
496 | unsigned char value) |
497 | { | |
498 | struct i2c_client *client = v4l2_get_subdevdata(sd); | |
499 | int ret = i2c_smbus_write_byte_data(client, reg, value); | |
500 | ||
501 | if (reg == REG_COM7 && (value & COM7_RESET)) | |
502 | msleep(5); /* Wait for reset to run */ | |
503 | return ret; | |
504 | } | |
505 | ||
46714209 JC |
506 | /* |
507 | * On most platforms, we'd rather do straight i2c I/O. | |
111f3356 | 508 | */ |
75e2bdad | 509 | static int ov7670_read_i2c(struct v4l2_subdev *sd, unsigned char reg, |
111f3356 JC |
510 | unsigned char *value) |
511 | { | |
14386c2b | 512 | struct i2c_client *client = v4l2_get_subdevdata(sd); |
2bf7de48 JC |
513 | u8 data = reg; |
514 | struct i2c_msg msg; | |
111f3356 JC |
515 | int ret; |
516 | ||
2bf7de48 JC |
517 | /* |
518 | * Send out the register address... | |
519 | */ | |
520 | msg.addr = client->addr; | |
521 | msg.flags = 0; | |
522 | msg.len = 1; | |
523 | msg.buf = &data; | |
524 | ret = i2c_transfer(client->adapter, &msg, 1); | |
525 | if (ret < 0) { | |
526 | printk(KERN_ERR "Error %d on register write\n", ret); | |
527 | return ret; | |
528 | } | |
529 | /* | |
530 | * ...then read back the result. | |
531 | */ | |
532 | msg.flags = I2C_M_RD; | |
533 | ret = i2c_transfer(client->adapter, &msg, 1); | |
bca5c2c5 | 534 | if (ret >= 0) { |
2bf7de48 | 535 | *value = data; |
bca5c2c5 AS |
536 | ret = 0; |
537 | } | |
111f3356 JC |
538 | return ret; |
539 | } | |
540 | ||
541 | ||
75e2bdad | 542 | static int ov7670_write_i2c(struct v4l2_subdev *sd, unsigned char reg, |
111f3356 JC |
543 | unsigned char value) |
544 | { | |
14386c2b | 545 | struct i2c_client *client = v4l2_get_subdevdata(sd); |
2bf7de48 JC |
546 | struct i2c_msg msg; |
547 | unsigned char data[2] = { reg, value }; | |
548 | int ret; | |
14386c2b | 549 | |
2bf7de48 JC |
550 | msg.addr = client->addr; |
551 | msg.flags = 0; | |
552 | msg.len = 2; | |
553 | msg.buf = data; | |
554 | ret = i2c_transfer(client->adapter, &msg, 1); | |
555 | if (ret > 0) | |
556 | ret = 0; | |
6d77444a | 557 | if (reg == REG_COM7 && (value & COM7_RESET)) |
97693f91 | 558 | msleep(5); /* Wait for reset to run */ |
6d77444a | 559 | return ret; |
111f3356 JC |
560 | } |
561 | ||
75e2bdad DD |
562 | static int ov7670_read(struct v4l2_subdev *sd, unsigned char reg, |
563 | unsigned char *value) | |
564 | { | |
565 | struct ov7670_info *info = to_state(sd); | |
566 | if (info->use_smbus) | |
567 | return ov7670_read_smbus(sd, reg, value); | |
568 | else | |
569 | return ov7670_read_i2c(sd, reg, value); | |
570 | } | |
571 | ||
572 | static int ov7670_write(struct v4l2_subdev *sd, unsigned char reg, | |
573 | unsigned char value) | |
574 | { | |
575 | struct ov7670_info *info = to_state(sd); | |
576 | if (info->use_smbus) | |
577 | return ov7670_write_smbus(sd, reg, value); | |
578 | else | |
579 | return ov7670_write_i2c(sd, reg, value); | |
580 | } | |
111f3356 | 581 | |
b48d908d AM |
582 | static int ov7670_update_bits(struct v4l2_subdev *sd, unsigned char reg, |
583 | unsigned char mask, unsigned char value) | |
584 | { | |
585 | unsigned char orig; | |
586 | int ret; | |
587 | ||
588 | ret = ov7670_read(sd, reg, &orig); | |
589 | if (ret) | |
590 | return ret; | |
591 | ||
592 | return ov7670_write(sd, reg, (orig & ~mask) | (value & mask)); | |
593 | } | |
594 | ||
111f3356 JC |
595 | /* |
596 | * Write a list of register settings; ff/ff stops the process. | |
597 | */ | |
14386c2b | 598 | static int ov7670_write_array(struct v4l2_subdev *sd, struct regval_list *vals) |
111f3356 JC |
599 | { |
600 | while (vals->reg_num != 0xff || vals->value != 0xff) { | |
14386c2b | 601 | int ret = ov7670_write(sd, vals->reg_num, vals->value); |
111f3356 JC |
602 | if (ret < 0) |
603 | return ret; | |
604 | vals++; | |
605 | } | |
606 | return 0; | |
607 | } | |
608 | ||
609 | ||
610 | /* | |
611 | * Stuff that knows about the sensor. | |
612 | */ | |
14386c2b | 613 | static int ov7670_reset(struct v4l2_subdev *sd, u32 val) |
111f3356 | 614 | { |
14386c2b | 615 | ov7670_write(sd, REG_COM7, COM7_RESET); |
111f3356 | 616 | msleep(1); |
14386c2b | 617 | return 0; |
111f3356 JC |
618 | } |
619 | ||
620 | ||
14386c2b | 621 | static int ov7670_init(struct v4l2_subdev *sd, u32 val) |
111f3356 | 622 | { |
14386c2b | 623 | return ov7670_write_array(sd, ov7670_default_regs); |
111f3356 JC |
624 | } |
625 | ||
14386c2b | 626 | static int ov7670_detect(struct v4l2_subdev *sd) |
111f3356 JC |
627 | { |
628 | unsigned char v; | |
629 | int ret; | |
630 | ||
14386c2b | 631 | ret = ov7670_init(sd, 0); |
111f3356 JC |
632 | if (ret < 0) |
633 | return ret; | |
14386c2b | 634 | ret = ov7670_read(sd, REG_MIDH, &v); |
111f3356 JC |
635 | if (ret < 0) |
636 | return ret; | |
637 | if (v != 0x7f) /* OV manuf. id. */ | |
638 | return -ENODEV; | |
14386c2b | 639 | ret = ov7670_read(sd, REG_MIDL, &v); |
111f3356 JC |
640 | if (ret < 0) |
641 | return ret; | |
642 | if (v != 0xa2) | |
643 | return -ENODEV; | |
644 | /* | |
645 | * OK, we know we have an OmniVision chip...but which one? | |
646 | */ | |
14386c2b | 647 | ret = ov7670_read(sd, REG_PID, &v); |
111f3356 JC |
648 | if (ret < 0) |
649 | return ret; | |
650 | if (v != 0x76) /* PID + VER = 0x76 / 0x73 */ | |
651 | return -ENODEV; | |
14386c2b | 652 | ret = ov7670_read(sd, REG_VER, &v); |
111f3356 JC |
653 | if (ret < 0) |
654 | return ret; | |
655 | if (v != 0x73) /* PID + VER = 0x76 / 0x73 */ | |
656 | return -ENODEV; | |
657 | return 0; | |
658 | } | |
659 | ||
660 | ||
f9a76156 JC |
661 | /* |
662 | * Store information about the video data format. The color matrix | |
663 | * is deeply tied into the format, so keep the relevant values here. | |
959f3bda | 664 | * The magic matrix numbers come from OmniVision. |
f9a76156 | 665 | */ |
111f3356 | 666 | static struct ov7670_format_struct { |
f5fe58fd | 667 | u32 mbus_code; |
959f3bda | 668 | enum v4l2_colorspace colorspace; |
111f3356 | 669 | struct regval_list *regs; |
f9a76156 | 670 | int cmatrix[CMATRIX_LEN]; |
111f3356 JC |
671 | } ov7670_formats[] = { |
672 | { | |
f5fe58fd | 673 | .mbus_code = MEDIA_BUS_FMT_YUYV8_2X8, |
75eb9847 | 674 | .colorspace = V4L2_COLORSPACE_SRGB, |
6e6a8b5a | 675 | .regs = ov7670_fmt_yuv422, |
f9a76156 | 676 | .cmatrix = { 128, -128, 0, -34, -94, 128 }, |
111f3356 JC |
677 | }, |
678 | { | |
f5fe58fd | 679 | .mbus_code = MEDIA_BUS_FMT_RGB444_2X8_PADHI_LE, |
959f3bda | 680 | .colorspace = V4L2_COLORSPACE_SRGB, |
111f3356 | 681 | .regs = ov7670_fmt_rgb444, |
f9a76156 | 682 | .cmatrix = { 179, -179, 0, -61, -176, 228 }, |
111f3356 JC |
683 | }, |
684 | { | |
f5fe58fd | 685 | .mbus_code = MEDIA_BUS_FMT_RGB565_2X8_LE, |
959f3bda | 686 | .colorspace = V4L2_COLORSPACE_SRGB, |
111f3356 | 687 | .regs = ov7670_fmt_rgb565, |
f9a76156 | 688 | .cmatrix = { 179, -179, 0, -61, -176, 228 }, |
585553ec JC |
689 | }, |
690 | { | |
f5fe58fd | 691 | .mbus_code = MEDIA_BUS_FMT_SBGGR8_1X8, |
959f3bda | 692 | .colorspace = V4L2_COLORSPACE_SRGB, |
6e6a8b5a | 693 | .regs = ov7670_fmt_raw, |
585553ec | 694 | .cmatrix = { 0, 0, 0, 0, 0, 0 }, |
111f3356 | 695 | }, |
111f3356 | 696 | }; |
585553ec | 697 | #define N_OV7670_FMTS ARRAY_SIZE(ov7670_formats) |
111f3356 | 698 | |
111f3356 JC |
699 | |
700 | /* | |
701 | * Then there is the issue of window sizes. Try to capture the info here. | |
702 | */ | |
f9a76156 JC |
703 | |
704 | /* | |
705 | * QCIF mode is done (by OV) in a very strange way - it actually looks like | |
706 | * VGA with weird scaling options - they do *not* use the canned QCIF mode | |
707 | * which is allegedly provided by the sensor. So here's the weird register | |
708 | * settings. | |
709 | */ | |
710 | static struct regval_list ov7670_qcif_regs[] = { | |
711 | { REG_COM3, COM3_SCALEEN|COM3_DCWEN }, | |
712 | { REG_COM3, COM3_DCWEN }, | |
713 | { REG_COM14, COM14_DCWEN | 0x01}, | |
714 | { 0x73, 0xf1 }, | |
715 | { 0xa2, 0x52 }, | |
716 | { 0x7b, 0x1c }, | |
717 | { 0x7c, 0x28 }, | |
718 | { 0x7d, 0x3c }, | |
719 | { 0x7f, 0x69 }, | |
720 | { REG_COM9, 0x38 }, | |
721 | { 0xa1, 0x0b }, | |
722 | { 0x74, 0x19 }, | |
723 | { 0x9a, 0x80 }, | |
724 | { 0x43, 0x14 }, | |
725 | { REG_COM13, 0xc0 }, | |
726 | { 0xff, 0xff }, | |
727 | }; | |
728 | ||
d058e237 | 729 | static struct ov7670_win_size ov7670_win_sizes[] = { |
111f3356 JC |
730 | /* VGA */ |
731 | { | |
732 | .width = VGA_WIDTH, | |
733 | .height = VGA_HEIGHT, | |
734 | .com7_bit = COM7_FMT_VGA, | |
d058e237 JM |
735 | .hstart = 158, /* These values from */ |
736 | .hstop = 14, /* Omnivision */ | |
111f3356 JC |
737 | .vstart = 10, |
738 | .vstop = 490, | |
d058e237 | 739 | .regs = NULL, |
111f3356 JC |
740 | }, |
741 | /* CIF */ | |
742 | { | |
743 | .width = CIF_WIDTH, | |
744 | .height = CIF_HEIGHT, | |
745 | .com7_bit = COM7_FMT_CIF, | |
d058e237 | 746 | .hstart = 170, /* Empirically determined */ |
111f3356 JC |
747 | .hstop = 90, |
748 | .vstart = 14, | |
749 | .vstop = 494, | |
d058e237 | 750 | .regs = NULL, |
111f3356 JC |
751 | }, |
752 | /* QVGA */ | |
753 | { | |
754 | .width = QVGA_WIDTH, | |
755 | .height = QVGA_HEIGHT, | |
756 | .com7_bit = COM7_FMT_QVGA, | |
d058e237 | 757 | .hstart = 168, /* Empirically determined */ |
dc4589c8 DD |
758 | .hstop = 24, |
759 | .vstart = 12, | |
760 | .vstop = 492, | |
d058e237 | 761 | .regs = NULL, |
f9a76156 JC |
762 | }, |
763 | /* QCIF */ | |
764 | { | |
765 | .width = QCIF_WIDTH, | |
766 | .height = QCIF_HEIGHT, | |
767 | .com7_bit = COM7_FMT_VGA, /* see comment above */ | |
d058e237 | 768 | .hstart = 456, /* Empirically determined */ |
f9a76156 JC |
769 | .hstop = 24, |
770 | .vstart = 14, | |
771 | .vstop = 494, | |
d058e237 JM |
772 | .regs = ov7670_qcif_regs, |
773 | } | |
111f3356 JC |
774 | }; |
775 | ||
d058e237 JM |
776 | static struct ov7670_win_size ov7675_win_sizes[] = { |
777 | /* | |
778 | * Currently, only VGA is supported. Theoretically it could be possible | |
779 | * to support CIF, QVGA and QCIF too. Taking values for ov7670 as a | |
780 | * base and tweak them empirically could be required. | |
781 | */ | |
782 | { | |
783 | .width = VGA_WIDTH, | |
784 | .height = VGA_HEIGHT, | |
785 | .com7_bit = COM7_FMT_VGA, | |
786 | .hstart = 158, /* These values from */ | |
787 | .hstop = 14, /* Omnivision */ | |
788 | .vstart = 14, /* Empirically determined */ | |
789 | .vstop = 494, | |
790 | .regs = NULL, | |
791 | } | |
792 | }; | |
111f3356 | 793 | |
f6dd927f JM |
794 | static void ov7675_get_framerate(struct v4l2_subdev *sd, |
795 | struct v4l2_fract *tpf) | |
796 | { | |
797 | struct ov7670_info *info = to_state(sd); | |
798 | u32 clkrc = info->clkrc; | |
04ee6d92 JM |
799 | int pll_factor; |
800 | ||
801 | if (info->pll_bypass) | |
802 | pll_factor = 1; | |
803 | else | |
804 | pll_factor = PLL_FACTOR; | |
f6dd927f JM |
805 | |
806 | clkrc++; | |
f5fe58fd | 807 | if (info->fmt->mbus_code == MEDIA_BUS_FMT_SBGGR8_1X8) |
f6dd927f JM |
808 | clkrc = (clkrc >> 1); |
809 | ||
810 | tpf->numerator = 1; | |
811 | tpf->denominator = (5 * pll_factor * info->clock_speed) / | |
812 | (4 * clkrc); | |
813 | } | |
814 | ||
40012cd5 LR |
815 | static int ov7675_apply_framerate(struct v4l2_subdev *sd) |
816 | { | |
817 | struct ov7670_info *info = to_state(sd); | |
818 | int ret; | |
819 | ||
820 | ret = ov7670_write(sd, REG_CLKRC, info->clkrc); | |
821 | if (ret < 0) | |
822 | return ret; | |
823 | ||
824 | return ov7670_write(sd, REG_DBLV, | |
825 | info->pll_bypass ? DBLV_BYPASS : DBLV_X4); | |
826 | } | |
827 | ||
f6dd927f JM |
828 | static int ov7675_set_framerate(struct v4l2_subdev *sd, |
829 | struct v4l2_fract *tpf) | |
830 | { | |
831 | struct ov7670_info *info = to_state(sd); | |
832 | u32 clkrc; | |
04ee6d92 | 833 | int pll_factor; |
f6dd927f JM |
834 | |
835 | /* | |
836 | * The formula is fps = 5/4*pixclk for YUV/RGB and | |
837 | * fps = 5/2*pixclk for RAW. | |
838 | * | |
839 | * pixclk = clock_speed / (clkrc + 1) * PLLfactor | |
840 | * | |
841 | */ | |
842 | if (tpf->numerator == 0 || tpf->denominator == 0) { | |
843 | clkrc = 0; | |
844 | } else { | |
40012cd5 | 845 | pll_factor = info->pll_bypass ? 1 : PLL_FACTOR; |
f6dd927f JM |
846 | clkrc = (5 * pll_factor * info->clock_speed * tpf->numerator) / |
847 | (4 * tpf->denominator); | |
f5fe58fd | 848 | if (info->fmt->mbus_code == MEDIA_BUS_FMT_SBGGR8_1X8) |
f6dd927f JM |
849 | clkrc = (clkrc << 1); |
850 | clkrc--; | |
851 | } | |
852 | ||
853 | /* | |
854 | * The datasheet claims that clkrc = 0 will divide the input clock by 1 | |
855 | * but we've checked with an oscilloscope that it divides by 2 instead. | |
856 | * So, if clkrc = 0 just bypass the divider. | |
857 | */ | |
858 | if (clkrc <= 0) | |
859 | clkrc = CLK_EXT; | |
860 | else if (clkrc > CLK_SCALE) | |
861 | clkrc = CLK_SCALE; | |
862 | info->clkrc = clkrc; | |
863 | ||
864 | /* Recalculate frame rate */ | |
865 | ov7675_get_framerate(sd, tpf); | |
866 | ||
40012cd5 | 867 | return ov7675_apply_framerate(sd); |
f6dd927f JM |
868 | } |
869 | ||
870 | static void ov7670_get_framerate_legacy(struct v4l2_subdev *sd, | |
871 | struct v4l2_fract *tpf) | |
872 | { | |
873 | struct ov7670_info *info = to_state(sd); | |
874 | ||
875 | tpf->numerator = 1; | |
876 | tpf->denominator = info->clock_speed; | |
877 | if ((info->clkrc & CLK_EXT) == 0 && (info->clkrc & CLK_SCALE) > 1) | |
878 | tpf->denominator /= (info->clkrc & CLK_SCALE); | |
879 | } | |
880 | ||
881 | static int ov7670_set_framerate_legacy(struct v4l2_subdev *sd, | |
882 | struct v4l2_fract *tpf) | |
883 | { | |
884 | struct ov7670_info *info = to_state(sd); | |
885 | int div; | |
886 | ||
887 | if (tpf->numerator == 0 || tpf->denominator == 0) | |
888 | div = 1; /* Reset to full rate */ | |
889 | else | |
890 | div = (tpf->numerator * info->clock_speed) / tpf->denominator; | |
891 | if (div == 0) | |
892 | div = 1; | |
893 | else if (div > CLK_SCALE) | |
894 | div = CLK_SCALE; | |
895 | info->clkrc = (info->clkrc & 0x80) | div; | |
896 | tpf->numerator = 1; | |
897 | tpf->denominator = info->clock_speed / div; | |
898 | return ov7670_write(sd, REG_CLKRC, info->clkrc); | |
899 | } | |
900 | ||
111f3356 JC |
901 | /* |
902 | * Store a set of start/stop values into the camera. | |
903 | */ | |
14386c2b | 904 | static int ov7670_set_hw(struct v4l2_subdev *sd, int hstart, int hstop, |
111f3356 JC |
905 | int vstart, int vstop) |
906 | { | |
907 | int ret; | |
908 | unsigned char v; | |
909 | /* | |
910 | * Horizontal: 11 bits, top 8 live in hstart and hstop. Bottom 3 of | |
911 | * hstart are in href[2:0], bottom 3 of hstop in href[5:3]. There is | |
912 | * a mystery "edge offset" value in the top two bits of href. | |
913 | */ | |
14386c2b HV |
914 | ret = ov7670_write(sd, REG_HSTART, (hstart >> 3) & 0xff); |
915 | ret += ov7670_write(sd, REG_HSTOP, (hstop >> 3) & 0xff); | |
916 | ret += ov7670_read(sd, REG_HREF, &v); | |
111f3356 JC |
917 | v = (v & 0xc0) | ((hstop & 0x7) << 3) | (hstart & 0x7); |
918 | msleep(10); | |
14386c2b | 919 | ret += ov7670_write(sd, REG_HREF, v); |
111f3356 JC |
920 | /* |
921 | * Vertical: similar arrangement, but only 10 bits. | |
922 | */ | |
14386c2b HV |
923 | ret += ov7670_write(sd, REG_VSTART, (vstart >> 2) & 0xff); |
924 | ret += ov7670_write(sd, REG_VSTOP, (vstop >> 2) & 0xff); | |
925 | ret += ov7670_read(sd, REG_VREF, &v); | |
111f3356 JC |
926 | v = (v & 0xf0) | ((vstop & 0x3) << 2) | (vstart & 0x3); |
927 | msleep(10); | |
14386c2b | 928 | ret += ov7670_write(sd, REG_VREF, v); |
111f3356 JC |
929 | return ret; |
930 | } | |
931 | ||
932 | ||
ebcff5fc HV |
933 | static int ov7670_enum_mbus_code(struct v4l2_subdev *sd, |
934 | struct v4l2_subdev_pad_config *cfg, | |
935 | struct v4l2_subdev_mbus_code_enum *code) | |
959f3bda | 936 | { |
ebcff5fc | 937 | if (code->pad || code->index >= N_OV7670_FMTS) |
959f3bda HV |
938 | return -EINVAL; |
939 | ||
ebcff5fc | 940 | code->code = ov7670_formats[code->index].mbus_code; |
959f3bda HV |
941 | return 0; |
942 | } | |
111f3356 | 943 | |
14386c2b | 944 | static int ov7670_try_fmt_internal(struct v4l2_subdev *sd, |
959f3bda | 945 | struct v4l2_mbus_framefmt *fmt, |
111f3356 JC |
946 | struct ov7670_format_struct **ret_fmt, |
947 | struct ov7670_win_size **ret_wsize) | |
948 | { | |
f748cd3e | 949 | int index, i; |
111f3356 | 950 | struct ov7670_win_size *wsize; |
d058e237 JM |
951 | struct ov7670_info *info = to_state(sd); |
952 | unsigned int n_win_sizes = info->devtype->n_win_sizes; | |
f748cd3e | 953 | unsigned int win_sizes_limit = n_win_sizes; |
111f3356 JC |
954 | |
955 | for (index = 0; index < N_OV7670_FMTS; index++) | |
959f3bda | 956 | if (ov7670_formats[index].mbus_code == fmt->code) |
111f3356 | 957 | break; |
cd257a6f DD |
958 | if (index >= N_OV7670_FMTS) { |
959 | /* default to first format */ | |
960 | index = 0; | |
959f3bda | 961 | fmt->code = ov7670_formats[0].mbus_code; |
cd257a6f | 962 | } |
111f3356 JC |
963 | if (ret_fmt != NULL) |
964 | *ret_fmt = ov7670_formats + index; | |
965 | /* | |
966 | * Fields: the OV devices claim to be progressive. | |
967 | */ | |
959f3bda | 968 | fmt->field = V4L2_FIELD_NONE; |
f748cd3e JM |
969 | |
970 | /* | |
971 | * Don't consider values that don't match min_height and min_width | |
972 | * constraints. | |
973 | */ | |
974 | if (info->min_width || info->min_height) | |
975 | for (i = 0; i < n_win_sizes; i++) { | |
976 | wsize = info->devtype->win_sizes + i; | |
977 | ||
978 | if (wsize->width < info->min_width || | |
979 | wsize->height < info->min_height) { | |
980 | win_sizes_limit = i; | |
981 | break; | |
982 | } | |
983 | } | |
111f3356 JC |
984 | /* |
985 | * Round requested image size down to the nearest | |
986 | * we support, but not below the smallest. | |
987 | */ | |
d058e237 | 988 | for (wsize = info->devtype->win_sizes; |
f748cd3e | 989 | wsize < info->devtype->win_sizes + win_sizes_limit; wsize++) |
959f3bda | 990 | if (fmt->width >= wsize->width && fmt->height >= wsize->height) |
111f3356 | 991 | break; |
f748cd3e | 992 | if (wsize >= info->devtype->win_sizes + win_sizes_limit) |
111f3356 JC |
993 | wsize--; /* Take the smallest one */ |
994 | if (ret_wsize != NULL) | |
995 | *ret_wsize = wsize; | |
996 | /* | |
997 | * Note the size we'll actually handle. | |
998 | */ | |
959f3bda HV |
999 | fmt->width = wsize->width; |
1000 | fmt->height = wsize->height; | |
1001 | fmt->colorspace = ov7670_formats[index].colorspace; | |
c0662dd4 WY |
1002 | |
1003 | info->format = *fmt; | |
1004 | ||
111f3356 | 1005 | return 0; |
111f3356 JC |
1006 | } |
1007 | ||
5556ab2a | 1008 | static int ov7670_apply_fmt(struct v4l2_subdev *sd) |
111f3356 | 1009 | { |
14386c2b | 1010 | struct ov7670_info *info = to_state(sd); |
5556ab2a | 1011 | struct ov7670_win_size *wsize = info->wsize; |
01b84448 | 1012 | unsigned char com7, com10 = 0; |
959f3bda | 1013 | int ret; |
111f3356 | 1014 | |
111f3356 JC |
1015 | /* |
1016 | * COM7 is a pain in the ass, it doesn't like to be read then | |
1017 | * quickly written afterward. But we have everything we need | |
1018 | * to set it absolutely here, as long as the format-specific | |
1019 | * register sets list it first. | |
1020 | */ | |
5556ab2a | 1021 | com7 = info->fmt->regs[0].value; |
111f3356 | 1022 | com7 |= wsize->com7_bit; |
01b84448 JM |
1023 | ret = ov7670_write(sd, REG_COM7, com7); |
1024 | if (ret) | |
1025 | return ret; | |
1026 | ||
1027 | /* | |
1028 | * Configure the media bus through COM10 register | |
1029 | */ | |
1030 | if (info->mbus_config & V4L2_MBUS_VSYNC_ACTIVE_LOW) | |
1031 | com10 |= COM10_VS_NEG; | |
1032 | if (info->mbus_config & V4L2_MBUS_HSYNC_ACTIVE_LOW) | |
1033 | com10 |= COM10_HREF_REV; | |
1034 | if (info->pclk_hb_disable) | |
1035 | com10 |= COM10_PCLK_HB; | |
1036 | ret = ov7670_write(sd, REG_COM10, com10); | |
1037 | if (ret) | |
1038 | return ret; | |
1039 | ||
111f3356 JC |
1040 | /* |
1041 | * Now write the rest of the array. Also store start/stops | |
1042 | */ | |
5556ab2a | 1043 | ret = ov7670_write_array(sd, info->fmt->regs + 1); |
01b84448 JM |
1044 | if (ret) |
1045 | return ret; | |
1046 | ||
1047 | ret = ov7670_set_hw(sd, wsize->hstart, wsize->hstop, wsize->vstart, | |
1048 | wsize->vstop); | |
1049 | if (ret) | |
1050 | return ret; | |
1051 | ||
1052 | if (wsize->regs) { | |
14386c2b | 1053 | ret = ov7670_write_array(sd, wsize->regs); |
01b84448 JM |
1054 | if (ret) |
1055 | return ret; | |
1056 | } | |
1057 | ||
d8d20155 JC |
1058 | /* |
1059 | * If we're running RGB565, we must rewrite clkrc after setting | |
1060 | * the other parameters or the image looks poor. If we're *not* | |
1061 | * doing RGB565, we must not rewrite clkrc or the image looks | |
1062 | * *really* poor. | |
a8e68c37 JC |
1063 | * |
1064 | * (Update) Now that we retain clkrc state, we should be able | |
1065 | * to write it unconditionally, and that will make the frame | |
1066 | * rate persistent too. | |
d8d20155 | 1067 | */ |
01b84448 JM |
1068 | ret = ov7670_write(sd, REG_CLKRC, info->clkrc); |
1069 | if (ret) | |
1070 | return ret; | |
1071 | ||
959f3bda HV |
1072 | return 0; |
1073 | } | |
1074 | ||
5556ab2a LR |
1075 | /* |
1076 | * Set a format. | |
1077 | */ | |
1078 | static int ov7670_set_fmt(struct v4l2_subdev *sd, | |
1079 | struct v4l2_subdev_pad_config *cfg, | |
1080 | struct v4l2_subdev_format *format) | |
1081 | { | |
1082 | struct ov7670_info *info = to_state(sd); | |
1083 | #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API | |
1084 | struct v4l2_mbus_framefmt *mbus_fmt; | |
1085 | #endif | |
1086 | int ret; | |
1087 | ||
1088 | if (format->pad) | |
1089 | return -EINVAL; | |
1090 | ||
1091 | if (format->which == V4L2_SUBDEV_FORMAT_TRY) { | |
1092 | ret = ov7670_try_fmt_internal(sd, &format->format, NULL, NULL); | |
1093 | if (ret) | |
1094 | return ret; | |
1095 | #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API | |
1096 | mbus_fmt = v4l2_subdev_get_try_format(sd, cfg, format->pad); | |
1097 | *mbus_fmt = format->format; | |
1098 | return 0; | |
1099 | #else | |
1100 | return -ENOTTY; | |
1101 | #endif | |
1102 | } | |
1103 | ||
1104 | ret = ov7670_try_fmt_internal(sd, &format->format, &info->fmt, &info->wsize); | |
1105 | if (ret) | |
1106 | return ret; | |
1107 | ||
1108 | ret = ov7670_apply_fmt(sd); | |
1109 | if (ret) | |
1110 | return ret; | |
1111 | ||
1112 | return 0; | |
1113 | } | |
1114 | ||
c0662dd4 WY |
1115 | static int ov7670_get_fmt(struct v4l2_subdev *sd, |
1116 | struct v4l2_subdev_pad_config *cfg, | |
1117 | struct v4l2_subdev_format *format) | |
1118 | { | |
1119 | struct ov7670_info *info = to_state(sd); | |
1120 | #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API | |
1121 | struct v4l2_mbus_framefmt *mbus_fmt; | |
1122 | #endif | |
1123 | ||
1124 | if (format->which == V4L2_SUBDEV_FORMAT_TRY) { | |
1125 | #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API | |
1126 | mbus_fmt = v4l2_subdev_get_try_format(sd, cfg, 0); | |
1127 | format->format = *mbus_fmt; | |
1128 | return 0; | |
1129 | #else | |
1130 | return -ENOTTY; | |
1131 | #endif | |
1132 | } else { | |
1133 | format->format = info->format; | |
1134 | } | |
1135 | ||
1136 | return 0; | |
1137 | } | |
1138 | ||
c8f5b2f5 JC |
1139 | /* |
1140 | * Implement G/S_PARM. There is a "high quality" mode we could try | |
1141 | * to do someday; for now, we just do the frame rate tweak. | |
1142 | */ | |
4471109e HV |
1143 | static int ov7670_g_frame_interval(struct v4l2_subdev *sd, |
1144 | struct v4l2_subdev_frame_interval *ival) | |
c8f5b2f5 | 1145 | { |
d8d20155 | 1146 | struct ov7670_info *info = to_state(sd); |
c8f5b2f5 | 1147 | |
d8d20155 | 1148 | |
4471109e | 1149 | info->devtype->get_framerate(sd, &ival->interval); |
f6dd927f | 1150 | |
c8f5b2f5 JC |
1151 | return 0; |
1152 | } | |
1153 | ||
4471109e HV |
1154 | static int ov7670_s_frame_interval(struct v4l2_subdev *sd, |
1155 | struct v4l2_subdev_frame_interval *ival) | |
c8f5b2f5 | 1156 | { |
4471109e | 1157 | struct v4l2_fract *tpf = &ival->interval; |
d8d20155 | 1158 | struct ov7670_info *info = to_state(sd); |
c8f5b2f5 | 1159 | |
d8d20155 | 1160 | |
f6dd927f | 1161 | return info->devtype->set_framerate(sd, tpf); |
c8f5b2f5 JC |
1162 | } |
1163 | ||
1164 | ||
111f3356 | 1165 | /* |
e99dfcf7 JC |
1166 | * Frame intervals. Since frame rates are controlled with the clock |
1167 | * divider, we can only do 30/n for integer n values. So no continuous | |
1168 | * or stepwise options. Here we just pick a handful of logical values. | |
111f3356 JC |
1169 | */ |
1170 | ||
e99dfcf7 | 1171 | static int ov7670_frame_rates[] = { 30, 15, 10, 5, 1 }; |
f9a76156 | 1172 | |
17bef885 HV |
1173 | static int ov7670_enum_frame_interval(struct v4l2_subdev *sd, |
1174 | struct v4l2_subdev_pad_config *cfg, | |
1175 | struct v4l2_subdev_frame_interval_enum *fie) | |
e99dfcf7 | 1176 | { |
b8cc79fd HV |
1177 | struct ov7670_info *info = to_state(sd); |
1178 | unsigned int n_win_sizes = info->devtype->n_win_sizes; | |
1179 | int i; | |
1180 | ||
17bef885 | 1181 | if (fie->pad) |
e99dfcf7 | 1182 | return -EINVAL; |
17bef885 HV |
1183 | if (fie->index >= ARRAY_SIZE(ov7670_frame_rates)) |
1184 | return -EINVAL; | |
b8cc79fd HV |
1185 | |
1186 | /* | |
1187 | * Check if the width/height is valid. | |
1188 | * | |
1189 | * If a minimum width/height was requested, filter out the capture | |
1190 | * windows that fall outside that. | |
1191 | */ | |
1192 | for (i = 0; i < n_win_sizes; i++) { | |
1193 | struct ov7670_win_size *win = &info->devtype->win_sizes[i]; | |
1194 | ||
1195 | if (info->min_width && win->width < info->min_width) | |
1196 | continue; | |
1197 | if (info->min_height && win->height < info->min_height) | |
1198 | continue; | |
1199 | if (fie->width == win->width && fie->height == win->height) | |
1200 | break; | |
1201 | } | |
1202 | if (i == n_win_sizes) | |
1203 | return -EINVAL; | |
17bef885 HV |
1204 | fie->interval.numerator = 1; |
1205 | fie->interval.denominator = ov7670_frame_rates[fie->index]; | |
e99dfcf7 JC |
1206 | return 0; |
1207 | } | |
f9a76156 | 1208 | |
b0326b7f DD |
1209 | /* |
1210 | * Frame size enumeration | |
1211 | */ | |
17bef885 HV |
1212 | static int ov7670_enum_frame_size(struct v4l2_subdev *sd, |
1213 | struct v4l2_subdev_pad_config *cfg, | |
1214 | struct v4l2_subdev_frame_size_enum *fse) | |
b0326b7f | 1215 | { |
75e2bdad DD |
1216 | struct ov7670_info *info = to_state(sd); |
1217 | int i; | |
1218 | int num_valid = -1; | |
17bef885 | 1219 | __u32 index = fse->index; |
d058e237 | 1220 | unsigned int n_win_sizes = info->devtype->n_win_sizes; |
b0326b7f | 1221 | |
17bef885 HV |
1222 | if (fse->pad) |
1223 | return -EINVAL; | |
1224 | ||
75e2bdad DD |
1225 | /* |
1226 | * If a minimum width/height was requested, filter out the capture | |
1227 | * windows that fall outside that. | |
1228 | */ | |
d058e237 | 1229 | for (i = 0; i < n_win_sizes; i++) { |
322e6d19 | 1230 | struct ov7670_win_size *win = &info->devtype->win_sizes[i]; |
75e2bdad DD |
1231 | if (info->min_width && win->width < info->min_width) |
1232 | continue; | |
1233 | if (info->min_height && win->height < info->min_height) | |
1234 | continue; | |
1235 | if (index == ++num_valid) { | |
17bef885 HV |
1236 | fse->min_width = fse->max_width = win->width; |
1237 | fse->min_height = fse->max_height = win->height; | |
75e2bdad DD |
1238 | return 0; |
1239 | } | |
1240 | } | |
1241 | ||
1242 | return -EINVAL; | |
b0326b7f DD |
1243 | } |
1244 | ||
e99dfcf7 JC |
1245 | /* |
1246 | * Code for dealing with controls. | |
1247 | */ | |
f9a76156 | 1248 | |
14386c2b | 1249 | static int ov7670_store_cmatrix(struct v4l2_subdev *sd, |
f9a76156 JC |
1250 | int matrix[CMATRIX_LEN]) |
1251 | { | |
1252 | int i, ret; | |
e3bf20de | 1253 | unsigned char signbits = 0; |
f9a76156 JC |
1254 | |
1255 | /* | |
1256 | * Weird crap seems to exist in the upper part of | |
1257 | * the sign bits register, so let's preserve it. | |
1258 | */ | |
14386c2b | 1259 | ret = ov7670_read(sd, REG_CMATRIX_SIGN, &signbits); |
f9a76156 JC |
1260 | signbits &= 0xc0; |
1261 | ||
1262 | for (i = 0; i < CMATRIX_LEN; i++) { | |
1263 | unsigned char raw; | |
1264 | ||
1265 | if (matrix[i] < 0) { | |
1266 | signbits |= (1 << i); | |
1267 | if (matrix[i] < -255) | |
1268 | raw = 0xff; | |
1269 | else | |
1270 | raw = (-1 * matrix[i]) & 0xff; | |
1271 | } | |
1272 | else { | |
1273 | if (matrix[i] > 255) | |
1274 | raw = 0xff; | |
1275 | else | |
1276 | raw = matrix[i] & 0xff; | |
1277 | } | |
14386c2b | 1278 | ret += ov7670_write(sd, REG_CMATRIX_BASE + i, raw); |
f9a76156 | 1279 | } |
14386c2b | 1280 | ret += ov7670_write(sd, REG_CMATRIX_SIGN, signbits); |
f9a76156 JC |
1281 | return ret; |
1282 | } | |
1283 | ||
1284 | ||
1285 | /* | |
1286 | * Hue also requires messing with the color matrix. It also requires | |
1287 | * trig functions, which tend not to be well supported in the kernel. | |
1288 | * So here is a simple table of sine values, 0-90 degrees, in steps | |
1289 | * of five degrees. Values are multiplied by 1000. | |
1290 | * | |
1291 | * The following naive approximate trig functions require an argument | |
1292 | * carefully limited to -180 <= theta <= 180. | |
1293 | */ | |
1294 | #define SIN_STEP 5 | |
1295 | static const int ov7670_sin_table[] = { | |
1296 | 0, 87, 173, 258, 342, 422, | |
1297 | 499, 573, 642, 707, 766, 819, | |
1298 | 866, 906, 939, 965, 984, 996, | |
1299 | 1000 | |
1300 | }; | |
1301 | ||
1302 | static int ov7670_sine(int theta) | |
1303 | { | |
1304 | int chs = 1; | |
1305 | int sine; | |
1306 | ||
1307 | if (theta < 0) { | |
1308 | theta = -theta; | |
1309 | chs = -1; | |
1310 | } | |
1311 | if (theta <= 90) | |
1312 | sine = ov7670_sin_table[theta/SIN_STEP]; | |
1313 | else { | |
1314 | theta -= 90; | |
1315 | sine = 1000 - ov7670_sin_table[theta/SIN_STEP]; | |
1316 | } | |
1317 | return sine*chs; | |
1318 | } | |
1319 | ||
1320 | static int ov7670_cosine(int theta) | |
1321 | { | |
1322 | theta = 90 - theta; | |
1323 | if (theta > 180) | |
1324 | theta -= 360; | |
1325 | else if (theta < -180) | |
1326 | theta += 360; | |
1327 | return ov7670_sine(theta); | |
1328 | } | |
1329 | ||
1330 | ||
1331 | ||
1332 | ||
1333 | static void ov7670_calc_cmatrix(struct ov7670_info *info, | |
492959c7 | 1334 | int matrix[CMATRIX_LEN], int sat, int hue) |
f9a76156 JC |
1335 | { |
1336 | int i; | |
1337 | /* | |
1338 | * Apply the current saturation setting first. | |
1339 | */ | |
1340 | for (i = 0; i < CMATRIX_LEN; i++) | |
492959c7 | 1341 | matrix[i] = (info->fmt->cmatrix[i] * sat) >> 7; |
f9a76156 JC |
1342 | /* |
1343 | * Then, if need be, rotate the hue value. | |
1344 | */ | |
492959c7 | 1345 | if (hue != 0) { |
f9a76156 JC |
1346 | int sinth, costh, tmpmatrix[CMATRIX_LEN]; |
1347 | ||
1348 | memcpy(tmpmatrix, matrix, CMATRIX_LEN*sizeof(int)); | |
492959c7 JM |
1349 | sinth = ov7670_sine(hue); |
1350 | costh = ov7670_cosine(hue); | |
f9a76156 JC |
1351 | |
1352 | matrix[0] = (matrix[3]*sinth + matrix[0]*costh)/1000; | |
1353 | matrix[1] = (matrix[4]*sinth + matrix[1]*costh)/1000; | |
1354 | matrix[2] = (matrix[5]*sinth + matrix[2]*costh)/1000; | |
1355 | matrix[3] = (matrix[3]*costh - matrix[0]*sinth)/1000; | |
1356 | matrix[4] = (matrix[4]*costh - matrix[1]*sinth)/1000; | |
1357 | matrix[5] = (matrix[5]*costh - matrix[2]*sinth)/1000; | |
1358 | } | |
1359 | } | |
1360 | ||
1361 | ||
1362 | ||
492959c7 | 1363 | static int ov7670_s_sat_hue(struct v4l2_subdev *sd, int sat, int hue) |
f9a76156 | 1364 | { |
14386c2b | 1365 | struct ov7670_info *info = to_state(sd); |
f9a76156 JC |
1366 | int matrix[CMATRIX_LEN]; |
1367 | int ret; | |
1368 | ||
492959c7 | 1369 | ov7670_calc_cmatrix(info, matrix, sat, hue); |
14386c2b | 1370 | ret = ov7670_store_cmatrix(sd, matrix); |
f9a76156 JC |
1371 | return ret; |
1372 | } | |
1373 | ||
f9a76156 | 1374 | |
111f3356 JC |
1375 | /* |
1376 | * Some weird registers seem to store values in a sign/magnitude format! | |
1377 | */ | |
111f3356 JC |
1378 | |
1379 | static unsigned char ov7670_abs_to_sm(unsigned char v) | |
1380 | { | |
1381 | if (v > 127) | |
1382 | return v & 0x7f; | |
14386c2b | 1383 | return (128 - v) | 0x80; |
111f3356 JC |
1384 | } |
1385 | ||
ca07561a | 1386 | static int ov7670_s_brightness(struct v4l2_subdev *sd, int value) |
111f3356 | 1387 | { |
e3bf20de | 1388 | unsigned char com8 = 0, v; |
111f3356 JC |
1389 | int ret; |
1390 | ||
14386c2b | 1391 | ov7670_read(sd, REG_COM8, &com8); |
111f3356 | 1392 | com8 &= ~COM8_AEC; |
14386c2b | 1393 | ov7670_write(sd, REG_COM8, com8); |
f9a76156 | 1394 | v = ov7670_abs_to_sm(value); |
14386c2b | 1395 | ret = ov7670_write(sd, REG_BRIGHT, v); |
111f3356 JC |
1396 | return ret; |
1397 | } | |
1398 | ||
ca07561a | 1399 | static int ov7670_s_contrast(struct v4l2_subdev *sd, int value) |
111f3356 | 1400 | { |
14386c2b | 1401 | return ov7670_write(sd, REG_CONTRAS, (unsigned char) value); |
111f3356 JC |
1402 | } |
1403 | ||
ca07561a | 1404 | static int ov7670_s_hflip(struct v4l2_subdev *sd, int value) |
111f3356 | 1405 | { |
e3bf20de | 1406 | unsigned char v = 0; |
111f3356 JC |
1407 | int ret; |
1408 | ||
14386c2b | 1409 | ret = ov7670_read(sd, REG_MVFP, &v); |
111f3356 JC |
1410 | if (value) |
1411 | v |= MVFP_MIRROR; | |
1412 | else | |
1413 | v &= ~MVFP_MIRROR; | |
1414 | msleep(10); /* FIXME */ | |
14386c2b | 1415 | ret += ov7670_write(sd, REG_MVFP, v); |
111f3356 JC |
1416 | return ret; |
1417 | } | |
1418 | ||
ca07561a | 1419 | static int ov7670_s_vflip(struct v4l2_subdev *sd, int value) |
111f3356 | 1420 | { |
e3bf20de | 1421 | unsigned char v = 0; |
111f3356 JC |
1422 | int ret; |
1423 | ||
14386c2b | 1424 | ret = ov7670_read(sd, REG_MVFP, &v); |
111f3356 JC |
1425 | if (value) |
1426 | v |= MVFP_FLIP; | |
1427 | else | |
1428 | v &= ~MVFP_FLIP; | |
1429 | msleep(10); /* FIXME */ | |
14386c2b | 1430 | ret += ov7670_write(sd, REG_MVFP, v); |
111f3356 JC |
1431 | return ret; |
1432 | } | |
1433 | ||
81898671 JC |
1434 | /* |
1435 | * GAIN is split between REG_GAIN and REG_VREF[7:6]. If one believes | |
1436 | * the data sheet, the VREF parts should be the most significant, but | |
1437 | * experience shows otherwise. There seems to be little value in | |
1438 | * messing with the VREF bits, so we leave them alone. | |
1439 | */ | |
1440 | static int ov7670_g_gain(struct v4l2_subdev *sd, __s32 *value) | |
1441 | { | |
1442 | int ret; | |
1443 | unsigned char gain; | |
1444 | ||
1445 | ret = ov7670_read(sd, REG_GAIN, &gain); | |
1446 | *value = gain; | |
1447 | return ret; | |
1448 | } | |
1449 | ||
1450 | static int ov7670_s_gain(struct v4l2_subdev *sd, int value) | |
1451 | { | |
1452 | int ret; | |
1453 | unsigned char com8; | |
1454 | ||
1455 | ret = ov7670_write(sd, REG_GAIN, value & 0xff); | |
1456 | /* Have to turn off AGC as well */ | |
1457 | if (ret == 0) { | |
1458 | ret = ov7670_read(sd, REG_COM8, &com8); | |
1459 | ret = ov7670_write(sd, REG_COM8, com8 & ~COM8_AGC); | |
1460 | } | |
1461 | return ret; | |
1462 | } | |
1463 | ||
1464 | /* | |
1465 | * Tweak autogain. | |
1466 | */ | |
81898671 JC |
1467 | static int ov7670_s_autogain(struct v4l2_subdev *sd, int value) |
1468 | { | |
1469 | int ret; | |
1470 | unsigned char com8; | |
1471 | ||
1472 | ret = ov7670_read(sd, REG_COM8, &com8); | |
1473 | if (ret == 0) { | |
1474 | if (value) | |
1475 | com8 |= COM8_AGC; | |
1476 | else | |
1477 | com8 &= ~COM8_AGC; | |
1478 | ret = ov7670_write(sd, REG_COM8, com8); | |
1479 | } | |
1480 | return ret; | |
1481 | } | |
1482 | ||
364e9337 JC |
1483 | static int ov7670_s_exp(struct v4l2_subdev *sd, int value) |
1484 | { | |
1485 | int ret; | |
1486 | unsigned char com1, com8, aech, aechh; | |
1487 | ||
1488 | ret = ov7670_read(sd, REG_COM1, &com1) + | |
d487df9e | 1489 | ov7670_read(sd, REG_COM8, &com8) + |
364e9337 JC |
1490 | ov7670_read(sd, REG_AECHH, &aechh); |
1491 | if (ret) | |
1492 | return ret; | |
1493 | ||
1494 | com1 = (com1 & 0xfc) | (value & 0x03); | |
1495 | aech = (value >> 2) & 0xff; | |
1496 | aechh = (aechh & 0xc0) | ((value >> 10) & 0x3f); | |
1497 | ret = ov7670_write(sd, REG_COM1, com1) + | |
1498 | ov7670_write(sd, REG_AECH, aech) + | |
1499 | ov7670_write(sd, REG_AECHH, aechh); | |
1500 | /* Have to turn off AEC as well */ | |
1501 | if (ret == 0) | |
1502 | ret = ov7670_write(sd, REG_COM8, com8 & ~COM8_AEC); | |
1503 | return ret; | |
1504 | } | |
1505 | ||
1506 | /* | |
1507 | * Tweak autoexposure. | |
1508 | */ | |
364e9337 JC |
1509 | static int ov7670_s_autoexp(struct v4l2_subdev *sd, |
1510 | enum v4l2_exposure_auto_type value) | |
1511 | { | |
1512 | int ret; | |
1513 | unsigned char com8; | |
1514 | ||
1515 | ret = ov7670_read(sd, REG_COM8, &com8); | |
1516 | if (ret == 0) { | |
1517 | if (value == V4L2_EXPOSURE_AUTO) | |
1518 | com8 |= COM8_AEC; | |
1519 | else | |
1520 | com8 &= ~COM8_AEC; | |
1521 | ret = ov7670_write(sd, REG_COM8, com8); | |
1522 | } | |
1523 | return ret; | |
1524 | } | |
1525 | ||
b48d908d AM |
1526 | static const char * const ov7670_test_pattern_menu[] = { |
1527 | "No test output", | |
1528 | "Shifting \"1\"", | |
1529 | "8-bar color bar", | |
1530 | "Fade to gray color bar", | |
1531 | }; | |
1532 | ||
1533 | static int ov7670_s_test_pattern(struct v4l2_subdev *sd, int value) | |
1534 | { | |
1535 | int ret; | |
1536 | ||
1537 | ret = ov7670_update_bits(sd, REG_SCALING_XSC, TEST_PATTTERN_0, | |
1538 | value & BIT(0) ? TEST_PATTTERN_0 : 0); | |
1539 | if (ret) | |
1540 | return ret; | |
1541 | ||
1542 | return ov7670_update_bits(sd, REG_SCALING_YSC, TEST_PATTTERN_1, | |
1543 | value & BIT(1) ? TEST_PATTTERN_1 : 0); | |
1544 | } | |
81898671 | 1545 | |
492959c7 | 1546 | static int ov7670_g_volatile_ctrl(struct v4l2_ctrl *ctrl) |
111f3356 | 1547 | { |
492959c7 JM |
1548 | struct v4l2_subdev *sd = to_sd(ctrl); |
1549 | struct ov7670_info *info = to_state(sd); | |
111f3356 | 1550 | |
ca07561a | 1551 | switch (ctrl->id) { |
81898671 | 1552 | case V4L2_CID_AUTOGAIN: |
492959c7 | 1553 | return ov7670_g_gain(sd, &info->gain->val); |
ca07561a HV |
1554 | } |
1555 | return -EINVAL; | |
111f3356 JC |
1556 | } |
1557 | ||
492959c7 | 1558 | static int ov7670_s_ctrl(struct v4l2_ctrl *ctrl) |
111f3356 | 1559 | { |
492959c7 JM |
1560 | struct v4l2_subdev *sd = to_sd(ctrl); |
1561 | struct ov7670_info *info = to_state(sd); | |
1562 | ||
ca07561a HV |
1563 | switch (ctrl->id) { |
1564 | case V4L2_CID_BRIGHTNESS: | |
492959c7 | 1565 | return ov7670_s_brightness(sd, ctrl->val); |
ca07561a | 1566 | case V4L2_CID_CONTRAST: |
492959c7 | 1567 | return ov7670_s_contrast(sd, ctrl->val); |
ca07561a | 1568 | case V4L2_CID_SATURATION: |
492959c7 JM |
1569 | return ov7670_s_sat_hue(sd, |
1570 | info->saturation->val, info->hue->val); | |
ca07561a | 1571 | case V4L2_CID_VFLIP: |
492959c7 | 1572 | return ov7670_s_vflip(sd, ctrl->val); |
ca07561a | 1573 | case V4L2_CID_HFLIP: |
492959c7 | 1574 | return ov7670_s_hflip(sd, ctrl->val); |
81898671 | 1575 | case V4L2_CID_AUTOGAIN: |
492959c7 JM |
1576 | /* Only set manual gain if auto gain is not explicitly |
1577 | turned on. */ | |
1578 | if (!ctrl->val) { | |
1579 | /* ov7670_s_gain turns off auto gain */ | |
1580 | return ov7670_s_gain(sd, info->gain->val); | |
1581 | } | |
1582 | return ov7670_s_autogain(sd, ctrl->val); | |
364e9337 | 1583 | case V4L2_CID_EXPOSURE_AUTO: |
492959c7 JM |
1584 | /* Only set manual exposure if auto exposure is not explicitly |
1585 | turned on. */ | |
1586 | if (ctrl->val == V4L2_EXPOSURE_MANUAL) { | |
1587 | /* ov7670_s_exp turns off auto exposure */ | |
1588 | return ov7670_s_exp(sd, info->exposure->val); | |
1589 | } | |
1590 | return ov7670_s_autoexp(sd, ctrl->val); | |
b48d908d AM |
1591 | case V4L2_CID_TEST_PATTERN: |
1592 | return ov7670_s_test_pattern(sd, ctrl->val); | |
ca07561a HV |
1593 | } |
1594 | return -EINVAL; | |
111f3356 JC |
1595 | } |
1596 | ||
492959c7 JM |
1597 | static const struct v4l2_ctrl_ops ov7670_ctrl_ops = { |
1598 | .s_ctrl = ov7670_s_ctrl, | |
1599 | .g_volatile_ctrl = ov7670_g_volatile_ctrl, | |
1600 | }; | |
1601 | ||
b794aabf HV |
1602 | #ifdef CONFIG_VIDEO_ADV_DEBUG |
1603 | static int ov7670_g_register(struct v4l2_subdev *sd, struct v4l2_dbg_register *reg) | |
1604 | { | |
b794aabf HV |
1605 | unsigned char val = 0; |
1606 | int ret; | |
1607 | ||
b794aabf HV |
1608 | ret = ov7670_read(sd, reg->reg & 0xff, &val); |
1609 | reg->val = val; | |
1610 | reg->size = 1; | |
1611 | return ret; | |
1612 | } | |
1613 | ||
977ba3b1 | 1614 | static int ov7670_s_register(struct v4l2_subdev *sd, const struct v4l2_dbg_register *reg) |
b794aabf | 1615 | { |
b794aabf HV |
1616 | ov7670_write(sd, reg->reg & 0xff, reg->val & 0xff); |
1617 | return 0; | |
1618 | } | |
1619 | #endif | |
1620 | ||
3d6a8fe2 | 1621 | static void ov7670_power_on(struct v4l2_subdev *sd) |
71862f63 WY |
1622 | { |
1623 | struct ov7670_info *info = to_state(sd); | |
1624 | ||
3d6a8fe2 LR |
1625 | if (info->on) |
1626 | return; | |
1627 | ||
030f9f68 LR |
1628 | clk_prepare_enable(info->clk); |
1629 | ||
71862f63 | 1630 | if (info->pwdn_gpio) |
3d6a8fe2 LR |
1631 | gpiod_set_value(info->pwdn_gpio, 0); |
1632 | if (info->resetb_gpio) { | |
71862f63 WY |
1633 | gpiod_set_value(info->resetb_gpio, 1); |
1634 | usleep_range(500, 1000); | |
1635 | gpiod_set_value(info->resetb_gpio, 0); | |
71862f63 | 1636 | } |
030f9f68 LR |
1637 | if (info->pwdn_gpio || info->resetb_gpio || info->clk) |
1638 | usleep_range(3000, 5000); | |
71862f63 | 1639 | |
3d6a8fe2 LR |
1640 | info->on = true; |
1641 | } | |
1642 | ||
1643 | static void ov7670_power_off(struct v4l2_subdev *sd) | |
1644 | { | |
1645 | struct ov7670_info *info = to_state(sd); | |
1646 | ||
1647 | if (!info->on) | |
1648 | return; | |
1649 | ||
030f9f68 LR |
1650 | clk_disable_unprepare(info->clk); |
1651 | ||
3d6a8fe2 LR |
1652 | if (info->pwdn_gpio) |
1653 | gpiod_set_value(info->pwdn_gpio, 1); | |
1654 | ||
1655 | info->on = false; | |
1656 | } | |
1657 | ||
1658 | static int ov7670_s_power(struct v4l2_subdev *sd, int on) | |
1659 | { | |
1660 | struct ov7670_info *info = to_state(sd); | |
1661 | ||
1662 | if (info->on == on) | |
1663 | return 0; | |
1664 | ||
1665 | if (on) { | |
1666 | ov7670_power_on (sd); | |
1667 | ov7670_apply_fmt(sd); | |
1668 | ov7675_apply_framerate(sd); | |
1669 | v4l2_ctrl_handler_setup(&info->hdl); | |
1670 | } else { | |
1671 | ov7670_power_off (sd); | |
1672 | } | |
1673 | ||
71862f63 WY |
1674 | return 0; |
1675 | } | |
1676 | ||
c0662dd4 WY |
1677 | static void ov7670_get_default_format(struct v4l2_subdev *sd, |
1678 | struct v4l2_mbus_framefmt *format) | |
1679 | { | |
1680 | struct ov7670_info *info = to_state(sd); | |
1681 | ||
1682 | format->width = info->devtype->win_sizes[0].width; | |
1683 | format->height = info->devtype->win_sizes[0].height; | |
1684 | format->colorspace = info->fmt->colorspace; | |
1685 | format->code = info->fmt->mbus_code; | |
1686 | format->field = V4L2_FIELD_NONE; | |
1687 | } | |
1688 | ||
1689 | #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API | |
1690 | static int ov7670_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh) | |
1691 | { | |
1692 | struct v4l2_mbus_framefmt *format = | |
1693 | v4l2_subdev_get_try_format(sd, fh->pad, 0); | |
1694 | ||
1695 | ov7670_get_default_format(sd, format); | |
1696 | ||
1697 | return 0; | |
1698 | } | |
1699 | #endif | |
1700 | ||
14386c2b | 1701 | /* ----------------------------------------------------------------------- */ |
111f3356 | 1702 | |
14386c2b | 1703 | static const struct v4l2_subdev_core_ops ov7670_core_ops = { |
14386c2b HV |
1704 | .reset = ov7670_reset, |
1705 | .init = ov7670_init, | |
3d6a8fe2 | 1706 | .s_power = ov7670_s_power, |
7852adf8 AM |
1707 | .log_status = v4l2_ctrl_subdev_log_status, |
1708 | .subscribe_event = v4l2_ctrl_subdev_subscribe_event, | |
1709 | .unsubscribe_event = v4l2_event_subdev_unsubscribe, | |
b794aabf HV |
1710 | #ifdef CONFIG_VIDEO_ADV_DEBUG |
1711 | .g_register = ov7670_g_register, | |
1712 | .s_register = ov7670_s_register, | |
1713 | #endif | |
14386c2b | 1714 | }; |
111f3356 | 1715 | |
14386c2b | 1716 | static const struct v4l2_subdev_video_ops ov7670_video_ops = { |
4471109e HV |
1717 | .s_frame_interval = ov7670_s_frame_interval, |
1718 | .g_frame_interval = ov7670_g_frame_interval, | |
17bef885 HV |
1719 | }; |
1720 | ||
1721 | static const struct v4l2_subdev_pad_ops ov7670_pad_ops = { | |
1722 | .enum_frame_interval = ov7670_enum_frame_interval, | |
1723 | .enum_frame_size = ov7670_enum_frame_size, | |
ebcff5fc | 1724 | .enum_mbus_code = ov7670_enum_mbus_code, |
c0662dd4 | 1725 | .get_fmt = ov7670_get_fmt, |
717fd5b4 | 1726 | .set_fmt = ov7670_set_fmt, |
14386c2b | 1727 | }; |
111f3356 | 1728 | |
14386c2b HV |
1729 | static const struct v4l2_subdev_ops ov7670_ops = { |
1730 | .core = &ov7670_core_ops, | |
1731 | .video = &ov7670_video_ops, | |
17bef885 | 1732 | .pad = &ov7670_pad_ops, |
14386c2b | 1733 | }; |
111f3356 | 1734 | |
c0662dd4 WY |
1735 | #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API |
1736 | static const struct v4l2_subdev_internal_ops ov7670_subdev_internal_ops = { | |
1737 | .open = ov7670_open, | |
1738 | }; | |
1739 | #endif | |
1740 | ||
14386c2b | 1741 | /* ----------------------------------------------------------------------- */ |
111f3356 | 1742 | |
d058e237 JM |
1743 | static const struct ov7670_devtype ov7670_devdata[] = { |
1744 | [MODEL_OV7670] = { | |
1745 | .win_sizes = ov7670_win_sizes, | |
1746 | .n_win_sizes = ARRAY_SIZE(ov7670_win_sizes), | |
f6dd927f JM |
1747 | .set_framerate = ov7670_set_framerate_legacy, |
1748 | .get_framerate = ov7670_get_framerate_legacy, | |
d058e237 JM |
1749 | }, |
1750 | [MODEL_OV7675] = { | |
1751 | .win_sizes = ov7675_win_sizes, | |
1752 | .n_win_sizes = ARRAY_SIZE(ov7675_win_sizes), | |
f6dd927f JM |
1753 | .set_framerate = ov7675_set_framerate, |
1754 | .get_framerate = ov7675_get_framerate, | |
d058e237 JM |
1755 | }, |
1756 | }; | |
1757 | ||
a0c4164e HV |
1758 | static int ov7670_init_gpio(struct i2c_client *client, struct ov7670_info *info) |
1759 | { | |
1760 | info->pwdn_gpio = devm_gpiod_get_optional(&client->dev, "powerdown", | |
1761 | GPIOD_OUT_LOW); | |
1762 | if (IS_ERR(info->pwdn_gpio)) { | |
1763 | dev_info(&client->dev, "can't get %s GPIO\n", "powerdown"); | |
1764 | return PTR_ERR(info->pwdn_gpio); | |
1765 | } | |
1766 | ||
1767 | info->resetb_gpio = devm_gpiod_get_optional(&client->dev, "reset", | |
1768 | GPIOD_OUT_LOW); | |
1769 | if (IS_ERR(info->resetb_gpio)) { | |
1770 | dev_info(&client->dev, "can't get %s GPIO\n", "reset"); | |
1771 | return PTR_ERR(info->resetb_gpio); | |
1772 | } | |
1773 | ||
1774 | usleep_range(3000, 5000); | |
1775 | ||
1776 | return 0; | |
1777 | } | |
1778 | ||
01b84448 JM |
1779 | /* |
1780 | * ov7670_parse_dt() - Parse device tree to collect mbus configuration | |
1781 | * properties | |
1782 | */ | |
1783 | static int ov7670_parse_dt(struct device *dev, | |
1784 | struct ov7670_info *info) | |
1785 | { | |
1786 | struct fwnode_handle *fwnode = dev_fwnode(dev); | |
60359a28 | 1787 | struct v4l2_fwnode_endpoint bus_cfg = { .bus_type = 0 }; |
01b84448 JM |
1788 | struct fwnode_handle *ep; |
1789 | int ret; | |
1790 | ||
1791 | if (!fwnode) | |
1792 | return -EINVAL; | |
1793 | ||
1794 | info->pclk_hb_disable = false; | |
1795 | if (fwnode_property_present(fwnode, "ov7670,pclk-hb-disable")) | |
1796 | info->pclk_hb_disable = true; | |
1797 | ||
1798 | ep = fwnode_graph_get_next_endpoint(fwnode, NULL); | |
1799 | if (!ep) | |
1800 | return -EINVAL; | |
1801 | ||
1802 | ret = v4l2_fwnode_endpoint_parse(ep, &bus_cfg); | |
09a48f74 JM |
1803 | fwnode_handle_put(ep); |
1804 | if (ret) | |
01b84448 | 1805 | return ret; |
01b84448 JM |
1806 | |
1807 | if (bus_cfg.bus_type != V4L2_MBUS_PARALLEL) { | |
1808 | dev_err(dev, "Unsupported media bus type\n"); | |
01b84448 JM |
1809 | return ret; |
1810 | } | |
1811 | info->mbus_config = bus_cfg.bus.parallel.flags; | |
1812 | ||
1813 | return 0; | |
1814 | } | |
1815 | ||
14386c2b HV |
1816 | static int ov7670_probe(struct i2c_client *client, |
1817 | const struct i2c_device_id *id) | |
111f3356 | 1818 | { |
f6dd927f | 1819 | struct v4l2_fract tpf; |
14386c2b | 1820 | struct v4l2_subdev *sd; |
f9a76156 | 1821 | struct ov7670_info *info; |
3c7c9370 | 1822 | int ret; |
111f3356 | 1823 | |
c02b211d | 1824 | info = devm_kzalloc(&client->dev, sizeof(*info), GFP_KERNEL); |
14386c2b | 1825 | if (info == NULL) |
111f3356 | 1826 | return -ENOMEM; |
14386c2b HV |
1827 | sd = &info->sd; |
1828 | v4l2_i2c_subdev_init(sd, client, &ov7670_ops); | |
1829 | ||
c0662dd4 WY |
1830 | #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API |
1831 | sd->internal_ops = &ov7670_subdev_internal_ops; | |
7852adf8 | 1832 | sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS; |
c0662dd4 WY |
1833 | #endif |
1834 | ||
3c7c9370 | 1835 | info->clock_speed = 30; /* default: a guess */ |
01b84448 JM |
1836 | |
1837 | if (dev_fwnode(&client->dev)) { | |
1838 | ret = ov7670_parse_dt(&client->dev, info); | |
1839 | if (ret) | |
1840 | return ret; | |
1841 | ||
1842 | } else if (client->dev.platform_data) { | |
3c7c9370 HV |
1843 | struct ov7670_config *config = client->dev.platform_data; |
1844 | ||
1845 | /* | |
1846 | * Must apply configuration before initializing device, because it | |
1847 | * selects I/O method. | |
1848 | */ | |
1849 | info->min_width = config->min_width; | |
1850 | info->min_height = config->min_height; | |
1851 | info->use_smbus = config->use_smbus; | |
1852 | ||
1853 | if (config->clock_speed) | |
1854 | info->clock_speed = config->clock_speed; | |
04ee6d92 | 1855 | |
61da76be | 1856 | if (config->pll_bypass) |
04ee6d92 | 1857 | info->pll_bypass = true; |
ee95258e JM |
1858 | |
1859 | if (config->pclk_hb_disable) | |
1860 | info->pclk_hb_disable = true; | |
3c7c9370 HV |
1861 | } |
1862 | ||
786fa584 LR |
1863 | info->clk = devm_clk_get(&client->dev, "xclk"); /* optional */ |
1864 | if (IS_ERR(info->clk)) { | |
1865 | ret = PTR_ERR(info->clk); | |
1866 | if (ret == -ENOENT) | |
1867 | info->clk = NULL; | |
1868 | else | |
1869 | return ret; | |
1870 | } | |
3d6a8fe2 | 1871 | |
030f9f68 LR |
1872 | ret = ov7670_init_gpio(client, info); |
1873 | if (ret) | |
1874 | return ret; | |
0a024d63 | 1875 | |
030f9f68 LR |
1876 | ov7670_power_on(sd); |
1877 | ||
1878 | if (info->clk) { | |
786fa584 LR |
1879 | info->clock_speed = clk_get_rate(info->clk) / 1000000; |
1880 | if (info->clock_speed < 10 || info->clock_speed > 48) { | |
1881 | ret = -EINVAL; | |
030f9f68 | 1882 | goto power_off; |
786fa584 | 1883 | } |
0a024d63 HV |
1884 | } |
1885 | ||
3c7c9370 HV |
1886 | /* Make sure it's an ov7670 */ |
1887 | ret = ov7670_detect(sd); | |
1888 | if (ret) { | |
1889 | v4l_dbg(1, debug, client, | |
1890 | "chip found @ 0x%x (%s) is not an ov7670 chip.\n", | |
1891 | client->addr << 1, client->adapter->name); | |
71862f63 | 1892 | goto power_off; |
3c7c9370 HV |
1893 | } |
1894 | v4l_info(client, "chip found @ 0x%02x (%s)\n", | |
1895 | client->addr << 1, client->adapter->name); | |
1896 | ||
d058e237 | 1897 | info->devtype = &ov7670_devdata[id->driver_data]; |
3c7c9370 | 1898 | info->fmt = &ov7670_formats[0]; |
5556ab2a | 1899 | info->wsize = &info->devtype->win_sizes[0]; |
c0662dd4 WY |
1900 | |
1901 | ov7670_get_default_format(sd, &info->format); | |
1902 | ||
f6dd927f JM |
1903 | info->clkrc = 0; |
1904 | ||
1905 | /* Set default frame rate to 30 fps */ | |
1906 | tpf.numerator = 1; | |
1907 | tpf.denominator = 30; | |
1908 | info->devtype->set_framerate(sd, &tpf); | |
1909 | ||
492959c7 JM |
1910 | v4l2_ctrl_handler_init(&info->hdl, 10); |
1911 | v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops, | |
1912 | V4L2_CID_BRIGHTNESS, 0, 255, 1, 128); | |
1913 | v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops, | |
1914 | V4L2_CID_CONTRAST, 0, 127, 1, 64); | |
1915 | v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops, | |
1916 | V4L2_CID_VFLIP, 0, 1, 1, 0); | |
1917 | v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops, | |
1918 | V4L2_CID_HFLIP, 0, 1, 1, 0); | |
1919 | info->saturation = v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops, | |
1920 | V4L2_CID_SATURATION, 0, 256, 1, 128); | |
1921 | info->hue = v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops, | |
1922 | V4L2_CID_HUE, -180, 180, 5, 0); | |
1923 | info->gain = v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops, | |
1924 | V4L2_CID_GAIN, 0, 255, 1, 128); | |
1925 | info->auto_gain = v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops, | |
1926 | V4L2_CID_AUTOGAIN, 0, 1, 1, 1); | |
1927 | info->exposure = v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops, | |
1928 | V4L2_CID_EXPOSURE, 0, 65535, 1, 500); | |
1929 | info->auto_exposure = v4l2_ctrl_new_std_menu(&info->hdl, &ov7670_ctrl_ops, | |
1930 | V4L2_CID_EXPOSURE_AUTO, V4L2_EXPOSURE_MANUAL, 0, | |
1931 | V4L2_EXPOSURE_AUTO); | |
b48d908d AM |
1932 | v4l2_ctrl_new_std_menu_items(&info->hdl, &ov7670_ctrl_ops, |
1933 | V4L2_CID_TEST_PATTERN, | |
1934 | ARRAY_SIZE(ov7670_test_pattern_menu) - 1, 0, 0, | |
1935 | ov7670_test_pattern_menu); | |
492959c7 JM |
1936 | sd->ctrl_handler = &info->hdl; |
1937 | if (info->hdl.error) { | |
7d1b8619 | 1938 | ret = info->hdl.error; |
492959c7 | 1939 | |
7d1b8619 | 1940 | goto hdl_free; |
492959c7 JM |
1941 | } |
1942 | /* | |
1943 | * We have checked empirically that hw allows to read back the gain | |
1944 | * value chosen by auto gain but that's not the case for auto exposure. | |
1945 | */ | |
1946 | v4l2_ctrl_auto_cluster(2, &info->auto_gain, 0, true); | |
1947 | v4l2_ctrl_auto_cluster(2, &info->auto_exposure, | |
1948 | V4L2_EXPOSURE_MANUAL, false); | |
1949 | v4l2_ctrl_cluster(2, &info->saturation); | |
d94a26f0 WY |
1950 | |
1951 | #if defined(CONFIG_MEDIA_CONTROLLER) | |
1952 | info->pad.flags = MEDIA_PAD_FL_SOURCE; | |
1953 | info->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR; | |
1954 | ret = media_entity_pads_init(&info->sd.entity, 1, &info->pad); | |
1955 | if (ret < 0) | |
1956 | goto hdl_free; | |
1957 | #endif | |
1958 | ||
492959c7 JM |
1959 | v4l2_ctrl_handler_setup(&info->hdl); |
1960 | ||
7d1b8619 HV |
1961 | ret = v4l2_async_register_subdev(&info->sd); |
1962 | if (ret < 0) | |
d94a26f0 | 1963 | goto entity_cleanup; |
7d1b8619 | 1964 | |
030f9f68 | 1965 | ov7670_power_off(sd); |
111f3356 | 1966 | return 0; |
7d1b8619 | 1967 | |
d94a26f0 | 1968 | entity_cleanup: |
d94a26f0 | 1969 | media_entity_cleanup(&info->sd.entity); |
7d1b8619 HV |
1970 | hdl_free: |
1971 | v4l2_ctrl_handler_free(&info->hdl); | |
71862f63 | 1972 | power_off: |
3d6a8fe2 | 1973 | ov7670_power_off(sd); |
7d1b8619 | 1974 | return ret; |
111f3356 JC |
1975 | } |
1976 | ||
14386c2b | 1977 | static int ov7670_remove(struct i2c_client *client) |
111f3356 | 1978 | { |
14386c2b | 1979 | struct v4l2_subdev *sd = i2c_get_clientdata(client); |
492959c7 | 1980 | struct ov7670_info *info = to_state(sd); |
111f3356 | 1981 | |
344aa836 | 1982 | v4l2_async_unregister_subdev(sd); |
492959c7 | 1983 | v4l2_ctrl_handler_free(&info->hdl); |
d94a26f0 | 1984 | media_entity_cleanup(&info->sd.entity); |
3d6a8fe2 | 1985 | ov7670_power_off(sd); |
14386c2b | 1986 | return 0; |
111f3356 JC |
1987 | } |
1988 | ||
14386c2b | 1989 | static const struct i2c_device_id ov7670_id[] = { |
d058e237 JM |
1990 | { "ov7670", MODEL_OV7670 }, |
1991 | { "ov7675", MODEL_OV7675 }, | |
14386c2b HV |
1992 | { } |
1993 | }; | |
1994 | MODULE_DEVICE_TABLE(i2c, ov7670_id); | |
1995 | ||
a0c4164e HV |
1996 | #if IS_ENABLED(CONFIG_OF) |
1997 | static const struct of_device_id ov7670_of_match[] = { | |
1998 | { .compatible = "ovti,ov7670", }, | |
1999 | { /* sentinel */ }, | |
2000 | }; | |
2001 | MODULE_DEVICE_TABLE(of, ov7670_of_match); | |
2002 | #endif | |
2003 | ||
ef2ac770 HV |
2004 | static struct i2c_driver ov7670_driver = { |
2005 | .driver = { | |
ef2ac770 | 2006 | .name = "ov7670", |
a0c4164e | 2007 | .of_match_table = of_match_ptr(ov7670_of_match), |
ef2ac770 HV |
2008 | }, |
2009 | .probe = ov7670_probe, | |
2010 | .remove = ov7670_remove, | |
2011 | .id_table = ov7670_id, | |
111f3356 | 2012 | }; |
ef2ac770 | 2013 | |
c6e8d86f | 2014 | module_i2c_driver(ov7670_driver); |