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111f3356 JC |
1 | /* |
2 | * A V4L2 driver for OmniVision OV7670 cameras. | |
3 | * | |
4 | * Copyright 2006 One Laptop Per Child Association, Inc. Written | |
5 | * by Jonathan Corbet with substantial inspiration from Mark | |
6 | * McClelland's ovcamchip code. | |
7 | * | |
77d5140f JC |
8 | * Copyright 2006-7 Jonathan Corbet <corbet@lwn.net> |
9 | * | |
111f3356 JC |
10 | * This file may be distributed under the terms of the GNU General |
11 | * Public License, version 2. | |
12 | */ | |
13 | #include <linux/init.h> | |
14 | #include <linux/module.h> | |
5a0e3ad6 | 15 | #include <linux/slab.h> |
14386c2b | 16 | #include <linux/i2c.h> |
111f3356 | 17 | #include <linux/delay.h> |
7e0a16f6 | 18 | #include <linux/videodev2.h> |
14386c2b | 19 | #include <media/v4l2-device.h> |
3434eb7e | 20 | #include <media/v4l2-chip-ident.h> |
959f3bda | 21 | #include <media/v4l2-mediabus.h> |
f8fc7298 | 22 | #include <media/ov7670.h> |
111f3356 | 23 | |
5e614475 | 24 | MODULE_AUTHOR("Jonathan Corbet <corbet@lwn.net>"); |
111f3356 JC |
25 | MODULE_DESCRIPTION("A low-level driver for OmniVision ov7670 sensors"); |
26 | MODULE_LICENSE("GPL"); | |
27 | ||
90ab5ee9 | 28 | static bool debug; |
14386c2b HV |
29 | module_param(debug, bool, 0644); |
30 | MODULE_PARM_DESC(debug, "Debug level (0-1)"); | |
31 | ||
111f3356 JC |
32 | /* |
33 | * Basic window sizes. These probably belong somewhere more globally | |
34 | * useful. | |
35 | */ | |
36 | #define VGA_WIDTH 640 | |
37 | #define VGA_HEIGHT 480 | |
38 | #define QVGA_WIDTH 320 | |
39 | #define QVGA_HEIGHT 240 | |
40 | #define CIF_WIDTH 352 | |
41 | #define CIF_HEIGHT 288 | |
42 | #define QCIF_WIDTH 176 | |
43 | #define QCIF_HEIGHT 144 | |
44 | ||
45 | /* | |
46 | * The 7670 sits on i2c with ID 0x42 | |
47 | */ | |
48 | #define OV7670_I2C_ADDR 0x42 | |
49 | ||
50 | /* Registers */ | |
51 | #define REG_GAIN 0x00 /* Gain lower 8 bits (rest in vref) */ | |
52 | #define REG_BLUE 0x01 /* blue gain */ | |
53 | #define REG_RED 0x02 /* red gain */ | |
54 | #define REG_VREF 0x03 /* Pieces of GAIN, VSTART, VSTOP */ | |
55 | #define REG_COM1 0x04 /* Control 1 */ | |
56 | #define COM1_CCIR656 0x40 /* CCIR656 enable */ | |
57 | #define REG_BAVE 0x05 /* U/B Average level */ | |
58 | #define REG_GbAVE 0x06 /* Y/Gb Average level */ | |
59 | #define REG_AECHH 0x07 /* AEC MS 5 bits */ | |
60 | #define REG_RAVE 0x08 /* V/R Average level */ | |
61 | #define REG_COM2 0x09 /* Control 2 */ | |
62 | #define COM2_SSLEEP 0x10 /* Soft sleep mode */ | |
63 | #define REG_PID 0x0a /* Product ID MSB */ | |
64 | #define REG_VER 0x0b /* Product ID LSB */ | |
65 | #define REG_COM3 0x0c /* Control 3 */ | |
66 | #define COM3_SWAP 0x40 /* Byte swap */ | |
67 | #define COM3_SCALEEN 0x08 /* Enable scaling */ | |
68 | #define COM3_DCWEN 0x04 /* Enable downsamp/crop/window */ | |
69 | #define REG_COM4 0x0d /* Control 4 */ | |
70 | #define REG_COM5 0x0e /* All "reserved" */ | |
71 | #define REG_COM6 0x0f /* Control 6 */ | |
72 | #define REG_AECH 0x10 /* More bits of AEC value */ | |
73 | #define REG_CLKRC 0x11 /* Clocl control */ | |
74 | #define CLK_EXT 0x40 /* Use external clock directly */ | |
75 | #define CLK_SCALE 0x3f /* Mask for internal clock scale */ | |
76 | #define REG_COM7 0x12 /* Control 7 */ | |
77 | #define COM7_RESET 0x80 /* Register reset */ | |
78 | #define COM7_FMT_MASK 0x38 | |
79 | #define COM7_FMT_VGA 0x00 | |
80 | #define COM7_FMT_CIF 0x20 /* CIF format */ | |
81 | #define COM7_FMT_QVGA 0x10 /* QVGA format */ | |
82 | #define COM7_FMT_QCIF 0x08 /* QCIF format */ | |
83 | #define COM7_RGB 0x04 /* bits 0 and 2 - RGB format */ | |
84 | #define COM7_YUV 0x00 /* YUV */ | |
85 | #define COM7_BAYER 0x01 /* Bayer format */ | |
86 | #define COM7_PBAYER 0x05 /* "Processed bayer" */ | |
87 | #define REG_COM8 0x13 /* Control 8 */ | |
88 | #define COM8_FASTAEC 0x80 /* Enable fast AGC/AEC */ | |
89 | #define COM8_AECSTEP 0x40 /* Unlimited AEC step size */ | |
90 | #define COM8_BFILT 0x20 /* Band filter enable */ | |
91 | #define COM8_AGC 0x04 /* Auto gain enable */ | |
92 | #define COM8_AWB 0x02 /* White balance enable */ | |
93 | #define COM8_AEC 0x01 /* Auto exposure enable */ | |
94 | #define REG_COM9 0x14 /* Control 9 - gain ceiling */ | |
95 | #define REG_COM10 0x15 /* Control 10 */ | |
96 | #define COM10_HSYNC 0x40 /* HSYNC instead of HREF */ | |
97 | #define COM10_PCLK_HB 0x20 /* Suppress PCLK on horiz blank */ | |
98 | #define COM10_HREF_REV 0x08 /* Reverse HREF */ | |
99 | #define COM10_VS_LEAD 0x04 /* VSYNC on clock leading edge */ | |
100 | #define COM10_VS_NEG 0x02 /* VSYNC negative */ | |
101 | #define COM10_HS_NEG 0x01 /* HSYNC negative */ | |
102 | #define REG_HSTART 0x17 /* Horiz start high bits */ | |
103 | #define REG_HSTOP 0x18 /* Horiz stop high bits */ | |
104 | #define REG_VSTART 0x19 /* Vert start high bits */ | |
105 | #define REG_VSTOP 0x1a /* Vert stop high bits */ | |
106 | #define REG_PSHFT 0x1b /* Pixel delay after HREF */ | |
107 | #define REG_MIDH 0x1c /* Manuf. ID high */ | |
108 | #define REG_MIDL 0x1d /* Manuf. ID low */ | |
109 | #define REG_MVFP 0x1e /* Mirror / vflip */ | |
110 | #define MVFP_MIRROR 0x20 /* Mirror image */ | |
111 | #define MVFP_FLIP 0x10 /* Vertical flip */ | |
112 | ||
113 | #define REG_AEW 0x24 /* AGC upper limit */ | |
114 | #define REG_AEB 0x25 /* AGC lower limit */ | |
115 | #define REG_VPT 0x26 /* AGC/AEC fast mode op region */ | |
116 | #define REG_HSYST 0x30 /* HSYNC rising edge delay */ | |
117 | #define REG_HSYEN 0x31 /* HSYNC falling edge delay */ | |
118 | #define REG_HREF 0x32 /* HREF pieces */ | |
119 | #define REG_TSLB 0x3a /* lots of stuff */ | |
120 | #define TSLB_YLAST 0x04 /* UYVY or VYUY - see com13 */ | |
121 | #define REG_COM11 0x3b /* Control 11 */ | |
122 | #define COM11_NIGHT 0x80 /* NIght mode enable */ | |
123 | #define COM11_NMFR 0x60 /* Two bit NM frame rate */ | |
124 | #define COM11_HZAUTO 0x10 /* Auto detect 50/60 Hz */ | |
125 | #define COM11_50HZ 0x08 /* Manual 50Hz select */ | |
126 | #define COM11_EXP 0x02 | |
127 | #define REG_COM12 0x3c /* Control 12 */ | |
128 | #define COM12_HREF 0x80 /* HREF always */ | |
129 | #define REG_COM13 0x3d /* Control 13 */ | |
130 | #define COM13_GAMMA 0x80 /* Gamma enable */ | |
131 | #define COM13_UVSAT 0x40 /* UV saturation auto adjustment */ | |
132 | #define COM13_UVSWAP 0x01 /* V before U - w/TSLB */ | |
133 | #define REG_COM14 0x3e /* Control 14 */ | |
134 | #define COM14_DCWEN 0x10 /* DCW/PCLK-scale enable */ | |
135 | #define REG_EDGE 0x3f /* Edge enhancement factor */ | |
136 | #define REG_COM15 0x40 /* Control 15 */ | |
137 | #define COM15_R10F0 0x00 /* Data range 10 to F0 */ | |
138 | #define COM15_R01FE 0x80 /* 01 to FE */ | |
139 | #define COM15_R00FF 0xc0 /* 00 to FF */ | |
140 | #define COM15_RGB565 0x10 /* RGB565 output */ | |
141 | #define COM15_RGB555 0x30 /* RGB555 output */ | |
142 | #define REG_COM16 0x41 /* Control 16 */ | |
143 | #define COM16_AWBGAIN 0x08 /* AWB gain enable */ | |
144 | #define REG_COM17 0x42 /* Control 17 */ | |
145 | #define COM17_AECWIN 0xc0 /* AEC window - must match COM4 */ | |
146 | #define COM17_CBAR 0x08 /* DSP Color bar */ | |
147 | ||
f9a76156 JC |
148 | /* |
149 | * This matrix defines how the colors are generated, must be | |
150 | * tweaked to adjust hue and saturation. | |
151 | * | |
152 | * Order: v-red, v-green, v-blue, u-red, u-green, u-blue | |
153 | * | |
154 | * They are nine-bit signed quantities, with the sign bit | |
155 | * stored in 0x58. Sign for v-red is bit 0, and up from there. | |
156 | */ | |
157 | #define REG_CMATRIX_BASE 0x4f | |
158 | #define CMATRIX_LEN 6 | |
159 | #define REG_CMATRIX_SIGN 0x58 | |
160 | ||
161 | ||
111f3356 JC |
162 | #define REG_BRIGHT 0x55 /* Brightness */ |
163 | #define REG_CONTRAS 0x56 /* Contrast control */ | |
164 | ||
165 | #define REG_GFIX 0x69 /* Fix gain control */ | |
166 | ||
585553ec JC |
167 | #define REG_REG76 0x76 /* OV's name */ |
168 | #define R76_BLKPCOR 0x80 /* Black pixel correction enable */ | |
169 | #define R76_WHTPCOR 0x40 /* White pixel correction enable */ | |
170 | ||
111f3356 JC |
171 | #define REG_RGB444 0x8c /* RGB 444 control */ |
172 | #define R444_ENABLE 0x02 /* Turn on RGB444, overrides 5x5 */ | |
173 | #define R444_RGBX 0x01 /* Empty nibble at end */ | |
174 | ||
175 | #define REG_HAECC1 0x9f /* Hist AEC/AGC control 1 */ | |
176 | #define REG_HAECC2 0xa0 /* Hist AEC/AGC control 2 */ | |
177 | ||
178 | #define REG_BD50MAX 0xa5 /* 50hz banding step limit */ | |
179 | #define REG_HAECC3 0xa6 /* Hist AEC/AGC control 3 */ | |
180 | #define REG_HAECC4 0xa7 /* Hist AEC/AGC control 4 */ | |
181 | #define REG_HAECC5 0xa8 /* Hist AEC/AGC control 5 */ | |
182 | #define REG_HAECC6 0xa9 /* Hist AEC/AGC control 6 */ | |
183 | #define REG_HAECC7 0xaa /* Hist AEC/AGC control 7 */ | |
184 | #define REG_BD60MAX 0xab /* 60hz banding step limit */ | |
185 | ||
d058e237 JM |
186 | enum ov7670_model { |
187 | MODEL_OV7670 = 0, | |
188 | MODEL_OV7675, | |
189 | }; | |
190 | ||
191 | struct ov7670_win_size { | |
192 | int width; | |
193 | int height; | |
194 | unsigned char com7_bit; | |
195 | int hstart; /* Start/stop values for the camera. Note */ | |
196 | int hstop; /* that they do not always make complete */ | |
197 | int vstart; /* sense to humans, but evidently the sensor */ | |
198 | int vstop; /* will do the right thing... */ | |
199 | struct regval_list *regs; /* Regs to tweak */ | |
200 | }; | |
201 | ||
202 | struct ov7670_devtype { | |
203 | /* formats supported for each model */ | |
204 | struct ov7670_win_size *win_sizes; | |
205 | unsigned int n_win_sizes; | |
206 | }; | |
111f3356 | 207 | |
f9a76156 JC |
208 | /* |
209 | * Information we maintain about a known sensor. | |
210 | */ | |
211 | struct ov7670_format_struct; /* coming later */ | |
212 | struct ov7670_info { | |
14386c2b | 213 | struct v4l2_subdev sd; |
f9a76156 JC |
214 | struct ov7670_format_struct *fmt; /* Current format */ |
215 | unsigned char sat; /* Saturation value */ | |
216 | int hue; /* Hue value */ | |
75e2bdad DD |
217 | int min_width; /* Filter out smaller sizes */ |
218 | int min_height; /* Filter out smaller sizes */ | |
219 | int clock_speed; /* External clock speed (MHz) */ | |
d8d20155 | 220 | u8 clkrc; /* Clock divider value */ |
75e2bdad | 221 | bool use_smbus; /* Use smbus I/O instead of I2C */ |
d058e237 | 222 | const struct ov7670_devtype *devtype; /* Device specifics */ |
f9a76156 JC |
223 | }; |
224 | ||
14386c2b HV |
225 | static inline struct ov7670_info *to_state(struct v4l2_subdev *sd) |
226 | { | |
227 | return container_of(sd, struct ov7670_info, sd); | |
228 | } | |
f9a76156 JC |
229 | |
230 | ||
231 | ||
111f3356 JC |
232 | /* |
233 | * The default register settings, as obtained from OmniVision. There | |
234 | * is really no making sense of most of these - lots of "reserved" values | |
235 | * and such. | |
236 | * | |
237 | * These settings give VGA YUYV. | |
238 | */ | |
239 | ||
240 | struct regval_list { | |
241 | unsigned char reg_num; | |
242 | unsigned char value; | |
243 | }; | |
244 | ||
245 | static struct regval_list ov7670_default_regs[] = { | |
246 | { REG_COM7, COM7_RESET }, | |
247 | /* | |
248 | * Clock scale: 3 = 15fps | |
249 | * 2 = 20fps | |
250 | * 1 = 30fps | |
251 | */ | |
f9a76156 | 252 | { REG_CLKRC, 0x1 }, /* OV: clock scale (30 fps) */ |
111f3356 JC |
253 | { REG_TSLB, 0x04 }, /* OV */ |
254 | { REG_COM7, 0 }, /* VGA */ | |
255 | /* | |
256 | * Set the hardware window. These values from OV don't entirely | |
257 | * make sense - hstop is less than hstart. But they work... | |
258 | */ | |
259 | { REG_HSTART, 0x13 }, { REG_HSTOP, 0x01 }, | |
260 | { REG_HREF, 0xb6 }, { REG_VSTART, 0x02 }, | |
261 | { REG_VSTOP, 0x7a }, { REG_VREF, 0x0a }, | |
262 | ||
263 | { REG_COM3, 0 }, { REG_COM14, 0 }, | |
264 | /* Mystery scaling numbers */ | |
265 | { 0x70, 0x3a }, { 0x71, 0x35 }, | |
266 | { 0x72, 0x11 }, { 0x73, 0xf0 }, | |
267 | { 0xa2, 0x02 }, { REG_COM10, 0x0 }, | |
268 | ||
269 | /* Gamma curve values */ | |
270 | { 0x7a, 0x20 }, { 0x7b, 0x10 }, | |
271 | { 0x7c, 0x1e }, { 0x7d, 0x35 }, | |
272 | { 0x7e, 0x5a }, { 0x7f, 0x69 }, | |
273 | { 0x80, 0x76 }, { 0x81, 0x80 }, | |
274 | { 0x82, 0x88 }, { 0x83, 0x8f }, | |
275 | { 0x84, 0x96 }, { 0x85, 0xa3 }, | |
276 | { 0x86, 0xaf }, { 0x87, 0xc4 }, | |
277 | { 0x88, 0xd7 }, { 0x89, 0xe8 }, | |
278 | ||
279 | /* AGC and AEC parameters. Note we start by disabling those features, | |
280 | then turn them only after tweaking the values. */ | |
281 | { REG_COM8, COM8_FASTAEC | COM8_AECSTEP | COM8_BFILT }, | |
282 | { REG_GAIN, 0 }, { REG_AECH, 0 }, | |
283 | { REG_COM4, 0x40 }, /* magic reserved bit */ | |
284 | { REG_COM9, 0x18 }, /* 4x gain + magic rsvd bit */ | |
285 | { REG_BD50MAX, 0x05 }, { REG_BD60MAX, 0x07 }, | |
286 | { REG_AEW, 0x95 }, { REG_AEB, 0x33 }, | |
287 | { REG_VPT, 0xe3 }, { REG_HAECC1, 0x78 }, | |
288 | { REG_HAECC2, 0x68 }, { 0xa1, 0x03 }, /* magic */ | |
289 | { REG_HAECC3, 0xd8 }, { REG_HAECC4, 0xd8 }, | |
290 | { REG_HAECC5, 0xf0 }, { REG_HAECC6, 0x90 }, | |
291 | { REG_HAECC7, 0x94 }, | |
292 | { REG_COM8, COM8_FASTAEC|COM8_AECSTEP|COM8_BFILT|COM8_AGC|COM8_AEC }, | |
293 | ||
294 | /* Almost all of these are magic "reserved" values. */ | |
295 | { REG_COM5, 0x61 }, { REG_COM6, 0x4b }, | |
7f7b12f0 | 296 | { 0x16, 0x02 }, { REG_MVFP, 0x07 }, |
111f3356 JC |
297 | { 0x21, 0x02 }, { 0x22, 0x91 }, |
298 | { 0x29, 0x07 }, { 0x33, 0x0b }, | |
299 | { 0x35, 0x0b }, { 0x37, 0x1d }, | |
300 | { 0x38, 0x71 }, { 0x39, 0x2a }, | |
301 | { REG_COM12, 0x78 }, { 0x4d, 0x40 }, | |
302 | { 0x4e, 0x20 }, { REG_GFIX, 0 }, | |
303 | { 0x6b, 0x4a }, { 0x74, 0x10 }, | |
304 | { 0x8d, 0x4f }, { 0x8e, 0 }, | |
305 | { 0x8f, 0 }, { 0x90, 0 }, | |
306 | { 0x91, 0 }, { 0x96, 0 }, | |
307 | { 0x9a, 0 }, { 0xb0, 0x84 }, | |
308 | { 0xb1, 0x0c }, { 0xb2, 0x0e }, | |
309 | { 0xb3, 0x82 }, { 0xb8, 0x0a }, | |
310 | ||
311 | /* More reserved magic, some of which tweaks white balance */ | |
312 | { 0x43, 0x0a }, { 0x44, 0xf0 }, | |
313 | { 0x45, 0x34 }, { 0x46, 0x58 }, | |
314 | { 0x47, 0x28 }, { 0x48, 0x3a }, | |
315 | { 0x59, 0x88 }, { 0x5a, 0x88 }, | |
316 | { 0x5b, 0x44 }, { 0x5c, 0x67 }, | |
317 | { 0x5d, 0x49 }, { 0x5e, 0x0e }, | |
318 | { 0x6c, 0x0a }, { 0x6d, 0x55 }, | |
319 | { 0x6e, 0x11 }, { 0x6f, 0x9f }, /* "9e for advance AWB" */ | |
320 | { 0x6a, 0x40 }, { REG_BLUE, 0x40 }, | |
321 | { REG_RED, 0x60 }, | |
322 | { REG_COM8, COM8_FASTAEC|COM8_AECSTEP|COM8_BFILT|COM8_AGC|COM8_AEC|COM8_AWB }, | |
323 | ||
324 | /* Matrix coefficients */ | |
325 | { 0x4f, 0x80 }, { 0x50, 0x80 }, | |
326 | { 0x51, 0 }, { 0x52, 0x22 }, | |
327 | { 0x53, 0x5e }, { 0x54, 0x80 }, | |
328 | { 0x58, 0x9e }, | |
329 | ||
330 | { REG_COM16, COM16_AWBGAIN }, { REG_EDGE, 0 }, | |
331 | { 0x75, 0x05 }, { 0x76, 0xe1 }, | |
332 | { 0x4c, 0 }, { 0x77, 0x01 }, | |
333 | { REG_COM13, 0xc3 }, { 0x4b, 0x09 }, | |
334 | { 0xc9, 0x60 }, { REG_COM16, 0x38 }, | |
335 | { 0x56, 0x40 }, | |
336 | ||
c8f5b2f5 | 337 | { 0x34, 0x11 }, { REG_COM11, COM11_EXP|COM11_HZAUTO }, |
111f3356 JC |
338 | { 0xa4, 0x88 }, { 0x96, 0 }, |
339 | { 0x97, 0x30 }, { 0x98, 0x20 }, | |
340 | { 0x99, 0x30 }, { 0x9a, 0x84 }, | |
341 | { 0x9b, 0x29 }, { 0x9c, 0x03 }, | |
342 | { 0x9d, 0x4c }, { 0x9e, 0x3f }, | |
343 | { 0x78, 0x04 }, | |
344 | ||
345 | /* Extra-weird stuff. Some sort of multiplexor register */ | |
346 | { 0x79, 0x01 }, { 0xc8, 0xf0 }, | |
347 | { 0x79, 0x0f }, { 0xc8, 0x00 }, | |
348 | { 0x79, 0x10 }, { 0xc8, 0x7e }, | |
349 | { 0x79, 0x0a }, { 0xc8, 0x80 }, | |
350 | { 0x79, 0x0b }, { 0xc8, 0x01 }, | |
351 | { 0x79, 0x0c }, { 0xc8, 0x0f }, | |
352 | { 0x79, 0x0d }, { 0xc8, 0x20 }, | |
353 | { 0x79, 0x09 }, { 0xc8, 0x80 }, | |
354 | { 0x79, 0x02 }, { 0xc8, 0xc0 }, | |
355 | { 0x79, 0x03 }, { 0xc8, 0x40 }, | |
356 | { 0x79, 0x05 }, { 0xc8, 0x30 }, | |
357 | { 0x79, 0x26 }, | |
358 | ||
111f3356 JC |
359 | { 0xff, 0xff }, /* END MARKER */ |
360 | }; | |
361 | ||
362 | ||
363 | /* | |
364 | * Here we'll try to encapsulate the changes for just the output | |
365 | * video format. | |
366 | * | |
367 | * RGB656 and YUV422 come from OV; RGB444 is homebrewed. | |
368 | * | |
369 | * IMPORTANT RULE: the first entry must be for COM7, see ov7670_s_fmt for why. | |
370 | */ | |
371 | ||
372 | ||
373 | static struct regval_list ov7670_fmt_yuv422[] = { | |
374 | { REG_COM7, 0x0 }, /* Selects YUV mode */ | |
375 | { REG_RGB444, 0 }, /* No RGB444 please */ | |
97693f91 | 376 | { REG_COM1, 0 }, /* CCIR601 */ |
111f3356 | 377 | { REG_COM15, COM15_R00FF }, |
c01b7429 | 378 | { REG_COM9, 0x48 }, /* 32x gain ceiling; 0x8 is reserved bit */ |
111f3356 JC |
379 | { 0x4f, 0x80 }, /* "matrix coefficient 1" */ |
380 | { 0x50, 0x80 }, /* "matrix coefficient 2" */ | |
f9a76156 | 381 | { 0x51, 0 }, /* vb */ |
111f3356 JC |
382 | { 0x52, 0x22 }, /* "matrix coefficient 4" */ |
383 | { 0x53, 0x5e }, /* "matrix coefficient 5" */ | |
384 | { 0x54, 0x80 }, /* "matrix coefficient 6" */ | |
385 | { REG_COM13, COM13_GAMMA|COM13_UVSAT }, | |
386 | { 0xff, 0xff }, | |
387 | }; | |
388 | ||
389 | static struct regval_list ov7670_fmt_rgb565[] = { | |
390 | { REG_COM7, COM7_RGB }, /* Selects RGB mode */ | |
391 | { REG_RGB444, 0 }, /* No RGB444 please */ | |
97693f91 | 392 | { REG_COM1, 0x0 }, /* CCIR601 */ |
111f3356 JC |
393 | { REG_COM15, COM15_RGB565 }, |
394 | { REG_COM9, 0x38 }, /* 16x gain ceiling; 0x8 is reserved bit */ | |
395 | { 0x4f, 0xb3 }, /* "matrix coefficient 1" */ | |
396 | { 0x50, 0xb3 }, /* "matrix coefficient 2" */ | |
f9a76156 | 397 | { 0x51, 0 }, /* vb */ |
111f3356 JC |
398 | { 0x52, 0x3d }, /* "matrix coefficient 4" */ |
399 | { 0x53, 0xa7 }, /* "matrix coefficient 5" */ | |
400 | { 0x54, 0xe4 }, /* "matrix coefficient 6" */ | |
401 | { REG_COM13, COM13_GAMMA|COM13_UVSAT }, | |
402 | { 0xff, 0xff }, | |
403 | }; | |
404 | ||
405 | static struct regval_list ov7670_fmt_rgb444[] = { | |
406 | { REG_COM7, COM7_RGB }, /* Selects RGB mode */ | |
407 | { REG_RGB444, R444_ENABLE }, /* Enable xxxxrrrr ggggbbbb */ | |
97693f91 | 408 | { REG_COM1, 0x0 }, /* CCIR601 */ |
111f3356 JC |
409 | { REG_COM15, COM15_R01FE|COM15_RGB565 }, /* Data range needed? */ |
410 | { REG_COM9, 0x38 }, /* 16x gain ceiling; 0x8 is reserved bit */ | |
411 | { 0x4f, 0xb3 }, /* "matrix coefficient 1" */ | |
412 | { 0x50, 0xb3 }, /* "matrix coefficient 2" */ | |
f9a76156 | 413 | { 0x51, 0 }, /* vb */ |
111f3356 JC |
414 | { 0x52, 0x3d }, /* "matrix coefficient 4" */ |
415 | { 0x53, 0xa7 }, /* "matrix coefficient 5" */ | |
416 | { 0x54, 0xe4 }, /* "matrix coefficient 6" */ | |
417 | { REG_COM13, COM13_GAMMA|COM13_UVSAT|0x2 }, /* Magic rsvd bit */ | |
418 | { 0xff, 0xff }, | |
419 | }; | |
420 | ||
585553ec JC |
421 | static struct regval_list ov7670_fmt_raw[] = { |
422 | { REG_COM7, COM7_BAYER }, | |
423 | { REG_COM13, 0x08 }, /* No gamma, magic rsvd bit */ | |
424 | { REG_COM16, 0x3d }, /* Edge enhancement, denoise */ | |
425 | { REG_REG76, 0xe1 }, /* Pix correction, magic rsvd */ | |
426 | { 0xff, 0xff }, | |
427 | }; | |
111f3356 JC |
428 | |
429 | ||
430 | ||
431 | /* | |
432 | * Low-level register I/O. | |
46714209 JC |
433 | * |
434 | * Note that there are two versions of these. On the XO 1, the | |
435 | * i2c controller only does SMBUS, so that's what we use. The | |
436 | * ov7670 is not really an SMBUS device, though, so the communication | |
437 | * is not always entirely reliable. | |
438 | */ | |
75e2bdad | 439 | static int ov7670_read_smbus(struct v4l2_subdev *sd, unsigned char reg, |
46714209 JC |
440 | unsigned char *value) |
441 | { | |
442 | struct i2c_client *client = v4l2_get_subdevdata(sd); | |
443 | int ret; | |
444 | ||
445 | ret = i2c_smbus_read_byte_data(client, reg); | |
446 | if (ret >= 0) { | |
447 | *value = (unsigned char)ret; | |
448 | ret = 0; | |
449 | } | |
450 | return ret; | |
451 | } | |
452 | ||
453 | ||
75e2bdad | 454 | static int ov7670_write_smbus(struct v4l2_subdev *sd, unsigned char reg, |
46714209 JC |
455 | unsigned char value) |
456 | { | |
457 | struct i2c_client *client = v4l2_get_subdevdata(sd); | |
458 | int ret = i2c_smbus_write_byte_data(client, reg, value); | |
459 | ||
460 | if (reg == REG_COM7 && (value & COM7_RESET)) | |
461 | msleep(5); /* Wait for reset to run */ | |
462 | return ret; | |
463 | } | |
464 | ||
46714209 JC |
465 | /* |
466 | * On most platforms, we'd rather do straight i2c I/O. | |
111f3356 | 467 | */ |
75e2bdad | 468 | static int ov7670_read_i2c(struct v4l2_subdev *sd, unsigned char reg, |
111f3356 JC |
469 | unsigned char *value) |
470 | { | |
14386c2b | 471 | struct i2c_client *client = v4l2_get_subdevdata(sd); |
2bf7de48 JC |
472 | u8 data = reg; |
473 | struct i2c_msg msg; | |
111f3356 JC |
474 | int ret; |
475 | ||
2bf7de48 JC |
476 | /* |
477 | * Send out the register address... | |
478 | */ | |
479 | msg.addr = client->addr; | |
480 | msg.flags = 0; | |
481 | msg.len = 1; | |
482 | msg.buf = &data; | |
483 | ret = i2c_transfer(client->adapter, &msg, 1); | |
484 | if (ret < 0) { | |
485 | printk(KERN_ERR "Error %d on register write\n", ret); | |
486 | return ret; | |
487 | } | |
488 | /* | |
489 | * ...then read back the result. | |
490 | */ | |
491 | msg.flags = I2C_M_RD; | |
492 | ret = i2c_transfer(client->adapter, &msg, 1); | |
bca5c2c5 | 493 | if (ret >= 0) { |
2bf7de48 | 494 | *value = data; |
bca5c2c5 AS |
495 | ret = 0; |
496 | } | |
111f3356 JC |
497 | return ret; |
498 | } | |
499 | ||
500 | ||
75e2bdad | 501 | static int ov7670_write_i2c(struct v4l2_subdev *sd, unsigned char reg, |
111f3356 JC |
502 | unsigned char value) |
503 | { | |
14386c2b | 504 | struct i2c_client *client = v4l2_get_subdevdata(sd); |
2bf7de48 JC |
505 | struct i2c_msg msg; |
506 | unsigned char data[2] = { reg, value }; | |
507 | int ret; | |
14386c2b | 508 | |
2bf7de48 JC |
509 | msg.addr = client->addr; |
510 | msg.flags = 0; | |
511 | msg.len = 2; | |
512 | msg.buf = data; | |
513 | ret = i2c_transfer(client->adapter, &msg, 1); | |
514 | if (ret > 0) | |
515 | ret = 0; | |
6d77444a | 516 | if (reg == REG_COM7 && (value & COM7_RESET)) |
97693f91 | 517 | msleep(5); /* Wait for reset to run */ |
6d77444a | 518 | return ret; |
111f3356 JC |
519 | } |
520 | ||
75e2bdad DD |
521 | static int ov7670_read(struct v4l2_subdev *sd, unsigned char reg, |
522 | unsigned char *value) | |
523 | { | |
524 | struct ov7670_info *info = to_state(sd); | |
525 | if (info->use_smbus) | |
526 | return ov7670_read_smbus(sd, reg, value); | |
527 | else | |
528 | return ov7670_read_i2c(sd, reg, value); | |
529 | } | |
530 | ||
531 | static int ov7670_write(struct v4l2_subdev *sd, unsigned char reg, | |
532 | unsigned char value) | |
533 | { | |
534 | struct ov7670_info *info = to_state(sd); | |
535 | if (info->use_smbus) | |
536 | return ov7670_write_smbus(sd, reg, value); | |
537 | else | |
538 | return ov7670_write_i2c(sd, reg, value); | |
539 | } | |
111f3356 JC |
540 | |
541 | /* | |
542 | * Write a list of register settings; ff/ff stops the process. | |
543 | */ | |
14386c2b | 544 | static int ov7670_write_array(struct v4l2_subdev *sd, struct regval_list *vals) |
111f3356 JC |
545 | { |
546 | while (vals->reg_num != 0xff || vals->value != 0xff) { | |
14386c2b | 547 | int ret = ov7670_write(sd, vals->reg_num, vals->value); |
111f3356 JC |
548 | if (ret < 0) |
549 | return ret; | |
550 | vals++; | |
551 | } | |
552 | return 0; | |
553 | } | |
554 | ||
555 | ||
556 | /* | |
557 | * Stuff that knows about the sensor. | |
558 | */ | |
14386c2b | 559 | static int ov7670_reset(struct v4l2_subdev *sd, u32 val) |
111f3356 | 560 | { |
14386c2b | 561 | ov7670_write(sd, REG_COM7, COM7_RESET); |
111f3356 | 562 | msleep(1); |
14386c2b | 563 | return 0; |
111f3356 JC |
564 | } |
565 | ||
566 | ||
14386c2b | 567 | static int ov7670_init(struct v4l2_subdev *sd, u32 val) |
111f3356 | 568 | { |
14386c2b | 569 | return ov7670_write_array(sd, ov7670_default_regs); |
111f3356 JC |
570 | } |
571 | ||
572 | ||
573 | ||
14386c2b | 574 | static int ov7670_detect(struct v4l2_subdev *sd) |
111f3356 JC |
575 | { |
576 | unsigned char v; | |
577 | int ret; | |
578 | ||
14386c2b | 579 | ret = ov7670_init(sd, 0); |
111f3356 JC |
580 | if (ret < 0) |
581 | return ret; | |
14386c2b | 582 | ret = ov7670_read(sd, REG_MIDH, &v); |
111f3356 JC |
583 | if (ret < 0) |
584 | return ret; | |
585 | if (v != 0x7f) /* OV manuf. id. */ | |
586 | return -ENODEV; | |
14386c2b | 587 | ret = ov7670_read(sd, REG_MIDL, &v); |
111f3356 JC |
588 | if (ret < 0) |
589 | return ret; | |
590 | if (v != 0xa2) | |
591 | return -ENODEV; | |
592 | /* | |
593 | * OK, we know we have an OmniVision chip...but which one? | |
594 | */ | |
14386c2b | 595 | ret = ov7670_read(sd, REG_PID, &v); |
111f3356 JC |
596 | if (ret < 0) |
597 | return ret; | |
598 | if (v != 0x76) /* PID + VER = 0x76 / 0x73 */ | |
599 | return -ENODEV; | |
14386c2b | 600 | ret = ov7670_read(sd, REG_VER, &v); |
111f3356 JC |
601 | if (ret < 0) |
602 | return ret; | |
603 | if (v != 0x73) /* PID + VER = 0x76 / 0x73 */ | |
604 | return -ENODEV; | |
605 | return 0; | |
606 | } | |
607 | ||
608 | ||
f9a76156 JC |
609 | /* |
610 | * Store information about the video data format. The color matrix | |
611 | * is deeply tied into the format, so keep the relevant values here. | |
959f3bda | 612 | * The magic matrix numbers come from OmniVision. |
f9a76156 | 613 | */ |
111f3356 | 614 | static struct ov7670_format_struct { |
959f3bda HV |
615 | enum v4l2_mbus_pixelcode mbus_code; |
616 | enum v4l2_colorspace colorspace; | |
111f3356 | 617 | struct regval_list *regs; |
f9a76156 | 618 | int cmatrix[CMATRIX_LEN]; |
111f3356 JC |
619 | } ov7670_formats[] = { |
620 | { | |
959f3bda HV |
621 | .mbus_code = V4L2_MBUS_FMT_YUYV8_2X8, |
622 | .colorspace = V4L2_COLORSPACE_JPEG, | |
111f3356 | 623 | .regs = ov7670_fmt_yuv422, |
f9a76156 | 624 | .cmatrix = { 128, -128, 0, -34, -94, 128 }, |
111f3356 JC |
625 | }, |
626 | { | |
959f3bda HV |
627 | .mbus_code = V4L2_MBUS_FMT_RGB444_2X8_PADHI_LE, |
628 | .colorspace = V4L2_COLORSPACE_SRGB, | |
111f3356 | 629 | .regs = ov7670_fmt_rgb444, |
f9a76156 | 630 | .cmatrix = { 179, -179, 0, -61, -176, 228 }, |
111f3356 JC |
631 | }, |
632 | { | |
959f3bda HV |
633 | .mbus_code = V4L2_MBUS_FMT_RGB565_2X8_LE, |
634 | .colorspace = V4L2_COLORSPACE_SRGB, | |
111f3356 | 635 | .regs = ov7670_fmt_rgb565, |
f9a76156 | 636 | .cmatrix = { 179, -179, 0, -61, -176, 228 }, |
585553ec JC |
637 | }, |
638 | { | |
959f3bda HV |
639 | .mbus_code = V4L2_MBUS_FMT_SBGGR8_1X8, |
640 | .colorspace = V4L2_COLORSPACE_SRGB, | |
585553ec JC |
641 | .regs = ov7670_fmt_raw, |
642 | .cmatrix = { 0, 0, 0, 0, 0, 0 }, | |
111f3356 | 643 | }, |
111f3356 | 644 | }; |
585553ec | 645 | #define N_OV7670_FMTS ARRAY_SIZE(ov7670_formats) |
111f3356 | 646 | |
111f3356 JC |
647 | |
648 | /* | |
649 | * Then there is the issue of window sizes. Try to capture the info here. | |
650 | */ | |
f9a76156 JC |
651 | |
652 | /* | |
653 | * QCIF mode is done (by OV) in a very strange way - it actually looks like | |
654 | * VGA with weird scaling options - they do *not* use the canned QCIF mode | |
655 | * which is allegedly provided by the sensor. So here's the weird register | |
656 | * settings. | |
657 | */ | |
658 | static struct regval_list ov7670_qcif_regs[] = { | |
659 | { REG_COM3, COM3_SCALEEN|COM3_DCWEN }, | |
660 | { REG_COM3, COM3_DCWEN }, | |
661 | { REG_COM14, COM14_DCWEN | 0x01}, | |
662 | { 0x73, 0xf1 }, | |
663 | { 0xa2, 0x52 }, | |
664 | { 0x7b, 0x1c }, | |
665 | { 0x7c, 0x28 }, | |
666 | { 0x7d, 0x3c }, | |
667 | { 0x7f, 0x69 }, | |
668 | { REG_COM9, 0x38 }, | |
669 | { 0xa1, 0x0b }, | |
670 | { 0x74, 0x19 }, | |
671 | { 0x9a, 0x80 }, | |
672 | { 0x43, 0x14 }, | |
673 | { REG_COM13, 0xc0 }, | |
674 | { 0xff, 0xff }, | |
675 | }; | |
676 | ||
d058e237 | 677 | static struct ov7670_win_size ov7670_win_sizes[] = { |
111f3356 JC |
678 | /* VGA */ |
679 | { | |
680 | .width = VGA_WIDTH, | |
681 | .height = VGA_HEIGHT, | |
682 | .com7_bit = COM7_FMT_VGA, | |
d058e237 JM |
683 | .hstart = 158, /* These values from */ |
684 | .hstop = 14, /* Omnivision */ | |
111f3356 JC |
685 | .vstart = 10, |
686 | .vstop = 490, | |
d058e237 | 687 | .regs = NULL, |
111f3356 JC |
688 | }, |
689 | /* CIF */ | |
690 | { | |
691 | .width = CIF_WIDTH, | |
692 | .height = CIF_HEIGHT, | |
693 | .com7_bit = COM7_FMT_CIF, | |
d058e237 | 694 | .hstart = 170, /* Empirically determined */ |
111f3356 JC |
695 | .hstop = 90, |
696 | .vstart = 14, | |
697 | .vstop = 494, | |
d058e237 | 698 | .regs = NULL, |
111f3356 JC |
699 | }, |
700 | /* QVGA */ | |
701 | { | |
702 | .width = QVGA_WIDTH, | |
703 | .height = QVGA_HEIGHT, | |
704 | .com7_bit = COM7_FMT_QVGA, | |
d058e237 | 705 | .hstart = 168, /* Empirically determined */ |
dc4589c8 DD |
706 | .hstop = 24, |
707 | .vstart = 12, | |
708 | .vstop = 492, | |
d058e237 | 709 | .regs = NULL, |
f9a76156 JC |
710 | }, |
711 | /* QCIF */ | |
712 | { | |
713 | .width = QCIF_WIDTH, | |
714 | .height = QCIF_HEIGHT, | |
715 | .com7_bit = COM7_FMT_VGA, /* see comment above */ | |
d058e237 | 716 | .hstart = 456, /* Empirically determined */ |
f9a76156 JC |
717 | .hstop = 24, |
718 | .vstart = 14, | |
719 | .vstop = 494, | |
d058e237 JM |
720 | .regs = ov7670_qcif_regs, |
721 | } | |
111f3356 JC |
722 | }; |
723 | ||
d058e237 JM |
724 | static struct ov7670_win_size ov7675_win_sizes[] = { |
725 | /* | |
726 | * Currently, only VGA is supported. Theoretically it could be possible | |
727 | * to support CIF, QVGA and QCIF too. Taking values for ov7670 as a | |
728 | * base and tweak them empirically could be required. | |
729 | */ | |
730 | { | |
731 | .width = VGA_WIDTH, | |
732 | .height = VGA_HEIGHT, | |
733 | .com7_bit = COM7_FMT_VGA, | |
734 | .hstart = 158, /* These values from */ | |
735 | .hstop = 14, /* Omnivision */ | |
736 | .vstart = 14, /* Empirically determined */ | |
737 | .vstop = 494, | |
738 | .regs = NULL, | |
739 | } | |
740 | }; | |
111f3356 JC |
741 | |
742 | /* | |
743 | * Store a set of start/stop values into the camera. | |
744 | */ | |
14386c2b | 745 | static int ov7670_set_hw(struct v4l2_subdev *sd, int hstart, int hstop, |
111f3356 JC |
746 | int vstart, int vstop) |
747 | { | |
748 | int ret; | |
749 | unsigned char v; | |
750 | /* | |
751 | * Horizontal: 11 bits, top 8 live in hstart and hstop. Bottom 3 of | |
752 | * hstart are in href[2:0], bottom 3 of hstop in href[5:3]. There is | |
753 | * a mystery "edge offset" value in the top two bits of href. | |
754 | */ | |
14386c2b HV |
755 | ret = ov7670_write(sd, REG_HSTART, (hstart >> 3) & 0xff); |
756 | ret += ov7670_write(sd, REG_HSTOP, (hstop >> 3) & 0xff); | |
757 | ret += ov7670_read(sd, REG_HREF, &v); | |
111f3356 JC |
758 | v = (v & 0xc0) | ((hstop & 0x7) << 3) | (hstart & 0x7); |
759 | msleep(10); | |
14386c2b | 760 | ret += ov7670_write(sd, REG_HREF, v); |
111f3356 JC |
761 | /* |
762 | * Vertical: similar arrangement, but only 10 bits. | |
763 | */ | |
14386c2b HV |
764 | ret += ov7670_write(sd, REG_VSTART, (vstart >> 2) & 0xff); |
765 | ret += ov7670_write(sd, REG_VSTOP, (vstop >> 2) & 0xff); | |
766 | ret += ov7670_read(sd, REG_VREF, &v); | |
111f3356 JC |
767 | v = (v & 0xf0) | ((vstop & 0x3) << 2) | (vstart & 0x3); |
768 | msleep(10); | |
14386c2b | 769 | ret += ov7670_write(sd, REG_VREF, v); |
111f3356 JC |
770 | return ret; |
771 | } | |
772 | ||
773 | ||
959f3bda HV |
774 | static int ov7670_enum_mbus_fmt(struct v4l2_subdev *sd, unsigned index, |
775 | enum v4l2_mbus_pixelcode *code) | |
776 | { | |
777 | if (index >= N_OV7670_FMTS) | |
778 | return -EINVAL; | |
779 | ||
780 | *code = ov7670_formats[index].mbus_code; | |
781 | return 0; | |
782 | } | |
111f3356 | 783 | |
14386c2b | 784 | static int ov7670_try_fmt_internal(struct v4l2_subdev *sd, |
959f3bda | 785 | struct v4l2_mbus_framefmt *fmt, |
111f3356 JC |
786 | struct ov7670_format_struct **ret_fmt, |
787 | struct ov7670_win_size **ret_wsize) | |
788 | { | |
789 | int index; | |
790 | struct ov7670_win_size *wsize; | |
d058e237 JM |
791 | struct ov7670_info *info = to_state(sd); |
792 | unsigned int n_win_sizes = info->devtype->n_win_sizes; | |
111f3356 JC |
793 | |
794 | for (index = 0; index < N_OV7670_FMTS; index++) | |
959f3bda | 795 | if (ov7670_formats[index].mbus_code == fmt->code) |
111f3356 | 796 | break; |
cd257a6f DD |
797 | if (index >= N_OV7670_FMTS) { |
798 | /* default to first format */ | |
799 | index = 0; | |
959f3bda | 800 | fmt->code = ov7670_formats[0].mbus_code; |
cd257a6f | 801 | } |
111f3356 JC |
802 | if (ret_fmt != NULL) |
803 | *ret_fmt = ov7670_formats + index; | |
804 | /* | |
805 | * Fields: the OV devices claim to be progressive. | |
806 | */ | |
959f3bda | 807 | fmt->field = V4L2_FIELD_NONE; |
111f3356 JC |
808 | /* |
809 | * Round requested image size down to the nearest | |
810 | * we support, but not below the smallest. | |
811 | */ | |
d058e237 JM |
812 | for (wsize = info->devtype->win_sizes; |
813 | wsize < info->devtype->win_sizes + n_win_sizes; wsize++) | |
959f3bda | 814 | if (fmt->width >= wsize->width && fmt->height >= wsize->height) |
111f3356 | 815 | break; |
d058e237 | 816 | if (wsize >= info->devtype->win_sizes + n_win_sizes) |
111f3356 JC |
817 | wsize--; /* Take the smallest one */ |
818 | if (ret_wsize != NULL) | |
819 | *ret_wsize = wsize; | |
820 | /* | |
821 | * Note the size we'll actually handle. | |
822 | */ | |
959f3bda HV |
823 | fmt->width = wsize->width; |
824 | fmt->height = wsize->height; | |
825 | fmt->colorspace = ov7670_formats[index].colorspace; | |
111f3356 | 826 | return 0; |
111f3356 JC |
827 | } |
828 | ||
959f3bda HV |
829 | static int ov7670_try_mbus_fmt(struct v4l2_subdev *sd, |
830 | struct v4l2_mbus_framefmt *fmt) | |
14386c2b HV |
831 | { |
832 | return ov7670_try_fmt_internal(sd, fmt, NULL, NULL); | |
833 | } | |
834 | ||
111f3356 JC |
835 | /* |
836 | * Set a format. | |
837 | */ | |
959f3bda HV |
838 | static int ov7670_s_mbus_fmt(struct v4l2_subdev *sd, |
839 | struct v4l2_mbus_framefmt *fmt) | |
111f3356 | 840 | { |
111f3356 JC |
841 | struct ov7670_format_struct *ovfmt; |
842 | struct ov7670_win_size *wsize; | |
14386c2b | 843 | struct ov7670_info *info = to_state(sd); |
d8d20155 | 844 | unsigned char com7; |
959f3bda | 845 | int ret; |
111f3356 | 846 | |
14386c2b | 847 | ret = ov7670_try_fmt_internal(sd, fmt, &ovfmt, &wsize); |
959f3bda | 848 | |
111f3356 JC |
849 | if (ret) |
850 | return ret; | |
851 | /* | |
852 | * COM7 is a pain in the ass, it doesn't like to be read then | |
853 | * quickly written afterward. But we have everything we need | |
854 | * to set it absolutely here, as long as the format-specific | |
855 | * register sets list it first. | |
856 | */ | |
857 | com7 = ovfmt->regs[0].value; | |
858 | com7 |= wsize->com7_bit; | |
14386c2b | 859 | ov7670_write(sd, REG_COM7, com7); |
111f3356 JC |
860 | /* |
861 | * Now write the rest of the array. Also store start/stops | |
862 | */ | |
14386c2b HV |
863 | ov7670_write_array(sd, ovfmt->regs + 1); |
864 | ov7670_set_hw(sd, wsize->hstart, wsize->hstop, wsize->vstart, | |
111f3356 | 865 | wsize->vstop); |
f9a76156 JC |
866 | ret = 0; |
867 | if (wsize->regs) | |
14386c2b | 868 | ret = ov7670_write_array(sd, wsize->regs); |
f9a76156 | 869 | info->fmt = ovfmt; |
edd75ede | 870 | |
d8d20155 JC |
871 | /* |
872 | * If we're running RGB565, we must rewrite clkrc after setting | |
873 | * the other parameters or the image looks poor. If we're *not* | |
874 | * doing RGB565, we must not rewrite clkrc or the image looks | |
875 | * *really* poor. | |
a8e68c37 JC |
876 | * |
877 | * (Update) Now that we retain clkrc state, we should be able | |
878 | * to write it unconditionally, and that will make the frame | |
879 | * rate persistent too. | |
d8d20155 | 880 | */ |
a8e68c37 | 881 | if (ret == 0) |
d8d20155 | 882 | ret = ov7670_write(sd, REG_CLKRC, info->clkrc); |
959f3bda HV |
883 | return 0; |
884 | } | |
885 | ||
c8f5b2f5 JC |
886 | /* |
887 | * Implement G/S_PARM. There is a "high quality" mode we could try | |
888 | * to do someday; for now, we just do the frame rate tweak. | |
889 | */ | |
14386c2b | 890 | static int ov7670_g_parm(struct v4l2_subdev *sd, struct v4l2_streamparm *parms) |
c8f5b2f5 JC |
891 | { |
892 | struct v4l2_captureparm *cp = &parms->parm.capture; | |
d8d20155 | 893 | struct ov7670_info *info = to_state(sd); |
c8f5b2f5 JC |
894 | |
895 | if (parms->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) | |
896 | return -EINVAL; | |
d8d20155 | 897 | |
c8f5b2f5 JC |
898 | memset(cp, 0, sizeof(struct v4l2_captureparm)); |
899 | cp->capability = V4L2_CAP_TIMEPERFRAME; | |
900 | cp->timeperframe.numerator = 1; | |
75e2bdad | 901 | cp->timeperframe.denominator = info->clock_speed; |
d8d20155 JC |
902 | if ((info->clkrc & CLK_EXT) == 0 && (info->clkrc & CLK_SCALE) > 1) |
903 | cp->timeperframe.denominator /= (info->clkrc & CLK_SCALE); | |
c8f5b2f5 JC |
904 | return 0; |
905 | } | |
906 | ||
14386c2b | 907 | static int ov7670_s_parm(struct v4l2_subdev *sd, struct v4l2_streamparm *parms) |
c8f5b2f5 JC |
908 | { |
909 | struct v4l2_captureparm *cp = &parms->parm.capture; | |
910 | struct v4l2_fract *tpf = &cp->timeperframe; | |
d8d20155 | 911 | struct ov7670_info *info = to_state(sd); |
380de498 | 912 | int div; |
c8f5b2f5 JC |
913 | |
914 | if (parms->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) | |
915 | return -EINVAL; | |
916 | if (cp->extendedmode != 0) | |
917 | return -EINVAL; | |
d8d20155 | 918 | |
c8f5b2f5 JC |
919 | if (tpf->numerator == 0 || tpf->denominator == 0) |
920 | div = 1; /* Reset to full rate */ | |
921 | else | |
75e2bdad | 922 | div = (tpf->numerator * info->clock_speed) / tpf->denominator; |
c8f5b2f5 JC |
923 | if (div == 0) |
924 | div = 1; | |
925 | else if (div > CLK_SCALE) | |
926 | div = CLK_SCALE; | |
d8d20155 | 927 | info->clkrc = (info->clkrc & 0x80) | div; |
c8f5b2f5 | 928 | tpf->numerator = 1; |
75e2bdad | 929 | tpf->denominator = info->clock_speed / div; |
d8d20155 | 930 | return ov7670_write(sd, REG_CLKRC, info->clkrc); |
c8f5b2f5 JC |
931 | } |
932 | ||
933 | ||
111f3356 | 934 | /* |
e99dfcf7 JC |
935 | * Frame intervals. Since frame rates are controlled with the clock |
936 | * divider, we can only do 30/n for integer n values. So no continuous | |
937 | * or stepwise options. Here we just pick a handful of logical values. | |
111f3356 JC |
938 | */ |
939 | ||
e99dfcf7 | 940 | static int ov7670_frame_rates[] = { 30, 15, 10, 5, 1 }; |
f9a76156 | 941 | |
e99dfcf7 JC |
942 | static int ov7670_enum_frameintervals(struct v4l2_subdev *sd, |
943 | struct v4l2_frmivalenum *interval) | |
944 | { | |
945 | if (interval->index >= ARRAY_SIZE(ov7670_frame_rates)) | |
946 | return -EINVAL; | |
947 | interval->type = V4L2_FRMIVAL_TYPE_DISCRETE; | |
948 | interval->discrete.numerator = 1; | |
949 | interval->discrete.denominator = ov7670_frame_rates[interval->index]; | |
950 | return 0; | |
951 | } | |
f9a76156 | 952 | |
b0326b7f DD |
953 | /* |
954 | * Frame size enumeration | |
955 | */ | |
956 | static int ov7670_enum_framesizes(struct v4l2_subdev *sd, | |
957 | struct v4l2_frmsizeenum *fsize) | |
958 | { | |
75e2bdad DD |
959 | struct ov7670_info *info = to_state(sd); |
960 | int i; | |
961 | int num_valid = -1; | |
b0326b7f | 962 | __u32 index = fsize->index; |
d058e237 | 963 | unsigned int n_win_sizes = info->devtype->n_win_sizes; |
b0326b7f | 964 | |
75e2bdad DD |
965 | /* |
966 | * If a minimum width/height was requested, filter out the capture | |
967 | * windows that fall outside that. | |
968 | */ | |
d058e237 JM |
969 | for (i = 0; i < n_win_sizes; i++) { |
970 | struct ov7670_win_size *win = &info->devtype->win_sizes[index]; | |
75e2bdad DD |
971 | if (info->min_width && win->width < info->min_width) |
972 | continue; | |
973 | if (info->min_height && win->height < info->min_height) | |
974 | continue; | |
975 | if (index == ++num_valid) { | |
976 | fsize->type = V4L2_FRMSIZE_TYPE_DISCRETE; | |
977 | fsize->discrete.width = win->width; | |
978 | fsize->discrete.height = win->height; | |
979 | return 0; | |
980 | } | |
981 | } | |
982 | ||
983 | return -EINVAL; | |
b0326b7f DD |
984 | } |
985 | ||
e99dfcf7 JC |
986 | /* |
987 | * Code for dealing with controls. | |
988 | */ | |
f9a76156 | 989 | |
14386c2b | 990 | static int ov7670_store_cmatrix(struct v4l2_subdev *sd, |
f9a76156 JC |
991 | int matrix[CMATRIX_LEN]) |
992 | { | |
993 | int i, ret; | |
e3bf20de | 994 | unsigned char signbits = 0; |
f9a76156 JC |
995 | |
996 | /* | |
997 | * Weird crap seems to exist in the upper part of | |
998 | * the sign bits register, so let's preserve it. | |
999 | */ | |
14386c2b | 1000 | ret = ov7670_read(sd, REG_CMATRIX_SIGN, &signbits); |
f9a76156 JC |
1001 | signbits &= 0xc0; |
1002 | ||
1003 | for (i = 0; i < CMATRIX_LEN; i++) { | |
1004 | unsigned char raw; | |
1005 | ||
1006 | if (matrix[i] < 0) { | |
1007 | signbits |= (1 << i); | |
1008 | if (matrix[i] < -255) | |
1009 | raw = 0xff; | |
1010 | else | |
1011 | raw = (-1 * matrix[i]) & 0xff; | |
1012 | } | |
1013 | else { | |
1014 | if (matrix[i] > 255) | |
1015 | raw = 0xff; | |
1016 | else | |
1017 | raw = matrix[i] & 0xff; | |
1018 | } | |
14386c2b | 1019 | ret += ov7670_write(sd, REG_CMATRIX_BASE + i, raw); |
f9a76156 | 1020 | } |
14386c2b | 1021 | ret += ov7670_write(sd, REG_CMATRIX_SIGN, signbits); |
f9a76156 JC |
1022 | return ret; |
1023 | } | |
1024 | ||
1025 | ||
1026 | /* | |
1027 | * Hue also requires messing with the color matrix. It also requires | |
1028 | * trig functions, which tend not to be well supported in the kernel. | |
1029 | * So here is a simple table of sine values, 0-90 degrees, in steps | |
1030 | * of five degrees. Values are multiplied by 1000. | |
1031 | * | |
1032 | * The following naive approximate trig functions require an argument | |
1033 | * carefully limited to -180 <= theta <= 180. | |
1034 | */ | |
1035 | #define SIN_STEP 5 | |
1036 | static const int ov7670_sin_table[] = { | |
1037 | 0, 87, 173, 258, 342, 422, | |
1038 | 499, 573, 642, 707, 766, 819, | |
1039 | 866, 906, 939, 965, 984, 996, | |
1040 | 1000 | |
1041 | }; | |
1042 | ||
1043 | static int ov7670_sine(int theta) | |
1044 | { | |
1045 | int chs = 1; | |
1046 | int sine; | |
1047 | ||
1048 | if (theta < 0) { | |
1049 | theta = -theta; | |
1050 | chs = -1; | |
1051 | } | |
1052 | if (theta <= 90) | |
1053 | sine = ov7670_sin_table[theta/SIN_STEP]; | |
1054 | else { | |
1055 | theta -= 90; | |
1056 | sine = 1000 - ov7670_sin_table[theta/SIN_STEP]; | |
1057 | } | |
1058 | return sine*chs; | |
1059 | } | |
1060 | ||
1061 | static int ov7670_cosine(int theta) | |
1062 | { | |
1063 | theta = 90 - theta; | |
1064 | if (theta > 180) | |
1065 | theta -= 360; | |
1066 | else if (theta < -180) | |
1067 | theta += 360; | |
1068 | return ov7670_sine(theta); | |
1069 | } | |
1070 | ||
1071 | ||
1072 | ||
1073 | ||
1074 | static void ov7670_calc_cmatrix(struct ov7670_info *info, | |
1075 | int matrix[CMATRIX_LEN]) | |
1076 | { | |
1077 | int i; | |
1078 | /* | |
1079 | * Apply the current saturation setting first. | |
1080 | */ | |
1081 | for (i = 0; i < CMATRIX_LEN; i++) | |
1082 | matrix[i] = (info->fmt->cmatrix[i]*info->sat) >> 7; | |
1083 | /* | |
1084 | * Then, if need be, rotate the hue value. | |
1085 | */ | |
1086 | if (info->hue != 0) { | |
1087 | int sinth, costh, tmpmatrix[CMATRIX_LEN]; | |
1088 | ||
1089 | memcpy(tmpmatrix, matrix, CMATRIX_LEN*sizeof(int)); | |
1090 | sinth = ov7670_sine(info->hue); | |
1091 | costh = ov7670_cosine(info->hue); | |
1092 | ||
1093 | matrix[0] = (matrix[3]*sinth + matrix[0]*costh)/1000; | |
1094 | matrix[1] = (matrix[4]*sinth + matrix[1]*costh)/1000; | |
1095 | matrix[2] = (matrix[5]*sinth + matrix[2]*costh)/1000; | |
1096 | matrix[3] = (matrix[3]*costh - matrix[0]*sinth)/1000; | |
1097 | matrix[4] = (matrix[4]*costh - matrix[1]*sinth)/1000; | |
1098 | matrix[5] = (matrix[5]*costh - matrix[2]*sinth)/1000; | |
1099 | } | |
1100 | } | |
1101 | ||
1102 | ||
1103 | ||
ca07561a | 1104 | static int ov7670_s_sat(struct v4l2_subdev *sd, int value) |
f9a76156 | 1105 | { |
14386c2b | 1106 | struct ov7670_info *info = to_state(sd); |
f9a76156 JC |
1107 | int matrix[CMATRIX_LEN]; |
1108 | int ret; | |
1109 | ||
1110 | info->sat = value; | |
1111 | ov7670_calc_cmatrix(info, matrix); | |
14386c2b | 1112 | ret = ov7670_store_cmatrix(sd, matrix); |
f9a76156 JC |
1113 | return ret; |
1114 | } | |
1115 | ||
ca07561a | 1116 | static int ov7670_g_sat(struct v4l2_subdev *sd, __s32 *value) |
f9a76156 | 1117 | { |
14386c2b | 1118 | struct ov7670_info *info = to_state(sd); |
f9a76156 JC |
1119 | |
1120 | *value = info->sat; | |
1121 | return 0; | |
1122 | } | |
1123 | ||
ca07561a | 1124 | static int ov7670_s_hue(struct v4l2_subdev *sd, int value) |
f9a76156 | 1125 | { |
14386c2b | 1126 | struct ov7670_info *info = to_state(sd); |
f9a76156 JC |
1127 | int matrix[CMATRIX_LEN]; |
1128 | int ret; | |
1129 | ||
1130 | if (value < -180 || value > 180) | |
1131 | return -EINVAL; | |
1132 | info->hue = value; | |
1133 | ov7670_calc_cmatrix(info, matrix); | |
14386c2b | 1134 | ret = ov7670_store_cmatrix(sd, matrix); |
f9a76156 JC |
1135 | return ret; |
1136 | } | |
1137 | ||
1138 | ||
ca07561a | 1139 | static int ov7670_g_hue(struct v4l2_subdev *sd, __s32 *value) |
f9a76156 | 1140 | { |
14386c2b | 1141 | struct ov7670_info *info = to_state(sd); |
f9a76156 JC |
1142 | |
1143 | *value = info->hue; | |
1144 | return 0; | |
1145 | } | |
1146 | ||
1147 | ||
111f3356 JC |
1148 | /* |
1149 | * Some weird registers seem to store values in a sign/magnitude format! | |
1150 | */ | |
1151 | static unsigned char ov7670_sm_to_abs(unsigned char v) | |
1152 | { | |
1153 | if ((v & 0x80) == 0) | |
1154 | return v + 128; | |
14386c2b | 1155 | return 128 - (v & 0x7f); |
111f3356 JC |
1156 | } |
1157 | ||
1158 | ||
1159 | static unsigned char ov7670_abs_to_sm(unsigned char v) | |
1160 | { | |
1161 | if (v > 127) | |
1162 | return v & 0x7f; | |
14386c2b | 1163 | return (128 - v) | 0x80; |
111f3356 JC |
1164 | } |
1165 | ||
ca07561a | 1166 | static int ov7670_s_brightness(struct v4l2_subdev *sd, int value) |
111f3356 | 1167 | { |
e3bf20de | 1168 | unsigned char com8 = 0, v; |
111f3356 JC |
1169 | int ret; |
1170 | ||
14386c2b | 1171 | ov7670_read(sd, REG_COM8, &com8); |
111f3356 | 1172 | com8 &= ~COM8_AEC; |
14386c2b | 1173 | ov7670_write(sd, REG_COM8, com8); |
f9a76156 | 1174 | v = ov7670_abs_to_sm(value); |
14386c2b | 1175 | ret = ov7670_write(sd, REG_BRIGHT, v); |
111f3356 JC |
1176 | return ret; |
1177 | } | |
1178 | ||
ca07561a | 1179 | static int ov7670_g_brightness(struct v4l2_subdev *sd, __s32 *value) |
111f3356 | 1180 | { |
e3bf20de | 1181 | unsigned char v = 0; |
14386c2b | 1182 | int ret = ov7670_read(sd, REG_BRIGHT, &v); |
f9a76156 JC |
1183 | |
1184 | *value = ov7670_sm_to_abs(v); | |
111f3356 JC |
1185 | return ret; |
1186 | } | |
1187 | ||
ca07561a | 1188 | static int ov7670_s_contrast(struct v4l2_subdev *sd, int value) |
111f3356 | 1189 | { |
14386c2b | 1190 | return ov7670_write(sd, REG_CONTRAS, (unsigned char) value); |
111f3356 JC |
1191 | } |
1192 | ||
ca07561a | 1193 | static int ov7670_g_contrast(struct v4l2_subdev *sd, __s32 *value) |
111f3356 | 1194 | { |
e3bf20de | 1195 | unsigned char v = 0; |
14386c2b | 1196 | int ret = ov7670_read(sd, REG_CONTRAS, &v); |
f9a76156 JC |
1197 | |
1198 | *value = v; | |
1199 | return ret; | |
111f3356 JC |
1200 | } |
1201 | ||
ca07561a | 1202 | static int ov7670_g_hflip(struct v4l2_subdev *sd, __s32 *value) |
111f3356 JC |
1203 | { |
1204 | int ret; | |
e3bf20de | 1205 | unsigned char v = 0; |
111f3356 | 1206 | |
14386c2b | 1207 | ret = ov7670_read(sd, REG_MVFP, &v); |
111f3356 JC |
1208 | *value = (v & MVFP_MIRROR) == MVFP_MIRROR; |
1209 | return ret; | |
1210 | } | |
1211 | ||
1212 | ||
ca07561a | 1213 | static int ov7670_s_hflip(struct v4l2_subdev *sd, int value) |
111f3356 | 1214 | { |
e3bf20de | 1215 | unsigned char v = 0; |
111f3356 JC |
1216 | int ret; |
1217 | ||
14386c2b | 1218 | ret = ov7670_read(sd, REG_MVFP, &v); |
111f3356 JC |
1219 | if (value) |
1220 | v |= MVFP_MIRROR; | |
1221 | else | |
1222 | v &= ~MVFP_MIRROR; | |
1223 | msleep(10); /* FIXME */ | |
14386c2b | 1224 | ret += ov7670_write(sd, REG_MVFP, v); |
111f3356 JC |
1225 | return ret; |
1226 | } | |
1227 | ||
1228 | ||
1229 | ||
ca07561a | 1230 | static int ov7670_g_vflip(struct v4l2_subdev *sd, __s32 *value) |
111f3356 JC |
1231 | { |
1232 | int ret; | |
e3bf20de | 1233 | unsigned char v = 0; |
111f3356 | 1234 | |
14386c2b | 1235 | ret = ov7670_read(sd, REG_MVFP, &v); |
111f3356 JC |
1236 | *value = (v & MVFP_FLIP) == MVFP_FLIP; |
1237 | return ret; | |
1238 | } | |
1239 | ||
1240 | ||
ca07561a | 1241 | static int ov7670_s_vflip(struct v4l2_subdev *sd, int value) |
111f3356 | 1242 | { |
e3bf20de | 1243 | unsigned char v = 0; |
111f3356 JC |
1244 | int ret; |
1245 | ||
14386c2b | 1246 | ret = ov7670_read(sd, REG_MVFP, &v); |
111f3356 JC |
1247 | if (value) |
1248 | v |= MVFP_FLIP; | |
1249 | else | |
1250 | v &= ~MVFP_FLIP; | |
1251 | msleep(10); /* FIXME */ | |
14386c2b | 1252 | ret += ov7670_write(sd, REG_MVFP, v); |
111f3356 JC |
1253 | return ret; |
1254 | } | |
1255 | ||
81898671 JC |
1256 | /* |
1257 | * GAIN is split between REG_GAIN and REG_VREF[7:6]. If one believes | |
1258 | * the data sheet, the VREF parts should be the most significant, but | |
1259 | * experience shows otherwise. There seems to be little value in | |
1260 | * messing with the VREF bits, so we leave them alone. | |
1261 | */ | |
1262 | static int ov7670_g_gain(struct v4l2_subdev *sd, __s32 *value) | |
1263 | { | |
1264 | int ret; | |
1265 | unsigned char gain; | |
1266 | ||
1267 | ret = ov7670_read(sd, REG_GAIN, &gain); | |
1268 | *value = gain; | |
1269 | return ret; | |
1270 | } | |
1271 | ||
1272 | static int ov7670_s_gain(struct v4l2_subdev *sd, int value) | |
1273 | { | |
1274 | int ret; | |
1275 | unsigned char com8; | |
1276 | ||
1277 | ret = ov7670_write(sd, REG_GAIN, value & 0xff); | |
1278 | /* Have to turn off AGC as well */ | |
1279 | if (ret == 0) { | |
1280 | ret = ov7670_read(sd, REG_COM8, &com8); | |
1281 | ret = ov7670_write(sd, REG_COM8, com8 & ~COM8_AGC); | |
1282 | } | |
1283 | return ret; | |
1284 | } | |
1285 | ||
1286 | /* | |
1287 | * Tweak autogain. | |
1288 | */ | |
1289 | static int ov7670_g_autogain(struct v4l2_subdev *sd, __s32 *value) | |
1290 | { | |
1291 | int ret; | |
1292 | unsigned char com8; | |
1293 | ||
1294 | ret = ov7670_read(sd, REG_COM8, &com8); | |
1295 | *value = (com8 & COM8_AGC) != 0; | |
1296 | return ret; | |
1297 | } | |
1298 | ||
1299 | static int ov7670_s_autogain(struct v4l2_subdev *sd, int value) | |
1300 | { | |
1301 | int ret; | |
1302 | unsigned char com8; | |
1303 | ||
1304 | ret = ov7670_read(sd, REG_COM8, &com8); | |
1305 | if (ret == 0) { | |
1306 | if (value) | |
1307 | com8 |= COM8_AGC; | |
1308 | else | |
1309 | com8 &= ~COM8_AGC; | |
1310 | ret = ov7670_write(sd, REG_COM8, com8); | |
1311 | } | |
1312 | return ret; | |
1313 | } | |
1314 | ||
364e9337 JC |
1315 | /* |
1316 | * Exposure is spread all over the place: top 6 bits in AECHH, middle | |
1317 | * 8 in AECH, and two stashed in COM1 just for the hell of it. | |
1318 | */ | |
1319 | static int ov7670_g_exp(struct v4l2_subdev *sd, __s32 *value) | |
1320 | { | |
1321 | int ret; | |
1322 | unsigned char com1, aech, aechh; | |
1323 | ||
1324 | ret = ov7670_read(sd, REG_COM1, &com1) + | |
1325 | ov7670_read(sd, REG_AECH, &aech) + | |
1326 | ov7670_read(sd, REG_AECHH, &aechh); | |
1327 | *value = ((aechh & 0x3f) << 10) | (aech << 2) | (com1 & 0x03); | |
1328 | return ret; | |
1329 | } | |
1330 | ||
1331 | static int ov7670_s_exp(struct v4l2_subdev *sd, int value) | |
1332 | { | |
1333 | int ret; | |
1334 | unsigned char com1, com8, aech, aechh; | |
1335 | ||
1336 | ret = ov7670_read(sd, REG_COM1, &com1) + | |
1337 | ov7670_read(sd, REG_COM8, &com8); | |
1338 | ov7670_read(sd, REG_AECHH, &aechh); | |
1339 | if (ret) | |
1340 | return ret; | |
1341 | ||
1342 | com1 = (com1 & 0xfc) | (value & 0x03); | |
1343 | aech = (value >> 2) & 0xff; | |
1344 | aechh = (aechh & 0xc0) | ((value >> 10) & 0x3f); | |
1345 | ret = ov7670_write(sd, REG_COM1, com1) + | |
1346 | ov7670_write(sd, REG_AECH, aech) + | |
1347 | ov7670_write(sd, REG_AECHH, aechh); | |
1348 | /* Have to turn off AEC as well */ | |
1349 | if (ret == 0) | |
1350 | ret = ov7670_write(sd, REG_COM8, com8 & ~COM8_AEC); | |
1351 | return ret; | |
1352 | } | |
1353 | ||
1354 | /* | |
1355 | * Tweak autoexposure. | |
1356 | */ | |
1357 | static int ov7670_g_autoexp(struct v4l2_subdev *sd, __s32 *value) | |
1358 | { | |
1359 | int ret; | |
1360 | unsigned char com8; | |
1361 | enum v4l2_exposure_auto_type *atype = (enum v4l2_exposure_auto_type *) value; | |
1362 | ||
1363 | ret = ov7670_read(sd, REG_COM8, &com8); | |
1364 | if (com8 & COM8_AEC) | |
380de498 | 1365 | *atype = V4L2_EXPOSURE_AUTO; |
364e9337 | 1366 | else |
380de498 | 1367 | *atype = V4L2_EXPOSURE_MANUAL; |
364e9337 JC |
1368 | return ret; |
1369 | } | |
1370 | ||
1371 | static int ov7670_s_autoexp(struct v4l2_subdev *sd, | |
1372 | enum v4l2_exposure_auto_type value) | |
1373 | { | |
1374 | int ret; | |
1375 | unsigned char com8; | |
1376 | ||
1377 | ret = ov7670_read(sd, REG_COM8, &com8); | |
1378 | if (ret == 0) { | |
1379 | if (value == V4L2_EXPOSURE_AUTO) | |
1380 | com8 |= COM8_AEC; | |
1381 | else | |
1382 | com8 &= ~COM8_AEC; | |
1383 | ret = ov7670_write(sd, REG_COM8, com8); | |
1384 | } | |
1385 | return ret; | |
1386 | } | |
1387 | ||
81898671 JC |
1388 | |
1389 | ||
14386c2b | 1390 | static int ov7670_queryctrl(struct v4l2_subdev *sd, |
111f3356 JC |
1391 | struct v4l2_queryctrl *qc) |
1392 | { | |
ca07561a HV |
1393 | /* Fill in min, max, step and default value for these controls. */ |
1394 | switch (qc->id) { | |
1395 | case V4L2_CID_BRIGHTNESS: | |
1396 | return v4l2_ctrl_query_fill(qc, 0, 255, 1, 128); | |
1397 | case V4L2_CID_CONTRAST: | |
1398 | return v4l2_ctrl_query_fill(qc, 0, 127, 1, 64); | |
1399 | case V4L2_CID_VFLIP: | |
1400 | case V4L2_CID_HFLIP: | |
1401 | return v4l2_ctrl_query_fill(qc, 0, 1, 1, 0); | |
1402 | case V4L2_CID_SATURATION: | |
1403 | return v4l2_ctrl_query_fill(qc, 0, 256, 1, 128); | |
1404 | case V4L2_CID_HUE: | |
1405 | return v4l2_ctrl_query_fill(qc, -180, 180, 5, 0); | |
81898671 JC |
1406 | case V4L2_CID_GAIN: |
1407 | return v4l2_ctrl_query_fill(qc, 0, 255, 1, 128); | |
1408 | case V4L2_CID_AUTOGAIN: | |
1409 | return v4l2_ctrl_query_fill(qc, 0, 1, 1, 1); | |
364e9337 JC |
1410 | case V4L2_CID_EXPOSURE: |
1411 | return v4l2_ctrl_query_fill(qc, 0, 65535, 1, 500); | |
1412 | case V4L2_CID_EXPOSURE_AUTO: | |
1413 | return v4l2_ctrl_query_fill(qc, 0, 1, 1, 0); | |
ca07561a HV |
1414 | } |
1415 | return -EINVAL; | |
111f3356 JC |
1416 | } |
1417 | ||
14386c2b | 1418 | static int ov7670_g_ctrl(struct v4l2_subdev *sd, struct v4l2_control *ctrl) |
111f3356 | 1419 | { |
ca07561a HV |
1420 | switch (ctrl->id) { |
1421 | case V4L2_CID_BRIGHTNESS: | |
1422 | return ov7670_g_brightness(sd, &ctrl->value); | |
1423 | case V4L2_CID_CONTRAST: | |
1424 | return ov7670_g_contrast(sd, &ctrl->value); | |
1425 | case V4L2_CID_SATURATION: | |
1426 | return ov7670_g_sat(sd, &ctrl->value); | |
1427 | case V4L2_CID_HUE: | |
1428 | return ov7670_g_hue(sd, &ctrl->value); | |
1429 | case V4L2_CID_VFLIP: | |
1430 | return ov7670_g_vflip(sd, &ctrl->value); | |
1431 | case V4L2_CID_HFLIP: | |
1432 | return ov7670_g_hflip(sd, &ctrl->value); | |
81898671 JC |
1433 | case V4L2_CID_GAIN: |
1434 | return ov7670_g_gain(sd, &ctrl->value); | |
1435 | case V4L2_CID_AUTOGAIN: | |
1436 | return ov7670_g_autogain(sd, &ctrl->value); | |
364e9337 JC |
1437 | case V4L2_CID_EXPOSURE: |
1438 | return ov7670_g_exp(sd, &ctrl->value); | |
1439 | case V4L2_CID_EXPOSURE_AUTO: | |
1440 | return ov7670_g_autoexp(sd, &ctrl->value); | |
ca07561a HV |
1441 | } |
1442 | return -EINVAL; | |
111f3356 JC |
1443 | } |
1444 | ||
14386c2b | 1445 | static int ov7670_s_ctrl(struct v4l2_subdev *sd, struct v4l2_control *ctrl) |
111f3356 | 1446 | { |
ca07561a HV |
1447 | switch (ctrl->id) { |
1448 | case V4L2_CID_BRIGHTNESS: | |
1449 | return ov7670_s_brightness(sd, ctrl->value); | |
1450 | case V4L2_CID_CONTRAST: | |
1451 | return ov7670_s_contrast(sd, ctrl->value); | |
1452 | case V4L2_CID_SATURATION: | |
1453 | return ov7670_s_sat(sd, ctrl->value); | |
1454 | case V4L2_CID_HUE: | |
1455 | return ov7670_s_hue(sd, ctrl->value); | |
1456 | case V4L2_CID_VFLIP: | |
1457 | return ov7670_s_vflip(sd, ctrl->value); | |
1458 | case V4L2_CID_HFLIP: | |
1459 | return ov7670_s_hflip(sd, ctrl->value); | |
81898671 JC |
1460 | case V4L2_CID_GAIN: |
1461 | return ov7670_s_gain(sd, ctrl->value); | |
1462 | case V4L2_CID_AUTOGAIN: | |
1463 | return ov7670_s_autogain(sd, ctrl->value); | |
364e9337 JC |
1464 | case V4L2_CID_EXPOSURE: |
1465 | return ov7670_s_exp(sd, ctrl->value); | |
1466 | case V4L2_CID_EXPOSURE_AUTO: | |
1467 | return ov7670_s_autoexp(sd, | |
1468 | (enum v4l2_exposure_auto_type) ctrl->value); | |
ca07561a HV |
1469 | } |
1470 | return -EINVAL; | |
111f3356 JC |
1471 | } |
1472 | ||
14386c2b HV |
1473 | static int ov7670_g_chip_ident(struct v4l2_subdev *sd, |
1474 | struct v4l2_dbg_chip_ident *chip) | |
1475 | { | |
1476 | struct i2c_client *client = v4l2_get_subdevdata(sd); | |
1477 | ||
1478 | return v4l2_chip_ident_i2c_client(client, chip, V4L2_IDENT_OV7670, 0); | |
1479 | } | |
1480 | ||
b794aabf HV |
1481 | #ifdef CONFIG_VIDEO_ADV_DEBUG |
1482 | static int ov7670_g_register(struct v4l2_subdev *sd, struct v4l2_dbg_register *reg) | |
1483 | { | |
1484 | struct i2c_client *client = v4l2_get_subdevdata(sd); | |
1485 | unsigned char val = 0; | |
1486 | int ret; | |
1487 | ||
1488 | if (!v4l2_chip_match_i2c_client(client, ®->match)) | |
1489 | return -EINVAL; | |
1490 | if (!capable(CAP_SYS_ADMIN)) | |
1491 | return -EPERM; | |
1492 | ret = ov7670_read(sd, reg->reg & 0xff, &val); | |
1493 | reg->val = val; | |
1494 | reg->size = 1; | |
1495 | return ret; | |
1496 | } | |
1497 | ||
1498 | static int ov7670_s_register(struct v4l2_subdev *sd, struct v4l2_dbg_register *reg) | |
1499 | { | |
1500 | struct i2c_client *client = v4l2_get_subdevdata(sd); | |
1501 | ||
1502 | if (!v4l2_chip_match_i2c_client(client, ®->match)) | |
1503 | return -EINVAL; | |
1504 | if (!capable(CAP_SYS_ADMIN)) | |
1505 | return -EPERM; | |
1506 | ov7670_write(sd, reg->reg & 0xff, reg->val & 0xff); | |
1507 | return 0; | |
1508 | } | |
1509 | #endif | |
1510 | ||
14386c2b | 1511 | /* ----------------------------------------------------------------------- */ |
111f3356 | 1512 | |
14386c2b HV |
1513 | static const struct v4l2_subdev_core_ops ov7670_core_ops = { |
1514 | .g_chip_ident = ov7670_g_chip_ident, | |
1515 | .g_ctrl = ov7670_g_ctrl, | |
1516 | .s_ctrl = ov7670_s_ctrl, | |
1517 | .queryctrl = ov7670_queryctrl, | |
1518 | .reset = ov7670_reset, | |
1519 | .init = ov7670_init, | |
b794aabf HV |
1520 | #ifdef CONFIG_VIDEO_ADV_DEBUG |
1521 | .g_register = ov7670_g_register, | |
1522 | .s_register = ov7670_s_register, | |
1523 | #endif | |
14386c2b | 1524 | }; |
111f3356 | 1525 | |
14386c2b | 1526 | static const struct v4l2_subdev_video_ops ov7670_video_ops = { |
959f3bda HV |
1527 | .enum_mbus_fmt = ov7670_enum_mbus_fmt, |
1528 | .try_mbus_fmt = ov7670_try_mbus_fmt, | |
1529 | .s_mbus_fmt = ov7670_s_mbus_fmt, | |
14386c2b HV |
1530 | .s_parm = ov7670_s_parm, |
1531 | .g_parm = ov7670_g_parm, | |
e99dfcf7 | 1532 | .enum_frameintervals = ov7670_enum_frameintervals, |
b0326b7f | 1533 | .enum_framesizes = ov7670_enum_framesizes, |
14386c2b | 1534 | }; |
111f3356 | 1535 | |
14386c2b HV |
1536 | static const struct v4l2_subdev_ops ov7670_ops = { |
1537 | .core = &ov7670_core_ops, | |
1538 | .video = &ov7670_video_ops, | |
1539 | }; | |
111f3356 | 1540 | |
14386c2b | 1541 | /* ----------------------------------------------------------------------- */ |
111f3356 | 1542 | |
d058e237 JM |
1543 | static const struct ov7670_devtype ov7670_devdata[] = { |
1544 | [MODEL_OV7670] = { | |
1545 | .win_sizes = ov7670_win_sizes, | |
1546 | .n_win_sizes = ARRAY_SIZE(ov7670_win_sizes), | |
1547 | }, | |
1548 | [MODEL_OV7675] = { | |
1549 | .win_sizes = ov7675_win_sizes, | |
1550 | .n_win_sizes = ARRAY_SIZE(ov7675_win_sizes), | |
1551 | }, | |
1552 | }; | |
1553 | ||
14386c2b HV |
1554 | static int ov7670_probe(struct i2c_client *client, |
1555 | const struct i2c_device_id *id) | |
111f3356 | 1556 | { |
14386c2b | 1557 | struct v4l2_subdev *sd; |
f9a76156 | 1558 | struct ov7670_info *info; |
3c7c9370 | 1559 | int ret; |
111f3356 | 1560 | |
14386c2b HV |
1561 | info = kzalloc(sizeof(struct ov7670_info), GFP_KERNEL); |
1562 | if (info == NULL) | |
111f3356 | 1563 | return -ENOMEM; |
14386c2b HV |
1564 | sd = &info->sd; |
1565 | v4l2_i2c_subdev_init(sd, client, &ov7670_ops); | |
1566 | ||
3c7c9370 HV |
1567 | info->clock_speed = 30; /* default: a guess */ |
1568 | if (client->dev.platform_data) { | |
1569 | struct ov7670_config *config = client->dev.platform_data; | |
1570 | ||
1571 | /* | |
1572 | * Must apply configuration before initializing device, because it | |
1573 | * selects I/O method. | |
1574 | */ | |
1575 | info->min_width = config->min_width; | |
1576 | info->min_height = config->min_height; | |
1577 | info->use_smbus = config->use_smbus; | |
1578 | ||
1579 | if (config->clock_speed) | |
1580 | info->clock_speed = config->clock_speed; | |
1581 | } | |
1582 | ||
1583 | /* Make sure it's an ov7670 */ | |
1584 | ret = ov7670_detect(sd); | |
1585 | if (ret) { | |
1586 | v4l_dbg(1, debug, client, | |
1587 | "chip found @ 0x%x (%s) is not an ov7670 chip.\n", | |
1588 | client->addr << 1, client->adapter->name); | |
1589 | kfree(info); | |
1590 | return ret; | |
1591 | } | |
1592 | v4l_info(client, "chip found @ 0x%02x (%s)\n", | |
1593 | client->addr << 1, client->adapter->name); | |
1594 | ||
d058e237 | 1595 | info->devtype = &ov7670_devdata[id->driver_data]; |
3c7c9370 HV |
1596 | info->fmt = &ov7670_formats[0]; |
1597 | info->sat = 128; /* Review this */ | |
1598 | info->clkrc = info->clock_speed / 30; | |
111f3356 | 1599 | return 0; |
111f3356 JC |
1600 | } |
1601 | ||
1602 | ||
14386c2b | 1603 | static int ov7670_remove(struct i2c_client *client) |
111f3356 | 1604 | { |
14386c2b | 1605 | struct v4l2_subdev *sd = i2c_get_clientdata(client); |
111f3356 | 1606 | |
14386c2b HV |
1607 | v4l2_device_unregister_subdev(sd); |
1608 | kfree(to_state(sd)); | |
1609 | return 0; | |
111f3356 JC |
1610 | } |
1611 | ||
14386c2b | 1612 | static const struct i2c_device_id ov7670_id[] = { |
d058e237 JM |
1613 | { "ov7670", MODEL_OV7670 }, |
1614 | { "ov7675", MODEL_OV7675 }, | |
14386c2b HV |
1615 | { } |
1616 | }; | |
1617 | MODULE_DEVICE_TABLE(i2c, ov7670_id); | |
1618 | ||
ef2ac770 HV |
1619 | static struct i2c_driver ov7670_driver = { |
1620 | .driver = { | |
1621 | .owner = THIS_MODULE, | |
1622 | .name = "ov7670", | |
1623 | }, | |
1624 | .probe = ov7670_probe, | |
1625 | .remove = ov7670_remove, | |
1626 | .id_table = ov7670_id, | |
111f3356 | 1627 | }; |
ef2ac770 | 1628 | |
c6e8d86f | 1629 | module_i2c_driver(ov7670_driver); |