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Commit | Line | Data |
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89f75ffc MCC |
1 | /* saa711x - Philips SAA711x video decoder driver |
2 | * This driver can work with saa7111, saa7111a, saa7113, saa7114, | |
3 | * saa7115 and saa7118. | |
e19b2fcc HV |
4 | * |
5 | * Based on saa7114 driver by Maxim Yevtyushkin, which is based on | |
6 | * the saa7111 driver by Dave Perks. | |
7 | * | |
8 | * Copyright (C) 1998 Dave Perks <dperks@ibm.net> | |
9 | * Copyright (C) 2002 Maxim Yevtyushkin <max@linuxmedialabs.com> | |
10 | * | |
11 | * Slight changes for video timing and attachment output by | |
12 | * Wolfgang Scherr <scherr@net4you.net> | |
13 | * | |
14 | * Moved over to the linux >= 2.4.x i2c protocol (1/1/2003) | |
15 | * by Ronald Bultje <rbultje@ronald.bitfreak.net> | |
16 | * | |
17 | * Added saa7115 support by Kevin Thayer <nufan_wfk at yahoo.com> | |
18 | * (2/17/2003) | |
19 | * | |
20 | * VBI support (2004) and cleanups (2005) by Hans Verkuil <hverkuil@xs4all.nl> | |
89f75ffc MCC |
21 | * |
22 | * Copyright (c) 2005-2006 Mauro Carvalho Chehab <mchehab@infradead.org> | |
23 | * SAA7111, SAA7113 and SAA7118 support | |
e19b2fcc HV |
24 | * |
25 | * This program is free software; you can redistribute it and/or | |
26 | * modify it under the terms of the GNU General Public License | |
27 | * as published by the Free Software Foundation; either version 2 | |
28 | * of the License, or (at your option) any later version. | |
29 | * | |
30 | * This program is distributed in the hope that it will be useful, | |
31 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
32 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
33 | * GNU General Public License for more details. | |
34 | * | |
35 | * You should have received a copy of the GNU General Public License | |
36 | * along with this program; if not, write to the Free Software | |
37 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. | |
38 | */ | |
39 | ||
96ecfc4e | 40 | #include "saa711x_regs.h" |
e19b2fcc HV |
41 | |
42 | #include <linux/kernel.h> | |
43 | #include <linux/module.h> | |
44 | #include <linux/slab.h> | |
45 | #include <linux/i2c.h> | |
46 | #include <linux/videodev2.h> | |
9415f4b2 | 47 | #include <media/v4l2-device.h> |
e3560543 | 48 | #include <media/v4l2-ctrls.h> |
1f8f5fa9 | 49 | #include <media/saa7115.h> |
3578d3dd | 50 | #include <asm/div64.h> |
e19b2fcc | 51 | |
97d9e80e | 52 | #define VRES_60HZ (480+16) |
d9dce96f | 53 | |
89f75ffc | 54 | MODULE_DESCRIPTION("Philips SAA7111/SAA7113/SAA7114/SAA7115/SAA7118 video decoder driver"); |
f5762e44 MCC |
55 | MODULE_AUTHOR( "Maxim Yevtyushkin, Kevin Thayer, Chris Kennedy, " |
56 | "Hans Verkuil, Mauro Carvalho Chehab"); | |
e19b2fcc HV |
57 | MODULE_LICENSE("GPL"); |
58 | ||
90ab5ee9 | 59 | static bool debug; |
fac9e899 | 60 | module_param(debug, bool, 0644); |
e19b2fcc HV |
61 | |
62 | MODULE_PARM_DESC(debug, "Debug level (0-1)"); | |
63 | ||
e19b2fcc | 64 | |
e1277110 HV |
65 | enum saa711x_model { |
66 | SAA7111A, | |
67 | SAA7111, | |
68 | SAA7113, | |
69 | GM7113C, | |
70 | SAA7114, | |
71 | SAA7115, | |
72 | SAA7118, | |
73 | }; | |
74 | ||
66ec1193 | 75 | struct saa711x_state { |
9415f4b2 | 76 | struct v4l2_subdev sd; |
e3560543 HV |
77 | struct v4l2_ctrl_handler hdl; |
78 | ||
79 | struct { | |
80 | /* chroma gain control cluster */ | |
81 | struct v4l2_ctrl *agc; | |
82 | struct v4l2_ctrl *gain; | |
83 | }; | |
84 | ||
e19b2fcc HV |
85 | v4l2_std_id std; |
86 | int input; | |
4cbca185 | 87 | int output; |
e19b2fcc | 88 | int enable; |
3faeeae4 | 89 | int radio; |
d9dce96f MCC |
90 | int width; |
91 | int height; | |
e1277110 | 92 | enum saa711x_model ident; |
3578d3dd | 93 | u32 audclk_freq; |
b7f8292c | 94 | u32 crystal_freq; |
1589037f | 95 | bool ucgc; |
b7f8292c | 96 | u8 cgcdiv; |
1589037f HV |
97 | bool apll; |
98 | bool double_asclk; | |
e19b2fcc HV |
99 | }; |
100 | ||
9415f4b2 HV |
101 | static inline struct saa711x_state *to_state(struct v4l2_subdev *sd) |
102 | { | |
103 | return container_of(sd, struct saa711x_state, sd); | |
104 | } | |
105 | ||
e3560543 HV |
106 | static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl) |
107 | { | |
108 | return &container_of(ctrl->handler, struct saa711x_state, hdl)->sd; | |
109 | } | |
110 | ||
e19b2fcc HV |
111 | /* ----------------------------------------------------------------------- */ |
112 | ||
9415f4b2 | 113 | static inline int saa711x_write(struct v4l2_subdev *sd, u8 reg, u8 value) |
e19b2fcc | 114 | { |
9415f4b2 HV |
115 | struct i2c_client *client = v4l2_get_subdevdata(sd); |
116 | ||
e19b2fcc HV |
117 | return i2c_smbus_write_byte_data(client, reg, value); |
118 | } | |
119 | ||
89f75ffc MCC |
120 | /* Sanity routine to check if a register is present */ |
121 | static int saa711x_has_reg(const int id, const u8 reg) | |
122 | { | |
e1277110 | 123 | if (id == SAA7111) |
d9dce96f MCC |
124 | return reg < 0x20 && reg != 0x01 && reg != 0x0f && |
125 | (reg < 0x13 || reg > 0x19) && reg != 0x1d && reg != 0x1e; | |
e1277110 | 126 | if (id == SAA7111A) |
340dde81 HV |
127 | return reg < 0x20 && reg != 0x01 && reg != 0x0f && |
128 | reg != 0x14 && reg != 0x18 && reg != 0x19 && | |
129 | reg != 0x1d && reg != 0x1e; | |
d9dce96f MCC |
130 | |
131 | /* common for saa7113/4/5/8 */ | |
132 | if (unlikely((reg >= 0x3b && reg <= 0x3f) || reg == 0x5c || reg == 0x5f || | |
133 | reg == 0xa3 || reg == 0xa7 || reg == 0xab || reg == 0xaf || (reg >= 0xb5 && reg <= 0xb7) || | |
134 | reg == 0xd3 || reg == 0xd7 || reg == 0xdb || reg == 0xdf || (reg >= 0xe5 && reg <= 0xe7) || | |
135 | reg == 0x82 || (reg >= 0x89 && reg <= 0x8e))) | |
136 | return 0; | |
137 | ||
89f75ffc | 138 | switch (id) { |
e1277110 | 139 | case GM7113C: |
241d89fc | 140 | return reg != 0x14 && (reg < 0x18 || reg > 0x1e) && reg < 0x20; |
e1277110 | 141 | case SAA7113: |
d9dce96f MCC |
142 | return reg != 0x14 && (reg < 0x18 || reg > 0x1e) && (reg < 0x20 || reg > 0x3f) && |
143 | reg != 0x5d && reg < 0x63; | |
e1277110 | 144 | case SAA7114: |
d9dce96f MCC |
145 | return (reg < 0x1a || reg > 0x1e) && (reg < 0x20 || reg > 0x2f) && |
146 | (reg < 0x63 || reg > 0x7f) && reg != 0x33 && reg != 0x37 && | |
147 | reg != 0x81 && reg < 0xf0; | |
e1277110 | 148 | case SAA7115: |
d9dce96f | 149 | return (reg < 0x20 || reg > 0x2f) && reg != 0x65 && (reg < 0xfc || reg > 0xfe); |
e1277110 | 150 | case SAA7118: |
d9dce96f MCC |
151 | return (reg < 0x1a || reg > 0x1d) && (reg < 0x20 || reg > 0x22) && |
152 | (reg < 0x26 || reg > 0x28) && reg != 0x33 && reg != 0x37 && | |
153 | (reg < 0x63 || reg > 0x7f) && reg != 0x81 && reg < 0xf0; | |
89f75ffc | 154 | } |
89f75ffc MCC |
155 | return 1; |
156 | } | |
157 | ||
9415f4b2 | 158 | static int saa711x_writeregs(struct v4l2_subdev *sd, const unsigned char *regs) |
e19b2fcc | 159 | { |
9415f4b2 | 160 | struct saa711x_state *state = to_state(sd); |
e19b2fcc HV |
161 | unsigned char reg, data; |
162 | ||
163 | while (*regs != 0x00) { | |
164 | reg = *(regs++); | |
165 | data = *(regs++); | |
89f75ffc MCC |
166 | |
167 | /* According with datasheets, reserved regs should be | |
168 | filled with 0 - seems better not to touch on they */ | |
9415f4b2 HV |
169 | if (saa711x_has_reg(state->ident, reg)) { |
170 | if (saa711x_write(sd, reg, data) < 0) | |
89f75ffc | 171 | return -1; |
d87edf26 | 172 | } else { |
9415f4b2 | 173 | v4l2_dbg(1, debug, sd, "tried to access reserved reg 0x%02x\n", reg); |
89f75ffc | 174 | } |
e19b2fcc HV |
175 | } |
176 | return 0; | |
177 | } | |
178 | ||
9415f4b2 | 179 | static inline int saa711x_read(struct v4l2_subdev *sd, u8 reg) |
e19b2fcc | 180 | { |
9415f4b2 HV |
181 | struct i2c_client *client = v4l2_get_subdevdata(sd); |
182 | ||
e19b2fcc HV |
183 | return i2c_smbus_read_byte_data(client, reg); |
184 | } | |
185 | ||
186 | /* ----------------------------------------------------------------------- */ | |
187 | ||
89f75ffc | 188 | /* SAA7111 initialization table */ |
183d896a | 189 | static const unsigned char saa7111_init[] = { |
89f75ffc MCC |
190 | R_01_INC_DELAY, 0x00, /* reserved */ |
191 | ||
192 | /*front end */ | |
193 | R_02_INPUT_CNTL_1, 0xd0, /* FUSE=3, GUDL=2, MODE=0 */ | |
194 | R_03_INPUT_CNTL_2, 0x23, /* HLNRS=0, VBSL=1, WPOFF=0, HOLDG=0, | |
195 | * GAFIX=0, GAI1=256, GAI2=256 */ | |
196 | R_04_INPUT_CNTL_3, 0x00, /* GAI1=256 */ | |
197 | R_05_INPUT_CNTL_4, 0x00, /* GAI2=256 */ | |
198 | ||
199 | /* decoder */ | |
200 | R_06_H_SYNC_START, 0xf3, /* HSB at 13(50Hz) / 17(60Hz) | |
201 | * pixels after end of last line */ | |
202 | R_07_H_SYNC_STOP, 0xe8, /* HSS seems to be needed to | |
203 | * work with NTSC, too */ | |
204 | R_08_SYNC_CNTL, 0xc8, /* AUFD=1, FSEL=1, EXFIL=0, | |
205 | * VTRC=1, HPLL=0, VNOI=0 */ | |
206 | R_09_LUMA_CNTL, 0x01, /* BYPS=0, PREF=0, BPSS=0, | |
207 | * VBLB=0, UPTCV=0, APER=1 */ | |
208 | R_0A_LUMA_BRIGHT_CNTL, 0x80, | |
209 | R_0B_LUMA_CONTRAST_CNTL, 0x47, /* 0b - CONT=1.109 */ | |
210 | R_0C_CHROMA_SAT_CNTL, 0x40, | |
211 | R_0D_CHROMA_HUE_CNTL, 0x00, | |
212 | R_0E_CHROMA_CNTL_1, 0x01, /* 0e - CDTO=0, CSTD=0, DCCF=0, | |
213 | * FCTC=0, CHBW=1 */ | |
214 | R_0F_CHROMA_GAIN_CNTL, 0x00, /* reserved */ | |
215 | R_10_CHROMA_CNTL_2, 0x48, /* 10 - OFTS=1, HDEL=0, VRLN=1, YDEL=0 */ | |
216 | R_11_MODE_DELAY_CNTL, 0x1c, /* 11 - GPSW=0, CM99=0, FECO=0, COMPO=1, | |
217 | * OEYC=1, OEHV=1, VIPB=0, COLO=0 */ | |
218 | R_12_RT_SIGNAL_CNTL, 0x00, /* 12 - output control 2 */ | |
219 | R_13_RT_X_PORT_OUT_CNTL, 0x00, /* 13 - output control 3 */ | |
220 | R_14_ANAL_ADC_COMPAT_CNTL, 0x00, | |
221 | R_15_VGATE_START_FID_CHG, 0x00, | |
222 | R_16_VGATE_STOP, 0x00, | |
223 | R_17_MISC_VGATE_CONF_AND_MSB, 0x00, | |
224 | ||
225 | 0x00, 0x00 | |
226 | }; | |
227 | ||
241d89fc JAJ |
228 | /* SAA7113/GM7113C init codes |
229 | * It's important that R_14... R_17 == 0x00 | |
230 | * for the gm7113c chip to deliver stable video | |
231 | */ | |
183d896a | 232 | static const unsigned char saa7113_init[] = { |
89f75ffc MCC |
233 | R_01_INC_DELAY, 0x08, |
234 | R_02_INPUT_CNTL_1, 0xc2, | |
235 | R_03_INPUT_CNTL_2, 0x30, | |
236 | R_04_INPUT_CNTL_3, 0x00, | |
237 | R_05_INPUT_CNTL_4, 0x00, | |
238 | R_06_H_SYNC_START, 0x89, | |
239 | R_07_H_SYNC_STOP, 0x0d, | |
240 | R_08_SYNC_CNTL, 0x88, | |
241 | R_09_LUMA_CNTL, 0x01, | |
242 | R_0A_LUMA_BRIGHT_CNTL, 0x80, | |
243 | R_0B_LUMA_CONTRAST_CNTL, 0x47, | |
244 | R_0C_CHROMA_SAT_CNTL, 0x40, | |
245 | R_0D_CHROMA_HUE_CNTL, 0x00, | |
246 | R_0E_CHROMA_CNTL_1, 0x01, | |
247 | R_0F_CHROMA_GAIN_CNTL, 0x2a, | |
248 | R_10_CHROMA_CNTL_2, 0x08, | |
249 | R_11_MODE_DELAY_CNTL, 0x0c, | |
250 | R_12_RT_SIGNAL_CNTL, 0x07, | |
251 | R_13_RT_X_PORT_OUT_CNTL, 0x00, | |
252 | R_14_ANAL_ADC_COMPAT_CNTL, 0x00, | |
253 | R_15_VGATE_START_FID_CHG, 0x00, | |
254 | R_16_VGATE_STOP, 0x00, | |
255 | R_17_MISC_VGATE_CONF_AND_MSB, 0x00, | |
256 | ||
257 | 0x00, 0x00 | |
258 | }; | |
259 | ||
e19b2fcc HV |
260 | /* If a value differs from the Hauppauge driver values, then the comment starts with |
261 | 'was 0xXX' to denote the Hauppauge value. Otherwise the value is identical to what the | |
262 | Hauppauge driver sets. */ | |
263 | ||
89f75ffc | 264 | /* SAA7114 and SAA7115 initialization table */ |
e19b2fcc | 265 | static const unsigned char saa7115_init_auto_input[] = { |
f5762e44 | 266 | /* Front-End Part */ |
96ecfc4e MCC |
267 | R_01_INC_DELAY, 0x48, /* white peak control disabled */ |
268 | R_03_INPUT_CNTL_2, 0x20, /* was 0x30. 0x20: long vertical blanking */ | |
269 | R_04_INPUT_CNTL_3, 0x90, /* analog gain set to 0 */ | |
270 | R_05_INPUT_CNTL_4, 0x90, /* analog gain set to 0 */ | |
f5762e44 | 271 | /* Decoder Part */ |
96ecfc4e MCC |
272 | R_06_H_SYNC_START, 0xeb, /* horiz sync begin = -21 */ |
273 | R_07_H_SYNC_STOP, 0xe0, /* horiz sync stop = -17 */ | |
183d896a | 274 | R_09_LUMA_CNTL, 0x53, /* 0x53, was 0x56 for 60hz. luminance control */ |
96ecfc4e MCC |
275 | R_0A_LUMA_BRIGHT_CNTL, 0x80, /* was 0x88. decoder brightness, 0x80 is itu standard */ |
276 | R_0B_LUMA_CONTRAST_CNTL, 0x44, /* was 0x48. decoder contrast, 0x44 is itu standard */ | |
277 | R_0C_CHROMA_SAT_CNTL, 0x40, /* was 0x47. decoder saturation, 0x40 is itu standard */ | |
278 | R_0D_CHROMA_HUE_CNTL, 0x00, | |
279 | R_0F_CHROMA_GAIN_CNTL, 0x00, /* use automatic gain */ | |
280 | R_10_CHROMA_CNTL_2, 0x06, /* chroma: active adaptive combfilter */ | |
281 | R_11_MODE_DELAY_CNTL, 0x00, | |
282 | R_12_RT_SIGNAL_CNTL, 0x9d, /* RTS0 output control: VGATE */ | |
283 | R_13_RT_X_PORT_OUT_CNTL, 0x80, /* ITU656 standard mode, RTCO output enable RTCE */ | |
284 | R_14_ANAL_ADC_COMPAT_CNTL, 0x00, | |
285 | R_18_RAW_DATA_GAIN_CNTL, 0x40, /* gain 0x00 = nominal */ | |
286 | R_19_RAW_DATA_OFF_CNTL, 0x80, | |
287 | R_1A_COLOR_KILL_LVL_CNTL, 0x77, /* recommended value */ | |
288 | R_1B_MISC_TVVCRDET, 0x42, /* recommended value */ | |
289 | R_1C_ENHAN_COMB_CTRL1, 0xa9, /* recommended value */ | |
290 | R_1D_ENHAN_COMB_CTRL2, 0x01, /* recommended value */ | |
f5762e44 | 291 | |
d9dce96f MCC |
292 | |
293 | R_80_GLOBAL_CNTL_1, 0x0, /* No tasks enabled at init */ | |
294 | ||
f5762e44 | 295 | /* Power Device Control */ |
96ecfc4e MCC |
296 | R_88_POWER_SAVE_ADC_PORT_CNTL, 0xd0, /* reset device */ |
297 | R_88_POWER_SAVE_ADC_PORT_CNTL, 0xf0, /* set device programmed, all in operational mode */ | |
e19b2fcc HV |
298 | 0x00, 0x00 |
299 | }; | |
300 | ||
89f75ffc | 301 | /* Used to reset saa7113, saa7114 and saa7115 */ |
e19b2fcc | 302 | static const unsigned char saa7115_cfg_reset_scaler[] = { |
96ecfc4e MCC |
303 | R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED, 0x00, /* disable I-port output */ |
304 | R_88_POWER_SAVE_ADC_PORT_CNTL, 0xd0, /* reset scaler */ | |
305 | R_88_POWER_SAVE_ADC_PORT_CNTL, 0xf0, /* activate scaler */ | |
306 | R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED, 0x01, /* enable I-port output */ | |
e19b2fcc HV |
307 | 0x00, 0x00 |
308 | }; | |
309 | ||
310 | /* ============== SAA7715 VIDEO templates ============= */ | |
311 | ||
e19b2fcc | 312 | static const unsigned char saa7115_cfg_60hz_video[] = { |
96ecfc4e MCC |
313 | R_80_GLOBAL_CNTL_1, 0x00, /* reset tasks */ |
314 | R_88_POWER_SAVE_ADC_PORT_CNTL, 0xd0, /* reset scaler */ | |
e19b2fcc | 315 | |
96ecfc4e MCC |
316 | R_15_VGATE_START_FID_CHG, 0x03, |
317 | R_16_VGATE_STOP, 0x11, | |
318 | R_17_MISC_VGATE_CONF_AND_MSB, 0x9c, | |
e19b2fcc | 319 | |
96ecfc4e MCC |
320 | R_08_SYNC_CNTL, 0x68, /* 0xBO: auto detection, 0x68 = NTSC */ |
321 | R_0E_CHROMA_CNTL_1, 0x07, /* video autodetection is on */ | |
e19b2fcc | 322 | |
96ecfc4e | 323 | R_5A_V_OFF_FOR_SLICER, 0x06, /* standard 60hz value for ITU656 line counting */ |
e19b2fcc HV |
324 | |
325 | /* Task A */ | |
96ecfc4e MCC |
326 | R_90_A_TASK_HANDLING_CNTL, 0x80, |
327 | R_91_A_X_PORT_FORMATS_AND_CONF, 0x48, | |
328 | R_92_A_X_PORT_INPUT_REFERENCE_SIGNAL, 0x40, | |
329 | R_93_A_I_PORT_OUTPUT_FORMATS_AND_CONF, 0x84, | |
330 | ||
331 | /* hoffset low (input), 0x0002 is minimum */ | |
332 | R_94_A_HORIZ_INPUT_WINDOW_START, 0x01, | |
333 | R_95_A_HORIZ_INPUT_WINDOW_START_MSB, 0x00, | |
334 | ||
335 | /* hsize low (input), 0x02d0 = 720 */ | |
336 | R_96_A_HORIZ_INPUT_WINDOW_LENGTH, 0xd0, | |
337 | R_97_A_HORIZ_INPUT_WINDOW_LENGTH_MSB, 0x02, | |
338 | ||
339 | R_98_A_VERT_INPUT_WINDOW_START, 0x05, | |
340 | R_99_A_VERT_INPUT_WINDOW_START_MSB, 0x00, | |
341 | ||
342 | R_9A_A_VERT_INPUT_WINDOW_LENGTH, 0x0c, | |
343 | R_9B_A_VERT_INPUT_WINDOW_LENGTH_MSB, 0x00, | |
344 | ||
345 | R_9C_A_HORIZ_OUTPUT_WINDOW_LENGTH, 0xa0, | |
346 | R_9D_A_HORIZ_OUTPUT_WINDOW_LENGTH_MSB, 0x05, | |
347 | ||
348 | R_9E_A_VERT_OUTPUT_WINDOW_LENGTH, 0x0c, | |
349 | R_9F_A_VERT_OUTPUT_WINDOW_LENGTH_MSB, 0x00, | |
e19b2fcc HV |
350 | |
351 | /* Task B */ | |
96ecfc4e MCC |
352 | R_C0_B_TASK_HANDLING_CNTL, 0x00, |
353 | R_C1_B_X_PORT_FORMATS_AND_CONF, 0x08, | |
354 | R_C2_B_INPUT_REFERENCE_SIGNAL_DEFINITION, 0x00, | |
355 | R_C3_B_I_PORT_FORMATS_AND_CONF, 0x80, | |
356 | ||
357 | /* 0x0002 is minimum */ | |
358 | R_C4_B_HORIZ_INPUT_WINDOW_START, 0x02, | |
359 | R_C5_B_HORIZ_INPUT_WINDOW_START_MSB, 0x00, | |
360 | ||
361 | /* 0x02d0 = 720 */ | |
362 | R_C6_B_HORIZ_INPUT_WINDOW_LENGTH, 0xd0, | |
363 | R_C7_B_HORIZ_INPUT_WINDOW_LENGTH_MSB, 0x02, | |
364 | ||
365 | /* vwindow start 0x12 = 18 */ | |
366 | R_C8_B_VERT_INPUT_WINDOW_START, 0x12, | |
367 | R_C9_B_VERT_INPUT_WINDOW_START_MSB, 0x00, | |
368 | ||
369 | /* vwindow length 0xf8 = 248 */ | |
97d9e80e MCC |
370 | R_CA_B_VERT_INPUT_WINDOW_LENGTH, VRES_60HZ>>1, |
371 | R_CB_B_VERT_INPUT_WINDOW_LENGTH_MSB, VRES_60HZ>>9, | |
96ecfc4e MCC |
372 | |
373 | /* hwindow 0x02d0 = 720 */ | |
374 | R_CC_B_HORIZ_OUTPUT_WINDOW_LENGTH, 0xd0, | |
375 | R_CD_B_HORIZ_OUTPUT_WINDOW_LENGTH_MSB, 0x02, | |
376 | ||
377 | R_F0_LFCO_PER_LINE, 0xad, /* Set PLL Register. 60hz 525 lines per frame, 27 MHz */ | |
378 | R_F1_P_I_PARAM_SELECT, 0x05, /* low bit with 0xF0 */ | |
379 | R_F5_PULSGEN_LINE_LENGTH, 0xad, | |
380 | R_F6_PULSE_A_POS_LSB_AND_PULSEGEN_CONFIG, 0x01, | |
381 | ||
e19b2fcc HV |
382 | 0x00, 0x00 |
383 | }; | |
384 | ||
e19b2fcc | 385 | static const unsigned char saa7115_cfg_50hz_video[] = { |
96ecfc4e MCC |
386 | R_80_GLOBAL_CNTL_1, 0x00, |
387 | R_88_POWER_SAVE_ADC_PORT_CNTL, 0xd0, /* reset scaler */ | |
e19b2fcc | 388 | |
96ecfc4e MCC |
389 | R_15_VGATE_START_FID_CHG, 0x37, /* VGATE start */ |
390 | R_16_VGATE_STOP, 0x16, | |
391 | R_17_MISC_VGATE_CONF_AND_MSB, 0x99, | |
e19b2fcc | 392 | |
96ecfc4e MCC |
393 | R_08_SYNC_CNTL, 0x28, /* 0x28 = PAL */ |
394 | R_0E_CHROMA_CNTL_1, 0x07, | |
e19b2fcc | 395 | |
96ecfc4e | 396 | R_5A_V_OFF_FOR_SLICER, 0x03, /* standard 50hz value */ |
e19b2fcc HV |
397 | |
398 | /* Task A */ | |
96ecfc4e MCC |
399 | R_90_A_TASK_HANDLING_CNTL, 0x81, |
400 | R_91_A_X_PORT_FORMATS_AND_CONF, 0x48, | |
401 | R_92_A_X_PORT_INPUT_REFERENCE_SIGNAL, 0x40, | |
402 | R_93_A_I_PORT_OUTPUT_FORMATS_AND_CONF, 0x84, | |
403 | ||
e19b2fcc HV |
404 | /* This is weird: the datasheet says that you should use 2 as the minimum value, */ |
405 | /* but Hauppauge uses 0, and changing that to 2 causes indeed problems (for 50hz) */ | |
96ecfc4e MCC |
406 | /* hoffset low (input), 0x0002 is minimum */ |
407 | R_94_A_HORIZ_INPUT_WINDOW_START, 0x00, | |
408 | R_95_A_HORIZ_INPUT_WINDOW_START_MSB, 0x00, | |
409 | ||
410 | /* hsize low (input), 0x02d0 = 720 */ | |
411 | R_96_A_HORIZ_INPUT_WINDOW_LENGTH, 0xd0, | |
412 | R_97_A_HORIZ_INPUT_WINDOW_LENGTH_MSB, 0x02, | |
413 | ||
414 | R_98_A_VERT_INPUT_WINDOW_START, 0x03, | |
415 | R_99_A_VERT_INPUT_WINDOW_START_MSB, 0x00, | |
416 | ||
417 | /* vsize 0x12 = 18 */ | |
418 | R_9A_A_VERT_INPUT_WINDOW_LENGTH, 0x12, | |
419 | R_9B_A_VERT_INPUT_WINDOW_LENGTH_MSB, 0x00, | |
420 | ||
421 | /* hsize 0x05a0 = 1440 */ | |
422 | R_9C_A_HORIZ_OUTPUT_WINDOW_LENGTH, 0xa0, | |
423 | R_9D_A_HORIZ_OUTPUT_WINDOW_LENGTH_MSB, 0x05, /* hsize hi (output) */ | |
424 | R_9E_A_VERT_OUTPUT_WINDOW_LENGTH, 0x12, /* vsize low (output), 0x12 = 18 */ | |
425 | R_9F_A_VERT_OUTPUT_WINDOW_LENGTH_MSB, 0x00, /* vsize hi (output) */ | |
e19b2fcc HV |
426 | |
427 | /* Task B */ | |
96ecfc4e MCC |
428 | R_C0_B_TASK_HANDLING_CNTL, 0x00, |
429 | R_C1_B_X_PORT_FORMATS_AND_CONF, 0x08, | |
430 | R_C2_B_INPUT_REFERENCE_SIGNAL_DEFINITION, 0x00, | |
431 | R_C3_B_I_PORT_FORMATS_AND_CONF, 0x80, | |
432 | ||
433 | /* This is weird: the datasheet says that you should use 2 as the minimum value, */ | |
434 | /* but Hauppauge uses 0, and changing that to 2 causes indeed problems (for 50hz) */ | |
435 | /* hoffset low (input), 0x0002 is minimum. See comment above. */ | |
436 | R_C4_B_HORIZ_INPUT_WINDOW_START, 0x00, | |
437 | R_C5_B_HORIZ_INPUT_WINDOW_START_MSB, 0x00, | |
438 | ||
439 | /* hsize 0x02d0 = 720 */ | |
440 | R_C6_B_HORIZ_INPUT_WINDOW_LENGTH, 0xd0, | |
441 | R_C7_B_HORIZ_INPUT_WINDOW_LENGTH_MSB, 0x02, | |
442 | ||
443 | /* voffset 0x16 = 22 */ | |
444 | R_C8_B_VERT_INPUT_WINDOW_START, 0x16, | |
445 | R_C9_B_VERT_INPUT_WINDOW_START_MSB, 0x00, | |
446 | ||
447 | /* vsize 0x0120 = 288 */ | |
448 | R_CA_B_VERT_INPUT_WINDOW_LENGTH, 0x20, | |
449 | R_CB_B_VERT_INPUT_WINDOW_LENGTH_MSB, 0x01, | |
450 | ||
451 | /* hsize 0x02d0 = 720 */ | |
452 | R_CC_B_HORIZ_OUTPUT_WINDOW_LENGTH, 0xd0, | |
453 | R_CD_B_HORIZ_OUTPUT_WINDOW_LENGTH_MSB, 0x02, | |
454 | ||
96ecfc4e MCC |
455 | R_F0_LFCO_PER_LINE, 0xb0, /* Set PLL Register. 50hz 625 lines per frame, 27 MHz */ |
456 | R_F1_P_I_PARAM_SELECT, 0x05, /* low bit with 0xF0, (was 0x05) */ | |
457 | R_F5_PULSGEN_LINE_LENGTH, 0xb0, | |
458 | R_F6_PULSE_A_POS_LSB_AND_PULSEGEN_CONFIG, 0x01, | |
459 | ||
e19b2fcc HV |
460 | 0x00, 0x00 |
461 | }; | |
462 | ||
463 | /* ============== SAA7715 VIDEO templates (end) ======= */ | |
464 | ||
241d89fc JAJ |
465 | /* ============== GM7113C VIDEO templates ============= */ |
466 | static const unsigned char gm7113c_cfg_60hz_video[] = { | |
467 | R_08_SYNC_CNTL, 0x68, /* 0xBO: auto detection, 0x68 = NTSC */ | |
468 | R_0E_CHROMA_CNTL_1, 0x07, /* video autodetection is on */ | |
469 | ||
470 | 0x00, 0x00 | |
471 | }; | |
472 | ||
473 | static const unsigned char gm7113c_cfg_50hz_video[] = { | |
474 | R_08_SYNC_CNTL, 0x28, /* 0x28 = PAL */ | |
475 | R_0E_CHROMA_CNTL_1, 0x07, | |
476 | ||
477 | 0x00, 0x00 | |
478 | }; | |
479 | ||
480 | /* ============== GM7113C VIDEO templates (end) ======= */ | |
481 | ||
482 | ||
e19b2fcc | 483 | static const unsigned char saa7115_cfg_vbi_on[] = { |
96ecfc4e MCC |
484 | R_80_GLOBAL_CNTL_1, 0x00, /* reset tasks */ |
485 | R_88_POWER_SAVE_ADC_PORT_CNTL, 0xd0, /* reset scaler */ | |
486 | R_80_GLOBAL_CNTL_1, 0x30, /* Activate both tasks */ | |
487 | R_88_POWER_SAVE_ADC_PORT_CNTL, 0xf0, /* activate scaler */ | |
488 | R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED, 0x01, /* Enable I-port output */ | |
489 | ||
e19b2fcc HV |
490 | 0x00, 0x00 |
491 | }; | |
492 | ||
493 | static const unsigned char saa7115_cfg_vbi_off[] = { | |
96ecfc4e MCC |
494 | R_80_GLOBAL_CNTL_1, 0x00, /* reset tasks */ |
495 | R_88_POWER_SAVE_ADC_PORT_CNTL, 0xd0, /* reset scaler */ | |
496 | R_80_GLOBAL_CNTL_1, 0x20, /* Activate only task "B" */ | |
497 | R_88_POWER_SAVE_ADC_PORT_CNTL, 0xf0, /* activate scaler */ | |
498 | R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED, 0x01, /* Enable I-port output */ | |
499 | ||
e19b2fcc HV |
500 | 0x00, 0x00 |
501 | }; | |
502 | ||
f5762e44 | 503 | |
e19b2fcc | 504 | static const unsigned char saa7115_init_misc[] = { |
96ecfc4e | 505 | R_81_V_SYNC_FLD_ID_SRC_SEL_AND_RETIMED_V_F, 0x01, |
96ecfc4e MCC |
506 | R_83_X_PORT_I_O_ENA_AND_OUT_CLK, 0x01, |
507 | R_84_I_PORT_SIGNAL_DEF, 0x20, | |
508 | R_85_I_PORT_SIGNAL_POLAR, 0x21, | |
509 | R_86_I_PORT_FIFO_FLAG_CNTL_AND_ARBIT, 0xc5, | |
510 | R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED, 0x01, | |
e19b2fcc HV |
511 | |
512 | /* Task A */ | |
96ecfc4e MCC |
513 | R_A0_A_HORIZ_PRESCALING, 0x01, |
514 | R_A1_A_ACCUMULATION_LENGTH, 0x00, | |
515 | R_A2_A_PRESCALER_DC_GAIN_AND_FIR_PREFILTER, 0x00, | |
516 | ||
517 | /* Configure controls at nominal value*/ | |
518 | R_A4_A_LUMA_BRIGHTNESS_CNTL, 0x80, | |
519 | R_A5_A_LUMA_CONTRAST_CNTL, 0x40, | |
520 | R_A6_A_CHROMA_SATURATION_CNTL, 0x40, | |
521 | ||
522 | /* note: 2 x zoom ensures that VBI lines have same length as video lines. */ | |
523 | R_A8_A_HORIZ_LUMA_SCALING_INC, 0x00, | |
524 | R_A9_A_HORIZ_LUMA_SCALING_INC_MSB, 0x02, | |
525 | ||
526 | R_AA_A_HORIZ_LUMA_PHASE_OFF, 0x00, | |
527 | ||
528 | /* must be horiz lum scaling / 2 */ | |
529 | R_AC_A_HORIZ_CHROMA_SCALING_INC, 0x00, | |
530 | R_AD_A_HORIZ_CHROMA_SCALING_INC_MSB, 0x01, | |
531 | ||
532 | /* must be offset luma / 2 */ | |
533 | R_AE_A_HORIZ_CHROMA_PHASE_OFF, 0x00, | |
534 | ||
535 | R_B0_A_VERT_LUMA_SCALING_INC, 0x00, | |
536 | R_B1_A_VERT_LUMA_SCALING_INC_MSB, 0x04, | |
537 | ||
538 | R_B2_A_VERT_CHROMA_SCALING_INC, 0x00, | |
539 | R_B3_A_VERT_CHROMA_SCALING_INC_MSB, 0x04, | |
540 | ||
541 | R_B4_A_VERT_SCALING_MODE_CNTL, 0x01, | |
542 | ||
543 | R_B8_A_VERT_CHROMA_PHASE_OFF_00, 0x00, | |
544 | R_B9_A_VERT_CHROMA_PHASE_OFF_01, 0x00, | |
545 | R_BA_A_VERT_CHROMA_PHASE_OFF_10, 0x00, | |
546 | R_BB_A_VERT_CHROMA_PHASE_OFF_11, 0x00, | |
547 | ||
548 | R_BC_A_VERT_LUMA_PHASE_OFF_00, 0x00, | |
549 | R_BD_A_VERT_LUMA_PHASE_OFF_01, 0x00, | |
550 | R_BE_A_VERT_LUMA_PHASE_OFF_10, 0x00, | |
551 | R_BF_A_VERT_LUMA_PHASE_OFF_11, 0x00, | |
e19b2fcc HV |
552 | |
553 | /* Task B */ | |
96ecfc4e MCC |
554 | R_D0_B_HORIZ_PRESCALING, 0x01, |
555 | R_D1_B_ACCUMULATION_LENGTH, 0x00, | |
556 | R_D2_B_PRESCALER_DC_GAIN_AND_FIR_PREFILTER, 0x00, | |
557 | ||
558 | /* Configure controls at nominal value*/ | |
559 | R_D4_B_LUMA_BRIGHTNESS_CNTL, 0x80, | |
560 | R_D5_B_LUMA_CONTRAST_CNTL, 0x40, | |
561 | R_D6_B_CHROMA_SATURATION_CNTL, 0x40, | |
562 | ||
563 | /* hor lum scaling 0x0400 = 1 */ | |
564 | R_D8_B_HORIZ_LUMA_SCALING_INC, 0x00, | |
565 | R_D9_B_HORIZ_LUMA_SCALING_INC_MSB, 0x04, | |
566 | ||
567 | R_DA_B_HORIZ_LUMA_PHASE_OFF, 0x00, | |
568 | ||
569 | /* must be hor lum scaling / 2 */ | |
570 | R_DC_B_HORIZ_CHROMA_SCALING, 0x00, | |
571 | R_DD_B_HORIZ_CHROMA_SCALING_MSB, 0x02, | |
572 | ||
573 | /* must be offset luma / 2 */ | |
574 | R_DE_B_HORIZ_PHASE_OFFSET_CRHOMA, 0x00, | |
575 | ||
576 | R_E0_B_VERT_LUMA_SCALING_INC, 0x00, | |
577 | R_E1_B_VERT_LUMA_SCALING_INC_MSB, 0x04, | |
578 | ||
579 | R_E2_B_VERT_CHROMA_SCALING_INC, 0x00, | |
580 | R_E3_B_VERT_CHROMA_SCALING_INC_MSB, 0x04, | |
581 | ||
582 | R_E4_B_VERT_SCALING_MODE_CNTL, 0x01, | |
583 | ||
584 | R_E8_B_VERT_CHROMA_PHASE_OFF_00, 0x00, | |
585 | R_E9_B_VERT_CHROMA_PHASE_OFF_01, 0x00, | |
586 | R_EA_B_VERT_CHROMA_PHASE_OFF_10, 0x00, | |
587 | R_EB_B_VERT_CHROMA_PHASE_OFF_11, 0x00, | |
588 | ||
589 | R_EC_B_VERT_LUMA_PHASE_OFF_00, 0x00, | |
590 | R_ED_B_VERT_LUMA_PHASE_OFF_01, 0x00, | |
591 | R_EE_B_VERT_LUMA_PHASE_OFF_10, 0x00, | |
592 | R_EF_B_VERT_LUMA_PHASE_OFF_11, 0x00, | |
593 | ||
594 | R_F2_NOMINAL_PLL2_DTO, 0x50, /* crystal clock = 24.576 MHz, target = 27MHz */ | |
595 | R_F3_PLL_INCREMENT, 0x46, | |
596 | R_F4_PLL2_STATUS, 0x00, | |
597 | R_F7_PULSE_A_POS_MSB, 0x4b, /* not the recommended settings! */ | |
598 | R_F8_PULSE_B_POS, 0x00, | |
599 | R_F9_PULSE_B_POS_MSB, 0x4b, | |
600 | R_FA_PULSE_C_POS, 0x00, | |
601 | R_FB_PULSE_C_POS_MSB, 0x4b, | |
602 | ||
603 | /* PLL2 lock detection settings: 71 lines 50% phase error */ | |
604 | R_FF_S_PLL_MAX_PHASE_ERR_THRESH_NUM_LINES, 0x88, | |
e19b2fcc HV |
605 | |
606 | /* Turn off VBI */ | |
96ecfc4e MCC |
607 | R_40_SLICER_CNTL_1, 0x20, /* No framing code errors allowed. */ |
608 | R_41_LCR_BASE, 0xff, | |
609 | R_41_LCR_BASE+1, 0xff, | |
610 | R_41_LCR_BASE+2, 0xff, | |
611 | R_41_LCR_BASE+3, 0xff, | |
612 | R_41_LCR_BASE+4, 0xff, | |
613 | R_41_LCR_BASE+5, 0xff, | |
614 | R_41_LCR_BASE+6, 0xff, | |
615 | R_41_LCR_BASE+7, 0xff, | |
616 | R_41_LCR_BASE+8, 0xff, | |
617 | R_41_LCR_BASE+9, 0xff, | |
618 | R_41_LCR_BASE+10, 0xff, | |
619 | R_41_LCR_BASE+11, 0xff, | |
620 | R_41_LCR_BASE+12, 0xff, | |
621 | R_41_LCR_BASE+13, 0xff, | |
622 | R_41_LCR_BASE+14, 0xff, | |
623 | R_41_LCR_BASE+15, 0xff, | |
624 | R_41_LCR_BASE+16, 0xff, | |
625 | R_41_LCR_BASE+17, 0xff, | |
626 | R_41_LCR_BASE+18, 0xff, | |
627 | R_41_LCR_BASE+19, 0xff, | |
628 | R_41_LCR_BASE+20, 0xff, | |
629 | R_41_LCR_BASE+21, 0xff, | |
630 | R_41_LCR_BASE+22, 0xff, | |
631 | R_58_PROGRAM_FRAMING_CODE, 0x40, | |
632 | R_59_H_OFF_FOR_SLICER, 0x47, | |
633 | R_5B_FLD_OFF_AND_MSB_FOR_H_AND_V_OFF, 0x83, | |
634 | R_5D_DID, 0xbd, | |
635 | R_5E_SDID, 0x35, | |
636 | ||
fea551fa | 637 | R_02_INPUT_CNTL_1, 0xc4, /* input tuner -> input 4, amplifier active */ |
96ecfc4e MCC |
638 | |
639 | R_80_GLOBAL_CNTL_1, 0x20, /* enable task B */ | |
640 | R_88_POWER_SAVE_ADC_PORT_CNTL, 0xd0, | |
641 | R_88_POWER_SAVE_ADC_PORT_CNTL, 0xf0, | |
e19b2fcc HV |
642 | 0x00, 0x00 |
643 | }; | |
644 | ||
66ec1193 | 645 | static int saa711x_odd_parity(u8 c) |
e19b2fcc HV |
646 | { |
647 | c ^= (c >> 4); | |
648 | c ^= (c >> 2); | |
649 | c ^= (c >> 1); | |
650 | ||
651 | return c & 1; | |
652 | } | |
653 | ||
9415f4b2 | 654 | static int saa711x_decode_vps(u8 *dst, u8 *p) |
e19b2fcc HV |
655 | { |
656 | static const u8 biphase_tbl[] = { | |
657 | 0xf0, 0x78, 0x70, 0xf0, 0xb4, 0x3c, 0x34, 0xb4, | |
658 | 0xb0, 0x38, 0x30, 0xb0, 0xf0, 0x78, 0x70, 0xf0, | |
659 | 0xd2, 0x5a, 0x52, 0xd2, 0x96, 0x1e, 0x16, 0x96, | |
660 | 0x92, 0x1a, 0x12, 0x92, 0xd2, 0x5a, 0x52, 0xd2, | |
661 | 0xd0, 0x58, 0x50, 0xd0, 0x94, 0x1c, 0x14, 0x94, | |
662 | 0x90, 0x18, 0x10, 0x90, 0xd0, 0x58, 0x50, 0xd0, | |
663 | 0xf0, 0x78, 0x70, 0xf0, 0xb4, 0x3c, 0x34, 0xb4, | |
664 | 0xb0, 0x38, 0x30, 0xb0, 0xf0, 0x78, 0x70, 0xf0, | |
665 | 0xe1, 0x69, 0x61, 0xe1, 0xa5, 0x2d, 0x25, 0xa5, | |
666 | 0xa1, 0x29, 0x21, 0xa1, 0xe1, 0x69, 0x61, 0xe1, | |
667 | 0xc3, 0x4b, 0x43, 0xc3, 0x87, 0x0f, 0x07, 0x87, | |
668 | 0x83, 0x0b, 0x03, 0x83, 0xc3, 0x4b, 0x43, 0xc3, | |
669 | 0xc1, 0x49, 0x41, 0xc1, 0x85, 0x0d, 0x05, 0x85, | |
670 | 0x81, 0x09, 0x01, 0x81, 0xc1, 0x49, 0x41, 0xc1, | |
671 | 0xe1, 0x69, 0x61, 0xe1, 0xa5, 0x2d, 0x25, 0xa5, | |
672 | 0xa1, 0x29, 0x21, 0xa1, 0xe1, 0x69, 0x61, 0xe1, | |
673 | 0xe0, 0x68, 0x60, 0xe0, 0xa4, 0x2c, 0x24, 0xa4, | |
674 | 0xa0, 0x28, 0x20, 0xa0, 0xe0, 0x68, 0x60, 0xe0, | |
675 | 0xc2, 0x4a, 0x42, 0xc2, 0x86, 0x0e, 0x06, 0x86, | |
676 | 0x82, 0x0a, 0x02, 0x82, 0xc2, 0x4a, 0x42, 0xc2, | |
677 | 0xc0, 0x48, 0x40, 0xc0, 0x84, 0x0c, 0x04, 0x84, | |
678 | 0x80, 0x08, 0x00, 0x80, 0xc0, 0x48, 0x40, 0xc0, | |
679 | 0xe0, 0x68, 0x60, 0xe0, 0xa4, 0x2c, 0x24, 0xa4, | |
680 | 0xa0, 0x28, 0x20, 0xa0, 0xe0, 0x68, 0x60, 0xe0, | |
681 | 0xf0, 0x78, 0x70, 0xf0, 0xb4, 0x3c, 0x34, 0xb4, | |
682 | 0xb0, 0x38, 0x30, 0xb0, 0xf0, 0x78, 0x70, 0xf0, | |
683 | 0xd2, 0x5a, 0x52, 0xd2, 0x96, 0x1e, 0x16, 0x96, | |
684 | 0x92, 0x1a, 0x12, 0x92, 0xd2, 0x5a, 0x52, 0xd2, | |
685 | 0xd0, 0x58, 0x50, 0xd0, 0x94, 0x1c, 0x14, 0x94, | |
686 | 0x90, 0x18, 0x10, 0x90, 0xd0, 0x58, 0x50, 0xd0, | |
687 | 0xf0, 0x78, 0x70, 0xf0, 0xb4, 0x3c, 0x34, 0xb4, | |
688 | 0xb0, 0x38, 0x30, 0xb0, 0xf0, 0x78, 0x70, 0xf0, | |
689 | }; | |
690 | int i; | |
691 | u8 c, err = 0; | |
692 | ||
693 | for (i = 0; i < 2 * 13; i += 2) { | |
694 | err |= biphase_tbl[p[i]] | biphase_tbl[p[i + 1]]; | |
695 | c = (biphase_tbl[p[i + 1]] & 0xf) | ((biphase_tbl[p[i]] & 0xf) << 4); | |
696 | dst[i / 2] = c; | |
697 | } | |
698 | return err & 0xf0; | |
699 | } | |
700 | ||
9415f4b2 | 701 | static int saa711x_decode_wss(u8 *p) |
e19b2fcc HV |
702 | { |
703 | static const int wss_bits[8] = { | |
704 | 0, 0, 0, 1, 0, 1, 1, 1 | |
705 | }; | |
706 | unsigned char parity; | |
707 | int wss = 0; | |
708 | int i; | |
709 | ||
710 | for (i = 0; i < 16; i++) { | |
711 | int b1 = wss_bits[p[i] & 7]; | |
712 | int b2 = wss_bits[(p[i] >> 3) & 7]; | |
713 | ||
714 | if (b1 == b2) | |
715 | return -1; | |
716 | wss |= b2 << i; | |
717 | } | |
718 | parity = wss & 15; | |
719 | parity ^= parity >> 2; | |
720 | parity ^= parity >> 1; | |
721 | ||
722 | if (!(parity & 1)) | |
723 | return -1; | |
724 | ||
725 | return wss; | |
726 | } | |
727 | ||
9415f4b2 | 728 | static int saa711x_s_clock_freq(struct v4l2_subdev *sd, u32 freq) |
e19b2fcc | 729 | { |
9415f4b2 | 730 | struct saa711x_state *state = to_state(sd); |
3578d3dd HV |
731 | u32 acpf; |
732 | u32 acni; | |
733 | u32 hz; | |
734 | u64 f; | |
b7f8292c | 735 | u8 acc = 0; /* reg 0x3a, audio clock control */ |
e19b2fcc | 736 | |
89f75ffc | 737 | /* Checks for chips that don't have audio clock (saa7111, saa7113) */ |
9415f4b2 | 738 | if (!saa711x_has_reg(state->ident, R_30_AUD_MAST_CLK_CYCLES_PER_FIELD)) |
89f75ffc MCC |
739 | return 0; |
740 | ||
9415f4b2 | 741 | v4l2_dbg(1, debug, sd, "set audio clock freq: %d\n", freq); |
3578d3dd HV |
742 | |
743 | /* sanity check */ | |
744 | if (freq < 32000 || freq > 48000) | |
745 | return -EINVAL; | |
746 | ||
747 | /* hz is the refresh rate times 100 */ | |
748 | hz = (state->std & V4L2_STD_525_60) ? 5994 : 5000; | |
749 | /* acpf = (256 * freq) / field_frequency == (256 * 100 * freq) / hz */ | |
750 | acpf = (25600 * freq) / hz; | |
751 | /* acni = (256 * freq * 2^23) / crystal_frequency = | |
752 | (freq * 2^(8+23)) / crystal_frequency = | |
b7f8292c | 753 | (freq << 31) / crystal_frequency */ |
3578d3dd HV |
754 | f = freq; |
755 | f = f << 31; | |
b7f8292c | 756 | do_div(f, state->crystal_freq); |
3578d3dd | 757 | acni = f; |
b7f8292c HV |
758 | if (state->ucgc) { |
759 | acpf = acpf * state->cgcdiv / 16; | |
760 | acni = acni * state->cgcdiv / 16; | |
761 | acc = 0x80; | |
762 | if (state->cgcdiv == 3) | |
763 | acc |= 0x40; | |
764 | } | |
765 | if (state->apll) | |
766 | acc |= 0x08; | |
3578d3dd | 767 | |
1589037f HV |
768 | if (state->double_asclk) { |
769 | acpf <<= 1; | |
770 | acni <<= 1; | |
771 | } | |
9415f4b2 | 772 | saa711x_write(sd, R_38_CLK_RATIO_AMXCLK_TO_ASCLK, 0x03); |
1589037f | 773 | saa711x_write(sd, R_39_CLK_RATIO_ASCLK_TO_ALRCLK, 0x10 << state->double_asclk); |
9415f4b2 | 774 | saa711x_write(sd, R_3A_AUD_CLK_GEN_BASIC_SETUP, acc); |
96ecfc4e | 775 | |
9415f4b2 HV |
776 | saa711x_write(sd, R_30_AUD_MAST_CLK_CYCLES_PER_FIELD, acpf & 0xff); |
777 | saa711x_write(sd, R_30_AUD_MAST_CLK_CYCLES_PER_FIELD+1, | |
96ecfc4e | 778 | (acpf >> 8) & 0xff); |
9415f4b2 | 779 | saa711x_write(sd, R_30_AUD_MAST_CLK_CYCLES_PER_FIELD+2, |
96ecfc4e MCC |
780 | (acpf >> 16) & 0x03); |
781 | ||
9415f4b2 HV |
782 | saa711x_write(sd, R_34_AUD_MAST_CLK_NOMINAL_INC, acni & 0xff); |
783 | saa711x_write(sd, R_34_AUD_MAST_CLK_NOMINAL_INC+1, (acni >> 8) & 0xff); | |
784 | saa711x_write(sd, R_34_AUD_MAST_CLK_NOMINAL_INC+2, (acni >> 16) & 0x3f); | |
e19b2fcc HV |
785 | state->audclk_freq = freq; |
786 | return 0; | |
787 | } | |
788 | ||
e3560543 | 789 | static int saa711x_g_volatile_ctrl(struct v4l2_ctrl *ctrl) |
e19b2fcc | 790 | { |
e3560543 | 791 | struct v4l2_subdev *sd = to_sd(ctrl); |
9415f4b2 | 792 | struct saa711x_state *state = to_state(sd); |
e19b2fcc HV |
793 | |
794 | switch (ctrl->id) { | |
87a6fe4a | 795 | case V4L2_CID_CHROMA_AGC: |
e3560543 | 796 | /* chroma gain cluster */ |
ddac5c10 HV |
797 | if (state->agc->val) |
798 | state->gain->val = | |
e3560543 | 799 | saa711x_read(sd, R_0F_CHROMA_GAIN_CNTL) & 0x7f; |
87a6fe4a | 800 | break; |
e19b2fcc | 801 | } |
e19b2fcc HV |
802 | return 0; |
803 | } | |
804 | ||
e3560543 | 805 | static int saa711x_s_ctrl(struct v4l2_ctrl *ctrl) |
e19b2fcc | 806 | { |
e3560543 | 807 | struct v4l2_subdev *sd = to_sd(ctrl); |
9415f4b2 | 808 | struct saa711x_state *state = to_state(sd); |
e19b2fcc HV |
809 | |
810 | switch (ctrl->id) { | |
811 | case V4L2_CID_BRIGHTNESS: | |
e3560543 | 812 | saa711x_write(sd, R_0A_LUMA_BRIGHT_CNTL, ctrl->val); |
e19b2fcc | 813 | break; |
e3560543 | 814 | |
e19b2fcc | 815 | case V4L2_CID_CONTRAST: |
e3560543 | 816 | saa711x_write(sd, R_0B_LUMA_CONTRAST_CNTL, ctrl->val); |
e19b2fcc | 817 | break; |
e3560543 | 818 | |
e19b2fcc | 819 | case V4L2_CID_SATURATION: |
e3560543 | 820 | saa711x_write(sd, R_0C_CHROMA_SAT_CNTL, ctrl->val); |
e19b2fcc | 821 | break; |
e3560543 | 822 | |
e19b2fcc | 823 | case V4L2_CID_HUE: |
e3560543 | 824 | saa711x_write(sd, R_0D_CHROMA_HUE_CNTL, ctrl->val); |
e19b2fcc | 825 | break; |
e3560543 | 826 | |
87a6fe4a | 827 | case V4L2_CID_CHROMA_AGC: |
e3560543 HV |
828 | /* chroma gain cluster */ |
829 | if (state->agc->val) | |
830 | saa711x_write(sd, R_0F_CHROMA_GAIN_CNTL, state->gain->val); | |
831 | else | |
832 | saa711x_write(sd, R_0F_CHROMA_GAIN_CNTL, state->gain->val | 0x80); | |
87a6fe4a | 833 | break; |
e3560543 | 834 | |
e19b2fcc HV |
835 | default: |
836 | return -EINVAL; | |
837 | } | |
838 | ||
839 | return 0; | |
840 | } | |
841 | ||
9415f4b2 | 842 | static int saa711x_set_size(struct v4l2_subdev *sd, int width, int height) |
d9dce96f | 843 | { |
9415f4b2 | 844 | struct saa711x_state *state = to_state(sd); |
d9dce96f MCC |
845 | int HPSC, HFSC; |
846 | int VSCY; | |
847 | int res; | |
848 | int is_50hz = state->std & V4L2_STD_625_50; | |
849 | int Vsrc = is_50hz ? 576 : 480; | |
850 | ||
9415f4b2 | 851 | v4l2_dbg(1, debug, sd, "decoder set size to %ix%i\n", width, height); |
d9dce96f MCC |
852 | |
853 | /* FIXME need better bounds checking here */ | |
854 | if ((width < 1) || (width > 1440)) | |
855 | return -EINVAL; | |
856 | if ((height < 1) || (height > Vsrc)) | |
857 | return -EINVAL; | |
858 | ||
9415f4b2 | 859 | if (!saa711x_has_reg(state->ident, R_D0_B_HORIZ_PRESCALING)) { |
d9dce96f MCC |
860 | /* Decoder only supports 720 columns and 480 or 576 lines */ |
861 | if (width != 720) | |
862 | return -EINVAL; | |
863 | if (height != Vsrc) | |
864 | return -EINVAL; | |
865 | } | |
866 | ||
867 | state->width = width; | |
868 | state->height = height; | |
869 | ||
870 | if (!saa711x_has_reg(state->ident, R_CC_B_HORIZ_OUTPUT_WINDOW_LENGTH)) | |
871 | return 0; | |
872 | ||
873 | /* probably have a valid size, let's set it */ | |
874 | /* Set output width/height */ | |
875 | /* width */ | |
876 | ||
9415f4b2 | 877 | saa711x_write(sd, R_CC_B_HORIZ_OUTPUT_WINDOW_LENGTH, |
d9dce96f | 878 | (u8) (width & 0xff)); |
9415f4b2 | 879 | saa711x_write(sd, R_CD_B_HORIZ_OUTPUT_WINDOW_LENGTH_MSB, |
d9dce96f MCC |
880 | (u8) ((width >> 8) & 0xff)); |
881 | ||
882 | /* Vertical Scaling uses height/2 */ | |
9415f4b2 | 883 | res = height / 2; |
d9dce96f MCC |
884 | |
885 | /* On 60Hz, it is using a higher Vertical Output Size */ | |
886 | if (!is_50hz) | |
d0d30c03 | 887 | res += (VRES_60HZ - 480) >> 1; |
d9dce96f MCC |
888 | |
889 | /* height */ | |
9415f4b2 | 890 | saa711x_write(sd, R_CE_B_VERT_OUTPUT_WINDOW_LENGTH, |
d9dce96f | 891 | (u8) (res & 0xff)); |
9415f4b2 | 892 | saa711x_write(sd, R_CF_B_VERT_OUTPUT_WINDOW_LENGTH_MSB, |
d9dce96f MCC |
893 | (u8) ((res >> 8) & 0xff)); |
894 | ||
895 | /* Scaling settings */ | |
896 | /* Hprescaler is floor(inres/outres) */ | |
897 | HPSC = (int)(720 / width); | |
898 | /* 0 is not allowed (div. by zero) */ | |
899 | HPSC = HPSC ? HPSC : 1; | |
900 | HFSC = (int)((1024 * 720) / (HPSC * width)); | |
901 | /* FIXME hardcodes to "Task B" | |
902 | * write H prescaler integer */ | |
9415f4b2 | 903 | saa711x_write(sd, R_D0_B_HORIZ_PRESCALING, |
d9dce96f MCC |
904 | (u8) (HPSC & 0x3f)); |
905 | ||
9415f4b2 | 906 | v4l2_dbg(1, debug, sd, "Hpsc: 0x%05x, Hfsc: 0x%05x\n", HPSC, HFSC); |
d9dce96f | 907 | /* write H fine-scaling (luminance) */ |
9415f4b2 | 908 | saa711x_write(sd, R_D8_B_HORIZ_LUMA_SCALING_INC, |
d9dce96f | 909 | (u8) (HFSC & 0xff)); |
9415f4b2 | 910 | saa711x_write(sd, R_D9_B_HORIZ_LUMA_SCALING_INC_MSB, |
d9dce96f MCC |
911 | (u8) ((HFSC >> 8) & 0xff)); |
912 | /* write H fine-scaling (chrominance) | |
913 | * must be lum/2, so i'll just bitshift :) */ | |
9415f4b2 | 914 | saa711x_write(sd, R_DC_B_HORIZ_CHROMA_SCALING, |
d9dce96f | 915 | (u8) ((HFSC >> 1) & 0xff)); |
9415f4b2 | 916 | saa711x_write(sd, R_DD_B_HORIZ_CHROMA_SCALING_MSB, |
d9dce96f MCC |
917 | (u8) ((HFSC >> 9) & 0xff)); |
918 | ||
919 | VSCY = (int)((1024 * Vsrc) / height); | |
9415f4b2 | 920 | v4l2_dbg(1, debug, sd, "Vsrc: %d, Vscy: 0x%05x\n", Vsrc, VSCY); |
d9dce96f MCC |
921 | |
922 | /* Correct Contrast and Luminance */ | |
9415f4b2 | 923 | saa711x_write(sd, R_D5_B_LUMA_CONTRAST_CNTL, |
d9dce96f | 924 | (u8) (64 * 1024 / VSCY)); |
9415f4b2 | 925 | saa711x_write(sd, R_D6_B_CHROMA_SATURATION_CNTL, |
d9dce96f MCC |
926 | (u8) (64 * 1024 / VSCY)); |
927 | ||
928 | /* write V fine-scaling (luminance) */ | |
9415f4b2 | 929 | saa711x_write(sd, R_E0_B_VERT_LUMA_SCALING_INC, |
d9dce96f | 930 | (u8) (VSCY & 0xff)); |
9415f4b2 | 931 | saa711x_write(sd, R_E1_B_VERT_LUMA_SCALING_INC_MSB, |
d9dce96f MCC |
932 | (u8) ((VSCY >> 8) & 0xff)); |
933 | /* write V fine-scaling (chrominance) */ | |
9415f4b2 | 934 | saa711x_write(sd, R_E2_B_VERT_CHROMA_SCALING_INC, |
d9dce96f | 935 | (u8) (VSCY & 0xff)); |
9415f4b2 | 936 | saa711x_write(sd, R_E3_B_VERT_CHROMA_SCALING_INC_MSB, |
d9dce96f MCC |
937 | (u8) ((VSCY >> 8) & 0xff)); |
938 | ||
9415f4b2 | 939 | saa711x_writeregs(sd, saa7115_cfg_reset_scaler); |
d9dce96f MCC |
940 | |
941 | /* Activates task "B" */ | |
9415f4b2 HV |
942 | saa711x_write(sd, R_80_GLOBAL_CNTL_1, |
943 | saa711x_read(sd, R_80_GLOBAL_CNTL_1) | 0x20); | |
d9dce96f MCC |
944 | |
945 | return 0; | |
946 | } | |
947 | ||
9415f4b2 | 948 | static void saa711x_set_v4lstd(struct v4l2_subdev *sd, v4l2_std_id std) |
e19b2fcc | 949 | { |
9415f4b2 | 950 | struct saa711x_state *state = to_state(sd); |
e19b2fcc | 951 | |
30b54d50 HV |
952 | /* Prevent unnecessary standard changes. During a standard |
953 | change the I-Port is temporarily disabled. Any devices | |
954 | reading from that port can get confused. | |
bccfa449 HV |
955 | Note that s_std is also used to switch from |
956 | radio to TV mode, so if a s_std is broadcast to | |
30b54d50 HV |
957 | all I2C devices then you do not want to have an unwanted |
958 | side-effect here. */ | |
959 | if (std == state->std) | |
960 | return; | |
961 | ||
d9dce96f MCC |
962 | state->std = std; |
963 | ||
e19b2fcc HV |
964 | // This works for NTSC-M, SECAM-L and the 50Hz PAL variants. |
965 | if (std & V4L2_STD_525_60) { | |
9415f4b2 | 966 | v4l2_dbg(1, debug, sd, "decoder set standard 60 Hz\n"); |
e1277110 | 967 | if (state->ident == GM7113C) |
241d89fc JAJ |
968 | saa711x_writeregs(sd, gm7113c_cfg_60hz_video); |
969 | else | |
970 | saa711x_writeregs(sd, saa7115_cfg_60hz_video); | |
9415f4b2 | 971 | saa711x_set_size(sd, 720, 480); |
e19b2fcc | 972 | } else { |
9415f4b2 | 973 | v4l2_dbg(1, debug, sd, "decoder set standard 50 Hz\n"); |
e1277110 | 974 | if (state->ident == GM7113C) |
241d89fc JAJ |
975 | saa711x_writeregs(sd, gm7113c_cfg_50hz_video); |
976 | else | |
977 | saa711x_writeregs(sd, saa7115_cfg_50hz_video); | |
9415f4b2 | 978 | saa711x_set_size(sd, 720, 576); |
e19b2fcc HV |
979 | } |
980 | ||
f89982a9 | 981 | /* Register 0E - Bits D6-D4 on NO-AUTO mode |
89f75ffc | 982 | (SAA7111 and SAA7113 doesn't have auto mode) |
f89982a9 MCC |
983 | 50 Hz / 625 lines 60 Hz / 525 lines |
984 | 000 PAL BGDHI (4.43Mhz) NTSC M (3.58MHz) | |
985 | 001 NTSC 4.43 (50 Hz) PAL 4.43 (60 Hz) | |
986 | 010 Combination-PAL N (3.58MHz) NTSC 4.43 (60 Hz) | |
987 | 011 NTSC N (3.58MHz) PAL M (3.58MHz) | |
988 | 100 reserved NTSC-Japan (3.58MHz) | |
989 | */ | |
e1277110 HV |
990 | if (state->ident <= SAA7113 || |
991 | state->ident == GM7113C) { | |
9415f4b2 | 992 | u8 reg = saa711x_read(sd, R_0E_CHROMA_CNTL_1) & 0x8f; |
f89982a9 | 993 | |
02c17224 | 994 | if (std == V4L2_STD_PAL_M) { |
01342358 | 995 | reg |= 0x30; |
e0028027 | 996 | } else if (std == V4L2_STD_PAL_Nc) { |
01342358 | 997 | reg |= 0x20; |
02c17224 | 998 | } else if (std == V4L2_STD_PAL_60) { |
01342358 | 999 | reg |= 0x10; |
02c17224 | 1000 | } else if (std == V4L2_STD_NTSC_M_JP) { |
01342358 | 1001 | reg |= 0x40; |
a9aaec4e | 1002 | } else if (std & V4L2_STD_SECAM) { |