]> git.proxmox.com Git - mirror_ubuntu-bionic-kernel.git/blame - drivers/media/i2c/saa7127.c
projects / mirror_ubuntu-bionic-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/mszeredi...
[mirror_ubuntu-bionic-kernel.git] / drivers / media / i2c / saa7127.c
CommitLineData
cfbb5b8c
HV		 1/*
2 * saa7127 - Philips SAA7127/SAA7129 video encoder driver
3 *
4 * Copyright (C) 2003 Roy Bulter <rbulter@hetnet.nl>
5 *
6 * Based on SAA7126 video encoder driver by Gillem & Andreas Oberritter
7 *
8 * Copyright (C) 2000-2001 Gillem <htoa@gmx.net>
9 * Copyright (C) 2002 Andreas Oberritter <obi@saftware.de>
10 *
11 * Based on Stadis 4:2:2 MPEG-2 Decoder Driver by Nathan Laredo
12 *
13 * Copyright (C) 1999 Nathan Laredo <laredo@gnu.org>
14 *
15 * This driver is designed for the Hauppauge 250/350 Linux driver
16 * from the ivtv Project
17 *
18 * Copyright (C) 2003 Kevin Thayer <nufan_wfk@yahoo.com>
19 *
20 * Dual output support:
21 * Copyright (C) 2004 Eric Varsanyi
22 *
23 * NTSC Tuning and 7.5 IRE Setup
24 * Copyright (C) 2004 Chris Kennedy <c@groovy.org>
25 *
26 * VBI additions & cleanup:
27 * Copyright (C) 2004, 2005 Hans Verkuil <hverkuil@xs4all.nl>
28 *
29 * Note: the saa7126 is identical to the saa7127, and the saa7128 is
30 * identical to the saa7129, except that the saa7126 and saa7128 have
31 * macrovision anti-taping support. This driver will almost certainly
2a1d245b 32 * work fine for those chips, except of course for the missing anti-taping
cfbb5b8c
HV		 33 * support.
34 *
35 * This program is free software; you can redistribute it and/or modify
36 * it under the terms of the GNU General Public License as published by
37 * the Free Software Foundation; either version 2 of the License, or
38 * (at your option) any later version.
39 *
40 * This program is distributed in the hope that it will be useful,
41 * but WITHOUT ANY WARRANTY; without even the implied warranty of
42 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
43 * GNU General Public License for more details.
44 *
45 * You should have received a copy of the GNU General Public License
46 * along with this program; if not, write to the Free Software
47 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
48 */
49
50
51#include <linux/kernel.h>
52#include <linux/module.h>
53#include <linux/slab.h>
54#include <linux/i2c.h>
55#include <linux/videodev2.h>
627426c6 56#include <media/v4l2-device.h>
39b6f687 57#include <media/saa7127.h>
cfbb5b8c 58
9fad368b
HV		 59static int debug;
60static int test_image;
cfbb5b8c
HV		 61
62MODULE_DESCRIPTION("Philips SAA7127/9 video encoder driver");
1f4b3365 63MODULE_AUTHOR("Kevin Thayer, Chris Kennedy, Hans Verkuil");
cfbb5b8c
HV		 64MODULE_LICENSE("GPL");
65module_param(debug, int, 0644);
66module_param(test_image, int, 0644);
67MODULE_PARM_DESC(debug, "debug level (0-2)");
68MODULE_PARM_DESC(test_image, "test_image (0-1)");
69
cfbb5b8c
HV		 70
71/*
72 * SAA7127 registers
73 */
74
75#define SAA7127_REG_STATUS 0x00
76#define SAA7127_REG_WIDESCREEN_CONFIG 0x26
77#define SAA7127_REG_WIDESCREEN_ENABLE 0x27
78#define SAA7127_REG_BURST_START 0x28
79#define SAA7127_REG_BURST_END 0x29
80#define SAA7127_REG_COPYGEN_0 0x2a
81#define SAA7127_REG_COPYGEN_1 0x2b
82#define SAA7127_REG_COPYGEN_2 0x2c
83#define SAA7127_REG_OUTPUT_PORT_CONTROL 0x2d
84#define SAA7127_REG_GAIN_LUMINANCE_RGB 0x38
85#define SAA7127_REG_GAIN_COLORDIFF_RGB 0x39
86#define SAA7127_REG_INPUT_PORT_CONTROL_1 0x3a
87#define SAA7129_REG_FADE_KEY_COL2 0x4f
88#define SAA7127_REG_CHROMA_PHASE 0x5a
89#define SAA7127_REG_GAINU 0x5b
90#define SAA7127_REG_GAINV 0x5c
91#define SAA7127_REG_BLACK_LEVEL 0x5d
92#define SAA7127_REG_BLANKING_LEVEL 0x5e
93#define SAA7127_REG_VBI_BLANKING 0x5f
94#define SAA7127_REG_DAC_CONTROL 0x61
95#define SAA7127_REG_BURST_AMP 0x62
96#define SAA7127_REG_SUBC3 0x63
97#define SAA7127_REG_SUBC2 0x64
98#define SAA7127_REG_SUBC1 0x65
99#define SAA7127_REG_SUBC0 0x66
100#define SAA7127_REG_LINE_21_ODD_0 0x67
101#define SAA7127_REG_LINE_21_ODD_1 0x68
102#define SAA7127_REG_LINE_21_EVEN_0 0x69
103#define SAA7127_REG_LINE_21_EVEN_1 0x6a
104#define SAA7127_REG_RCV_PORT_CONTROL 0x6b
105#define SAA7127_REG_VTRIG 0x6c
106#define SAA7127_REG_HTRIG_HI 0x6d
107#define SAA7127_REG_MULTI 0x6e
108#define SAA7127_REG_CLOSED_CAPTION 0x6f
109#define SAA7127_REG_RCV2_OUTPUT_START 0x70
110#define SAA7127_REG_RCV2_OUTPUT_END 0x71
111#define SAA7127_REG_RCV2_OUTPUT_MSBS 0x72
112#define SAA7127_REG_TTX_REQUEST_H_START 0x73
113#define SAA7127_REG_TTX_REQUEST_H_DELAY_LENGTH 0x74
114#define SAA7127_REG_CSYNC_ADVANCE_VSYNC_SHIFT 0x75
115#define SAA7127_REG_TTX_ODD_REQ_VERT_START 0x76
116#define SAA7127_REG_TTX_ODD_REQ_VERT_END 0x77
117#define SAA7127_REG_TTX_EVEN_REQ_VERT_START 0x78
118#define SAA7127_REG_TTX_EVEN_REQ_VERT_END 0x79
119#define SAA7127_REG_FIRST_ACTIVE 0x7a
120#define SAA7127_REG_LAST_ACTIVE 0x7b
121#define SAA7127_REG_MSB_VERTICAL 0x7c
122#define SAA7127_REG_DISABLE_TTX_LINE_LO_0 0x7e
123#define SAA7127_REG_DISABLE_TTX_LINE_LO_1 0x7f
124
125/*
126 **********************************************************************
127 *
128 * Arrays with configuration parameters for the SAA7127
129 *
130 **********************************************************************
131 */
132
133struct i2c_reg_value {
134 unsigned char reg;
135 unsigned char value;
136};
137
138static const struct i2c_reg_value saa7129_init_config_extra[] = {
139 { SAA7127_REG_OUTPUT_PORT_CONTROL, 0x38 },
140 { SAA7127_REG_VTRIG, 0xfa },
ea76ce52 141 { 0, 0 }
cfbb5b8c
HV		 142};
143
144static const struct i2c_reg_value saa7127_init_config_common[] = {
145 { SAA7127_REG_WIDESCREEN_CONFIG, 0x0d },
146 { SAA7127_REG_WIDESCREEN_ENABLE, 0x00 },
147 { SAA7127_REG_COPYGEN_0, 0x77 },
148 { SAA7127_REG_COPYGEN_1, 0x41 },
149 { SAA7127_REG_COPYGEN_2, 0x00 }, /* Macrovision enable/disable */
0f3559ef 150 { SAA7127_REG_OUTPUT_PORT_CONTROL, 0xbf },
cfbb5b8c
HV		 151 { SAA7127_REG_GAIN_LUMINANCE_RGB, 0x00 },
152 { SAA7127_REG_GAIN_COLORDIFF_RGB, 0x00 },
153 { SAA7127_REG_INPUT_PORT_CONTROL_1, 0x80 }, /* for color bars */
154 { SAA7127_REG_LINE_21_ODD_0, 0x77 },
155 { SAA7127_REG_LINE_21_ODD_1, 0x41 },
156 { SAA7127_REG_LINE_21_EVEN_0, 0x88 },
157 { SAA7127_REG_LINE_21_EVEN_1, 0x41 },
158 { SAA7127_REG_RCV_PORT_CONTROL, 0x12 },
159 { SAA7127_REG_VTRIG, 0xf9 },
160 { SAA7127_REG_HTRIG_HI, 0x00 },
161 { SAA7127_REG_RCV2_OUTPUT_START, 0x41 },
162 { SAA7127_REG_RCV2_OUTPUT_END, 0xc3 },
163 { SAA7127_REG_RCV2_OUTPUT_MSBS, 0x00 },
164 { SAA7127_REG_TTX_REQUEST_H_START, 0x3e },
165 { SAA7127_REG_TTX_REQUEST_H_DELAY_LENGTH, 0xb8 },
166 { SAA7127_REG_CSYNC_ADVANCE_VSYNC_SHIFT, 0x03 },
167 { SAA7127_REG_TTX_ODD_REQ_VERT_START, 0x15 },
168 { SAA7127_REG_TTX_ODD_REQ_VERT_END, 0x16 },
169 { SAA7127_REG_TTX_EVEN_REQ_VERT_START, 0x15 },
170 { SAA7127_REG_TTX_EVEN_REQ_VERT_END, 0x16 },
171 { SAA7127_REG_FIRST_ACTIVE, 0x1a },
172 { SAA7127_REG_LAST_ACTIVE, 0x01 },
173 { SAA7127_REG_MSB_VERTICAL, 0xc0 },
174 { SAA7127_REG_DISABLE_TTX_LINE_LO_0, 0x00 },
175 { SAA7127_REG_DISABLE_TTX_LINE_LO_1, 0x00 },
176 { 0, 0 }
177};
178
179#define SAA7127_60HZ_DAC_CONTROL 0x15
180static const struct i2c_reg_value saa7127_init_config_60hz[] = {
181 { SAA7127_REG_BURST_START, 0x19 },
f05b7f5e 182 /* BURST_END is also used as a chip ID in saa7127_probe */
cfbb5b8c
HV		 183 { SAA7127_REG_BURST_END, 0x1d },
184 { SAA7127_REG_CHROMA_PHASE, 0xa3 },
185 { SAA7127_REG_GAINU, 0x98 },
186 { SAA7127_REG_GAINV, 0xd3 },
187 { SAA7127_REG_BLACK_LEVEL, 0x39 },
188 { SAA7127_REG_BLANKING_LEVEL, 0x2e },
189 { SAA7127_REG_VBI_BLANKING, 0x2e },
190 { SAA7127_REG_DAC_CONTROL, 0x15 },
191 { SAA7127_REG_BURST_AMP, 0x4d },
192 { SAA7127_REG_SUBC3, 0x1f },
193 { SAA7127_REG_SUBC2, 0x7c },
194 { SAA7127_REG_SUBC1, 0xf0 },
195 { SAA7127_REG_SUBC0, 0x21 },
196 { SAA7127_REG_MULTI, 0x90 },
197 { SAA7127_REG_CLOSED_CAPTION, 0x11 },
198 { 0, 0 }
199};
200
f05b7f5e
AW		 201#define SAA7127_50HZ_PAL_DAC_CONTROL 0x02
202static struct i2c_reg_value saa7127_init_config_50hz_pal[] = {
cfbb5b8c 203 { SAA7127_REG_BURST_START, 0x21 },
f05b7f5e 204 /* BURST_END is also used as a chip ID in saa7127_probe */
cfbb5b8c
HV		 205 { SAA7127_REG_BURST_END, 0x1d },
206 { SAA7127_REG_CHROMA_PHASE, 0x3f },
207 { SAA7127_REG_GAINU, 0x7d },
208 { SAA7127_REG_GAINV, 0xaf },
209 { SAA7127_REG_BLACK_LEVEL, 0x33 },
210 { SAA7127_REG_BLANKING_LEVEL, 0x35 },
211 { SAA7127_REG_VBI_BLANKING, 0x35 },
212 { SAA7127_REG_DAC_CONTROL, 0x02 },
213 { SAA7127_REG_BURST_AMP, 0x2f },
214 { SAA7127_REG_SUBC3, 0xcb },
215 { SAA7127_REG_SUBC2, 0x8a },
216 { SAA7127_REG_SUBC1, 0x09 },
217 { SAA7127_REG_SUBC0, 0x2a },
218 { SAA7127_REG_MULTI, 0xa0 },
219 { SAA7127_REG_CLOSED_CAPTION, 0x00 },
220 { 0, 0 }
221};
222
f05b7f5e
AW		 223#define SAA7127_50HZ_SECAM_DAC_CONTROL 0x08
224static struct i2c_reg_value saa7127_init_config_50hz_secam[] = {
225 { SAA7127_REG_BURST_START, 0x21 },
226 /* BURST_END is also used as a chip ID in saa7127_probe */
227 { SAA7127_REG_BURST_END, 0x1d },
228 { SAA7127_REG_CHROMA_PHASE, 0x3f },
229 { SAA7127_REG_GAINU, 0x6a },
230 { SAA7127_REG_GAINV, 0x81 },
231 { SAA7127_REG_BLACK_LEVEL, 0x33 },
232 { SAA7127_REG_BLANKING_LEVEL, 0x35 },
233 { SAA7127_REG_VBI_BLANKING, 0x35 },
234 { SAA7127_REG_DAC_CONTROL, 0x08 },
235 { SAA7127_REG_BURST_AMP, 0x2f },
236 { SAA7127_REG_SUBC3, 0xb2 },
237 { SAA7127_REG_SUBC2, 0x3b },
238 { SAA7127_REG_SUBC1, 0xa3 },
239 { SAA7127_REG_SUBC0, 0x28 },
240 { SAA7127_REG_MULTI, 0x90 },
241 { SAA7127_REG_CLOSED_CAPTION, 0x00 },
242 { 0, 0 }
243};
244
cfbb5b8c
HV		 245/*
246 **********************************************************************
247 *
248 * Encoder Struct, holds the configuration state of the encoder
249 *
250 **********************************************************************
251 */
252
e1277110
HV		 253enum saa712x_model {
254 SAA7127,
255 SAA7129,
256};
257
cfbb5b8c 258struct saa7127_state {
627426c6 259 struct v4l2_subdev sd;
cfbb5b8c 260 v4l2_std_id std;
e1277110 261 enum saa712x_model ident;
cfbb5b8c
HV		 262 enum saa7127_input_type input_type;
263 enum saa7127_output_type output_type;
264 int video_enable;
265 int wss_enable;
266 u16 wss_mode;
267 int cc_enable;
268 u16 cc_data;
269 int xds_enable;
270 u16 xds_data;
271 int vps_enable;
272 u8 vps_data[5];
273 u8 reg_2d;
274 u8 reg_3a;
275 u8 reg_3a_cb; /* colorbar bit */
276 u8 reg_61;
277};
278
627426c6
HV		 279static inline struct saa7127_state *to_state(struct v4l2_subdev *sd)
280{
281 return container_of(sd, struct saa7127_state, sd);
282}
283
cfbb5b8c
HV		 284static const char * const output_strs[] =
285{
286 "S-Video + Composite",
287 "Composite",
288 "S-Video",
289 "RGB",
290 "YUV C",
291 "YUV V"
292};
293
294static const char * const wss_strs[] = {
295 "invalid",
296 "letterbox 14:9 center",
297 "letterbox 14:9 top",
298 "invalid",
299 "letterbox 16:9 top",
300 "invalid",
301 "invalid",
35a303b1 302 "16:9 full format anamorphic",
cfbb5b8c
HV		 303 "4:3 full format",
304 "invalid",
305 "invalid",
306 "letterbox 16:9 center",
307 "invalid",
308 "letterbox >16:9 center",
309 "14:9 full format center",
310 "invalid",
311};
312
313/* ----------------------------------------------------------------------- */
314
627426c6 315static int saa7127_read(struct v4l2_subdev *sd, u8 reg)
cfbb5b8c 316{
627426c6
HV		 317 struct i2c_client *client = v4l2_get_subdevdata(sd);
318
cfbb5b8c
HV		 319 return i2c_smbus_read_byte_data(client, reg);
320}
321
322/* ----------------------------------------------------------------------- */
323
627426c6 324static int saa7127_write(struct v4l2_subdev *sd, u8 reg, u8 val)
cfbb5b8c 325{
627426c6 326 struct i2c_client *client = v4l2_get_subdevdata(sd);
cfbb5b8c
HV		 327 int i;
328
329 for (i = 0; i < 3; i++) {
330 if (i2c_smbus_write_byte_data(client, reg, val) == 0)
331 return 0;
332 }
627426c6 333 v4l2_err(sd, "I2C Write Problem\n");
cfbb5b8c
HV		 334 return -1;
335}
336
337/* ----------------------------------------------------------------------- */
338
627426c6 339static int saa7127_write_inittab(struct v4l2_subdev *sd,
cfbb5b8c
HV		 340 const struct i2c_reg_value *regs)
341{
342 while (regs->reg != 0) {
627426c6 343 saa7127_write(sd, regs->reg, regs->value);
cfbb5b8c
HV		 344 regs++;
345 }
346 return 0;
347}
348
349/* ----------------------------------------------------------------------- */
350
627426c6 351static int saa7127_set_vps(struct v4l2_subdev *sd, const struct v4l2_sliced_vbi_data *data)
cfbb5b8c 352{
627426c6 353 struct saa7127_state *state = to_state(sd);
cfbb5b8c
HV		 354 int enable = (data->line != 0);
355
356 if (enable && (data->field != 0 || data->line != 16))
357 return -EINVAL;
358 if (state->vps_enable != enable) {
627426c6
HV		 359 v4l2_dbg(1, debug, sd, "Turn VPS Signal %s\n", enable ? "on" : "off");
360 saa7127_write(sd, 0x54, enable << 7);
cfbb5b8c
HV		 361 state->vps_enable = enable;
362 }
363 if (!enable)
364 return 0;
365
2f3a9893
HV		 366 state->vps_data[0] = data->data[2];
367 state->vps_data[1] = data->data[8];
368 state->vps_data[2] = data->data[9];
369 state->vps_data[3] = data->data[10];
370 state->vps_data[4] = data->data[11];
6f28f75a 371 v4l2_dbg(1, debug, sd, "Set VPS data %*ph\n", 5, state->vps_data);
627426c6
HV		 372 saa7127_write(sd, 0x55, state->vps_data[0]);
373 saa7127_write(sd, 0x56, state->vps_data[1]);
374 saa7127_write(sd, 0x57, state->vps_data[2]);
375 saa7127_write(sd, 0x58, state->vps_data[3]);
376 saa7127_write(sd, 0x59, state->vps_data[4]);
cfbb5b8c
HV		 377 return 0;
378}
379
380/* ----------------------------------------------------------------------- */
381
627426c6 382static int saa7127_set_cc(struct v4l2_subdev *sd, const struct v4l2_sliced_vbi_data *data)
cfbb5b8c 383{
627426c6 384 struct saa7127_state *state = to_state(sd);
515432aa 385 u16 cc = data->data[1] << 8 | data->data[0];
cfbb5b8c
HV		 386 int enable = (data->line != 0);
387
388 if (enable && (data->field != 0 || data->line != 21))
389 return -EINVAL;
390 if (state->cc_enable != enable) {
627426c6 391 v4l2_dbg(1, debug, sd,
9fad368b 392 "Turn CC %s\n", enable ? "on" : "off");
627426c6 393 saa7127_write(sd, SAA7127_REG_CLOSED_CAPTION,
9fad368b 394 (state->xds_enable << 7) | (enable << 6) | 0x11);
cfbb5b8c
HV		 395 state->cc_enable = enable;
396 }
397 if (!enable)
398 return 0;
399
627426c6
HV		 400 v4l2_dbg(2, debug, sd, "CC data: %04x\n", cc);
401 saa7127_write(sd, SAA7127_REG_LINE_21_ODD_0, cc & 0xff);
402 saa7127_write(sd, SAA7127_REG_LINE_21_ODD_1, cc >> 8);
cfbb5b8c
HV		 403 state->cc_data = cc;
404 return 0;
405}
406
407/* ----------------------------------------------------------------------- */
408
627426c6 409static int saa7127_set_xds(struct v4l2_subdev *sd, const struct v4l2_sliced_vbi_data *data)
cfbb5b8c 410{
627426c6 411 struct saa7127_state *state = to_state(sd);
cfbb5b8c
HV		 412 u16 xds = data->data[1] << 8 | data->data[0];
413 int enable = (data->line != 0);
414
415 if (enable && (data->field != 1 || data->line != 21))
416 return -EINVAL;
417 if (state->xds_enable != enable) {
627426c6
HV		 418 v4l2_dbg(1, debug, sd, "Turn XDS %s\n", enable ? "on" : "off");
419 saa7127_write(sd, SAA7127_REG_CLOSED_CAPTION,
515432aa 420 (enable << 7) | (state->cc_enable << 6) | 0x11);
cfbb5b8c
HV		 421 state->xds_enable = enable;
422 }
423 if (!enable)
424 return 0;
425
627426c6
HV		 426 v4l2_dbg(2, debug, sd, "XDS data: %04x\n", xds);
427 saa7127_write(sd, SAA7127_REG_LINE_21_EVEN_0, xds & 0xff);
428 saa7127_write(sd, SAA7127_REG_LINE_21_EVEN_1, xds >> 8);
cfbb5b8c
HV		 429 state->xds_data = xds;
430 return 0;
431}
432
433/* ----------------------------------------------------------------------- */
434
627426c6 435static int saa7127_set_wss(struct v4l2_subdev *sd, const struct v4l2_sliced_vbi_data *data)
cfbb5b8c 436{
627426c6 437 struct saa7127_state *state = to_state(sd);
cfbb5b8c
HV		 438 int enable = (data->line != 0);
439
440 if (enable && (data->field != 0 || data->line != 23))
441 return -EINVAL;
442 if (state->wss_enable != enable) {
627426c6
HV		 443 v4l2_dbg(1, debug, sd, "Turn WSS %s\n", enable ? "on" : "off");
444 saa7127_write(sd, 0x27, enable << 7);
cfbb5b8c
HV		 445 state->wss_enable = enable;
446 }
447 if (!enable)
448 return 0;
449
627426c6
HV		 450 saa7127_write(sd, 0x26, data->data[0]);
451 saa7127_write(sd, 0x27, 0x80 | (data->data[1] & 0x3f));
452 v4l2_dbg(1, debug, sd,
9fad368b 453 "WSS mode: %s\n", wss_strs[data->data[0] & 0xf]);
cfbb5b8c
HV		 454 state->wss_mode = (data->data[1] & 0x3f) << 8 | data->data[0];
455 return 0;
456}
457
458/* ----------------------------------------------------------------------- */
459
627426c6 460static int saa7127_set_video_enable(struct v4l2_subdev *sd, int enable)
cfbb5b8c 461{
627426c6 462 struct saa7127_state *state = to_state(sd);
cfbb5b8c
HV		 463
464 if (enable) {
627426c6
HV		 465 v4l2_dbg(1, debug, sd, "Enable Video Output\n");
466 saa7127_write(sd, 0x2d, state->reg_2d);
467 saa7127_write(sd, 0x61, state->reg_61);
cfbb5b8c 468 } else {
627426c6
HV		 469 v4l2_dbg(1, debug, sd, "Disable Video Output\n");
470 saa7127_write(sd, 0x2d, (state->reg_2d & 0xf0));
471 saa7127_write(sd, 0x61, (state->reg_61 | 0xc0));
cfbb5b8c
HV		 472 }
473 state->video_enable = enable;
474 return 0;
475}
476
477/* ----------------------------------------------------------------------- */
478
627426c6 479static int saa7127_set_std(struct v4l2_subdev *sd, v4l2_std_id std)
cfbb5b8c 480{
627426c6 481 struct saa7127_state *state = to_state(sd);
cfbb5b8c
HV		 482 const struct i2c_reg_value *inittab;
483
484 if (std & V4L2_STD_525_60) {
627426c6 485 v4l2_dbg(1, debug, sd, "Selecting 60 Hz video Standard\n");
cfbb5b8c
HV		 486 inittab = saa7127_init_config_60hz;
487 state->reg_61 = SAA7127_60HZ_DAC_CONTROL;
f05b7f5e 488
e1277110 489 } else if (state->ident == SAA7129 &&
f05b7f5e
AW		 490 (std & V4L2_STD_SECAM) &&
491 !(std & (V4L2_STD_625_50 & ~V4L2_STD_SECAM))) {
492
493 /* If and only if SECAM, with a SAA712[89] */
494 v4l2_dbg(1, debug, sd,
495 "Selecting 50 Hz SECAM video Standard\n");
496 inittab = saa7127_init_config_50hz_secam;
497 state->reg_61 = SAA7127_50HZ_SECAM_DAC_CONTROL;
498
cfbb5b8c 499 } else {
f05b7f5e
AW		 500 v4l2_dbg(1, debug, sd, "Selecting 50 Hz PAL video Standard\n");
501 inittab = saa7127_init_config_50hz_pal;
502 state->reg_61 = SAA7127_50HZ_PAL_DAC_CONTROL;
cfbb5b8c
HV		 503 }
504
505 /* Write Table */
627426c6 506 saa7127_write_inittab(sd, inittab);
cfbb5b8c
HV		 507 state->std = std;
508 return 0;
509}
510
511/* ----------------------------------------------------------------------- */
512
627426c6 513static int saa7127_set_output_type(struct v4l2_subdev *sd, int output)
cfbb5b8c 514{
627426c6 515 struct saa7127_state *state = to_state(sd);
cfbb5b8c
HV		 516
517 switch (output) {
518 case SAA7127_OUTPUT_TYPE_RGB:
519 state->reg_2d = 0x0f; /* RGB + CVBS (for sync) */
520 state->reg_3a = 0x13; /* by default switch YUV to RGB-matrix on */
521 break;
522
523 case SAA7127_OUTPUT_TYPE_COMPOSITE:
e1277110 524 if (state->ident == SAA7129)
0f3559ef
MD		 525 state->reg_2d = 0x20; /* CVBS only */
526 else
527 state->reg_2d = 0x08; /* 00001000 CVBS only, RGB DAC's off (high impedance mode) */
cfbb5b8c
HV		 528 state->reg_3a = 0x13; /* by default switch YUV to RGB-matrix on */
529 break;
530
531 case SAA7127_OUTPUT_TYPE_SVIDEO:
e1277110 532 if (state->ident == SAA7129)
0f3559ef
MD		 533 state->reg_2d = 0x18; /* Y + C */
534 else
535 state->reg_2d = 0xff; /*11111111 croma -> R, luma -> CVBS + G + B */
cfbb5b8c
HV		 536 state->reg_3a = 0x13; /* by default switch YUV to RGB-matrix on */
537 break;
538
539 case SAA7127_OUTPUT_TYPE_YUV_V:
540 state->reg_2d = 0x4f; /* reg 2D = 01001111, all DAC's on, RGB + VBS */
541 state->reg_3a = 0x0b; /* reg 3A = 00001011, bypass RGB-matrix */
542 break;
543
544 case SAA7127_OUTPUT_TYPE_YUV_C:
545 state->reg_2d = 0x0f; /* reg 2D = 00001111, all DAC's on, RGB + CVBS */
546 state->reg_3a = 0x0b; /* reg 3A = 00001011, bypass RGB-matrix */
547 break;
548
549 case SAA7127_OUTPUT_TYPE_BOTH:
e1277110 550 if (state->ident == SAA7129)
0f3559ef
MD		 551 state->reg_2d = 0x38;
552 else
553 state->reg_2d = 0xbf;
cfbb5b8c
HV		 554 state->reg_3a = 0x13; /* by default switch YUV to RGB-matrix on */
555 break;
556
557 default:
558 return -EINVAL;
559 }
627426c6 560 v4l2_dbg(1, debug, sd,
9fad368b 561 "Selecting %s output type\n", output_strs[output]);
cfbb5b8c
HV		 562
563 /* Configure Encoder */
627426c6
HV		 564 saa7127_write(sd, 0x2d, state->reg_2d);
565 saa7127_write(sd, 0x3a, state->reg_3a | state->reg_3a_cb);
cfbb5b8c
HV		 566 state->output_type = output;
567 return 0;
568}
569
570/* ----------------------------------------------------------------------- */
571
627426c6 572static int saa7127_set_input_type(struct v4l2_subdev *sd, int input)
cfbb5b8c 573{
627426c6 574 struct saa7127_state *state = to_state(sd);
cfbb5b8c
HV		 575
576 switch (input) {
577 case SAA7127_INPUT_TYPE_NORMAL: /* avia */
627426c6 578 v4l2_dbg(1, debug, sd, "Selecting Normal Encoder Input\n");
cfbb5b8c
HV		 579 state->reg_3a_cb = 0;
580 break;
581
582 case SAA7127_INPUT_TYPE_TEST_IMAGE: /* color bar */
627426c6 583 v4l2_dbg(1, debug, sd, "Selecting Color Bar generator\n");
cfbb5b8c
HV		 584 state->reg_3a_cb = 0x80;
585 break;
586
587 default:
588 return -EINVAL;
589 }
627426c6 590 saa7127_write(sd, 0x3a, state->reg_3a | state->reg_3a_cb);
cfbb5b8c
HV		 591 state->input_type = input;
592 return 0;
593}
594
595/* ----------------------------------------------------------------------- */
596
627426c6 597static int saa7127_s_std_output(struct v4l2_subdev *sd, v4l2_std_id std)
cfbb5b8c 598{
627426c6 599 struct saa7127_state *state = to_state(sd);
cfbb5b8c 600
627426c6
HV		 601 if (state->std == std)
602 return 0;
603 return saa7127_set_std(sd, std);
604}
cfbb5b8c 605
5325b427
HV		 606static int saa7127_s_routing(struct v4l2_subdev *sd,
607 u32 input, u32 output, u32 config)
627426c6
HV		 608{
609 struct saa7127_state *state = to_state(sd);
610 int rc = 0;
611
5325b427
HV		 612 if (state->input_type != input)
613 rc = saa7127_set_input_type(sd, input);
614 if (rc == 0 && state->output_type != output)
615 rc = saa7127_set_output_type(sd, output);
627426c6
HV		 616 return rc;
617}
39b6f687 618
627426c6
HV		 619static int saa7127_s_stream(struct v4l2_subdev *sd, int enable)
620{
621 struct saa7127_state *state = to_state(sd);
cfbb5b8c 622
627426c6
HV		 623 if (state->video_enable == enable)
624 return 0;
625 return saa7127_set_video_enable(sd, enable);
626}
cfbb5b8c 627
1dbf8539 628static int saa7127_g_sliced_fmt(struct v4l2_subdev *sd, struct v4l2_sliced_vbi_format *fmt)
627426c6
HV		 629{
630 struct saa7127_state *state = to_state(sd);
cfbb5b8c 631
30634e8e 632 memset(fmt->service_lines, 0, sizeof(fmt->service_lines));
627426c6 633 if (state->vps_enable)
1dbf8539 634 fmt->service_lines[0][16] = V4L2_SLICED_VPS;
627426c6 635 if (state->wss_enable)
1dbf8539 636 fmt->service_lines[0][23] = V4L2_SLICED_WSS_625;
627426c6 637 if (state->cc_enable) {
1dbf8539
HV		 638 fmt->service_lines[0][21] = V4L2_SLICED_CAPTION_525;
639 fmt->service_lines[1][21] = V4L2_SLICED_CAPTION_525;
cfbb5b8c 640 }
1dbf8539 641 fmt->service_set =
627426c6
HV		 642 (state->vps_enable ? V4L2_SLICED_VPS : 0) |
643 (state->wss_enable ? V4L2_SLICED_WSS_625 : 0) |
644 (state->cc_enable ? V4L2_SLICED_CAPTION_525 : 0);
645 return 0;
646}
cfbb5b8c 647
627426c6
HV		 648static int saa7127_s_vbi_data(struct v4l2_subdev *sd, const struct v4l2_sliced_vbi_data *data)
649{
650 switch (data->id) {
651 case V4L2_SLICED_WSS_625:
652 return saa7127_set_wss(sd, data);
653 case V4L2_SLICED_VPS:
654 return saa7127_set_vps(sd, data);
655 case V4L2_SLICED_CAPTION_525:
656 if (data->field == 0)
657 return saa7127_set_cc(sd, data);
658 return saa7127_set_xds(sd, data);
cfbb5b8c
HV		 659 default:
660 return -EINVAL;
661 }
662 return 0;
663}
664
627426c6 665#ifdef CONFIG_VIDEO_ADV_DEBUG
aecde8b5 666static int saa7127_g_register(struct v4l2_subdev *sd, struct v4l2_dbg_register *reg)
627426c6 667{
627426c6 668 reg->val = saa7127_read(sd, reg->reg & 0xff);
aecde8b5 669 reg->size = 1;
627426c6
HV		 670 return 0;
671}
672
977ba3b1 673static int saa7127_s_register(struct v4l2_subdev *sd, const struct v4l2_dbg_register *reg)
627426c6 674{
627426c6
HV		 675 saa7127_write(sd, reg->reg & 0xff, reg->val & 0xff);
676 return 0;
677}
678#endif
679
627426c6
HV		 680static int saa7127_log_status(struct v4l2_subdev *sd)
681{
682 struct saa7127_state *state = to_state(sd);
683
684 v4l2_info(sd, "Standard: %s\n", (state->std & V4L2_STD_525_60) ? "60 Hz" : "50 Hz");
685 v4l2_info(sd, "Input: %s\n", state->input_type ? "color bars" : "normal");
686 v4l2_info(sd, "Output: %s\n", state->video_enable ?
687 output_strs[state->output_type] : "disabled");
688 v4l2_info(sd, "WSS: %s\n", state->wss_enable ?
689 wss_strs[state->wss_mode] : "disabled");
690 v4l2_info(sd, "VPS: %s\n", state->vps_enable ? "enabled" : "disabled");
691 v4l2_info(sd, "CC: %s\n", state->cc_enable ? "enabled" : "disabled");
692 return 0;
693}
694
695/* ----------------------------------------------------------------------- */
696
697static const struct v4l2_subdev_core_ops saa7127_core_ops = {
698 .log_status = saa7127_log_status,
627426c6
HV		 699#ifdef CONFIG_VIDEO_ADV_DEBUG
700 .g_register = saa7127_g_register,
701 .s_register = saa7127_s_register,
702#endif
703};
704
705static const struct v4l2_subdev_video_ops saa7127_video_ops = {
627426c6
HV		 706 .s_std_output = saa7127_s_std_output,
707 .s_routing = saa7127_s_routing,
708 .s_stream = saa7127_s_stream,
709};
710
32cd527f
HV		 711static const struct v4l2_subdev_vbi_ops saa7127_vbi_ops = {
712 .s_vbi_data = saa7127_s_vbi_data,
1dbf8539 713 .g_sliced_fmt = saa7127_g_sliced_fmt,
32cd527f
HV		 714};
715
627426c6
HV		 716static const struct v4l2_subdev_ops saa7127_ops = {
717 .core = &saa7127_core_ops,
718 .video = &saa7127_video_ops,
32cd527f 719 .vbi = &saa7127_vbi_ops,
627426c6
HV		 720};
721
cfbb5b8c
HV		 722/* ----------------------------------------------------------------------- */
723
d2653e92
JD		 724static int saa7127_probe(struct i2c_client *client,
725 const struct i2c_device_id *id)
cfbb5b8c 726{
cfbb5b8c 727 struct saa7127_state *state;
627426c6 728 struct v4l2_subdev *sd;
cfbb5b8c 729 struct v4l2_sliced_vbi_data vbi = { 0, 0, 0, 0 }; /* set to disabled */
cfbb5b8c
HV		 730
731 /* Check if the adapter supports the needed features */
77566dd7 732 if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
188f3457 733 return -EIO;
cfbb5b8c 734
9fad368b
HV		 735 v4l_dbg(1, debug, client, "detecting saa7127 client on address 0x%x\n",
736 client->addr << 1);
cfbb5b8c 737
c02b211d 738 state = devm_kzalloc(&client->dev, sizeof(*state), GFP_KERNEL);
627426c6
HV		 739 if (state == NULL)
740 return -ENOMEM;
741
742 sd = &state->sd;
743 v4l2_i2c_subdev_init(sd, client, &saa7127_ops);
744
cfbb5b8c
HV		 745 /* First test register 0: Bits 5-7 are a version ID (should be 0),
746 and bit 2 should also be 0.
747 This is rather general, so the second test is more specific and
748 looks at the 'ending point of burst in clock cycles' which is
749 0x1d after a reset and not expected to ever change. */
627426c6
HV		 750 if ((saa7127_read(sd, 0) & 0xe4) != 0 ||
751 (saa7127_read(sd, 0x29) & 0x3f) != 0x1d) {
752 v4l2_dbg(1, debug, sd, "saa7127 not found\n");
188f3457 753 return -ENODEV;
cfbb5b8c 754 }
cfbb5b8c 755
5daed074
JD		 756 if (id->driver_data) { /* Chip type is already known */
757 state->ident = id->driver_data;
758 } else { /* Needs detection */
759 int read_result;
760
761 /* Detect if it's an saa7129 */
627426c6
HV		 762 read_result = saa7127_read(sd, SAA7129_REG_FADE_KEY_COL2);
763 saa7127_write(sd, SAA7129_REG_FADE_KEY_COL2, 0xaa);
764 if (saa7127_read(sd, SAA7129_REG_FADE_KEY_COL2) == 0xaa) {
765 saa7127_write(sd, SAA7129_REG_FADE_KEY_COL2,
5daed074 766 read_result);
e1277110 767 state->ident = SAA7129;
5daed074
JD		 768 strlcpy(client->name, "saa7129", I2C_NAME_SIZE);
769 } else {
e1277110 770 state->ident = SAA7127;
5daed074
JD		 771 strlcpy(client->name, "saa7127", I2C_NAME_SIZE);
772 }
cfbb5b8c 773 }
5daed074 774
627426c6 775 v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name,
5daed074 776 client->addr << 1, client->adapter->name);
0f3559ef
MD		 777
778 v4l2_dbg(1, debug, sd, "Configuring encoder\n");
779 saa7127_write_inittab(sd, saa7127_init_config_common);
780 saa7127_set_std(sd, V4L2_STD_NTSC);
781 saa7127_set_output_type(sd, SAA7127_OUTPUT_TYPE_BOTH);
782 saa7127_set_vps(sd, &vbi);
783 saa7127_set_wss(sd, &vbi);
784 saa7127_set_cc(sd, &vbi);
785 saa7127_set_xds(sd, &vbi);
786 if (test_image == 1)
787 /* The Encoder has an internal Colorbar generator */
788 /* This can be used for debugging */
789 saa7127_set_input_type(sd, SAA7127_INPUT_TYPE_TEST_IMAGE);
790 else
791 saa7127_set_input_type(sd, SAA7127_INPUT_TYPE_NORMAL);
792 saa7127_set_video_enable(sd, 1);
793
e1277110 794 if (state->ident == SAA7129)
627426c6 795 saa7127_write_inittab(sd, saa7129_init_config_extra);
cfbb5b8c
HV		 796 return 0;
797}
798
799/* ----------------------------------------------------------------------- */
800
77566dd7 801static int saa7127_remove(struct i2c_client *client)
cfbb5b8c 802{
627426c6
HV		 803 struct v4l2_subdev *sd = i2c_get_clientdata(client);
804
805 v4l2_device_unregister_subdev(sd);
cfbb5b8c 806 /* Turn off TV output */
627426c6 807 saa7127_set_video_enable(sd, 0);
cfbb5b8c
HV		 808 return 0;
809}
810
811/* ----------------------------------------------------------------------- */
812
af294867 813static struct i2c_device_id saa7127_id[] = {
5daed074 814 { "saa7127_auto", 0 }, /* auto-detection */
e1277110
HV		 815 { "saa7126", SAA7127 },
816 { "saa7127", SAA7127 },
817 { "saa7128", SAA7129 },
818 { "saa7129", SAA7129 },
af294867
JD		 819 { }
820};
821MODULE_DEVICE_TABLE(i2c, saa7127_id);
822
96209a20
HV		 823static struct i2c_driver saa7127_driver = {
824 .driver = {
825 .owner = THIS_MODULE,
826 .name = "saa7127",
827 },
828 .probe = saa7127_probe,
829 .remove = saa7127_remove,
830 .id_table = saa7127_id,
cfbb5b8c 831};
96209a20 832
c6e8d86f 833module_i2c_driver(saa7127_driver);
ubuntu-bionic-kernel mirror