[mirror_ubuntu-artful-kernel.git] / drivers / media / i2c / saa7191.h

/*
 *  saa7191.h - Philips SAA7191 video decoder driver
 *
 *  Copyright (C) 2003 Ladislav Michl <ladis@linux-mips.org>
 *  Copyright (C) 2004,2005 Mikael Nousiainen <tmnousia@cc.hut.fi>
 *
 *  This program is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License version 2 as
 *  published by the Free Software Foundation.
 */

#ifndef _SAA7191_H_
#define _SAA7191_H_

/* Philips SAA7191 DMSD I2C bus address */
#define SAA7191_ADDR		0x8a

/* Register subaddresses. */
#define SAA7191_REG_IDEL	0x00
#define SAA7191_REG_HSYB	0x01
#define SAA7191_REG_HSYS	0x02
#define SAA7191_REG_HCLB	0x03
#define SAA7191_REG_HCLS	0x04
#define SAA7191_REG_HPHI	0x05
#define SAA7191_REG_LUMA	0x06
#define SAA7191_REG_HUEC	0x07
#define SAA7191_REG_CKTQ	0x08 /* bits 3-7 */
#define SAA7191_REG_CKTS	0x09 /* bits 3-7 */
#define SAA7191_REG_PLSE	0x0a
#define SAA7191_REG_SESE	0x0b
#define SAA7191_REG_GAIN	0x0c
#define SAA7191_REG_STDC	0x0d
#define SAA7191_REG_IOCK	0x0e
#define SAA7191_REG_CTL3	0x0f
#define SAA7191_REG_CTL4	0x10
#define SAA7191_REG_CHCV	0x11
#define SAA7191_REG_HS6B	0x14
#define SAA7191_REG_HS6S	0x15
#define SAA7191_REG_HC6B	0x16
#define SAA7191_REG_HC6S	0x17
#define SAA7191_REG_HP6I	0x18
#define SAA7191_REG_STATUS	0xff	/* not really a subaddress */

/* Status Register definitions */
#define SAA7191_STATUS_CODE	0x01	/* color detected flag */
#define SAA7191_STATUS_FIDT	0x20	/* signal type 50/60 Hz */
#define SAA7191_STATUS_HLCK	0x40	/* PLL unlocked(1)/locked(0) */
#define SAA7191_STATUS_STTC	0x80	/* tv/vtr time constant */

/* Luminance Control Register definitions */
/* input mode select bit:
 * 0=CVBS (chrominance trap active), 1=S-Video (trap bypassed) */
#define SAA7191_LUMA_BYPS	0x80
/* pre-filter (only when chrominance trap is active) */
#define SAA7191_LUMA_PREF	0x40
/* aperture bandpass to select different characteristics with maximums
 * (bits 4-5) */
#define SAA7191_LUMA_BPSS_MASK	0x30
#define SAA7191_LUMA_BPSS_SHIFT	4
#define SAA7191_LUMA_BPSS_3	0x30
#define SAA7191_LUMA_BPSS_2	0x20
#define SAA7191_LUMA_BPSS_1	0x10
#define SAA7191_LUMA_BPSS_0	0x00
/* coring range for high frequency components according to 8-bit luminance
 * (bits 2-3)
 * 0=coring off, n= (+-)n LSB */
#define SAA7191_LUMA_CORI_MASK	0x0c
#define SAA7191_LUMA_CORI_SHIFT	2
#define SAA7191_LUMA_CORI_3	0x0c
#define SAA7191_LUMA_CORI_2	0x08
#define SAA7191_LUMA_CORI_1	0x04
#define SAA7191_LUMA_CORI_0	0x00
/* aperture bandpass filter weights high frequency components of luminance
 * signal (bits 0-1)
 * 0=factor 0, 1=0.25, 2=0.5, 3=1 */
#define SAA7191_LUMA_APER_MASK	0x03
#define SAA7191_LUMA_APER_SHIFT	0
#define SAA7191_LUMA_APER_3	0x03
#define SAA7191_LUMA_APER_2	0x02
#define SAA7191_LUMA_APER_1	0x01
#define SAA7191_LUMA_APER_0	0x00

/* Chrominance Gain Control Settings Register definitions */
/* colour on: 0=automatic colour-killer enabled, 1=forced colour on */
#define SAA7191_GAIN_COLO	0x80
/* chrominance gain control (AGC filter)
 * 0=loop filter time constant slow, 1=medium, 2=fast, 3=actual gain */
#define SAA7191_GAIN_LFIS_MASK	0x60
#define SAA7191_GAIN_LFIS_SHIFT	5
#define SAA7191_GAIN_LFIS_3	0x60
#define SAA7191_GAIN_LFIS_2	0x40
#define SAA7191_GAIN_LFIS_1	0x20
#define SAA7191_GAIN_LFIS_0	0x00

/* Standard/Mode Control Register definitions */
/* tv/vtr mode bit: 0=TV mode (slow time constant),
 * 1=VTR mode (fast time constant) */
#define SAA7191_STDC_VTRC	0x80
/* SAA7191B-specific functions enable (RTCO, ODD and GPSW0 outputs)
 * 0=outputs set to high-impedance (circuit equals SAA7191), 1=enabled */
#define SAA7191_STDC_NFEN	0x08
/* HREF generation: 0=like SAA7191, 1=HREF is 8xLLC2 clocks earlier */
#define SAA7191_STDC_HRMV	0x04
/* general purpose switch 0
 * (not used with VINO afaik) */
#define SAA7191_STDC_GPSW0	0x02
/* SECAM mode bit: 0=other standards, 1=SECAM */
#define SAA7191_STDC_SECS	0x01

/* I/O and Clock Control Register definitions */
/* horizontal clock PLL: 0=PLL closed,
 * 1=PLL circuit open and horizontal freq fixed */
#define SAA7191_IOCK_HPLL	0x80
/* colour-difference output enable (outputs UV0-UV7) */
#define SAA7191_IOCK_OEDC	0x40
/* H-sync output enable */
#define SAA7191_IOCK_OEHS	0x20
/* V-sync output enable */
#define SAA7191_IOCK_OEVS	0x10
/* luminance output enable (outputs Y0-Y7) */
#define SAA7191_IOCK_OEDY	0x08
/* S-VHS bit (chrominance from CVBS or from chrominance input):
 * 0=controlled by BYPS-bit, 1=from chrominance input */
#define SAA7191_IOCK_CHRS	0x04
/* general purpose switch 2
 * VINO-specific: 0=used with CVBS, 1=used with S-Video */
#define SAA7191_IOCK_GPSW2	0x02
/* general purpose switch 1 */
/* VINO-specific: 0=always, 1=not used!*/
#define SAA7191_IOCK_GPSW1	0x01

/* Miscellaneous Control #1 Register definitions */
/* automatic field detection (50/60Hz standard) */
#define SAA7191_CTL3_AUFD	0x80
/* field select: (if AUFD=0)
 * 0=50Hz (625 lines), 1=60Hz (525 lines) */
#define SAA7191_CTL3_FSEL	0x40
/* SECAM cross-colour reduction enable */
#define SAA7191_CTL3_SXCR	0x20
/* sync and clamping pulse enable (HCL and HSY outputs) */
#define SAA7191_CTL3_SCEN	0x10
/* output format: 0=4:1:1, 1=4:2:2 (4:2:2 for VINO) */
#define SAA7191_CTL3_OFTS	0x08
/* luminance delay compensation
 * 0=0*2/LLC,  1=+1*2/LLC, 2=+2*2/LLC, 3=+3*2/LLC,
 * 4=-4*2/LLC, 5=-3*2/LLC, 6=-2*2/LLC, 7=-1*2/LLC
 * step size = 2/LLC = 67.8ns for 50Hz, 81.5ns for 60Hz */
#define SAA7191_CTL3_YDEL_MASK	0x07
#define SAA7191_CTL3_YDEL_SHIFT	0
#define SAA7191_CTL3_YDEL2	0x04
#define SAA7191_CTL3_YDEL1	0x02
#define SAA7191_CTL3_YDEL0	0x01

/* Miscellaneous Control #2 Register definitions */
/* select HREF position
 * 0=normal, HREF is matched to YUV output port,
 * 1=HREF is matched to CVBS input port */
#define SAA7191_CTL4_HRFS	0x04
/* vertical noise reduction
 * 0=normal, 1=searching window, 2=auto-deflection, 3=reduction bypassed */
#define SAA7191_CTL4_VNOI_MASK	0x03
#define SAA7191_CTL4_VNOI_SHIFT	0
#define SAA7191_CTL4_VNOI_3	0x03
#define SAA7191_CTL4_VNOI_2	0x02
#define SAA7191_CTL4_VNOI_1	0x01
#define SAA7191_CTL4_VNOI_0	0x00

/* Chrominance Gain Control Register definitions
 * - for QAM-modulated input signals, effects output amplitude
 * (SECAM gain fixed)
 * (nominal values for UV CCIR level) */
#define SAA7191_CHCV_NTSC	0x2c
#define SAA7191_CHCV_PAL	0x59

/* Driver interface definitions */
#define SAA7191_INPUT_COMPOSITE	0
#define SAA7191_INPUT_SVIDEO	1

#define SAA7191_NORM_PAL	1
#define SAA7191_NORM_NTSC	2
#define SAA7191_NORM_SECAM	3

struct saa7191_status {
	/* 0=no signal, 1=signal detected */
	int signal;
	/* 0=50hz (pal) signal, 1=60hz (ntsc) signal */
	int signal_60hz;
	/* 0=no color detected, 1=color detected */
	int color;

	/* current SAA7191_INPUT_ */
	int input;
	/* current SAA7191_NORM_ */
	int norm;
};

#define SAA7191_BANDPASS_MIN		0x00
#define SAA7191_BANDPASS_MAX		0x03
#define SAA7191_BANDPASS_DEFAULT	0x00

#define SAA7191_BANDPASS_WEIGHT_MIN	0x00
#define SAA7191_BANDPASS_WEIGHT_MAX	0x03
#define SAA7191_BANDPASS_WEIGHT_DEFAULT	0x01

#define SAA7191_CORING_MIN		0x00
#define SAA7191_CORING_MAX		0x03
#define SAA7191_CORING_DEFAULT		0x00

#define SAA7191_HUE_MIN			0x00
#define SAA7191_HUE_MAX			0xff
#define SAA7191_HUE_DEFAULT		0x80

#define SAA7191_VTRC_MIN		0x00
#define SAA7191_VTRC_MAX		0x01
#define SAA7191_VTRC_DEFAULT		0x00

#define SAA7191_FORCE_COLOUR_MIN	0x00
#define SAA7191_FORCE_COLOUR_MAX	0x01
#define SAA7191_FORCE_COLOUR_DEFAULT	0x00

#define SAA7191_CHROMA_GAIN_MIN		0x00
#define SAA7191_CHROMA_GAIN_MAX		0x03
#define SAA7191_CHROMA_GAIN_DEFAULT	0x00

#define SAA7191_LUMA_DELAY_MIN		-0x04
#define SAA7191_LUMA_DELAY_MAX		0x03
#define SAA7191_LUMA_DELAY_DEFAULT	0x01

#define SAA7191_VNR_MIN			0x00
#define SAA7191_VNR_MAX			0x03
#define SAA7191_VNR_DEFAULT		0x00

#define SAA7191_CONTROL_BANDPASS	(V4L2_CID_PRIVATE_BASE + 0)
#define SAA7191_CONTROL_BANDPASS_WEIGHT	(V4L2_CID_PRIVATE_BASE + 1)
#define SAA7191_CONTROL_CORING		(V4L2_CID_PRIVATE_BASE + 2)
#define SAA7191_CONTROL_FORCE_COLOUR	(V4L2_CID_PRIVATE_BASE + 3)
#define SAA7191_CONTROL_CHROMA_GAIN	(V4L2_CID_PRIVATE_BASE + 4)
#define SAA7191_CONTROL_VTRC		(V4L2_CID_PRIVATE_BASE + 5)
#define SAA7191_CONTROL_LUMA_DELAY	(V4L2_CID_PRIVATE_BASE + 6)
#define SAA7191_CONTROL_VNR		(V4L2_CID_PRIVATE_BASE + 7)

#define	DECODER_SAA7191_GET_STATUS	_IOR('d', 195, struct saa7191_status)
#define	DECODER_SAA7191_SET_NORM	_IOW('d', 196, int)

#endif
Commit	Line	Data
d203a7ec RB	1	/*
	2	* saa7191.h - Philips SAA7191 video decoder driver
	3	*
	4	* Copyright (C) 2003 Ladislav Michl <ladis@linux-mips.org>
	5	* Copyright (C) 2004,2005 Mikael Nousiainen <tmnousia@cc.hut.fi>
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*/
	11
	12	#ifndef _SAA7191_H_
	13	#define _SAA7191_H_
	14
	15	/* Philips SAA7191 DMSD I2C bus address */
	16	#define SAA7191_ADDR 0x8a
	17
	18	/* Register subaddresses. */
	19	#define SAA7191_REG_IDEL 0x00
	20	#define SAA7191_REG_HSYB 0x01
	21	#define SAA7191_REG_HSYS 0x02
	22	#define SAA7191_REG_HCLB 0x03
	23	#define SAA7191_REG_HCLS 0x04
	24	#define SAA7191_REG_HPHI 0x05
	25	#define SAA7191_REG_LUMA 0x06
	26	#define SAA7191_REG_HUEC 0x07
a637a114 LM	27	#define SAA7191_REG_CKTQ 0x08 /* bits 3-7 */
a637a114 LM	28	#define SAA7191_REG_CKTS 0x09 /* bits 3-7 */
d203a7ec RB	29	#define SAA7191_REG_PLSE 0x0a
	30	#define SAA7191_REG_SESE 0x0b
	31	#define SAA7191_REG_GAIN 0x0c
	32	#define SAA7191_REG_STDC 0x0d
	33	#define SAA7191_REG_IOCK 0x0e
	34	#define SAA7191_REG_CTL3 0x0f
	35	#define SAA7191_REG_CTL4 0x10
	36	#define SAA7191_REG_CHCV 0x11
	37	#define SAA7191_REG_HS6B 0x14
	38	#define SAA7191_REG_HS6S 0x15
	39	#define SAA7191_REG_HC6B 0x16
	40	#define SAA7191_REG_HC6S 0x17
	41	#define SAA7191_REG_HP6I 0x18
	42	#define SAA7191_REG_STATUS 0xff /* not really a subaddress */
	43
	44	/* Status Register definitions */
	45	#define SAA7191_STATUS_CODE 0x01 /* color detected flag */
a637a114 LM	46	#define SAA7191_STATUS_FIDT 0x20 /* signal type 50/60 Hz */
a637a114 LM	47	#define SAA7191_STATUS_HLCK 0x40 /* PLL unlocked(1)/locked(0) */
d203a7ec RB	48	#define SAA7191_STATUS_STTC 0x80 /* tv/vtr time constant */
	49
	50	/* Luminance Control Register definitions */
a637a114 LM	51	/* input mode select bit:
a637a114 LM	52	* 0=CVBS (chrominance trap active), 1=S-Video (trap bypassed) */
d203a7ec	53	#define SAA7191_LUMA_BYPS 0x80
a637a114 LM	54	/* pre-filter (only when chrominance trap is active) */
	55	#define SAA7191_LUMA_PREF 0x40
	56	/* aperture bandpass to select different characteristics with maximums
	57	* (bits 4-5) */
	58	#define SAA7191_LUMA_BPSS_MASK 0x30
	59	#define SAA7191_LUMA_BPSS_SHIFT 4
	60	#define SAA7191_LUMA_BPSS_3 0x30
	61	#define SAA7191_LUMA_BPSS_2 0x20
	62	#define SAA7191_LUMA_BPSS_1 0x10
	63	#define SAA7191_LUMA_BPSS_0 0x00
	64	/* coring range for high frequency components according to 8-bit luminance
	65	* (bits 2-3)
	66	* 0=coring off, n= (+-)n LSB */
	67	#define SAA7191_LUMA_CORI_MASK 0x0c
	68	#define SAA7191_LUMA_CORI_SHIFT 2
	69	#define SAA7191_LUMA_CORI_3 0x0c
	70	#define SAA7191_LUMA_CORI_2 0x08
	71	#define SAA7191_LUMA_CORI_1 0x04
	72	#define SAA7191_LUMA_CORI_0 0x00
	73	/* aperture bandpass filter weights high frequency components of luminance
	74	* signal (bits 0-1)
	75	* 0=factor 0, 1=0.25, 2=0.5, 3=1 */
	76	#define SAA7191_LUMA_APER_MASK 0x03
	77	#define SAA7191_LUMA_APER_SHIFT 0
	78	#define SAA7191_LUMA_APER_3 0x03
	79	#define SAA7191_LUMA_APER_2 0x02
	80	#define SAA7191_LUMA_APER_1 0x01
	81	#define SAA7191_LUMA_APER_0 0x00
	82
	83	/* Chrominance Gain Control Settings Register definitions */
	84	/* colour on: 0=automatic colour-killer enabled, 1=forced colour on */
d203a7ec	85	#define SAA7191_GAIN_COLO 0x80
a637a114 LM	86	/* chrominance gain control (AGC filter)
	87	* 0=loop filter time constant slow, 1=medium, 2=fast, 3=actual gain */
	88	#define SAA7191_GAIN_LFIS_MASK 0x60
	89	#define SAA7191_GAIN_LFIS_SHIFT 5
	90	#define SAA7191_GAIN_LFIS_3 0x60
	91	#define SAA7191_GAIN_LFIS_2 0x40
	92	#define SAA7191_GAIN_LFIS_1 0x20
	93	#define SAA7191_GAIN_LFIS_0 0x00
d203a7ec RB	94
	95	/* Standard/Mode Control Register definitions */
	96	/* tv/vtr mode bit: 0=TV mode (slow time constant),
	97	* 1=VTR mode (fast time constant) */
	98	#define SAA7191_STDC_VTRC 0x80
a637a114 LM	99	/* SAA7191B-specific functions enable (RTCO, ODD and GPSW0 outputs)
	100	* 0=outputs set to high-impedance (circuit equals SAA7191), 1=enabled */
	101	#define SAA7191_STDC_NFEN 0x08
	102	/* HREF generation: 0=like SAA7191, 1=HREF is 8xLLC2 clocks earlier */
	103	#define SAA7191_STDC_HRMV 0x04
	104	/* general purpose switch 0
	105	* (not used with VINO afaik) */
	106	#define SAA7191_STDC_GPSW0 0x02
d203a7ec RB	107	/* SECAM mode bit: 0=other standards, 1=SECAM */
d203a7ec RB	108	#define SAA7191_STDC_SECS 0x01
d203a7ec RB	109
	110	/* I/O and Clock Control Register definitions */
	111	/* horizontal clock PLL: 0=PLL closed,
	112	* 1=PLL circuit open and horizontal freq fixed */
	113	#define SAA7191_IOCK_HPLL 0x80
a637a114 LM	114	/* colour-difference output enable (outputs UV0-UV7) */
	115	#define SAA7191_IOCK_OEDC 0x40
	116	/* H-sync output enable */
	117	#define SAA7191_IOCK_OEHS 0x20
	118	/* V-sync output enable */
	119	#define SAA7191_IOCK_OEVS 0x10
	120	/* luminance output enable (outputs Y0-Y7) */
	121	#define SAA7191_IOCK_OEDY 0x08
d203a7ec RB	122	/* S-VHS bit (chrominance from CVBS or from chrominance input):
	123	* 0=controlled by BYPS-bit, 1=from chrominance input */
	124	#define SAA7191_IOCK_CHRS 0x04
	125	/* general purpose switch 2
	126	* VINO-specific: 0=used with CVBS, 1=used with S-Video */
	127	#define SAA7191_IOCK_GPSW2 0x02
	128	/* general purpose switch 1 */
	129	/* VINO-specific: 0=always, 1=not used!*/
	130	#define SAA7191_IOCK_GPSW1 0x01
	131
	132	/* Miscellaneous Control #1 Register definitions */
	133	/* automatic field detection (50/60Hz standard) */
	134	#define SAA7191_CTL3_AUFD 0x80
	135	/* field select: (if AUFD=0)
	136	* 0=50Hz (625 lines), 1=60Hz (525 lines) */
	137	#define SAA7191_CTL3_FSEL 0x40
a637a114 LM	138	/* SECAM cross-colour reduction enable */
	139	#define SAA7191_CTL3_SXCR 0x20
	140	/* sync and clamping pulse enable (HCL and HSY outputs) */
	141	#define SAA7191_CTL3_SCEN 0x10
	142	/* output format: 0=4:1:1, 1=4:2:2 (4:2:2 for VINO) */
	143	#define SAA7191_CTL3_OFTS 0x08
	144	/* luminance delay compensation
	145	* 0=02/LLC, 1=+12/LLC, 2=+22/LLC, 3=+32/LLC,
	146	* 4=-42/LLC, 5=-32/LLC, 6=-22/LLC, 7=-12/LLC
	147	* step size = 2/LLC = 67.8ns for 50Hz, 81.5ns for 60Hz */
	148	#define SAA7191_CTL3_YDEL_MASK 0x07
	149	#define SAA7191_CTL3_YDEL_SHIFT 0
	150	#define SAA7191_CTL3_YDEL2 0x04
	151	#define SAA7191_CTL3_YDEL1 0x02
	152	#define SAA7191_CTL3_YDEL0 0x01
	153
	154	/* Miscellaneous Control #2 Register definitions */
	155	/* select HREF position
	156	* 0=normal, HREF is matched to YUV output port,
	157	* 1=HREF is matched to CVBS input port */
	158	#define SAA7191_CTL4_HRFS 0x04
	159	/* vertical noise reduction
	160	* 0=normal, 1=searching window, 2=auto-deflection, 3=reduction bypassed */
	161	#define SAA7191_CTL4_VNOI_MASK 0x03
	162	#define SAA7191_CTL4_VNOI_SHIFT 0
	163	#define SAA7191_CTL4_VNOI_3 0x03
	164	#define SAA7191_CTL4_VNOI_2 0x02
	165	#define SAA7191_CTL4_VNOI_1 0x01
	166	#define SAA7191_CTL4_VNOI_0 0x00
d203a7ec RB	167
d203a7ec RB	168	/* Chrominance Gain Control Register definitions
a637a114 LM	169	* - for QAM-modulated input signals, effects output amplitude
	170	* (SECAM gain fixed)
	171	* (nominal values for UV CCIR level) */
d203a7ec RB	172	#define SAA7191_CHCV_NTSC 0x2c
	173	#define SAA7191_CHCV_PAL 0x59
	174
	175	/* Driver interface definitions */
	176	#define SAA7191_INPUT_COMPOSITE 0
	177	#define SAA7191_INPUT_SVIDEO 1
	178
d203a7ec RB	179	#define SAA7191_NORM_PAL 1
	180	#define SAA7191_NORM_NTSC 2
	181	#define SAA7191_NORM_SECAM 3
d203a7ec RB	182
d203a7ec RB	183	struct saa7191_status {
a637a114	184	/* 0=no signal, 1=signal detected */
d203a7ec RB	185	int signal;
d203a7ec RB	186	/* 0=50hz (pal) signal, 1=60hz (ntsc) signal */
a637a114	187	int signal_60hz;
d203a7ec RB	188	/* 0=no color detected, 1=color detected */
	189	int color;
	190
	191	/* current SAA7191_INPUT_ */
	192	int input;
	193	/* current SAA7191_NORM_ */
	194	int norm;
	195	};
	196
a637a114 LM	197	#define SAA7191_BANDPASS_MIN 0x00
	198	#define SAA7191_BANDPASS_MAX 0x03
	199	#define SAA7191_BANDPASS_DEFAULT 0x00
	200
	201	#define SAA7191_BANDPASS_WEIGHT_MIN 0x00
	202	#define SAA7191_BANDPASS_WEIGHT_MAX 0x03
	203	#define SAA7191_BANDPASS_WEIGHT_DEFAULT 0x01
	204
	205	#define SAA7191_CORING_MIN 0x00
	206	#define SAA7191_CORING_MAX 0x03
	207	#define SAA7191_CORING_DEFAULT 0x00
	208
	209	#define SAA7191_HUE_MIN 0x00
	210	#define SAA7191_HUE_MAX 0xff
	211	#define SAA7191_HUE_DEFAULT 0x80
	212
	213	#define SAA7191_VTRC_MIN 0x00
	214	#define SAA7191_VTRC_MAX 0x01
	215	#define SAA7191_VTRC_DEFAULT 0x00
	216
	217	#define SAA7191_FORCE_COLOUR_MIN 0x00
	218	#define SAA7191_FORCE_COLOUR_MAX 0x01
	219	#define SAA7191_FORCE_COLOUR_DEFAULT 0x00
	220
	221	#define SAA7191_CHROMA_GAIN_MIN 0x00
	222	#define SAA7191_CHROMA_GAIN_MAX 0x03
	223	#define SAA7191_CHROMA_GAIN_DEFAULT 0x00
	224
	225	#define SAA7191_LUMA_DELAY_MIN -0x04
	226	#define SAA7191_LUMA_DELAY_MAX 0x03
	227	#define SAA7191_LUMA_DELAY_DEFAULT 0x01
	228
	229	#define SAA7191_VNR_MIN 0x00
	230	#define SAA7191_VNR_MAX 0x03
	231	#define SAA7191_VNR_DEFAULT 0x00
d203a7ec	232
cf4e9484 HV	233	#define SAA7191_CONTROL_BANDPASS (V4L2_CID_PRIVATE_BASE + 0)
	234	#define SAA7191_CONTROL_BANDPASS_WEIGHT (V4L2_CID_PRIVATE_BASE + 1)
	235	#define SAA7191_CONTROL_CORING (V4L2_CID_PRIVATE_BASE + 2)
	236	#define SAA7191_CONTROL_FORCE_COLOUR (V4L2_CID_PRIVATE_BASE + 3)
	237	#define SAA7191_CONTROL_CHROMA_GAIN (V4L2_CID_PRIVATE_BASE + 4)
	238	#define SAA7191_CONTROL_VTRC (V4L2_CID_PRIVATE_BASE + 5)
	239	#define SAA7191_CONTROL_LUMA_DELAY (V4L2_CID_PRIVATE_BASE + 6)
	240	#define SAA7191_CONTROL_VNR (V4L2_CID_PRIVATE_BASE + 7)
d203a7ec RB	241
	242	#define DECODER_SAA7191_GET_STATUS _IOR('d', 195, struct saa7191_status)
	243	#define DECODER_SAA7191_SET_NORM _IOW('d', 196, int)
d203a7ec RB	244
d203a7ec RB	245	#endif