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[mirror_ubuntu-artful-kernel.git] / drivers / media / i2c / tc358743.c
CommitLineData
d32d9864
MR		 1/*
2 * tc358743 - Toshiba HDMI to CSI-2 bridge
3 *
4 * Copyright 2015 Cisco Systems, Inc. and/or its affiliates. All rights
5 * reserved.
6 *
7 * This program is free software; you may redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
12 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
13 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
14 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
15 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
16 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
17 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
18 * SOFTWARE.
19 *
20 */
21
22/*
23 * References (c = chapter, p = page):
24 * REF_01 - Toshiba, TC358743XBG (H2C), Functional Specification, Rev 0.60
25 * REF_02 - Toshiba, TC358743XBG_HDMI-CSI_Tv11p_nm.xls
26 */
27
28#include <linux/kernel.h>
29#include <linux/module.h>
30#include <linux/slab.h>
31#include <linux/i2c.h>
25614824 32#include <linux/clk.h>
d32d9864 33#include <linux/delay.h>
25614824 34#include <linux/gpio/consumer.h>
d747b806 35#include <linux/interrupt.h>
d32d9864
MR		 36#include <linux/videodev2.h>
37#include <linux/workqueue.h>
38#include <linux/v4l2-dv-timings.h>
39#include <linux/hdmi.h>
40#include <media/v4l2-dv-timings.h>
41#include <media/v4l2-device.h>
42#include <media/v4l2-ctrls.h>
1140f919 43#include <media/v4l2-event.h>
25614824 44#include <media/v4l2-of.h>
b5dcee22 45#include <media/i2c/tc358743.h>
d32d9864
MR		 46
47#include "tc358743_regs.h"
48
49static int debug;
50module_param(debug, int, 0644);
51MODULE_PARM_DESC(debug, "debug level (0-3)");
52
53MODULE_DESCRIPTION("Toshiba TC358743 HDMI to CSI-2 bridge driver");
54MODULE_AUTHOR("Ramakrishnan Muthukrishnan <ram@rkrishnan.org>");
55MODULE_AUTHOR("Mikhail Khelik <mkhelik@cisco.com>");
56MODULE_AUTHOR("Mats Randgaard <matrandg@cisco.com>");
57MODULE_LICENSE("GPL");
58
59#define EDID_NUM_BLOCKS_MAX 8
60#define EDID_BLOCK_SIZE 128
61
fcae73fa 62#define I2C_MAX_XFER_SIZE (EDID_BLOCK_SIZE + 2)
1d88f831 63
d32d9864
MR		 64static const struct v4l2_dv_timings_cap tc358743_timings_cap = {
65 .type = V4L2_DV_BT_656_1120,
66 /* keep this initialization for compatibility with GCC < 4.4.6 */
67 .reserved = { 0 },
68 /* Pixel clock from REF_01 p. 20. Min/max height/width are unknown */
69 V4L2_INIT_BT_TIMINGS(1, 10000, 1, 10000, 0, 165000000,
70 V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
71 V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT,
72 V4L2_DV_BT_CAP_PROGRESSIVE |
73 V4L2_DV_BT_CAP_REDUCED_BLANKING |
74 V4L2_DV_BT_CAP_CUSTOM)
75};
76
77struct tc358743_state {
78 struct tc358743_platform_data pdata;
25614824 79 struct v4l2_of_bus_mipi_csi2 bus;
d32d9864
MR		 80 struct v4l2_subdev sd;
81 struct media_pad pad;
82 struct v4l2_ctrl_handler hdl;
83 struct i2c_client *i2c_client;
84 /* CONFCTL is modified in ops and tc358743_hdmi_sys_int_handler */
85 struct mutex confctl_mutex;
86
87 /* controls */
88 struct v4l2_ctrl *detect_tx_5v_ctrl;
89 struct v4l2_ctrl *audio_sampling_rate_ctrl;
90 struct v4l2_ctrl *audio_present_ctrl;
91
d32d9864
MR		 92 struct delayed_work delayed_work_enable_hotplug;
93
94 /* edid */
95 u8 edid_blocks_written;
96
97 struct v4l2_dv_timings timings;
98 u32 mbus_fmt_code;
59e34ba8 99 u8 csi_lanes_in_use;
25614824
PZ		 100
101 struct gpio_desc *reset_gpio;
d32d9864
MR		 102};
103
104static void tc358743_enable_interrupts(struct v4l2_subdev *sd,
105 bool cable_connected);
106static int tc358743_s_ctrl_detect_tx_5v(struct v4l2_subdev *sd);
107
108static inline struct tc358743_state *to_state(struct v4l2_subdev *sd)
109{
110 return container_of(sd, struct tc358743_state, sd);
111}
112
113/* --------------- I2C --------------- */
114
115static void i2c_rd(struct v4l2_subdev *sd, u16 reg, u8 *values, u32 n)
116{
117 struct tc358743_state *state = to_state(sd);
118 struct i2c_client *client = state->i2c_client;
119 int err;
120 u8 buf[2] = { reg >> 8, reg & 0xff };
121 struct i2c_msg msgs[] = {
122 {
123 .addr = client->addr,
124 .flags = 0,
125 .len = 2,
126 .buf = buf,
127 },
128 {
129 .addr = client->addr,
130 .flags = I2C_M_RD,
131 .len = n,
132 .buf = values,
133 },
134 };
135
136 err = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
137 if (err != ARRAY_SIZE(msgs)) {
138 v4l2_err(sd, "%s: reading register 0x%x from 0x%x failed\n",
139 __func__, reg, client->addr);
140 }
141}
142
143static void i2c_wr(struct v4l2_subdev *sd, u16 reg, u8 *values, u32 n)
144{
145 struct tc358743_state *state = to_state(sd);
146 struct i2c_client *client = state->i2c_client;
147 int err, i;
148 struct i2c_msg msg;
fcae73fa 149 u8 data[I2C_MAX_XFER_SIZE];
1d88f831 150
fcae73fa
MR		 151 if ((2 + n) > I2C_MAX_XFER_SIZE) {
152 n = I2C_MAX_XFER_SIZE - 2;
1d88f831
MCC		 153 v4l2_warn(sd, "i2c wr reg=%04x: len=%d is too big!\n",
154 reg, 2 + n);
fcae73fa 155 }
d32d9864
MR		 156
157 msg.addr = client->addr;
158 msg.buf = data;
159 msg.len = 2 + n;
160 msg.flags = 0;
161
162 data[0] = reg >> 8;
163 data[1] = reg & 0xff;
164
165 for (i = 0; i < n; i++)
166 data[2 + i] = values[i];
167
168 err = i2c_transfer(client->adapter, &msg, 1);
169 if (err != 1) {
170 v4l2_err(sd, "%s: writing register 0x%x from 0x%x failed\n",
171 __func__, reg, client->addr);
172 return;
173 }
174
175 if (debug < 3)
176 return;
177
178 switch (n) {
179 case 1:
180 v4l2_info(sd, "I2C write 0x%04x = 0x%02x",
181 reg, data[2]);
182 break;
183 case 2:
184 v4l2_info(sd, "I2C write 0x%04x = 0x%02x%02x",
185 reg, data[3], data[2]);
186 break;
187 case 4:
188 v4l2_info(sd, "I2C write 0x%04x = 0x%02x%02x%02x%02x",
189 reg, data[5], data[4], data[3], data[2]);
190 break;
191 default:
192 v4l2_info(sd, "I2C write %d bytes from address 0x%04x\n",
193 n, reg);
194 }
195}
196
197static u8 i2c_rd8(struct v4l2_subdev *sd, u16 reg)
198{
199 u8 val;
200
201 i2c_rd(sd, reg, &val, 1);
202
203 return val;
204}
205
206static void i2c_wr8(struct v4l2_subdev *sd, u16 reg, u8 val)
207{
208 i2c_wr(sd, reg, &val, 1);
209}
210
211static void i2c_wr8_and_or(struct v4l2_subdev *sd, u16 reg,
212 u8 mask, u8 val)
213{
214 i2c_wr8(sd, reg, (i2c_rd8(sd, reg) & mask) | val);
215}
216
217static u16 i2c_rd16(struct v4l2_subdev *sd, u16 reg)
218{
219 u16 val;
220
221 i2c_rd(sd, reg, (u8 *)&val, 2);
222
223 return val;
224}
225
226static void i2c_wr16(struct v4l2_subdev *sd, u16 reg, u16 val)
227{
228 i2c_wr(sd, reg, (u8 *)&val, 2);
229}
230
231static void i2c_wr16_and_or(struct v4l2_subdev *sd, u16 reg, u16 mask, u16 val)
232{
233 i2c_wr16(sd, reg, (i2c_rd16(sd, reg) & mask) | val);
234}
235
236static u32 i2c_rd32(struct v4l2_subdev *sd, u16 reg)
237{
238 u32 val;
239
240 i2c_rd(sd, reg, (u8 *)&val, 4);
241
242 return val;
243}
244
245static void i2c_wr32(struct v4l2_subdev *sd, u16 reg, u32 val)
246{
247 i2c_wr(sd, reg, (u8 *)&val, 4);
248}
249
250/* --------------- STATUS --------------- */
251
252static inline bool is_hdmi(struct v4l2_subdev *sd)
253{
254 return i2c_rd8(sd, SYS_STATUS) & MASK_S_HDMI;
255}
256
257static inline bool tx_5v_power_present(struct v4l2_subdev *sd)
258{
259 return i2c_rd8(sd, SYS_STATUS) & MASK_S_DDC5V;
260}
261
262static inline bool no_signal(struct v4l2_subdev *sd)
263{
264 return !(i2c_rd8(sd, SYS_STATUS) & MASK_S_TMDS);
265}
266
267static inline bool no_sync(struct v4l2_subdev *sd)
268{
269 return !(i2c_rd8(sd, SYS_STATUS) & MASK_S_SYNC);
270}
271
272static inline bool audio_present(struct v4l2_subdev *sd)
273{
274 return i2c_rd8(sd, AU_STATUS0) & MASK_S_A_SAMPLE;
275}
276
277static int get_audio_sampling_rate(struct v4l2_subdev *sd)
278{
279 static const int code_to_rate[] = {
280 44100, 0, 48000, 32000, 22050, 384000, 24000, 352800,
281 88200, 768000, 96000, 705600, 176400, 0, 192000, 0
282 };
283
284 /* Register FS_SET is not cleared when the cable is disconnected */
285 if (no_signal(sd))
286 return 0;
287
288 return code_to_rate[i2c_rd8(sd, FS_SET) & MASK_FS];
289}
290
d32d9864
MR		 291/* --------------- TIMINGS --------------- */
292
293static inline unsigned fps(const struct v4l2_bt_timings *t)
294{
295 if (!V4L2_DV_BT_FRAME_HEIGHT(t) || !V4L2_DV_BT_FRAME_WIDTH(t))
296 return 0;
297
298 return DIV_ROUND_CLOSEST((unsigned)t->pixelclock,
299 V4L2_DV_BT_FRAME_HEIGHT(t) * V4L2_DV_BT_FRAME_WIDTH(t));
300}
301
302static int tc358743_get_detected_timings(struct v4l2_subdev *sd,
303 struct v4l2_dv_timings *timings)
304{
305 struct v4l2_bt_timings *bt = &timings->bt;
306 unsigned width, height, frame_width, frame_height, frame_interval, fps;
307
308 memset(timings, 0, sizeof(struct v4l2_dv_timings));
309
310 if (no_signal(sd)) {
311 v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__);
312 return -ENOLINK;
313 }
314 if (no_sync(sd)) {
315 v4l2_dbg(1, debug, sd, "%s: no sync on signal\n", __func__);
316 return -ENOLCK;
317 }
318
319 timings->type = V4L2_DV_BT_656_1120;
320 bt->interlaced = i2c_rd8(sd, VI_STATUS1) & MASK_S_V_INTERLACE ?
321 V4L2_DV_INTERLACED : V4L2_DV_PROGRESSIVE;
322
323 width = ((i2c_rd8(sd, DE_WIDTH_H_HI) & 0x1f) << 8) +
324 i2c_rd8(sd, DE_WIDTH_H_LO);
325 height = ((i2c_rd8(sd, DE_WIDTH_V_HI) & 0x1f) << 8) +
326 i2c_rd8(sd, DE_WIDTH_V_LO);
327 frame_width = ((i2c_rd8(sd, H_SIZE_HI) & 0x1f) << 8) +
328 i2c_rd8(sd, H_SIZE_LO);
329 frame_height = (((i2c_rd8(sd, V_SIZE_HI) & 0x3f) << 8) +
330 i2c_rd8(sd, V_SIZE_LO)) / 2;
331 /* frame interval in milliseconds * 10
332 * Require SYS_FREQ0 and SYS_FREQ1 are precisely set */
333 frame_interval = ((i2c_rd8(sd, FV_CNT_HI) & 0x3) << 8) +
334 i2c_rd8(sd, FV_CNT_LO);
335 fps = (frame_interval > 0) ?
336 DIV_ROUND_CLOSEST(10000, frame_interval) : 0;
337
338 bt->width = width;
339 bt->height = height;
340 bt->vsync = frame_height - height;
341 bt->hsync = frame_width - width;
342 bt->pixelclock = frame_width * frame_height * fps;
343 if (bt->interlaced == V4L2_DV_INTERLACED) {
344 bt->height *= 2;
345 bt->il_vsync = bt->vsync + 1;
346 bt->pixelclock /= 2;
347 }
348
349 return 0;
350}
351
352/* --------------- HOTPLUG / HDCP / EDID --------------- */
353
354static void tc358743_delayed_work_enable_hotplug(struct work_struct *work)
355{
356 struct delayed_work *dwork = to_delayed_work(work);
357 struct tc358743_state *state = container_of(dwork,
358 struct tc358743_state, delayed_work_enable_hotplug);
359 struct v4l2_subdev *sd = &state->sd;
360
361 v4l2_dbg(2, debug, sd, "%s:\n", __func__);
362
363 i2c_wr8_and_or(sd, HPD_CTL, ~MASK_HPD_OUT0, MASK_HPD_OUT0);
364}
365
366static void tc358743_set_hdmi_hdcp(struct v4l2_subdev *sd, bool enable)
367{
368 v4l2_dbg(2, debug, sd, "%s: %s\n", __func__, enable ?
369 "enable" : "disable");
370
0a1f0850
MR		 371 if (enable) {
372 i2c_wr8_and_or(sd, HDCP_REG3, ~KEY_RD_CMD, KEY_RD_CMD);
373
374 i2c_wr8_and_or(sd, HDCP_MODE, ~MASK_MANUAL_AUTHENTICATION, 0);
375
376 i2c_wr8_and_or(sd, HDCP_REG1, 0xff,
377 MASK_AUTH_UNAUTH_SEL_16_FRAMES |
378 MASK_AUTH_UNAUTH_AUTO);
379
380 i2c_wr8_and_or(sd, HDCP_REG2, ~MASK_AUTO_P3_RESET,
381 SET_AUTO_P3_RESET_FRAMES(0x0f));
382 } else {
383 i2c_wr8_and_or(sd, HDCP_MODE, ~MASK_MANUAL_AUTHENTICATION,
384 MASK_MANUAL_AUTHENTICATION);
385 }
d32d9864
MR		 386}
387
388static void tc358743_disable_edid(struct v4l2_subdev *sd)
389{
390 struct tc358743_state *state = to_state(sd);
391
392 v4l2_dbg(2, debug, sd, "%s:\n", __func__);
393
394 cancel_delayed_work_sync(&state->delayed_work_enable_hotplug);
395
396 /* DDC access to EDID is also disabled when hotplug is disabled. See
397 * register DDC_CTL */
398 i2c_wr8_and_or(sd, HPD_CTL, ~MASK_HPD_OUT0, 0x0);
399}
400
401static void tc358743_enable_edid(struct v4l2_subdev *sd)
402{
403 struct tc358743_state *state = to_state(sd);
404
405 if (state->edid_blocks_written == 0) {
406 v4l2_dbg(2, debug, sd, "%s: no EDID -> no hotplug\n", __func__);
676c002a 407 tc358743_s_ctrl_detect_tx_5v(sd);
d32d9864
MR		 408 return;
409 }
410
411 v4l2_dbg(2, debug, sd, "%s:\n", __func__);
412
413 /* Enable hotplug after 100 ms. DDC access to EDID is also enabled when
414 * hotplug is enabled. See register DDC_CTL */
1ce39546 415 schedule_delayed_work(&state->delayed_work_enable_hotplug, HZ / 10);
d32d9864
MR		 416
417 tc358743_enable_interrupts(sd, true);
418 tc358743_s_ctrl_detect_tx_5v(sd);
419}
420
421static void tc358743_erase_bksv(struct v4l2_subdev *sd)
422{
423 int i;
424
425 for (i = 0; i < 5; i++)
426 i2c_wr8(sd, BKSV + i, 0);
427}
428
429/* --------------- AVI infoframe --------------- */
430
431static void print_avi_infoframe(struct v4l2_subdev *sd)
432{
433 struct i2c_client *client = v4l2_get_subdevdata(sd);
434 struct device *dev = &client->dev;
435 union hdmi_infoframe frame;
436 u8 buffer[HDMI_INFOFRAME_SIZE(AVI)];
437
438 if (!is_hdmi(sd)) {
439 v4l2_info(sd, "DVI-D signal - AVI infoframe not supported\n");
440 return;
441 }
442
443 i2c_rd(sd, PK_AVI_0HEAD, buffer, HDMI_INFOFRAME_SIZE(AVI));
444
445 if (hdmi_infoframe_unpack(&frame, buffer) < 0) {
446 v4l2_err(sd, "%s: unpack of AVI infoframe failed\n", __func__);
447 return;
448 }
449
450 hdmi_infoframe_log(KERN_INFO, dev, &frame);
451}
452
453/* --------------- CTRLS --------------- */
454
455static int tc358743_s_ctrl_detect_tx_5v(struct v4l2_subdev *sd)
456{
457 struct tc358743_state *state = to_state(sd);
458
459 return v4l2_ctrl_s_ctrl(state->detect_tx_5v_ctrl,
460 tx_5v_power_present(sd));
461}
462
463static int tc358743_s_ctrl_audio_sampling_rate(struct v4l2_subdev *sd)
464{
465 struct tc358743_state *state = to_state(sd);
466
467 return v4l2_ctrl_s_ctrl(state->audio_sampling_rate_ctrl,
468 get_audio_sampling_rate(sd));
469}
470
471static int tc358743_s_ctrl_audio_present(struct v4l2_subdev *sd)
472{
473 struct tc358743_state *state = to_state(sd);
474
475 return v4l2_ctrl_s_ctrl(state->audio_present_ctrl,
476 audio_present(sd));
477}
478
479static int tc358743_update_controls(struct v4l2_subdev *sd)
480{
481 int ret = 0;
482
483 ret |= tc358743_s_ctrl_detect_tx_5v(sd);
484 ret |= tc358743_s_ctrl_audio_sampling_rate(sd);
485 ret |= tc358743_s_ctrl_audio_present(sd);
486
487 return ret;
488}
489
490/* --------------- INIT --------------- */
491
492static void tc358743_reset_phy(struct v4l2_subdev *sd)
493{
494 v4l2_dbg(1, debug, sd, "%s:\n", __func__);
495
496 i2c_wr8_and_or(sd, PHY_RST, ~MASK_RESET_CTRL, 0);
497 i2c_wr8_and_or(sd, PHY_RST, ~MASK_RESET_CTRL, MASK_RESET_CTRL);
498}
499
500static void tc358743_reset(struct v4l2_subdev *sd, uint16_t mask)
501{
502 u16 sysctl = i2c_rd16(sd, SYSCTL);
503
504 i2c_wr16(sd, SYSCTL, sysctl | mask);
505 i2c_wr16(sd, SYSCTL, sysctl & ~mask);
506}
507
508static inline void tc358743_sleep_mode(struct v4l2_subdev *sd, bool enable)
509{
510 i2c_wr16_and_or(sd, SYSCTL, ~MASK_SLEEP,
511 enable ? MASK_SLEEP : 0);
512}
513
514static inline void enable_stream(struct v4l2_subdev *sd, bool enable)
515{
516 struct tc358743_state *state = to_state(sd);
517
518 v4l2_dbg(3, debug, sd, "%s: %sable\n",
519 __func__, enable ? "en" : "dis");
520
521 if (enable) {
522 /* It is critical for CSI receiver to see lane transition
523 * LP11->HS. Set to non-continuous mode to enable clock lane
524 * LP11 state. */
525 i2c_wr32(sd, TXOPTIONCNTRL, 0);
526 /* Set to continuous mode to trigger LP11->HS transition */
527 i2c_wr32(sd, TXOPTIONCNTRL, MASK_CONTCLKMODE);
528 /* Unmute video */
529 i2c_wr8(sd, VI_MUTE, MASK_AUTO_MUTE);
530 } else {
531 /* Mute video so that all data lanes go to LSP11 state.
532 * No data is output to CSI Tx block. */
533 i2c_wr8(sd, VI_MUTE, MASK_AUTO_MUTE | MASK_VI_MUTE);
534 }
535
536 mutex_lock(&state->confctl_mutex);
537 i2c_wr16_and_or(sd, CONFCTL, ~(MASK_VBUFEN | MASK_ABUFEN),
538 enable ? (MASK_VBUFEN | MASK_ABUFEN) : 0x0);
539 mutex_unlock(&state->confctl_mutex);
540}
541
542static void tc358743_set_pll(struct v4l2_subdev *sd)
543{
544 struct tc358743_state *state = to_state(sd);
545 struct tc358743_platform_data *pdata = &state->pdata;
546 u16 pllctl0 = i2c_rd16(sd, PLLCTL0);
547 u16 pllctl1 = i2c_rd16(sd, PLLCTL1);
548 u16 pllctl0_new = SET_PLL_PRD(pdata->pll_prd) |
549 SET_PLL_FBD(pdata->pll_fbd);
550 u32 hsck = (pdata->refclk_hz / pdata->pll_prd) * pdata->pll_fbd;
551
552 v4l2_dbg(2, debug, sd, "%s:\n", __func__);
553
554 /* Only rewrite when needed (new value or disabled), since rewriting
555 * triggers another format change event. */
556 if ((pllctl0 != pllctl0_new) || ((pllctl1 & MASK_PLL_EN) == 0)) {
557 u16 pll_frs;
558
559 if (hsck > 500000000)
560 pll_frs = 0x0;
561 else if (hsck > 250000000)
562 pll_frs = 0x1;
563 else if (hsck > 125000000)
564 pll_frs = 0x2;
565 else
566 pll_frs = 0x3;
567
568 v4l2_dbg(1, debug, sd, "%s: updating PLL clock\n", __func__);
569 tc358743_sleep_mode(sd, true);
570 i2c_wr16(sd, PLLCTL0, pllctl0_new);
571 i2c_wr16_and_or(sd, PLLCTL1,
572 ~(MASK_PLL_FRS | MASK_RESETB | MASK_PLL_EN),
573 (SET_PLL_FRS(pll_frs) | MASK_RESETB |
574 MASK_PLL_EN));
575 udelay(10); /* REF_02, Sheet "Source HDMI" */
576 i2c_wr16_and_or(sd, PLLCTL1, ~MASK_CKEN, MASK_CKEN);
577 tc358743_sleep_mode(sd, false);
578 }
579}
580
581static void tc358743_set_ref_clk(struct v4l2_subdev *sd)
582{
583 struct tc358743_state *state = to_state(sd);
584 struct tc358743_platform_data *pdata = &state->pdata;
585 u32 sys_freq;
586 u32 lockdet_ref;
587 u16 fh_min;
588 u16 fh_max;
589
590 BUG_ON(!(pdata->refclk_hz == 26000000 ||
591 pdata->refclk_hz == 27000000 ||
592 pdata->refclk_hz == 42000000));
593
594 sys_freq = pdata->refclk_hz / 10000;
595 i2c_wr8(sd, SYS_FREQ0, sys_freq & 0x00ff);
596 i2c_wr8(sd, SYS_FREQ1, (sys_freq & 0xff00) >> 8);
597
598 i2c_wr8_and_or(sd, PHY_CTL0, ~MASK_PHY_SYSCLK_IND,
599 (pdata->refclk_hz == 42000000) ?
600 MASK_PHY_SYSCLK_IND : 0x0);
601
602 fh_min = pdata->refclk_hz / 100000;
603 i2c_wr8(sd, FH_MIN0, fh_min & 0x00ff);
604 i2c_wr8(sd, FH_MIN1, (fh_min & 0xff00) >> 8);
605
606 fh_max = (fh_min * 66) / 10;
607 i2c_wr8(sd, FH_MAX0, fh_max & 0x00ff);
608 i2c_wr8(sd, FH_MAX1, (fh_max & 0xff00) >> 8);
609
610 lockdet_ref = pdata->refclk_hz / 100;
611 i2c_wr8(sd, LOCKDET_REF0, lockdet_ref & 0x0000ff);
612 i2c_wr8(sd, LOCKDET_REF1, (lockdet_ref & 0x00ff00) >> 8);
613 i2c_wr8(sd, LOCKDET_REF2, (lockdet_ref & 0x0f0000) >> 16);
614
615 i2c_wr8_and_or(sd, NCO_F0_MOD, ~MASK_NCO_F0_MOD,
616 (pdata->refclk_hz == 27000000) ?
617 MASK_NCO_F0_MOD_27MHZ : 0x0);
618}
619
620static void tc358743_set_csi_color_space(struct v4l2_subdev *sd)
621{
622 struct tc358743_state *state = to_state(sd);
623
624 switch (state->mbus_fmt_code) {
625 case MEDIA_BUS_FMT_UYVY8_1X16:
626 v4l2_dbg(2, debug, sd, "%s: YCbCr 422 16-bit\n", __func__);
627 i2c_wr8_and_or(sd, VOUT_SET2,
628 ~(MASK_SEL422 | MASK_VOUT_422FIL_100) & 0xff,
629 MASK_SEL422 | MASK_VOUT_422FIL_100);
630 i2c_wr8_and_or(sd, VI_REP, ~MASK_VOUT_COLOR_SEL & 0xff,
631 MASK_VOUT_COLOR_601_YCBCR_LIMITED);
632 mutex_lock(&state->confctl_mutex);
633 i2c_wr16_and_or(sd, CONFCTL, ~MASK_YCBCRFMT,
634 MASK_YCBCRFMT_422_8_BIT);
635 mutex_unlock(&state->confctl_mutex);
636 break;
637 case MEDIA_BUS_FMT_RGB888_1X24:
638 v4l2_dbg(2, debug, sd, "%s: RGB 888 24-bit\n", __func__);
639 i2c_wr8_and_or(sd, VOUT_SET2,
640 ~(MASK_SEL422 | MASK_VOUT_422FIL_100) & 0xff,
641 0x00);
642 i2c_wr8_and_or(sd, VI_REP, ~MASK_VOUT_COLOR_SEL & 0xff,
643 MASK_VOUT_COLOR_RGB_FULL);
644 mutex_lock(&state->confctl_mutex);
645 i2c_wr16_and_or(sd, CONFCTL, ~MASK_YCBCRFMT, 0);
646 mutex_unlock(&state->confctl_mutex);
647 break;
648 default:
649 v4l2_dbg(2, debug, sd, "%s: Unsupported format code 0x%x\n",
650 __func__, state->mbus_fmt_code);
651 }
652}
653
654static unsigned tc358743_num_csi_lanes_needed(struct v4l2_subdev *sd)
655{
656 struct tc358743_state *state = to_state(sd);
657 struct v4l2_bt_timings *bt = &state->timings.bt;
658 struct tc358743_platform_data *pdata = &state->pdata;
659 u32 bits_pr_pixel =
660 (state->mbus_fmt_code == MEDIA_BUS_FMT_UYVY8_1X16) ? 16 : 24;
661 u32 bps = bt->width * bt->height * fps(bt) * bits_pr_pixel;
662 u32 bps_pr_lane = (pdata->refclk_hz / pdata->pll_prd) * pdata->pll_fbd;
663
664 return DIV_ROUND_UP(bps, bps_pr_lane);
665}
666
667static void tc358743_set_csi(struct v4l2_subdev *sd)
668{
669 struct tc358743_state *state = to_state(sd);
670 struct tc358743_platform_data *pdata = &state->pdata;
671 unsigned lanes = tc358743_num_csi_lanes_needed(sd);
672
673 v4l2_dbg(3, debug, sd, "%s:\n", __func__);
674
59e34ba8
MR		 675 state->csi_lanes_in_use = lanes;
676
d32d9864
MR		 677 tc358743_reset(sd, MASK_CTXRST);
678
679 if (lanes < 1)
680 i2c_wr32(sd, CLW_CNTRL, MASK_CLW_LANEDISABLE);
681 if (lanes < 1)
682 i2c_wr32(sd, D0W_CNTRL, MASK_D0W_LANEDISABLE);
683 if (lanes < 2)
684 i2c_wr32(sd, D1W_CNTRL, MASK_D1W_LANEDISABLE);
685 if (lanes < 3)
686 i2c_wr32(sd, D2W_CNTRL, MASK_D2W_LANEDISABLE);
687 if (lanes < 4)
688 i2c_wr32(sd, D3W_CNTRL, MASK_D3W_LANEDISABLE);
689
690 i2c_wr32(sd, LINEINITCNT, pdata->lineinitcnt);
691 i2c_wr32(sd, LPTXTIMECNT, pdata->lptxtimecnt);
692 i2c_wr32(sd, TCLK_HEADERCNT, pdata->tclk_headercnt);
693 i2c_wr32(sd, TCLK_TRAILCNT, pdata->tclk_trailcnt);
694 i2c_wr32(sd, THS_HEADERCNT, pdata->ths_headercnt);
695 i2c_wr32(sd, TWAKEUP, pdata->twakeup);
696 i2c_wr32(sd, TCLK_POSTCNT, pdata->tclk_postcnt);
697 i2c_wr32(sd, THS_TRAILCNT, pdata->ths_trailcnt);
698 i2c_wr32(sd, HSTXVREGCNT, pdata->hstxvregcnt);
699
700 i2c_wr32(sd, HSTXVREGEN,
701 ((lanes > 0) ? MASK_CLM_HSTXVREGEN : 0x0) |
702 ((lanes > 0) ? MASK_D0M_HSTXVREGEN : 0x0) |
703 ((lanes > 1) ? MASK_D1M_HSTXVREGEN : 0x0) |
704 ((lanes > 2) ? MASK_D2M_HSTXVREGEN : 0x0) |
705 ((lanes > 3) ? MASK_D3M_HSTXVREGEN : 0x0));
706
25614824
PZ		 707 i2c_wr32(sd, TXOPTIONCNTRL, (state->bus.flags &
708 V4L2_MBUS_CSI2_CONTINUOUS_CLOCK) ? MASK_CONTCLKMODE : 0);
d32d9864
MR		 709 i2c_wr32(sd, STARTCNTRL, MASK_START);
710 i2c_wr32(sd, CSI_START, MASK_STRT);
711
712 i2c_wr32(sd, CSI_CONFW, MASK_MODE_SET |
713 MASK_ADDRESS_CSI_CONTROL |
714 MASK_CSI_MODE |
715 MASK_TXHSMD |
716 ((lanes == 4) ? MASK_NOL_4 :
717 (lanes == 3) ? MASK_NOL_3 :
718 (lanes == 2) ? MASK_NOL_2 : MASK_NOL_1));
719
720 i2c_wr32(sd, CSI_CONFW, MASK_MODE_SET |
721 MASK_ADDRESS_CSI_ERR_INTENA | MASK_TXBRK | MASK_QUNK |
722 MASK_WCER | MASK_INER);
723
724 i2c_wr32(sd, CSI_CONFW, MASK_MODE_CLEAR |
725 MASK_ADDRESS_CSI_ERR_HALT | MASK_TXBRK | MASK_QUNK);
726
727 i2c_wr32(sd, CSI_CONFW, MASK_MODE_SET |
728 MASK_ADDRESS_CSI_INT_ENA | MASK_INTER);
729}
730
731static void tc358743_set_hdmi_phy(struct v4l2_subdev *sd)
732{
733 struct tc358743_state *state = to_state(sd);
734 struct tc358743_platform_data *pdata = &state->pdata;
735
736 /* Default settings from REF_02, sheet "Source HDMI"
737 * and custom settings as platform data */
738 i2c_wr8_and_or(sd, PHY_EN, ~MASK_ENABLE_PHY, 0x0);
739 i2c_wr8(sd, PHY_CTL1, SET_PHY_AUTO_RST1_US(1600) |
740 SET_FREQ_RANGE_MODE_CYCLES(1));
741 i2c_wr8_and_or(sd, PHY_CTL2, ~MASK_PHY_AUTO_RSTn,
742 (pdata->hdmi_phy_auto_reset_tmds_detected ?
743 MASK_PHY_AUTO_RST2 : 0) |
744 (pdata->hdmi_phy_auto_reset_tmds_in_range ?
745 MASK_PHY_AUTO_RST3 : 0) |
746 (pdata->hdmi_phy_auto_reset_tmds_valid ?
747 MASK_PHY_AUTO_RST4 : 0));
748 i2c_wr8(sd, PHY_BIAS, 0x40);
749 i2c_wr8(sd, PHY_CSQ, SET_CSQ_CNT_LEVEL(0x0a));
750 i2c_wr8(sd, AVM_CTL, 45);
751 i2c_wr8_and_or(sd, HDMI_DET, ~MASK_HDMI_DET_V,
752 pdata->hdmi_detection_delay << 4);
753 i2c_wr8_and_or(sd, HV_RST, ~(MASK_H_PI_RST | MASK_V_PI_RST),
754 (pdata->hdmi_phy_auto_reset_hsync_out_of_range ?
755 MASK_H_PI_RST : 0) |
756 (pdata->hdmi_phy_auto_reset_vsync_out_of_range ?
757 MASK_V_PI_RST : 0));
758 i2c_wr8_and_or(sd, PHY_EN, ~MASK_ENABLE_PHY, MASK_ENABLE_PHY);
759}
760
761static void tc358743_set_hdmi_audio(struct v4l2_subdev *sd)
762{
763 struct tc358743_state *state = to_state(sd);
764
765 /* Default settings from REF_02, sheet "Source HDMI" */
766 i2c_wr8(sd, FORCE_MUTE, 0x00);
767 i2c_wr8(sd, AUTO_CMD0, MASK_AUTO_MUTE7 | MASK_AUTO_MUTE6 |
768 MASK_AUTO_MUTE5 | MASK_AUTO_MUTE4 |
769 MASK_AUTO_MUTE1 | MASK_AUTO_MUTE0);
770 i2c_wr8(sd, AUTO_CMD1, MASK_AUTO_MUTE9);
771 i2c_wr8(sd, AUTO_CMD2, MASK_AUTO_PLAY3 | MASK_AUTO_PLAY2);
772 i2c_wr8(sd, BUFINIT_START, SET_BUFINIT_START_MS(500));
773 i2c_wr8(sd, FS_MUTE, 0x00);
774 i2c_wr8(sd, FS_IMODE, MASK_NLPCM_SMODE | MASK_FS_SMODE);
775 i2c_wr8(sd, ACR_MODE, MASK_CTS_MODE);
776 i2c_wr8(sd, ACR_MDF0, MASK_ACR_L2MDF_1976_PPM | MASK_ACR_L1MDF_976_PPM);
777 i2c_wr8(sd, ACR_MDF1, MASK_ACR_L3MDF_3906_PPM);
778 i2c_wr8(sd, SDO_MODE1, MASK_SDO_FMT_I2S);
779 i2c_wr8(sd, DIV_MODE, SET_DIV_DLY_MS(100));
780
781 mutex_lock(&state->confctl_mutex);
782 i2c_wr16_and_or(sd, CONFCTL, 0xffff, MASK_AUDCHNUM_2 |
783 MASK_AUDOUTSEL_I2S | MASK_AUTOINDEX);
784 mutex_unlock(&state->confctl_mutex);
785}
786
787static void tc358743_set_hdmi_info_frame_mode(struct v4l2_subdev *sd)
788{
789 /* Default settings from REF_02, sheet "Source HDMI" */
790 i2c_wr8(sd, PK_INT_MODE, MASK_ISRC2_INT_MODE | MASK_ISRC_INT_MODE |
791 MASK_ACP_INT_MODE | MASK_VS_INT_MODE |
792 MASK_SPD_INT_MODE | MASK_MS_INT_MODE |
793 MASK_AUD_INT_MODE | MASK_AVI_INT_MODE);
794 i2c_wr8(sd, NO_PKT_LIMIT, 0x2c);
795 i2c_wr8(sd, NO_PKT_CLR, 0x53);
796 i2c_wr8(sd, ERR_PK_LIMIT, 0x01);
797 i2c_wr8(sd, NO_PKT_LIMIT2, 0x30);
798 i2c_wr8(sd, NO_GDB_LIMIT, 0x10);
799}
800
801static void tc358743_initial_setup(struct v4l2_subdev *sd)
802{
803 struct tc358743_state *state = to_state(sd);
804 struct tc358743_platform_data *pdata = &state->pdata;
805
806 /* CEC and IR are not supported by this driver */
807 i2c_wr16_and_or(sd, SYSCTL, ~(MASK_CECRST | MASK_IRRST),
808 (MASK_CECRST | MASK_IRRST));
809
810 tc358743_reset(sd, MASK_CTXRST | MASK_HDMIRST);
811 tc358743_sleep_mode(sd, false);
812
813 i2c_wr16(sd, FIFOCTL, pdata->fifo_level);
814
815 tc358743_set_ref_clk(sd);
816
817 i2c_wr8_and_or(sd, DDC_CTL, ~MASK_DDC5V_MODE,
818 pdata->ddc5v_delay & MASK_DDC5V_MODE);
819 i2c_wr8_and_or(sd, EDID_MODE, ~MASK_EDID_MODE, MASK_EDID_MODE_E_DDC);
820
821 tc358743_set_hdmi_phy(sd);
822 tc358743_set_hdmi_hdcp(sd, pdata->enable_hdcp);
823 tc358743_set_hdmi_audio(sd);
824 tc358743_set_hdmi_info_frame_mode(sd);
825
826 /* All CE and IT formats are detected as RGB full range in DVI mode */
827 i2c_wr8_and_or(sd, VI_MODE, ~MASK_RGB_DVI, 0);
828
829 i2c_wr8_and_or(sd, VOUT_SET2, ~MASK_VOUTCOLORMODE,
830 MASK_VOUTCOLORMODE_AUTO);
831 i2c_wr8(sd, VOUT_SET3, MASK_VOUT_EXTCNT);
832}
833
834/* --------------- IRQ --------------- */
835
836static void tc358743_format_change(struct v4l2_subdev *sd)
837{
838 struct tc358743_state *state = to_state(sd);
839 struct v4l2_dv_timings timings;
840 const struct v4l2_event tc358743_ev_fmt = {
841 .type = V4L2_EVENT_SOURCE_CHANGE,
842 .u.src_change.changes = V4L2_EVENT_SRC_CH_RESOLUTION,
843 };
844
845 if (tc358743_get_detected_timings(sd, &timings)) {
846 enable_stream(sd, false);
847
2874bf3e 848 v4l2_dbg(1, debug, sd, "%s: No signal\n",
d32d9864
MR		 849 __func__);
850 } else {
85f9e06c 851 if (!v4l2_match_dv_timings(&state->timings, &timings, 0, false))
d32d9864
MR		 852 enable_stream(sd, false);
853
2874bf3e
MR		 854 if (debug)
855 v4l2_print_dv_timings(sd->name,
856 "tc358743_format_change: New format: ",
857 &timings, false);
d32d9864
MR		 858 }
859
abeaca0f
PZ		 860 if (sd->devnode)
861 v4l2_subdev_notify_event(sd, &tc358743_ev_fmt);
d32d9864
MR		 862}
863
864static void tc358743_init_interrupts(struct v4l2_subdev *sd)
865{
866 u16 i;
867
868 /* clear interrupt status registers */
869 for (i = SYS_INT; i <= KEY_INT; i++)
870 i2c_wr8(sd, i, 0xff);
871
872 i2c_wr16(sd, INTSTATUS, 0xffff);
873}
874
875static void tc358743_enable_interrupts(struct v4l2_subdev *sd,
876 bool cable_connected)
877{
878 v4l2_dbg(2, debug, sd, "%s: cable connected = %d\n", __func__,
879 cable_connected);
880
881 if (cable_connected) {
882 i2c_wr8(sd, SYS_INTM, ~(MASK_M_DDC | MASK_M_DVI_DET |
883 MASK_M_HDMI_DET) & 0xff);
884 i2c_wr8(sd, CLK_INTM, ~MASK_M_IN_DE_CHG);
885 i2c_wr8(sd, CBIT_INTM, ~(MASK_M_CBIT_FS | MASK_M_AF_LOCK |
886 MASK_M_AF_UNLOCK) & 0xff);
887 i2c_wr8(sd, AUDIO_INTM, ~MASK_M_BUFINIT_END);
888 i2c_wr8(sd, MISC_INTM, ~MASK_M_SYNC_CHG);
889 } else {
890 i2c_wr8(sd, SYS_INTM, ~MASK_M_DDC & 0xff);
891 i2c_wr8(sd, CLK_INTM, 0xff);
892 i2c_wr8(sd, CBIT_INTM, 0xff);
893 i2c_wr8(sd, AUDIO_INTM, 0xff);
894 i2c_wr8(sd, MISC_INTM, 0xff);
895 }
896}
897
898static void tc358743_hdmi_audio_int_handler(struct v4l2_subdev *sd,
899 bool *handled)
900{
901 u8 audio_int_mask = i2c_rd8(sd, AUDIO_INTM);
902 u8 audio_int = i2c_rd8(sd, AUDIO_INT) & ~audio_int_mask;
903
904 i2c_wr8(sd, AUDIO_INT, audio_int);
905
906 v4l2_dbg(3, debug, sd, "%s: AUDIO_INT = 0x%02x\n", __func__, audio_int);
907
908 tc358743_s_ctrl_audio_sampling_rate(sd);
909 tc358743_s_ctrl_audio_present(sd);
910}
911
912static void tc358743_csi_err_int_handler(struct v4l2_subdev *sd, bool *handled)
913{
914 v4l2_err(sd, "%s: CSI_ERR = 0x%x\n", __func__, i2c_rd32(sd, CSI_ERR));
915
916 i2c_wr32(sd, CSI_INT_CLR, MASK_ICRER);
917}
918
919static void tc358743_hdmi_misc_int_handler(struct v4l2_subdev *sd,
920 bool *handled)
921{
922 u8 misc_int_mask = i2c_rd8(sd, MISC_INTM);
923 u8 misc_int = i2c_rd8(sd, MISC_INT) & ~misc_int_mask;
924
925 i2c_wr8(sd, MISC_INT, misc_int);
926
927 v4l2_dbg(3, debug, sd, "%s: MISC_INT = 0x%02x\n", __func__, misc_int);
928
929 if (misc_int & MASK_I_SYNC_CHG) {
930 /* Reset the HDMI PHY to try to trigger proper lock on the
931 * incoming video format. Erase BKSV to prevent that old keys
932 * are used when a new source is connected. */
933 if (no_sync(sd) || no_signal(sd)) {
934 tc358743_reset_phy(sd);
935 tc358743_erase_bksv(sd);
936 }
937
938 tc358743_format_change(sd);
939
940 misc_int &= ~MASK_I_SYNC_CHG;
941 if (handled)
942 *handled = true;
943 }
944
945 if (misc_int) {
946 v4l2_err(sd, "%s: Unhandled MISC_INT interrupts: 0x%02x\n",
947 __func__, misc_int);
948 }
949}
950
951static void tc358743_hdmi_cbit_int_handler(struct v4l2_subdev *sd,
952 bool *handled)
953{
954 u8 cbit_int_mask = i2c_rd8(sd, CBIT_INTM);
955 u8 cbit_int = i2c_rd8(sd, CBIT_INT) & ~cbit_int_mask;
956
957 i2c_wr8(sd, CBIT_INT, cbit_int);
958
959 v4l2_dbg(3, debug, sd, "%s: CBIT_INT = 0x%02x\n", __func__, cbit_int);
960
961 if (cbit_int & MASK_I_CBIT_FS) {
962
963 v4l2_dbg(1, debug, sd, "%s: Audio sample rate changed\n",
964 __func__);
965 tc358743_s_ctrl_audio_sampling_rate(sd);
966
967 cbit_int &= ~MASK_I_CBIT_FS;
968 if (handled)
969 *handled = true;
970 }
971
972 if (cbit_int & (MASK_I_AF_LOCK | MASK_I_AF_UNLOCK)) {
973
974 v4l2_dbg(1, debug, sd, "%s: Audio present changed\n",
975 __func__);
976 tc358743_s_ctrl_audio_present(sd);
977
978 cbit_int &= ~(MASK_I_AF_LOCK | MASK_I_AF_UNLOCK);
979 if (handled)
980 *handled = true;
981 }
982
983 if (cbit_int) {
984 v4l2_err(sd, "%s: Unhandled CBIT_INT interrupts: 0x%02x\n",
985 __func__, cbit_int);
986 }
987}
988
989static void tc358743_hdmi_clk_int_handler(struct v4l2_subdev *sd, bool *handled)
990{
991 u8 clk_int_mask = i2c_rd8(sd, CLK_INTM);
992 u8 clk_int = i2c_rd8(sd, CLK_INT) & ~clk_int_mask;
993
994 /* Bit 7 and bit 6 are set even when they are masked */
995 i2c_wr8(sd, CLK_INT, clk_int | 0x80 | MASK_I_OUT_H_CHG);
996
997 v4l2_dbg(3, debug, sd, "%s: CLK_INT = 0x%02x\n", __func__, clk_int);
998
999 if (clk_int & (MASK_I_IN_DE_CHG)) {
1000
1001 v4l2_dbg(1, debug, sd, "%s: DE size or position has changed\n",
1002 __func__);
1003
1004 /* If the source switch to a new resolution with the same pixel
1005 * frequency as the existing (e.g. 1080p25 -> 720p50), the
1006 * I_SYNC_CHG interrupt is not always triggered, while the
1007 * I_IN_DE_CHG interrupt seems to work fine. Format change
1008 * notifications are only sent when the signal is stable to
1009 * reduce the number of notifications. */
1010 if (!no_signal(sd) && !no_sync(sd))
1011 tc358743_format_change(sd);
1012
1013 clk_int &= ~(MASK_I_IN_DE_CHG);
1014 if (handled)
1015 *handled = true;
1016 }
1017
1018 if (clk_int) {
1019 v4l2_err(sd, "%s: Unhandled CLK_INT interrupts: 0x%02x\n",
1020 __func__, clk_int);
1021 }
1022}
1023
1024static void tc358743_hdmi_sys_int_handler(struct v4l2_subdev *sd, bool *handled)
1025{
1026 struct tc358743_state *state = to_state(sd);
1027 u8 sys_int_mask = i2c_rd8(sd, SYS_INTM);
1028 u8 sys_int = i2c_rd8(sd, SYS_INT) & ~sys_int_mask;
1029
1030 i2c_wr8(sd, SYS_INT, sys_int);
1031
1032 v4l2_dbg(3, debug, sd, "%s: SYS_INT = 0x%02x\n", __func__, sys_int);
1033
1034 if (sys_int & MASK_I_DDC) {
1035 bool tx_5v = tx_5v_power_present(sd);
1036
1037 v4l2_dbg(1, debug, sd, "%s: Tx 5V power present: %s\n",
1038 __func__, tx_5v ? "yes" : "no");
1039
1040 if (tx_5v) {
1041 tc358743_enable_edid(sd);
1042 } else {
1043 tc358743_enable_interrupts(sd, false);
1044 tc358743_disable_edid(sd);
1045 memset(&state->timings, 0, sizeof(state->timings));
1046 tc358743_erase_bksv(sd);
1047 tc358743_update_controls(sd);
1048 }
1049
1050 sys_int &= ~MASK_I_DDC;
1051 if (handled)
1052 *handled = true;
1053 }
1054
1055 if (sys_int & MASK_I_DVI) {
1056 v4l2_dbg(1, debug, sd, "%s: HDMI->DVI change detected\n",
1057 __func__);
1058
1059 /* Reset the HDMI PHY to try to trigger proper lock on the
1060 * incoming video format. Erase BKSV to prevent that old keys
1061 * are used when a new source is connected. */
1062 if (no_sync(sd) || no_signal(sd)) {
1063 tc358743_reset_phy(sd);
1064 tc358743_erase_bksv(sd);
1065 }
1066
1067 sys_int &= ~MASK_I_DVI;
1068 if (handled)
1069 *handled = true;
1070 }
1071
1072 if (sys_int & MASK_I_HDMI) {
1073 v4l2_dbg(1, debug, sd, "%s: DVI->HDMI change detected\n",
1074 __func__);
1075
1076 /* Register is reset in DVI mode (REF_01, c. 6.6.41) */
1077 i2c_wr8(sd, ANA_CTL, MASK_APPL_PCSX_NORMAL | MASK_ANALOG_ON);
1078
1079 sys_int &= ~MASK_I_HDMI;
1080 if (handled)
1081 *handled = true;
1082 }
1083
1084 if (sys_int) {
1085 v4l2_err(sd, "%s: Unhandled SYS_INT interrupts: 0x%02x\n",
1086 __func__, sys_int);
1087 }
1088}
1089
1090/* --------------- CORE OPS --------------- */
1091
1092static int tc358743_log_status(struct v4l2_subdev *sd)
1093{
1094 struct tc358743_state *state = to_state(sd);
1095 struct v4l2_dv_timings timings;
1096 uint8_t hdmi_sys_status = i2c_rd8(sd, SYS_STATUS);
1097 uint16_t sysctl = i2c_rd16(sd, SYSCTL);
1098 u8 vi_status3 = i2c_rd8(sd, VI_STATUS3);
1099 const int deep_color_mode[4] = { 8, 10, 12, 16 };
1100 static const char * const input_color_space[] = {
1101 "RGB", "YCbCr 601", "Adobe RGB", "YCbCr 709", "NA (4)",
1102 "xvYCC 601", "NA(6)", "xvYCC 709", "NA(8)", "sYCC601",
1103 "NA(10)", "NA(11)", "NA(12)", "Adobe YCC 601"};
1104
1105 v4l2_info(sd, "-----Chip status-----\n");
1106 v4l2_info(sd, "Chip ID: 0x%02x\n",
1107 (i2c_rd16(sd, CHIPID) & MASK_CHIPID) >> 8);
1108 v4l2_info(sd, "Chip revision: 0x%02x\n",
1109 i2c_rd16(sd, CHIPID) & MASK_REVID);
1110 v4l2_info(sd, "Reset: IR: %d, CEC: %d, CSI TX: %d, HDMI: %d\n",
1111 !!(sysctl & MASK_IRRST),
1112 !!(sysctl & MASK_CECRST),
1113 !!(sysctl & MASK_CTXRST),
1114 !!(sysctl & MASK_HDMIRST));
1115 v4l2_info(sd, "Sleep mode: %s\n", sysctl & MASK_SLEEP ? "on" : "off");
1116 v4l2_info(sd, "Cable detected (+5V power): %s\n",
1117 hdmi_sys_status & MASK_S_DDC5V ? "yes" : "no");
1118 v4l2_info(sd, "DDC lines enabled: %s\n",
1119 (i2c_rd8(sd, EDID_MODE) & MASK_EDID_MODE_E_DDC) ?
1120 "yes" : "no");
1121 v4l2_info(sd, "Hotplug enabled: %s\n",
1122 (i2c_rd8(sd, HPD_CTL) & MASK_HPD_OUT0) ?
1123 "yes" : "no");
1124 v4l2_info(sd, "CEC enabled: %s\n",
1125 (i2c_rd16(sd, CECEN) & MASK_CECEN) ? "yes" : "no");
1126 v4l2_info(sd, "-----Signal status-----\n");
1127 v4l2_info(sd, "TMDS signal detected: %s\n",
1128 hdmi_sys_status & MASK_S_TMDS ? "yes" : "no");
1129 v4l2_info(sd, "Stable sync signal: %s\n",
1130 hdmi_sys_status & MASK_S_SYNC ? "yes" : "no");
1131 v4l2_info(sd, "PHY PLL locked: %s\n",
1132 hdmi_sys_status & MASK_S_PHY_PLL ? "yes" : "no");
1133 v4l2_info(sd, "PHY DE detected: %s\n",
1134 hdmi_sys_status & MASK_S_PHY_SCDT ? "yes" : "no");
1135
1136 if (tc358743_get_detected_timings(sd, &timings)) {
1137 v4l2_info(sd, "No video detected\n");
1138 } else {
1139 v4l2_print_dv_timings(sd->name, "Detected format: ", &timings,
1140 true);
1141 }
1142 v4l2_print_dv_timings(sd->name, "Configured format: ", &state->timings,
1143 true);
1144
1145 v4l2_info(sd, "-----CSI-TX status-----\n");
1146 v4l2_info(sd, "Lanes needed: %d\n",
1147 tc358743_num_csi_lanes_needed(sd));
1148 v4l2_info(sd, "Lanes in use: %d\n",
59e34ba8 1149 state->csi_lanes_in_use);
d32d9864
MR		 1150 v4l2_info(sd, "Waiting for particular sync signal: %s\n",
1151 (i2c_rd16(sd, CSI_STATUS) & MASK_S_WSYNC) ?
1152 "yes" : "no");
1153 v4l2_info(sd, "Transmit mode: %s\n",
1154 (i2c_rd16(sd, CSI_STATUS) & MASK_S_TXACT) ?
1155 "yes" : "no");
1156 v4l2_info(sd, "Receive mode: %s\n",
1157 (i2c_rd16(sd, CSI_STATUS) & MASK_S_RXACT) ?
1158 "yes" : "no");
1159 v4l2_info(sd, "Stopped: %s\n",
1160 (i2c_rd16(sd, CSI_STATUS) & MASK_S_HLT) ?
1161 "yes" : "no");
1162 v4l2_info(sd, "Color space: %s\n",
1163 state->mbus_fmt_code == MEDIA_BUS_FMT_UYVY8_1X16 ?
1164 "YCbCr 422 16-bit" :
1165 state->mbus_fmt_code == MEDIA_BUS_FMT_RGB888_1X24 ?
1166 "RGB 888 24-bit" : "Unsupported");
1167
1168 v4l2_info(sd, "-----%s status-----\n", is_hdmi(sd) ? "HDMI" : "DVI-D");
1169 v4l2_info(sd, "HDCP encrypted content: %s\n",
1170 hdmi_sys_status & MASK_S_HDCP ? "yes" : "no");
1171 v4l2_info(sd, "Input color space: %s %s range\n",
1172 input_color_space[(vi_status3 & MASK_S_V_COLOR) >> 1],
1173 (vi_status3 & MASK_LIMITED) ? "limited" : "full");
1174 if (!is_hdmi(sd))
1175 return 0;
1176 v4l2_info(sd, "AV Mute: %s\n", hdmi_sys_status & MASK_S_AVMUTE ? "on" :
1177 "off");
1178 v4l2_info(sd, "Deep color mode: %d-bits per channel\n",
1179 deep_color_mode[(i2c_rd8(sd, VI_STATUS1) &
1180 MASK_S_DEEPCOLOR) >> 2]);
1181 print_avi_infoframe(sd);
1182
1183 return 0;
1184}
1185
1186#ifdef CONFIG_VIDEO_ADV_DEBUG
1187static void tc358743_print_register_map(struct v4l2_subdev *sd)
1188{
85e510a1
HV		 1189 v4l2_info(sd, "0x0000-0x00FF: Global Control Register\n");
1190 v4l2_info(sd, "0x0100-0x01FF: CSI2-TX PHY Register\n");
1191 v4l2_info(sd, "0x0200-0x03FF: CSI2-TX PPI Register\n");
1192 v4l2_info(sd, "0x0400-0x05FF: Reserved\n");
1193 v4l2_info(sd, "0x0600-0x06FF: CEC Register\n");
1194 v4l2_info(sd, "0x0700-0x84FF: Reserved\n");
1195 v4l2_info(sd, "0x8500-0x85FF: HDMIRX System Control Register\n");
1196 v4l2_info(sd, "0x8600-0x86FF: HDMIRX Audio Control Register\n");
1197 v4l2_info(sd, "0x8700-0x87FF: HDMIRX InfoFrame packet data Register\n");
1198 v4l2_info(sd, "0x8800-0x88FF: HDMIRX HDCP Port Register\n");
1199 v4l2_info(sd, "0x8900-0x89FF: HDMIRX Video Output Port & 3D Register\n");
1200 v4l2_info(sd, "0x8A00-0x8BFF: Reserved\n");
1201 v4l2_info(sd, "0x8C00-0x8FFF: HDMIRX EDID-RAM (1024bytes)\n");
1202 v4l2_info(sd, "0x9000-0x90FF: HDMIRX GBD Extraction Control\n");
1203 v4l2_info(sd, "0x9100-0x92FF: HDMIRX GBD RAM read\n");
d32d9864
MR		 1204 v4l2_info(sd, "0x9300- : Reserved\n");
1205}
1206
1207static int tc358743_get_reg_size(u16 address)
1208{
1209 /* REF_01 p. 66-72 */
1210 if (address <= 0x00ff)
1211 return 2;
1212 else if ((address >= 0x0100) && (address <= 0x06FF))
1213 return 4;
1214 else if ((address >= 0x0700) && (address <= 0x84ff))
1215 return 2;
1216 else
1217 return 1;
1218}
1219
1220static int tc358743_g_register(struct v4l2_subdev *sd,
1221 struct v4l2_dbg_register *reg)
1222{
1223 if (reg->reg > 0xffff) {
1224 tc358743_print_register_map(sd);
1225 return -EINVAL;
1226 }
1227
1228 reg->size = tc358743_get_reg_size(reg->reg);
1229
1230 i2c_rd(sd, reg->reg, (u8 *)&reg->val, reg->size);
1231
1232 return 0;
1233}
1234
1235static int tc358743_s_register(struct v4l2_subdev *sd,
1236 const struct v4l2_dbg_register *reg)
1237{
1238 if (reg->reg > 0xffff) {
1239 tc358743_print_register_map(sd);
1240 return -EINVAL;
1241 }
1242
1243 /* It should not be possible for the user to enable HDCP with a simple
1244 * v4l2-dbg command.
1245 *
1246 * DO NOT REMOVE THIS unless all other issues with HDCP have been
1247 * resolved.
1248 */
1249 if (reg->reg == HDCP_MODE ||
1250 reg->reg == HDCP_REG1 ||
1251 reg->reg == HDCP_REG2 ||
1252 reg->reg == HDCP_REG3 ||
1253 reg->reg == BCAPS)
1254 return 0;
1255
1256 i2c_wr(sd, (u16)reg->reg, (u8 *)&reg->val,
1257 tc358743_get_reg_size(reg->reg));
1258
1259 return 0;
1260}
1261#endif
1262
1263static int tc358743_isr(struct v4l2_subdev *sd, u32 status, bool *handled)
1264{
1265 u16 intstatus = i2c_rd16(sd, INTSTATUS);
1266
1267 v4l2_dbg(1, debug, sd, "%s: IntStatus = 0x%04x\n", __func__, intstatus);
1268
1269 if (intstatus & MASK_HDMI_INT) {
1270 u8 hdmi_int0 = i2c_rd8(sd, HDMI_INT0);
1271 u8 hdmi_int1 = i2c_rd8(sd, HDMI_INT1);
1272
1273 if (hdmi_int0 & MASK_I_MISC)
1274 tc358743_hdmi_misc_int_handler(sd, handled);
1275 if (hdmi_int1 & MASK_I_CBIT)
1276 tc358743_hdmi_cbit_int_handler(sd, handled);
1277 if (hdmi_int1 & MASK_I_CLK)
1278 tc358743_hdmi_clk_int_handler(sd, handled);
1279 if (hdmi_int1 & MASK_I_SYS)
1280 tc358743_hdmi_sys_int_handler(sd, handled);
1281 if (hdmi_int1 & MASK_I_AUD)
1282 tc358743_hdmi_audio_int_handler(sd, handled);
1283
1284 i2c_wr16(sd, INTSTATUS, MASK_HDMI_INT);
1285 intstatus &= ~MASK_HDMI_INT;
1286 }
1287
1288 if (intstatus & MASK_CSI_INT) {
1289 u32 csi_int = i2c_rd32(sd, CSI_INT);
1290
1291 if (csi_int & MASK_INTER)
1292 tc358743_csi_err_int_handler(sd, handled);
1293
1294 i2c_wr16(sd, INTSTATUS, MASK_CSI_INT);
1295 intstatus &= ~MASK_CSI_INT;
1296 }
1297
1298 intstatus = i2c_rd16(sd, INTSTATUS);
1299 if (intstatus) {
1300 v4l2_dbg(1, debug, sd,
1301 "%s: Unhandled IntStatus interrupts: 0x%02x\n",
1302 __func__, intstatus);
1303 }
1304
1305 return 0;
1306}
1307
d747b806
PZ		 1308static irqreturn_t tc358743_irq_handler(int irq, void *dev_id)
1309{
1310 struct tc358743_state *state = dev_id;
1311 bool handled;
1312
1313 tc358743_isr(&state->sd, 0, &handled);
1314
1315 return handled ? IRQ_HANDLED : IRQ_NONE;
1316}
1317
1140f919
PZ		 1318static int tc358743_subscribe_event(struct v4l2_subdev *sd, struct v4l2_fh *fh,
1319 struct v4l2_event_subscription *sub)
1320{
1321 switch (sub->type) {
1322 case V4L2_EVENT_SOURCE_CHANGE:
1323 return v4l2_src_change_event_subdev_subscribe(sd, fh, sub);
1324 case V4L2_EVENT_CTRL:
1325 return v4l2_ctrl_subdev_subscribe_event(sd, fh, sub);
1326 default:
1327 return -EINVAL;
1328 }
1329}
1330
d32d9864
MR		 1331/* --------------- VIDEO OPS --------------- */
1332
1333static int tc358743_g_input_status(struct v4l2_subdev *sd, u32 *status)
1334{
1335 *status = 0;
1336 *status |= no_signal(sd) ? V4L2_IN_ST_NO_SIGNAL : 0;
1337 *status |= no_sync(sd) ? V4L2_IN_ST_NO_SYNC : 0;
1338
1339 v4l2_dbg(1, debug, sd, "%s: status = 0x%x\n", __func__, *status);
1340
1341 return 0;
1342}
1343
1344static int tc358743_s_dv_timings(struct v4l2_subdev *sd,
1345 struct v4l2_dv_timings *timings)
1346{
1347 struct tc358743_state *state = to_state(sd);
d32d9864
MR		 1348
1349 if (!timings)
1350 return -EINVAL;
1351
1352 if (debug)
1353 v4l2_print_dv_timings(sd->name, "tc358743_s_dv_timings: ",
1354 timings, false);
1355
85f9e06c 1356 if (v4l2_match_dv_timings(&state->timings, timings, 0, false)) {
d32d9864
MR		 1357 v4l2_dbg(1, debug, sd, "%s: no change\n", __func__);
1358 return 0;
1359 }
1360
d32d9864
MR		 1361 if (!v4l2_valid_dv_timings(timings,
1362 &tc358743_timings_cap, NULL, NULL)) {
1363 v4l2_dbg(1, debug, sd, "%s: timings out of range\n", __func__);
1364 return -ERANGE;
1365 }
1366
1367 state->timings = *timings;
1368
1369 enable_stream(sd, false);
1370 tc358743_set_pll(sd);
1371 tc358743_set_csi(sd);
1372
1373 return 0;
1374}
1375
1376static int tc358743_g_dv_timings(struct v4l2_subdev *sd,
1377 struct v4l2_dv_timings *timings)
1378{
1379 struct tc358743_state *state = to_state(sd);
1380
1381 *timings = state->timings;
1382
1383 return 0;
1384}
1385
1386static int tc358743_enum_dv_timings(struct v4l2_subdev *sd,
1387 struct v4l2_enum_dv_timings *timings)
1388{
1389 if (timings->pad != 0)
1390 return -EINVAL;
1391
1392 return v4l2_enum_dv_timings_cap(timings,
1393 &tc358743_timings_cap, NULL, NULL);
1394}
1395
1396static int tc358743_query_dv_timings(struct v4l2_subdev *sd,
1397 struct v4l2_dv_timings *timings)
1398{
1399 int ret;
1400
1401 ret = tc358743_get_detected_timings(sd, timings);
1402 if (ret)
1403 return ret;
1404
1405 if (debug)
1406 v4l2_print_dv_timings(sd->name, "tc358743_query_dv_timings: ",
1407 timings, false);
1408
1409 if (!v4l2_valid_dv_timings(timings,
1410 &tc358743_timings_cap, NULL, NULL)) {
1411 v4l2_dbg(1, debug, sd, "%s: timings out of range\n", __func__);
1412 return -ERANGE;
1413 }
1414
1415 return 0;
1416}
1417
1418static int tc358743_dv_timings_cap(struct v4l2_subdev *sd,
1419 struct v4l2_dv_timings_cap *cap)
1420{
1421 if (cap->pad != 0)
1422 return -EINVAL;
1423
1424 *cap = tc358743_timings_cap;
1425
1426 return 0;
1427}
1428
1429static int tc358743_g_mbus_config(struct v4l2_subdev *sd,
1430 struct v4l2_mbus_config *cfg)
1431{
59e34ba8
MR		 1432 struct tc358743_state *state = to_state(sd);
1433
d32d9864
MR		 1434 cfg->type = V4L2_MBUS_CSI2;
1435
1436 /* Support for non-continuous CSI-2 clock is missing in the driver */
1437 cfg->flags = V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
1438
59e34ba8 1439 switch (state->csi_lanes_in_use) {
d32d9864
MR		 1440 case 1:
1441 cfg->flags |= V4L2_MBUS_CSI2_1_LANE;
1442 break;
1443 case 2:
1444 cfg->flags |= V4L2_MBUS_CSI2_2_LANE;
1445 break;
1446 case 3:
1447 cfg->flags |= V4L2_MBUS_CSI2_3_LANE;
1448 break;
1449 case 4:
1450 cfg->flags |= V4L2_MBUS_CSI2_4_LANE;
1451 break;
1452 default:
1453 return -EINVAL;
1454 }
1455
1456 return 0;
1457}
1458
1459static int tc358743_s_stream(struct v4l2_subdev *sd, int enable)
1460{
1461 enable_stream(sd, enable);
1462
1463 return 0;
1464}
1465
1466/* --------------- PAD OPS --------------- */
1467
1468static int tc358743_get_fmt(struct v4l2_subdev *sd,
1469 struct v4l2_subdev_pad_config *cfg,
1470 struct v4l2_subdev_format *format)
1471{
1472 struct tc358743_state *state = to_state(sd);
1473 u8 vi_rep = i2c_rd8(sd, VI_REP);
1474
1475 if (format->pad != 0)
1476 return -EINVAL;
1477
1478 format->format.code = state->mbus_fmt_code;
1479 format->format.width = state->timings.bt.width;
1480 format->format.height = state->timings.bt.height;
1481 format->format.field = V4L2_FIELD_NONE;
1482
1483 switch (vi_rep & MASK_VOUT_COLOR_SEL) {
1484 case MASK_VOUT_COLOR_RGB_FULL:
1485 case MASK_VOUT_COLOR_RGB_LIMITED:
1486 format->format.colorspace = V4L2_COLORSPACE_SRGB;
1487 break;
1488 case MASK_VOUT_COLOR_601_YCBCR_LIMITED:
1489 case MASK_VOUT_COLOR_601_YCBCR_FULL:
1490 format->format.colorspace = V4L2_COLORSPACE_SMPTE170M;
1491 break;
1492 case MASK_VOUT_COLOR_709_YCBCR_FULL:
1493 case MASK_VOUT_COLOR_709_YCBCR_LIMITED:
1494 format->format.colorspace = V4L2_COLORSPACE_REC709;
1495 break;
1496 default:
1497 format->format.colorspace = 0;
1498 break;
1499 }
1500
1501 return 0;
1502}
1503
1504static int tc358743_set_fmt(struct v4l2_subdev *sd,
1505 struct v4l2_subdev_pad_config *cfg,
1506 struct v4l2_subdev_format *format)
1507{
1508 struct tc358743_state *state = to_state(sd);
1509
1510 u32 code = format->format.code; /* is overwritten by get_fmt */
1511 int ret = tc358743_get_fmt(sd, cfg, format);
1512
1513 format->format.code = code;
1514
1515 if (ret)
1516 return ret;
1517
1518 switch (code) {
1519 case MEDIA_BUS_FMT_RGB888_1X24:
1520 case MEDIA_BUS_FMT_UYVY8_1X16:
1521 break;
1522 default:
1523 return -EINVAL;
1524 }
1525
1526 if (format->which == V4L2_SUBDEV_FORMAT_TRY)
1527 return 0;
1528
1529 state->mbus_fmt_code = format->format.code;
1530
1531 enable_stream(sd, false);
1532 tc358743_set_pll(sd);
1533 tc358743_set_csi(sd);
1534 tc358743_set_csi_color_space(sd);
1535
1536 return 0;
1537}
1538
1539static int tc358743_g_edid(struct v4l2_subdev *sd,
1540 struct v4l2_subdev_edid *edid)
1541{
1542 struct tc358743_state *state = to_state(sd);
1543
72777724
HV		 1544 memset(edid->reserved, 0, sizeof(edid->reserved));
1545
d32d9864
MR		 1546 if (edid->pad != 0)
1547 return -EINVAL;
1548
1549 if (edid->start_block == 0 && edid->blocks == 0) {
1550 edid->blocks = state->edid_blocks_written;
1551 return 0;
1552 }
1553
1554 if (state->edid_blocks_written == 0)
1555 return -ENODATA;
1556
1557 if (edid->start_block >= state->edid_blocks_written ||
1558 edid->blocks == 0)
1559 return -EINVAL;
1560
1561 if (edid->start_block + edid->blocks > state->edid_blocks_written)
1562 edid->blocks = state->edid_blocks_written - edid->start_block;
1563
1564 i2c_rd(sd, EDID_RAM + (edid->start_block * EDID_BLOCK_SIZE), edid->edid,
1565 edid->blocks * EDID_BLOCK_SIZE);
1566
1567 return 0;
1568}
1569
1570static int tc358743_s_edid(struct v4l2_subdev *sd,
1571 struct v4l2_subdev_edid *edid)
1572{
1573 struct tc358743_state *state = to_state(sd);
1574 u16 edid_len = edid->blocks * EDID_BLOCK_SIZE;
fcae73fa 1575 int i;
d32d9864
MR		 1576
1577 v4l2_dbg(2, debug, sd, "%s, pad %d, start block %d, blocks %d\n",
1578 __func__, edid->pad, edid->start_block, edid->blocks);
1579
72777724
HV		 1580 memset(edid->reserved, 0, sizeof(edid->reserved));
1581
d32d9864
MR		 1582 if (edid->pad != 0)
1583 return -EINVAL;
1584
1585 if (edid->start_block != 0)
1586 return -EINVAL;
1587
1588 if (edid->blocks > EDID_NUM_BLOCKS_MAX) {
1589 edid->blocks = EDID_NUM_BLOCKS_MAX;
1590 return -E2BIG;
1591 }
1592
1593 tc358743_disable_edid(sd);
1594
1595 i2c_wr8(sd, EDID_LEN1, edid_len & 0xff);
1596 i2c_wr8(sd, EDID_LEN2, edid_len >> 8);
1597
1598 if (edid->blocks == 0) {
1599 state->edid_blocks_written = 0;
1600 return 0;
1601 }
1602
fcae73fa
MR		 1603 for (i = 0; i < edid_len; i += EDID_BLOCK_SIZE)
1604 i2c_wr(sd, EDID_RAM + i, edid->edid + i, EDID_BLOCK_SIZE);
d32d9864
MR		 1605
1606 state->edid_blocks_written = edid->blocks;
1607
1608 if (tx_5v_power_present(sd))
1609 tc358743_enable_edid(sd);
1610
1611 return 0;
1612}
1613
1614/* -------------------------------------------------------------------------- */
1615
1616static const struct v4l2_subdev_core_ops tc358743_core_ops = {
1617 .log_status = tc358743_log_status,
1618#ifdef CONFIG_VIDEO_ADV_DEBUG
1619 .g_register = tc358743_g_register,
1620 .s_register = tc358743_s_register,
1621#endif
1622 .interrupt_service_routine = tc358743_isr,
1140f919
PZ		 1623 .subscribe_event = tc358743_subscribe_event,
1624 .unsubscribe_event = v4l2_event_subdev_unsubscribe,
d32d9864
MR		 1625};
1626
1627static const struct v4l2_subdev_video_ops tc358743_video_ops = {
1628 .g_input_status = tc358743_g_input_status,
1629 .s_dv_timings = tc358743_s_dv_timings,
1630 .g_dv_timings = tc358743_g_dv_timings,
1631 .query_dv_timings = tc358743_query_dv_timings,
1632 .g_mbus_config = tc358743_g_mbus_config,
1633 .s_stream = tc358743_s_stream,
1634};
1635
1636static const struct v4l2_subdev_pad_ops tc358743_pad_ops = {
1637 .set_fmt = tc358743_set_fmt,
1638 .get_fmt = tc358743_get_fmt,
1639 .get_edid = tc358743_g_edid,
1640 .set_edid = tc358743_s_edid,
1641 .enum_dv_timings = tc358743_enum_dv_timings,
1642 .dv_timings_cap = tc358743_dv_timings_cap,
1643};
1644
1645static const struct v4l2_subdev_ops tc358743_ops = {
1646 .core = &tc358743_core_ops,
1647 .video = &tc358743_video_ops,
1648 .pad = &tc358743_pad_ops,
1649};
1650
1651/* --------------- CUSTOM CTRLS --------------- */
1652
1653static const struct v4l2_ctrl_config tc358743_ctrl_audio_sampling_rate = {
1654 .id = TC358743_CID_AUDIO_SAMPLING_RATE,
1655 .name = "Audio sampling rate",
1656 .type = V4L2_CTRL_TYPE_INTEGER,
1657 .min = 0,
1658 .max = 768000,
1659 .step = 1,
1660 .def = 0,
1661 .flags = V4L2_CTRL_FLAG_READ_ONLY,
1662};
1663
1664static const struct v4l2_ctrl_config tc358743_ctrl_audio_present = {
1665 .id = TC358743_CID_AUDIO_PRESENT,
1666 .name = "Audio present",
1667 .type = V4L2_CTRL_TYPE_BOOLEAN,
1668 .min = 0,
1669 .max = 1,
1670 .step = 1,
1671 .def = 0,
1672 .flags = V4L2_CTRL_FLAG_READ_ONLY,
1673};
1674
1675/* --------------- PROBE / REMOVE --------------- */
1676
25614824
PZ		 1677#ifdef CONFIG_OF
1678static void tc358743_gpio_reset(struct tc358743_state *state)
1679{
25614824
PZ		 1680 usleep_range(5000, 10000);
1681 gpiod_set_value(state->reset_gpio, 1);
1682 usleep_range(1000, 2000);
1683 gpiod_set_value(state->reset_gpio, 0);
1684 msleep(20);
1685}
1686
1687static int tc358743_probe_of(struct tc358743_state *state)
1688{
1689 struct device *dev = &state->i2c_client->dev;
1690 struct v4l2_of_endpoint *endpoint;
1691 struct device_node *ep;
1692 struct clk *refclk;
1693 u32 bps_pr_lane;
1694 int ret = -EINVAL;
1695
1696 refclk = devm_clk_get(dev, "refclk");
1697 if (IS_ERR(refclk)) {
1698 if (PTR_ERR(refclk) != -EPROBE_DEFER)
1699 dev_err(dev, "failed to get refclk: %ld\n",
1700 PTR_ERR(refclk));
1701 return PTR_ERR(refclk);
1702 }
1703
1704 ep = of_graph_get_next_endpoint(dev->of_node, NULL);
1705 if (!ep) {
1706 dev_err(dev, "missing endpoint node\n");
1707 return -EINVAL;
1708 }
1709
1710 endpoint = v4l2_of_alloc_parse_endpoint(ep);
1711 if (IS_ERR(endpoint)) {
1712 dev_err(dev, "failed to parse endpoint\n");
1713 return PTR_ERR(endpoint);
1714 }
1715
1716 if (endpoint->bus_type != V4L2_MBUS_CSI2 ||
1717 endpoint->bus.mipi_csi2.num_data_lanes == 0 ||
1718 endpoint->nr_of_link_frequencies == 0) {
1719 dev_err(dev, "missing CSI-2 properties in endpoint\n");
1720 goto free_endpoint;
1721 }
1722
1723 state->bus = endpoint->bus.mipi_csi2;
1724
1725 clk_prepare_enable(refclk);
1726
1727 state->pdata.refclk_hz = clk_get_rate(refclk);
1728 state->pdata.ddc5v_delay = DDC5V_DELAY_100_MS;
1729 state->pdata.enable_hdcp = false;
1730 /* A FIFO level of 16 should be enough for 2-lane 720p60 at 594 MHz. */
1731 state->pdata.fifo_level = 16;
1732 /*
1733 * The PLL input clock is obtained by dividing refclk by pll_prd.
1734 * It must be between 6 MHz and 40 MHz, lower frequency is better.
1735 */
1736 switch (state->pdata.refclk_hz) {
1737 case 26000000:
1738 case 27000000:
1739 case 42000000:
1740 state->pdata.pll_prd = state->pdata.refclk_hz / 6000000;
1741 break;
1742 default:
1743 dev_err(dev, "unsupported refclk rate: %u Hz\n",
1744 state->pdata.refclk_hz);
1745 goto disable_clk;
1746 }
1747
1748 /*
1749 * The CSI bps per lane must be between 62.5 Mbps and 1 Gbps.
1750 * The default is 594 Mbps for 4-lane 1080p60 or 2-lane 720p60.
1751 */
1752 bps_pr_lane = 2 * endpoint->link_frequencies[0];
1753 if (bps_pr_lane < 62500000U || bps_pr_lane > 1000000000U) {
1754 dev_err(dev, "unsupported bps per lane: %u bps\n", bps_pr_lane);
1755 goto disable_clk;
1756 }
1757
1758 /* The CSI speed per lane is refclk / pll_prd * pll_fbd */
1759 state->pdata.pll_fbd = bps_pr_lane /
1760 state->pdata.refclk_hz * state->pdata.pll_prd;
1761
1762 /*
1763 * FIXME: These timings are from REF_02 for 594 Mbps per lane (297 MHz
1764 * link frequency). In principle it should be possible to calculate
1765 * them based on link frequency and resolution.
1766 */
1767 if (bps_pr_lane != 594000000U)
1768 dev_warn(dev, "untested bps per lane: %u bps\n", bps_pr_lane);
1769 state->pdata.lineinitcnt = 0xe80;
1770 state->pdata.lptxtimecnt = 0x003;
1771 /* tclk-preparecnt: 3, tclk-zerocnt: 20 */
1772 state->pdata.tclk_headercnt = 0x1403;
1773 state->pdata.tclk_trailcnt = 0x00;
1774 /* ths-preparecnt: 3, ths-zerocnt: 1 */
1775 state->pdata.ths_headercnt = 0x0103;
1776 state->pdata.twakeup = 0x4882;
1777 state->pdata.tclk_postcnt = 0x008;
1778 state->pdata.ths_trailcnt = 0x2;
1779 state->pdata.hstxvregcnt = 0;
1780
1e137d92
UKK		 1781 state->reset_gpio = devm_gpiod_get_optional(dev, "reset",
1782 GPIOD_OUT_LOW);
25614824
PZ		 1783 if (IS_ERR(state->reset_gpio)) {
1784 dev_err(dev, "failed to get reset gpio\n");
1785 ret = PTR_ERR(state->reset_gpio);
1786 goto disable_clk;
1787 }
1788
1e137d92
UKK		 1789 if (state->reset_gpio)
1790 tc358743_gpio_reset(state);
25614824
PZ		 1791
1792 ret = 0;
1793 goto free_endpoint;
1794
1795disable_clk:
1796 clk_disable_unprepare(refclk);
1797free_endpoint:
1798 v4l2_of_free_endpoint(endpoint);
1799 return ret;
1800}
1801#else
1802static inline int tc358743_probe_of(struct tc358743_state *state)
1803{
1804 return -ENODEV;
1805}
1806#endif
1807
d32d9864
MR		 1808static int tc358743_probe(struct i2c_client *client,
1809 const struct i2c_device_id *id)
1810{
1811 static struct v4l2_dv_timings default_timing =
1812 V4L2_DV_BT_CEA_640X480P59_94;
1813 struct tc358743_state *state;
1814 struct tc358743_platform_data *pdata = client->dev.platform_data;
1815 struct v4l2_subdev *sd;
1816 int err;
1817
1818 if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
1819 return -EIO;
1820 v4l_dbg(1, debug, client, "chip found @ 0x%x (%s)\n",
1821 client->addr << 1, client->adapter->name);
1822
1823 state = devm_kzalloc(&client->dev, sizeof(struct tc358743_state),
1824 GFP_KERNEL);
1825 if (!state)
1826 return -ENOMEM;
1827
25614824
PZ		 1828 state->i2c_client = client;
1829
d32d9864 1830 /* platform data */
25614824
PZ		 1831 if (pdata) {
1832 state->pdata = *pdata;
1833 state->bus.flags = V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
1834 } else {
1835 err = tc358743_probe_of(state);
1836 if (err == -ENODEV)
1837 v4l_err(client, "No platform data!\n");
1838 if (err)
1839 return err;
d32d9864 1840 }
d32d9864 1841
d32d9864
MR		 1842 sd = &state->sd;
1843 v4l2_i2c_subdev_init(sd, client, &tc358743_ops);
8ec23da7 1844 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS;
d32d9864
MR		 1845
1846 /* i2c access */
1847 if ((i2c_rd16(sd, CHIPID) & MASK_CHIPID) != 0) {
1848 v4l2_info(sd, "not a TC358743 on address 0x%x\n",
1849 client->addr << 1);
1850 return -ENODEV;
1851 }
1852
1853 /* control handlers */
1854 v4l2_ctrl_handler_init(&state->hdl, 3);
1855
d32d9864
MR		 1856 state->detect_tx_5v_ctrl = v4l2_ctrl_new_std(&state->hdl, NULL,
1857 V4L2_CID_DV_RX_POWER_PRESENT, 0, 1, 0, 0);
1858
1859 /* custom controls */
1860 state->audio_sampling_rate_ctrl = v4l2_ctrl_new_custom(&state->hdl,
1861 &tc358743_ctrl_audio_sampling_rate, NULL);
1862
1863 state->audio_present_ctrl = v4l2_ctrl_new_custom(&state->hdl,
1864 &tc358743_ctrl_audio_present, NULL);
1865
1866 sd->ctrl_handler = &state->hdl;
1867 if (state->hdl.error) {
1868 err = state->hdl.error;
1869 goto err_hdl;
1870 }
1871
1872 if (tc358743_update_controls(sd)) {
1873 err = -ENODEV;
1874 goto err_hdl;
1875 }
1876
4c5211a1 1877 state->pad.flags = MEDIA_PAD_FL_SOURCE;
ab22e77c 1878 err = media_entity_pads_init(&sd->entity, 1, &state->pad);
4c5211a1
PZ		 1879 if (err < 0)
1880 goto err_hdl;
1881
1882 sd->dev = &client->dev;
1883 err = v4l2_async_register_subdev(sd);
1884 if (err < 0)
1885 goto err_hdl;
1886
d32d9864
MR		 1887 mutex_init(&state->confctl_mutex);
1888
1889 INIT_DELAYED_WORK(&state->delayed_work_enable_hotplug,
1890 tc358743_delayed_work_enable_hotplug);
1891
1892 tc358743_initial_setup(sd);
1893
1894 tc358743_s_dv_timings(sd, &default_timing);
1895
1896 state->mbus_fmt_code = MEDIA_BUS_FMT_RGB888_1X24;
1897 tc358743_set_csi_color_space(sd);
1898
1899 tc358743_init_interrupts(sd);
d747b806
PZ		 1900
1901 if (state->i2c_client->irq) {
1902 err = devm_request_threaded_irq(&client->dev,
1903 state->i2c_client->irq,
1904 NULL, tc358743_irq_handler,
1905 IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
1906 "tc358743", state);
1907 if (err)
1908 goto err_work_queues;
1909 }
1910
d32d9864
MR		 1911 tc358743_enable_interrupts(sd, tx_5v_power_present(sd));
1912 i2c_wr16(sd, INTMASK, ~(MASK_HDMI_MSK | MASK_CSI_MSK) & 0xffff);
1913
1914 err = v4l2_ctrl_handler_setup(sd->ctrl_handler);
1915 if (err)
1916 goto err_work_queues;
1917
1918 v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name,
1919 client->addr << 1, client->adapter->name);
1920
1921 return 0;
1922
1923err_work_queues:
1924 cancel_delayed_work(&state->delayed_work_enable_hotplug);
d32d9864
MR		 1925 mutex_destroy(&state->confctl_mutex);
1926err_hdl:
4c5211a1 1927 media_entity_cleanup(&sd->entity);
d32d9864
MR		 1928 v4l2_ctrl_handler_free(&state->hdl);
1929 return err;
1930}
1931
1932static int tc358743_remove(struct i2c_client *client)
1933{
1934 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1935 struct tc358743_state *state = to_state(sd);
1936
1937 cancel_delayed_work(&state->delayed_work_enable_hotplug);
4c5211a1 1938 v4l2_async_unregister_subdev(sd);
d32d9864
MR		 1939 v4l2_device_unregister_subdev(sd);
1940 mutex_destroy(&state->confctl_mutex);
4c5211a1 1941 media_entity_cleanup(&sd->entity);
d32d9864
MR		 1942 v4l2_ctrl_handler_free(&state->hdl);
1943
1944 return 0;
1945}
1946
1947static struct i2c_device_id tc358743_id[] = {
1948 {"tc358743", 0},
1949 {}
1950};
1951
1952MODULE_DEVICE_TABLE(i2c, tc358743_id);
1953
1954static struct i2c_driver tc358743_driver = {
1955 .driver = {
d32d9864
MR		 1956 .name = "tc358743",
1957 },
1958 .probe = tc358743_probe,
1959 .remove = tc358743_remove,
1960 .id_table = tc358743_id,
1961};
1962
1963module_i2c_driver(tc358743_driver);
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