]> git.proxmox.com Git - mirror_ubuntu-artful-kernel.git/blame - drivers/media/i2c/tc358743.c
projects / mirror_ubuntu-artful-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
[media] v4l2-dv-timings: skip standards check for V4L2_DV_BT_CAP_CUSTOM
[mirror_ubuntu-artful-kernel.git] / drivers / media / i2c / tc358743.c
CommitLineData
d32d9864
MR		 1/*
2 * tc358743 - Toshiba HDMI to CSI-2 bridge
3 *
4 * Copyright 2015 Cisco Systems, Inc. and/or its affiliates. All rights
5 * reserved.
6 *
7 * This program is free software; you may redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
12 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
13 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
14 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
15 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
16 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
17 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
18 * SOFTWARE.
19 *
20 */
21
22/*
23 * References (c = chapter, p = page):
24 * REF_01 - Toshiba, TC358743XBG (H2C), Functional Specification, Rev 0.60
25 * REF_02 - Toshiba, TC358743XBG_HDMI-CSI_Tv11p_nm.xls
26 */
27
28#include <linux/kernel.h>
29#include <linux/module.h>
30#include <linux/slab.h>
31#include <linux/i2c.h>
25614824 32#include <linux/clk.h>
d32d9864 33#include <linux/delay.h>
25614824 34#include <linux/gpio/consumer.h>
d747b806 35#include <linux/interrupt.h>
d32d9864
MR		 36#include <linux/videodev2.h>
37#include <linux/workqueue.h>
38#include <linux/v4l2-dv-timings.h>
39#include <linux/hdmi.h>
40#include <media/v4l2-dv-timings.h>
41#include <media/v4l2-device.h>
42#include <media/v4l2-ctrls.h>
1140f919 43#include <media/v4l2-event.h>
25614824 44#include <media/v4l2-of.h>
b5dcee22 45#include <media/i2c/tc358743.h>
d32d9864
MR		 46
47#include "tc358743_regs.h"
48
49static int debug;
50module_param(debug, int, 0644);
51MODULE_PARM_DESC(debug, "debug level (0-3)");
52
53MODULE_DESCRIPTION("Toshiba TC358743 HDMI to CSI-2 bridge driver");
54MODULE_AUTHOR("Ramakrishnan Muthukrishnan <ram@rkrishnan.org>");
55MODULE_AUTHOR("Mikhail Khelik <mkhelik@cisco.com>");
56MODULE_AUTHOR("Mats Randgaard <matrandg@cisco.com>");
57MODULE_LICENSE("GPL");
58
59#define EDID_NUM_BLOCKS_MAX 8
60#define EDID_BLOCK_SIZE 128
61
1d88f831
MCC		 62/* Max transfer size done by I2C transfer functions */
63#define MAX_XFER_SIZE (EDID_NUM_BLOCKS_MAX * EDID_BLOCK_SIZE + 2)
64
d32d9864
MR		 65static const struct v4l2_dv_timings_cap tc358743_timings_cap = {
66 .type = V4L2_DV_BT_656_1120,
67 /* keep this initialization for compatibility with GCC < 4.4.6 */
68 .reserved = { 0 },
69 /* Pixel clock from REF_01 p. 20. Min/max height/width are unknown */
70 V4L2_INIT_BT_TIMINGS(1, 10000, 1, 10000, 0, 165000000,
71 V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
72 V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT,
73 V4L2_DV_BT_CAP_PROGRESSIVE |
74 V4L2_DV_BT_CAP_REDUCED_BLANKING |
75 V4L2_DV_BT_CAP_CUSTOM)
76};
77
78struct tc358743_state {
79 struct tc358743_platform_data pdata;
25614824 80 struct v4l2_of_bus_mipi_csi2 bus;
d32d9864
MR		 81 struct v4l2_subdev sd;
82 struct media_pad pad;
83 struct v4l2_ctrl_handler hdl;
84 struct i2c_client *i2c_client;
85 /* CONFCTL is modified in ops and tc358743_hdmi_sys_int_handler */
86 struct mutex confctl_mutex;
87
88 /* controls */
89 struct v4l2_ctrl *detect_tx_5v_ctrl;
90 struct v4l2_ctrl *audio_sampling_rate_ctrl;
91 struct v4l2_ctrl *audio_present_ctrl;
92
93 /* work queues */
94 struct workqueue_struct *work_queues;
95 struct delayed_work delayed_work_enable_hotplug;
96
97 /* edid */
98 u8 edid_blocks_written;
99
1d88f831
MCC		 100 /* used by i2c_wr() */
101 u8 wr_data[MAX_XFER_SIZE];
102
d32d9864
MR		 103 struct v4l2_dv_timings timings;
104 u32 mbus_fmt_code;
25614824
PZ		 105
106 struct gpio_desc *reset_gpio;
d32d9864
MR		 107};
108
109static void tc358743_enable_interrupts(struct v4l2_subdev *sd,
110 bool cable_connected);
111static int tc358743_s_ctrl_detect_tx_5v(struct v4l2_subdev *sd);
112
113static inline struct tc358743_state *to_state(struct v4l2_subdev *sd)
114{
115 return container_of(sd, struct tc358743_state, sd);
116}
117
118/* --------------- I2C --------------- */
119
120static void i2c_rd(struct v4l2_subdev *sd, u16 reg, u8 *values, u32 n)
121{
122 struct tc358743_state *state = to_state(sd);
123 struct i2c_client *client = state->i2c_client;
124 int err;
125 u8 buf[2] = { reg >> 8, reg & 0xff };
126 struct i2c_msg msgs[] = {
127 {
128 .addr = client->addr,
129 .flags = 0,
130 .len = 2,
131 .buf = buf,
132 },
133 {
134 .addr = client->addr,
135 .flags = I2C_M_RD,
136 .len = n,
137 .buf = values,
138 },
139 };
140
141 err = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
142 if (err != ARRAY_SIZE(msgs)) {
143 v4l2_err(sd, "%s: reading register 0x%x from 0x%x failed\n",
144 __func__, reg, client->addr);
145 }
146}
147
148static void i2c_wr(struct v4l2_subdev *sd, u16 reg, u8 *values, u32 n)
149{
150 struct tc358743_state *state = to_state(sd);
151 struct i2c_client *client = state->i2c_client;
1d88f831 152 u8 *data = state->wr_data;
d32d9864
MR		 153 int err, i;
154 struct i2c_msg msg;
1d88f831
MCC		 155
156 if ((2 + n) > sizeof(state->wr_data))
157 v4l2_warn(sd, "i2c wr reg=%04x: len=%d is too big!\n",
158 reg, 2 + n);
d32d9864
MR		 159
160 msg.addr = client->addr;
161 msg.buf = data;
162 msg.len = 2 + n;
163 msg.flags = 0;
164
165 data[0] = reg >> 8;
166 data[1] = reg & 0xff;
167
168 for (i = 0; i < n; i++)
169 data[2 + i] = values[i];
170
171 err = i2c_transfer(client->adapter, &msg, 1);
172 if (err != 1) {
173 v4l2_err(sd, "%s: writing register 0x%x from 0x%x failed\n",
174 __func__, reg, client->addr);
175 return;
176 }
177
178 if (debug < 3)
179 return;
180
181 switch (n) {
182 case 1:
183 v4l2_info(sd, "I2C write 0x%04x = 0x%02x",
184 reg, data[2]);
185 break;
186 case 2:
187 v4l2_info(sd, "I2C write 0x%04x = 0x%02x%02x",
188 reg, data[3], data[2]);
189 break;
190 case 4:
191 v4l2_info(sd, "I2C write 0x%04x = 0x%02x%02x%02x%02x",
192 reg, data[5], data[4], data[3], data[2]);
193 break;
194 default:
195 v4l2_info(sd, "I2C write %d bytes from address 0x%04x\n",
196 n, reg);
197 }
198}
199
200static u8 i2c_rd8(struct v4l2_subdev *sd, u16 reg)
201{
202 u8 val;
203
204 i2c_rd(sd, reg, &val, 1);
205
206 return val;
207}
208
209static void i2c_wr8(struct v4l2_subdev *sd, u16 reg, u8 val)
210{
211 i2c_wr(sd, reg, &val, 1);
212}
213
214static void i2c_wr8_and_or(struct v4l2_subdev *sd, u16 reg,
215 u8 mask, u8 val)
216{
217 i2c_wr8(sd, reg, (i2c_rd8(sd, reg) & mask) | val);
218}
219
220static u16 i2c_rd16(struct v4l2_subdev *sd, u16 reg)
221{
222 u16 val;
223
224 i2c_rd(sd, reg, (u8 *)&val, 2);
225
226 return val;
227}
228
229static void i2c_wr16(struct v4l2_subdev *sd, u16 reg, u16 val)
230{
231 i2c_wr(sd, reg, (u8 *)&val, 2);
232}
233
234static void i2c_wr16_and_or(struct v4l2_subdev *sd, u16 reg, u16 mask, u16 val)
235{
236 i2c_wr16(sd, reg, (i2c_rd16(sd, reg) & mask) | val);
237}
238
239static u32 i2c_rd32(struct v4l2_subdev *sd, u16 reg)
240{
241 u32 val;
242
243 i2c_rd(sd, reg, (u8 *)&val, 4);
244
245 return val;
246}
247
248static void i2c_wr32(struct v4l2_subdev *sd, u16 reg, u32 val)
249{
250 i2c_wr(sd, reg, (u8 *)&val, 4);
251}
252
253/* --------------- STATUS --------------- */
254
255static inline bool is_hdmi(struct v4l2_subdev *sd)
256{
257 return i2c_rd8(sd, SYS_STATUS) & MASK_S_HDMI;
258}
259
260static inline bool tx_5v_power_present(struct v4l2_subdev *sd)
261{
262 return i2c_rd8(sd, SYS_STATUS) & MASK_S_DDC5V;
263}
264
265static inline bool no_signal(struct v4l2_subdev *sd)
266{
267 return !(i2c_rd8(sd, SYS_STATUS) & MASK_S_TMDS);
268}
269
270static inline bool no_sync(struct v4l2_subdev *sd)
271{
272 return !(i2c_rd8(sd, SYS_STATUS) & MASK_S_SYNC);
273}
274
275static inline bool audio_present(struct v4l2_subdev *sd)
276{
277 return i2c_rd8(sd, AU_STATUS0) & MASK_S_A_SAMPLE;
278}
279
280static int get_audio_sampling_rate(struct v4l2_subdev *sd)
281{
282 static const int code_to_rate[] = {
283 44100, 0, 48000, 32000, 22050, 384000, 24000, 352800,
284 88200, 768000, 96000, 705600, 176400, 0, 192000, 0
285 };
286
287 /* Register FS_SET is not cleared when the cable is disconnected */
288 if (no_signal(sd))
289 return 0;
290
291 return code_to_rate[i2c_rd8(sd, FS_SET) & MASK_FS];
292}
293
294static unsigned tc358743_num_csi_lanes_in_use(struct v4l2_subdev *sd)
295{
296 return ((i2c_rd32(sd, CSI_CONTROL) & MASK_NOL) >> 1) + 1;
297}
298
299/* --------------- TIMINGS --------------- */
300
301static inline unsigned fps(const struct v4l2_bt_timings *t)
302{
303 if (!V4L2_DV_BT_FRAME_HEIGHT(t) || !V4L2_DV_BT_FRAME_WIDTH(t))
304 return 0;
305
306 return DIV_ROUND_CLOSEST((unsigned)t->pixelclock,
307 V4L2_DV_BT_FRAME_HEIGHT(t) * V4L2_DV_BT_FRAME_WIDTH(t));
308}
309
310static int tc358743_get_detected_timings(struct v4l2_subdev *sd,
311 struct v4l2_dv_timings *timings)
312{
313 struct v4l2_bt_timings *bt = &timings->bt;
314 unsigned width, height, frame_width, frame_height, frame_interval, fps;
315
316 memset(timings, 0, sizeof(struct v4l2_dv_timings));
317
318 if (no_signal(sd)) {
319 v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__);
320 return -ENOLINK;
321 }
322 if (no_sync(sd)) {
323 v4l2_dbg(1, debug, sd, "%s: no sync on signal\n", __func__);
324 return -ENOLCK;
325 }
326
327 timings->type = V4L2_DV_BT_656_1120;
328 bt->interlaced = i2c_rd8(sd, VI_STATUS1) & MASK_S_V_INTERLACE ?
329 V4L2_DV_INTERLACED : V4L2_DV_PROGRESSIVE;
330
331 width = ((i2c_rd8(sd, DE_WIDTH_H_HI) & 0x1f) << 8) +
332 i2c_rd8(sd, DE_WIDTH_H_LO);
333 height = ((i2c_rd8(sd, DE_WIDTH_V_HI) & 0x1f) << 8) +
334 i2c_rd8(sd, DE_WIDTH_V_LO);
335 frame_width = ((i2c_rd8(sd, H_SIZE_HI) & 0x1f) << 8) +
336 i2c_rd8(sd, H_SIZE_LO);
337 frame_height = (((i2c_rd8(sd, V_SIZE_HI) & 0x3f) << 8) +
338 i2c_rd8(sd, V_SIZE_LO)) / 2;
339 /* frame interval in milliseconds * 10
340 * Require SYS_FREQ0 and SYS_FREQ1 are precisely set */
341 frame_interval = ((i2c_rd8(sd, FV_CNT_HI) & 0x3) << 8) +
342 i2c_rd8(sd, FV_CNT_LO);
343 fps = (frame_interval > 0) ?
344 DIV_ROUND_CLOSEST(10000, frame_interval) : 0;
345
346 bt->width = width;
347 bt->height = height;
348 bt->vsync = frame_height - height;
349 bt->hsync = frame_width - width;
350 bt->pixelclock = frame_width * frame_height * fps;
351 if (bt->interlaced == V4L2_DV_INTERLACED) {
352 bt->height *= 2;
353 bt->il_vsync = bt->vsync + 1;
354 bt->pixelclock /= 2;
355 }
356
357 return 0;
358}
359
360/* --------------- HOTPLUG / HDCP / EDID --------------- */
361
362static void tc358743_delayed_work_enable_hotplug(struct work_struct *work)
363{
364 struct delayed_work *dwork = to_delayed_work(work);
365 struct tc358743_state *state = container_of(dwork,
366 struct tc358743_state, delayed_work_enable_hotplug);
367 struct v4l2_subdev *sd = &state->sd;
368
369 v4l2_dbg(2, debug, sd, "%s:\n", __func__);
370
371 i2c_wr8_and_or(sd, HPD_CTL, ~MASK_HPD_OUT0, MASK_HPD_OUT0);
372}
373
374static void tc358743_set_hdmi_hdcp(struct v4l2_subdev *sd, bool enable)
375{
376 v4l2_dbg(2, debug, sd, "%s: %s\n", __func__, enable ?
377 "enable" : "disable");
378
379 i2c_wr8_and_or(sd, HDCP_REG1,
380 ~(MASK_AUTH_UNAUTH_SEL | MASK_AUTH_UNAUTH),
381 MASK_AUTH_UNAUTH_SEL_16_FRAMES | MASK_AUTH_UNAUTH_AUTO);
382
383 i2c_wr8_and_or(sd, HDCP_REG2, ~MASK_AUTO_P3_RESET,
384 SET_AUTO_P3_RESET_FRAMES(0x0f));
385
386 /* HDCP is disabled by configuring the receiver as HDCP repeater. The
387 * repeater mode require software support to work, so HDCP
388 * authentication will fail.
389 */
390 i2c_wr8_and_or(sd, HDCP_REG3, ~KEY_RD_CMD, enable ? KEY_RD_CMD : 0);
391 i2c_wr8_and_or(sd, HDCP_MODE, ~(MASK_AUTO_CLR | MASK_MODE_RST_TN),
392 enable ? (MASK_AUTO_CLR | MASK_MODE_RST_TN) : 0);
393
394 /* Apple MacBook Pro gen.8 has a bug that makes it freeze every fifth
395 * second when HDCP is disabled, but the MAX_EXCED bit is handled
396 * correctly and HDCP is disabled on the HDMI output.
397 */
398 i2c_wr8_and_or(sd, BSTATUS1, ~MASK_MAX_EXCED,
399 enable ? 0 : MASK_MAX_EXCED);
400 i2c_wr8_and_or(sd, BCAPS, ~(MASK_REPEATER | MASK_READY),
401 enable ? 0 : MASK_REPEATER | MASK_READY);
402}
403
404static void tc358743_disable_edid(struct v4l2_subdev *sd)
405{
406 struct tc358743_state *state = to_state(sd);
407
408 v4l2_dbg(2, debug, sd, "%s:\n", __func__);
409
410 cancel_delayed_work_sync(&state->delayed_work_enable_hotplug);
411
412 /* DDC access to EDID is also disabled when hotplug is disabled. See
413 * register DDC_CTL */
414 i2c_wr8_and_or(sd, HPD_CTL, ~MASK_HPD_OUT0, 0x0);
415}
416
417static void tc358743_enable_edid(struct v4l2_subdev *sd)
418{
419 struct tc358743_state *state = to_state(sd);
420
421 if (state->edid_blocks_written == 0) {
422 v4l2_dbg(2, debug, sd, "%s: no EDID -> no hotplug\n", __func__);
423 return;
424 }
425
426 v4l2_dbg(2, debug, sd, "%s:\n", __func__);
427
428 /* Enable hotplug after 100 ms. DDC access to EDID is also enabled when
429 * hotplug is enabled. See register DDC_CTL */
430 queue_delayed_work(state->work_queues,
431 &state->delayed_work_enable_hotplug, HZ / 10);
432
433 tc358743_enable_interrupts(sd, true);
434 tc358743_s_ctrl_detect_tx_5v(sd);
435}
436
437static void tc358743_erase_bksv(struct v4l2_subdev *sd)
438{
439 int i;
440
441 for (i = 0; i < 5; i++)
442 i2c_wr8(sd, BKSV + i, 0);
443}
444
445/* --------------- AVI infoframe --------------- */
446
447static void print_avi_infoframe(struct v4l2_subdev *sd)
448{
449 struct i2c_client *client = v4l2_get_subdevdata(sd);
450 struct device *dev = &client->dev;
451 union hdmi_infoframe frame;
452 u8 buffer[HDMI_INFOFRAME_SIZE(AVI)];
453
454 if (!is_hdmi(sd)) {
455 v4l2_info(sd, "DVI-D signal - AVI infoframe not supported\n");
456 return;
457 }
458
459 i2c_rd(sd, PK_AVI_0HEAD, buffer, HDMI_INFOFRAME_SIZE(AVI));
460
461 if (hdmi_infoframe_unpack(&frame, buffer) < 0) {
462 v4l2_err(sd, "%s: unpack of AVI infoframe failed\n", __func__);
463 return;
464 }
465
466 hdmi_infoframe_log(KERN_INFO, dev, &frame);
467}
468
469/* --------------- CTRLS --------------- */
470
471static int tc358743_s_ctrl_detect_tx_5v(struct v4l2_subdev *sd)
472{
473 struct tc358743_state *state = to_state(sd);
474
475 return v4l2_ctrl_s_ctrl(state->detect_tx_5v_ctrl,
476 tx_5v_power_present(sd));
477}
478
479static int tc358743_s_ctrl_audio_sampling_rate(struct v4l2_subdev *sd)
480{
481 struct tc358743_state *state = to_state(sd);
482
483 return v4l2_ctrl_s_ctrl(state->audio_sampling_rate_ctrl,
484 get_audio_sampling_rate(sd));
485}
486
487static int tc358743_s_ctrl_audio_present(struct v4l2_subdev *sd)
488{
489 struct tc358743_state *state = to_state(sd);
490
491 return v4l2_ctrl_s_ctrl(state->audio_present_ctrl,
492 audio_present(sd));
493}
494
495static int tc358743_update_controls(struct v4l2_subdev *sd)
496{
497 int ret = 0;
498
499 ret |= tc358743_s_ctrl_detect_tx_5v(sd);
500 ret |= tc358743_s_ctrl_audio_sampling_rate(sd);
501 ret |= tc358743_s_ctrl_audio_present(sd);
502
503 return ret;
504}
505
506/* --------------- INIT --------------- */
507
508static void tc358743_reset_phy(struct v4l2_subdev *sd)
509{
510 v4l2_dbg(1, debug, sd, "%s:\n", __func__);
511
512 i2c_wr8_and_or(sd, PHY_RST, ~MASK_RESET_CTRL, 0);
513 i2c_wr8_and_or(sd, PHY_RST, ~MASK_RESET_CTRL, MASK_RESET_CTRL);
514}
515
516static void tc358743_reset(struct v4l2_subdev *sd, uint16_t mask)
517{
518 u16 sysctl = i2c_rd16(sd, SYSCTL);
519
520 i2c_wr16(sd, SYSCTL, sysctl | mask);
521 i2c_wr16(sd, SYSCTL, sysctl & ~mask);
522}
523
524static inline void tc358743_sleep_mode(struct v4l2_subdev *sd, bool enable)
525{
526 i2c_wr16_and_or(sd, SYSCTL, ~MASK_SLEEP,
527 enable ? MASK_SLEEP : 0);
528}
529
530static inline void enable_stream(struct v4l2_subdev *sd, bool enable)
531{
532 struct tc358743_state *state = to_state(sd);
533
534 v4l2_dbg(3, debug, sd, "%s: %sable\n",
535 __func__, enable ? "en" : "dis");
536
537 if (enable) {
538 /* It is critical for CSI receiver to see lane transition
539 * LP11->HS. Set to non-continuous mode to enable clock lane
540 * LP11 state. */
541 i2c_wr32(sd, TXOPTIONCNTRL, 0);
542 /* Set to continuous mode to trigger LP11->HS transition */
543 i2c_wr32(sd, TXOPTIONCNTRL, MASK_CONTCLKMODE);
544 /* Unmute video */
545 i2c_wr8(sd, VI_MUTE, MASK_AUTO_MUTE);
546 } else {
547 /* Mute video so that all data lanes go to LSP11 state.
548 * No data is output to CSI Tx block. */
549 i2c_wr8(sd, VI_MUTE, MASK_AUTO_MUTE | MASK_VI_MUTE);
550 }
551
552 mutex_lock(&state->confctl_mutex);
553 i2c_wr16_and_or(sd, CONFCTL, ~(MASK_VBUFEN | MASK_ABUFEN),
554 enable ? (MASK_VBUFEN | MASK_ABUFEN) : 0x0);
555 mutex_unlock(&state->confctl_mutex);
556}
557
558static void tc358743_set_pll(struct v4l2_subdev *sd)
559{
560 struct tc358743_state *state = to_state(sd);
561 struct tc358743_platform_data *pdata = &state->pdata;
562 u16 pllctl0 = i2c_rd16(sd, PLLCTL0);
563 u16 pllctl1 = i2c_rd16(sd, PLLCTL1);
564 u16 pllctl0_new = SET_PLL_PRD(pdata->pll_prd) |
565 SET_PLL_FBD(pdata->pll_fbd);
566 u32 hsck = (pdata->refclk_hz / pdata->pll_prd) * pdata->pll_fbd;
567
568 v4l2_dbg(2, debug, sd, "%s:\n", __func__);
569
570 /* Only rewrite when needed (new value or disabled), since rewriting
571 * triggers another format change event. */
572 if ((pllctl0 != pllctl0_new) || ((pllctl1 & MASK_PLL_EN) == 0)) {
573 u16 pll_frs;
574
575 if (hsck > 500000000)
576 pll_frs = 0x0;
577 else if (hsck > 250000000)
578 pll_frs = 0x1;
579 else if (hsck > 125000000)
580 pll_frs = 0x2;
581 else
582 pll_frs = 0x3;
583
584 v4l2_dbg(1, debug, sd, "%s: updating PLL clock\n", __func__);
585 tc358743_sleep_mode(sd, true);
586 i2c_wr16(sd, PLLCTL0, pllctl0_new);
587 i2c_wr16_and_or(sd, PLLCTL1,
588 ~(MASK_PLL_FRS | MASK_RESETB | MASK_PLL_EN),
589 (SET_PLL_FRS(pll_frs) | MASK_RESETB |
590 MASK_PLL_EN));
591 udelay(10); /* REF_02, Sheet "Source HDMI" */
592 i2c_wr16_and_or(sd, PLLCTL1, ~MASK_CKEN, MASK_CKEN);
593 tc358743_sleep_mode(sd, false);
594 }
595}
596
597static void tc358743_set_ref_clk(struct v4l2_subdev *sd)
598{
599 struct tc358743_state *state = to_state(sd);
600 struct tc358743_platform_data *pdata = &state->pdata;
601 u32 sys_freq;
602 u32 lockdet_ref;
603 u16 fh_min;
604 u16 fh_max;
605
606 BUG_ON(!(pdata->refclk_hz == 26000000 ||
607 pdata->refclk_hz == 27000000 ||
608 pdata->refclk_hz == 42000000));
609
610 sys_freq = pdata->refclk_hz / 10000;
611 i2c_wr8(sd, SYS_FREQ0, sys_freq & 0x00ff);
612 i2c_wr8(sd, SYS_FREQ1, (sys_freq & 0xff00) >> 8);
613
614 i2c_wr8_and_or(sd, PHY_CTL0, ~MASK_PHY_SYSCLK_IND,
615 (pdata->refclk_hz == 42000000) ?
616 MASK_PHY_SYSCLK_IND : 0x0);
617
618 fh_min = pdata->refclk_hz / 100000;
619 i2c_wr8(sd, FH_MIN0, fh_min & 0x00ff);
620 i2c_wr8(sd, FH_MIN1, (fh_min & 0xff00) >> 8);
621
622 fh_max = (fh_min * 66) / 10;
623 i2c_wr8(sd, FH_MAX0, fh_max & 0x00ff);
624 i2c_wr8(sd, FH_MAX1, (fh_max & 0xff00) >> 8);
625
626 lockdet_ref = pdata->refclk_hz / 100;
627 i2c_wr8(sd, LOCKDET_REF0, lockdet_ref & 0x0000ff);
628 i2c_wr8(sd, LOCKDET_REF1, (lockdet_ref & 0x00ff00) >> 8);
629 i2c_wr8(sd, LOCKDET_REF2, (lockdet_ref & 0x0f0000) >> 16);
630
631 i2c_wr8_and_or(sd, NCO_F0_MOD, ~MASK_NCO_F0_MOD,
632 (pdata->refclk_hz == 27000000) ?
633 MASK_NCO_F0_MOD_27MHZ : 0x0);
634}
635
636static void tc358743_set_csi_color_space(struct v4l2_subdev *sd)
637{
638 struct tc358743_state *state = to_state(sd);
639
640 switch (state->mbus_fmt_code) {
641 case MEDIA_BUS_FMT_UYVY8_1X16:
642 v4l2_dbg(2, debug, sd, "%s: YCbCr 422 16-bit\n", __func__);
643 i2c_wr8_and_or(sd, VOUT_SET2,
644 ~(MASK_SEL422 | MASK_VOUT_422FIL_100) & 0xff,
645 MASK_SEL422 | MASK_VOUT_422FIL_100);
646 i2c_wr8_and_or(sd, VI_REP, ~MASK_VOUT_COLOR_SEL & 0xff,
647 MASK_VOUT_COLOR_601_YCBCR_LIMITED);
648 mutex_lock(&state->confctl_mutex);
649 i2c_wr16_and_or(sd, CONFCTL, ~MASK_YCBCRFMT,
650 MASK_YCBCRFMT_422_8_BIT);
651 mutex_unlock(&state->confctl_mutex);
652 break;
653 case MEDIA_BUS_FMT_RGB888_1X24:
654 v4l2_dbg(2, debug, sd, "%s: RGB 888 24-bit\n", __func__);
655 i2c_wr8_and_or(sd, VOUT_SET2,
656 ~(MASK_SEL422 | MASK_VOUT_422FIL_100) & 0xff,
657 0x00);
658 i2c_wr8_and_or(sd, VI_REP, ~MASK_VOUT_COLOR_SEL & 0xff,
659 MASK_VOUT_COLOR_RGB_FULL);
660 mutex_lock(&state->confctl_mutex);
661 i2c_wr16_and_or(sd, CONFCTL, ~MASK_YCBCRFMT, 0);
662 mutex_unlock(&state->confctl_mutex);
663 break;
664 default:
665 v4l2_dbg(2, debug, sd, "%s: Unsupported format code 0x%x\n",
666 __func__, state->mbus_fmt_code);
667 }
668}
669
670static unsigned tc358743_num_csi_lanes_needed(struct v4l2_subdev *sd)
671{
672 struct tc358743_state *state = to_state(sd);
673 struct v4l2_bt_timings *bt = &state->timings.bt;
674 struct tc358743_platform_data *pdata = &state->pdata;
675 u32 bits_pr_pixel =
676 (state->mbus_fmt_code == MEDIA_BUS_FMT_UYVY8_1X16) ? 16 : 24;
677 u32 bps = bt->width * bt->height * fps(bt) * bits_pr_pixel;
678 u32 bps_pr_lane = (pdata->refclk_hz / pdata->pll_prd) * pdata->pll_fbd;
679
680 return DIV_ROUND_UP(bps, bps_pr_lane);
681}
682
683static void tc358743_set_csi(struct v4l2_subdev *sd)
684{
685 struct tc358743_state *state = to_state(sd);
686 struct tc358743_platform_data *pdata = &state->pdata;
687 unsigned lanes = tc358743_num_csi_lanes_needed(sd);
688
689 v4l2_dbg(3, debug, sd, "%s:\n", __func__);
690
691 tc358743_reset(sd, MASK_CTXRST);
692
693 if (lanes < 1)
694 i2c_wr32(sd, CLW_CNTRL, MASK_CLW_LANEDISABLE);
695 if (lanes < 1)
696 i2c_wr32(sd, D0W_CNTRL, MASK_D0W_LANEDISABLE);
697 if (lanes < 2)
698 i2c_wr32(sd, D1W_CNTRL, MASK_D1W_LANEDISABLE);
699 if (lanes < 3)
700 i2c_wr32(sd, D2W_CNTRL, MASK_D2W_LANEDISABLE);
701 if (lanes < 4)
702 i2c_wr32(sd, D3W_CNTRL, MASK_D3W_LANEDISABLE);
703
704 i2c_wr32(sd, LINEINITCNT, pdata->lineinitcnt);
705 i2c_wr32(sd, LPTXTIMECNT, pdata->lptxtimecnt);
706 i2c_wr32(sd, TCLK_HEADERCNT, pdata->tclk_headercnt);
707 i2c_wr32(sd, TCLK_TRAILCNT, pdata->tclk_trailcnt);
708 i2c_wr32(sd, THS_HEADERCNT, pdata->ths_headercnt);
709 i2c_wr32(sd, TWAKEUP, pdata->twakeup);
710 i2c_wr32(sd, TCLK_POSTCNT, pdata->tclk_postcnt);
711 i2c_wr32(sd, THS_TRAILCNT, pdata->ths_trailcnt);
712 i2c_wr32(sd, HSTXVREGCNT, pdata->hstxvregcnt);
713
714 i2c_wr32(sd, HSTXVREGEN,
715 ((lanes > 0) ? MASK_CLM_HSTXVREGEN : 0x0) |
716 ((lanes > 0) ? MASK_D0M_HSTXVREGEN : 0x0) |
717 ((lanes > 1) ? MASK_D1M_HSTXVREGEN : 0x0) |
718 ((lanes > 2) ? MASK_D2M_HSTXVREGEN : 0x0) |
719 ((lanes > 3) ? MASK_D3M_HSTXVREGEN : 0x0));
720
25614824
PZ		 721 i2c_wr32(sd, TXOPTIONCNTRL, (state->bus.flags &
722 V4L2_MBUS_CSI2_CONTINUOUS_CLOCK) ? MASK_CONTCLKMODE : 0);
d32d9864
MR		 723 i2c_wr32(sd, STARTCNTRL, MASK_START);
724 i2c_wr32(sd, CSI_START, MASK_STRT);
725
726 i2c_wr32(sd, CSI_CONFW, MASK_MODE_SET |
727 MASK_ADDRESS_CSI_CONTROL |
728 MASK_CSI_MODE |
729 MASK_TXHSMD |
730 ((lanes == 4) ? MASK_NOL_4 :
731 (lanes == 3) ? MASK_NOL_3 :
732 (lanes == 2) ? MASK_NOL_2 : MASK_NOL_1));
733
734 i2c_wr32(sd, CSI_CONFW, MASK_MODE_SET |
735 MASK_ADDRESS_CSI_ERR_INTENA | MASK_TXBRK | MASK_QUNK |
736 MASK_WCER | MASK_INER);
737
738 i2c_wr32(sd, CSI_CONFW, MASK_MODE_CLEAR |
739 MASK_ADDRESS_CSI_ERR_HALT | MASK_TXBRK | MASK_QUNK);
740
741 i2c_wr32(sd, CSI_CONFW, MASK_MODE_SET |
742 MASK_ADDRESS_CSI_INT_ENA | MASK_INTER);
743}
744
745static void tc358743_set_hdmi_phy(struct v4l2_subdev *sd)
746{
747 struct tc358743_state *state = to_state(sd);
748 struct tc358743_platform_data *pdata = &state->pdata;
749
750 /* Default settings from REF_02, sheet "Source HDMI"
751 * and custom settings as platform data */
752 i2c_wr8_and_or(sd, PHY_EN, ~MASK_ENABLE_PHY, 0x0);
753 i2c_wr8(sd, PHY_CTL1, SET_PHY_AUTO_RST1_US(1600) |
754 SET_FREQ_RANGE_MODE_CYCLES(1));
755 i2c_wr8_and_or(sd, PHY_CTL2, ~MASK_PHY_AUTO_RSTn,
756 (pdata->hdmi_phy_auto_reset_tmds_detected ?
757 MASK_PHY_AUTO_RST2 : 0) |
758 (pdata->hdmi_phy_auto_reset_tmds_in_range ?
759 MASK_PHY_AUTO_RST3 : 0) |
760 (pdata->hdmi_phy_auto_reset_tmds_valid ?
761 MASK_PHY_AUTO_RST4 : 0));
762 i2c_wr8(sd, PHY_BIAS, 0x40);
763 i2c_wr8(sd, PHY_CSQ, SET_CSQ_CNT_LEVEL(0x0a));
764 i2c_wr8(sd, AVM_CTL, 45);
765 i2c_wr8_and_or(sd, HDMI_DET, ~MASK_HDMI_DET_V,
766 pdata->hdmi_detection_delay << 4);
767 i2c_wr8_and_or(sd, HV_RST, ~(MASK_H_PI_RST | MASK_V_PI_RST),
768 (pdata->hdmi_phy_auto_reset_hsync_out_of_range ?
769 MASK_H_PI_RST : 0) |
770 (pdata->hdmi_phy_auto_reset_vsync_out_of_range ?
771 MASK_V_PI_RST : 0));
772 i2c_wr8_and_or(sd, PHY_EN, ~MASK_ENABLE_PHY, MASK_ENABLE_PHY);
773}
774
775static void tc358743_set_hdmi_audio(struct v4l2_subdev *sd)
776{
777 struct tc358743_state *state = to_state(sd);
778
779 /* Default settings from REF_02, sheet "Source HDMI" */
780 i2c_wr8(sd, FORCE_MUTE, 0x00);
781 i2c_wr8(sd, AUTO_CMD0, MASK_AUTO_MUTE7 | MASK_AUTO_MUTE6 |
782 MASK_AUTO_MUTE5 | MASK_AUTO_MUTE4 |
783 MASK_AUTO_MUTE1 | MASK_AUTO_MUTE0);
784 i2c_wr8(sd, AUTO_CMD1, MASK_AUTO_MUTE9);
785 i2c_wr8(sd, AUTO_CMD2, MASK_AUTO_PLAY3 | MASK_AUTO_PLAY2);
786 i2c_wr8(sd, BUFINIT_START, SET_BUFINIT_START_MS(500));
787 i2c_wr8(sd, FS_MUTE, 0x00);
788 i2c_wr8(sd, FS_IMODE, MASK_NLPCM_SMODE | MASK_FS_SMODE);
789 i2c_wr8(sd, ACR_MODE, MASK_CTS_MODE);
790 i2c_wr8(sd, ACR_MDF0, MASK_ACR_L2MDF_1976_PPM | MASK_ACR_L1MDF_976_PPM);
791 i2c_wr8(sd, ACR_MDF1, MASK_ACR_L3MDF_3906_PPM);
792 i2c_wr8(sd, SDO_MODE1, MASK_SDO_FMT_I2S);
793 i2c_wr8(sd, DIV_MODE, SET_DIV_DLY_MS(100));
794
795 mutex_lock(&state->confctl_mutex);
796 i2c_wr16_and_or(sd, CONFCTL, 0xffff, MASK_AUDCHNUM_2 |
797 MASK_AUDOUTSEL_I2S | MASK_AUTOINDEX);
798 mutex_unlock(&state->confctl_mutex);
799}
800
801static void tc358743_set_hdmi_info_frame_mode(struct v4l2_subdev *sd)
802{
803 /* Default settings from REF_02, sheet "Source HDMI" */
804 i2c_wr8(sd, PK_INT_MODE, MASK_ISRC2_INT_MODE | MASK_ISRC_INT_MODE |
805 MASK_ACP_INT_MODE | MASK_VS_INT_MODE |
806 MASK_SPD_INT_MODE | MASK_MS_INT_MODE |
807 MASK_AUD_INT_MODE | MASK_AVI_INT_MODE);
808 i2c_wr8(sd, NO_PKT_LIMIT, 0x2c);
809 i2c_wr8(sd, NO_PKT_CLR, 0x53);
810 i2c_wr8(sd, ERR_PK_LIMIT, 0x01);
811 i2c_wr8(sd, NO_PKT_LIMIT2, 0x30);
812 i2c_wr8(sd, NO_GDB_LIMIT, 0x10);
813}
814
815static void tc358743_initial_setup(struct v4l2_subdev *sd)
816{
817 struct tc358743_state *state = to_state(sd);
818 struct tc358743_platform_data *pdata = &state->pdata;
819
820 /* CEC and IR are not supported by this driver */
821 i2c_wr16_and_or(sd, SYSCTL, ~(MASK_CECRST | MASK_IRRST),
822 (MASK_CECRST | MASK_IRRST));
823
824 tc358743_reset(sd, MASK_CTXRST | MASK_HDMIRST);
825 tc358743_sleep_mode(sd, false);
826
827 i2c_wr16(sd, FIFOCTL, pdata->fifo_level);
828
829 tc358743_set_ref_clk(sd);
830
831 i2c_wr8_and_or(sd, DDC_CTL, ~MASK_DDC5V_MODE,
832 pdata->ddc5v_delay & MASK_DDC5V_MODE);
833 i2c_wr8_and_or(sd, EDID_MODE, ~MASK_EDID_MODE, MASK_EDID_MODE_E_DDC);
834
835 tc358743_set_hdmi_phy(sd);
836 tc358743_set_hdmi_hdcp(sd, pdata->enable_hdcp);
837 tc358743_set_hdmi_audio(sd);
838 tc358743_set_hdmi_info_frame_mode(sd);
839
840 /* All CE and IT formats are detected as RGB full range in DVI mode */
841 i2c_wr8_and_or(sd, VI_MODE, ~MASK_RGB_DVI, 0);
842
843 i2c_wr8_and_or(sd, VOUT_SET2, ~MASK_VOUTCOLORMODE,
844 MASK_VOUTCOLORMODE_AUTO);
845 i2c_wr8(sd, VOUT_SET3, MASK_VOUT_EXTCNT);
846}
847
848/* --------------- IRQ --------------- */
849
850static void tc358743_format_change(struct v4l2_subdev *sd)
851{
852 struct tc358743_state *state = to_state(sd);
853 struct v4l2_dv_timings timings;
854 const struct v4l2_event tc358743_ev_fmt = {
855 .type = V4L2_EVENT_SOURCE_CHANGE,
856 .u.src_change.changes = V4L2_EVENT_SRC_CH_RESOLUTION,
857 };
858
859 if (tc358743_get_detected_timings(sd, &timings)) {
860 enable_stream(sd, false);
861
2874bf3e 862 v4l2_dbg(1, debug, sd, "%s: No signal\n",
d32d9864
MR		 863 __func__);
864 } else {
85f9e06c 865 if (!v4l2_match_dv_timings(&state->timings, &timings, 0, false))
d32d9864
MR		 866 enable_stream(sd, false);
867
2874bf3e
MR		 868 if (debug)
869 v4l2_print_dv_timings(sd->name,
870 "tc358743_format_change: New format: ",
871 &timings, false);
d32d9864
MR		 872 }
873
abeaca0f
PZ		 874 if (sd->devnode)
875 v4l2_subdev_notify_event(sd, &tc358743_ev_fmt);
d32d9864
MR		 876}
877
878static void tc358743_init_interrupts(struct v4l2_subdev *sd)
879{
880 u16 i;
881
882 /* clear interrupt status registers */
883 for (i = SYS_INT; i <= KEY_INT; i++)
884 i2c_wr8(sd, i, 0xff);
885
886 i2c_wr16(sd, INTSTATUS, 0xffff);
887}
888
889static void tc358743_enable_interrupts(struct v4l2_subdev *sd,
890 bool cable_connected)
891{
892 v4l2_dbg(2, debug, sd, "%s: cable connected = %d\n", __func__,
893 cable_connected);
894
895 if (cable_connected) {
896 i2c_wr8(sd, SYS_INTM, ~(MASK_M_DDC | MASK_M_DVI_DET |
897 MASK_M_HDMI_DET) & 0xff);
898 i2c_wr8(sd, CLK_INTM, ~MASK_M_IN_DE_CHG);
899 i2c_wr8(sd, CBIT_INTM, ~(MASK_M_CBIT_FS | MASK_M_AF_LOCK |
900 MASK_M_AF_UNLOCK) & 0xff);
901 i2c_wr8(sd, AUDIO_INTM, ~MASK_M_BUFINIT_END);
902 i2c_wr8(sd, MISC_INTM, ~MASK_M_SYNC_CHG);
903 } else {
904 i2c_wr8(sd, SYS_INTM, ~MASK_M_DDC & 0xff);
905 i2c_wr8(sd, CLK_INTM, 0xff);
906 i2c_wr8(sd, CBIT_INTM, 0xff);
907 i2c_wr8(sd, AUDIO_INTM, 0xff);
908 i2c_wr8(sd, MISC_INTM, 0xff);
909 }
910}
911
912static void tc358743_hdmi_audio_int_handler(struct v4l2_subdev *sd,
913 bool *handled)
914{
915 u8 audio_int_mask = i2c_rd8(sd, AUDIO_INTM);
916 u8 audio_int = i2c_rd8(sd, AUDIO_INT) & ~audio_int_mask;
917
918 i2c_wr8(sd, AUDIO_INT, audio_int);
919
920 v4l2_dbg(3, debug, sd, "%s: AUDIO_INT = 0x%02x\n", __func__, audio_int);
921
922 tc358743_s_ctrl_audio_sampling_rate(sd);
923 tc358743_s_ctrl_audio_present(sd);
924}
925
926static void tc358743_csi_err_int_handler(struct v4l2_subdev *sd, bool *handled)
927{
928 v4l2_err(sd, "%s: CSI_ERR = 0x%x\n", __func__, i2c_rd32(sd, CSI_ERR));
929
930 i2c_wr32(sd, CSI_INT_CLR, MASK_ICRER);
931}
932
933static void tc358743_hdmi_misc_int_handler(struct v4l2_subdev *sd,
934 bool *handled)
935{
936 u8 misc_int_mask = i2c_rd8(sd, MISC_INTM);
937 u8 misc_int = i2c_rd8(sd, MISC_INT) & ~misc_int_mask;
938
939 i2c_wr8(sd, MISC_INT, misc_int);
940
941 v4l2_dbg(3, debug, sd, "%s: MISC_INT = 0x%02x\n", __func__, misc_int);
942
943 if (misc_int & MASK_I_SYNC_CHG) {
944 /* Reset the HDMI PHY to try to trigger proper lock on the
945 * incoming video format. Erase BKSV to prevent that old keys
946 * are used when a new source is connected. */
947 if (no_sync(sd) || no_signal(sd)) {
948 tc358743_reset_phy(sd);
949 tc358743_erase_bksv(sd);
950 }
951
952 tc358743_format_change(sd);
953
954 misc_int &= ~MASK_I_SYNC_CHG;
955 if (handled)
956 *handled = true;
957 }
958
959 if (misc_int) {
960 v4l2_err(sd, "%s: Unhandled MISC_INT interrupts: 0x%02x\n",
961 __func__, misc_int);
962 }
963}
964
965static void tc358743_hdmi_cbit_int_handler(struct v4l2_subdev *sd,
966 bool *handled)
967{
968 u8 cbit_int_mask = i2c_rd8(sd, CBIT_INTM);
969 u8 cbit_int = i2c_rd8(sd, CBIT_INT) & ~cbit_int_mask;
970
971 i2c_wr8(sd, CBIT_INT, cbit_int);
972
973 v4l2_dbg(3, debug, sd, "%s: CBIT_INT = 0x%02x\n", __func__, cbit_int);
974
975 if (cbit_int & MASK_I_CBIT_FS) {
976
977 v4l2_dbg(1, debug, sd, "%s: Audio sample rate changed\n",
978 __func__);
979 tc358743_s_ctrl_audio_sampling_rate(sd);
980
981 cbit_int &= ~MASK_I_CBIT_FS;
982 if (handled)
983 *handled = true;
984 }
985
986 if (cbit_int & (MASK_I_AF_LOCK | MASK_I_AF_UNLOCK)) {
987
988 v4l2_dbg(1, debug, sd, "%s: Audio present changed\n",
989 __func__);
990 tc358743_s_ctrl_audio_present(sd);
991
992 cbit_int &= ~(MASK_I_AF_LOCK | MASK_I_AF_UNLOCK);
993 if (handled)
994 *handled = true;
995 }
996
997 if (cbit_int) {
998 v4l2_err(sd, "%s: Unhandled CBIT_INT interrupts: 0x%02x\n",
999 __func__, cbit_int);
1000 }
1001}
1002
1003static void tc358743_hdmi_clk_int_handler(struct v4l2_subdev *sd, bool *handled)
1004{
1005 u8 clk_int_mask = i2c_rd8(sd, CLK_INTM);
1006 u8 clk_int = i2c_rd8(sd, CLK_INT) & ~clk_int_mask;
1007
1008 /* Bit 7 and bit 6 are set even when they are masked */
1009 i2c_wr8(sd, CLK_INT, clk_int | 0x80 | MASK_I_OUT_H_CHG);
1010
1011 v4l2_dbg(3, debug, sd, "%s: CLK_INT = 0x%02x\n", __func__, clk_int);
1012
1013 if (clk_int & (MASK_I_IN_DE_CHG)) {
1014
1015 v4l2_dbg(1, debug, sd, "%s: DE size or position has changed\n",
1016 __func__);
1017
1018 /* If the source switch to a new resolution with the same pixel
1019 * frequency as the existing (e.g. 1080p25 -> 720p50), the
1020 * I_SYNC_CHG interrupt is not always triggered, while the
1021 * I_IN_DE_CHG interrupt seems to work fine. Format change
1022 * notifications are only sent when the signal is stable to
1023 * reduce the number of notifications. */
1024 if (!no_signal(sd) && !no_sync(sd))
1025 tc358743_format_change(sd);
1026
1027 clk_int &= ~(MASK_I_IN_DE_CHG);
1028 if (handled)
1029 *handled = true;
1030 }
1031
1032 if (clk_int) {
1033 v4l2_err(sd, "%s: Unhandled CLK_INT interrupts: 0x%02x\n",
1034 __func__, clk_int);
1035 }
1036}
1037
1038static void tc358743_hdmi_sys_int_handler(struct v4l2_subdev *sd, bool *handled)
1039{
1040 struct tc358743_state *state = to_state(sd);
1041 u8 sys_int_mask = i2c_rd8(sd, SYS_INTM);
1042 u8 sys_int = i2c_rd8(sd, SYS_INT) & ~sys_int_mask;
1043
1044 i2c_wr8(sd, SYS_INT, sys_int);
1045
1046 v4l2_dbg(3, debug, sd, "%s: SYS_INT = 0x%02x\n", __func__, sys_int);
1047
1048 if (sys_int & MASK_I_DDC) {
1049 bool tx_5v = tx_5v_power_present(sd);
1050
1051 v4l2_dbg(1, debug, sd, "%s: Tx 5V power present: %s\n",
1052 __func__, tx_5v ? "yes" : "no");
1053
1054 if (tx_5v) {
1055 tc358743_enable_edid(sd);
1056 } else {
1057 tc358743_enable_interrupts(sd, false);
1058 tc358743_disable_edid(sd);
1059 memset(&state->timings, 0, sizeof(state->timings));
1060 tc358743_erase_bksv(sd);
1061 tc358743_update_controls(sd);
1062 }
1063
1064 sys_int &= ~MASK_I_DDC;
1065 if (handled)
1066 *handled = true;
1067 }
1068
1069 if (sys_int & MASK_I_DVI) {
1070 v4l2_dbg(1, debug, sd, "%s: HDMI->DVI change detected\n",
1071 __func__);
1072
1073 /* Reset the HDMI PHY to try to trigger proper lock on the
1074 * incoming video format. Erase BKSV to prevent that old keys
1075 * are used when a new source is connected. */
1076 if (no_sync(sd) || no_signal(sd)) {
1077 tc358743_reset_phy(sd);
1078 tc358743_erase_bksv(sd);
1079 }
1080
1081 sys_int &= ~MASK_I_DVI;
1082 if (handled)
1083 *handled = true;
1084 }
1085
1086 if (sys_int & MASK_I_HDMI) {
1087 v4l2_dbg(1, debug, sd, "%s: DVI->HDMI change detected\n",
1088 __func__);
1089
1090 /* Register is reset in DVI mode (REF_01, c. 6.6.41) */
1091 i2c_wr8(sd, ANA_CTL, MASK_APPL_PCSX_NORMAL | MASK_ANALOG_ON);
1092
1093 sys_int &= ~MASK_I_HDMI;
1094 if (handled)
1095 *handled = true;
1096 }
1097
1098 if (sys_int) {
1099 v4l2_err(sd, "%s: Unhandled SYS_INT interrupts: 0x%02x\n",
1100 __func__, sys_int);
1101 }
1102}
1103
1104/* --------------- CORE OPS --------------- */
1105
1106static int tc358743_log_status(struct v4l2_subdev *sd)
1107{
1108 struct tc358743_state *state = to_state(sd);
1109 struct v4l2_dv_timings timings;
1110 uint8_t hdmi_sys_status = i2c_rd8(sd, SYS_STATUS);
1111 uint16_t sysctl = i2c_rd16(sd, SYSCTL);
1112 u8 vi_status3 = i2c_rd8(sd, VI_STATUS3);
1113 const int deep_color_mode[4] = { 8, 10, 12, 16 };
1114 static const char * const input_color_space[] = {
1115 "RGB", "YCbCr 601", "Adobe RGB", "YCbCr 709", "NA (4)",
1116 "xvYCC 601", "NA(6)", "xvYCC 709", "NA(8)", "sYCC601",
1117 "NA(10)", "NA(11)", "NA(12)", "Adobe YCC 601"};
1118
1119 v4l2_info(sd, "-----Chip status-----\n");
1120 v4l2_info(sd, "Chip ID: 0x%02x\n",
1121 (i2c_rd16(sd, CHIPID) & MASK_CHIPID) >> 8);
1122 v4l2_info(sd, "Chip revision: 0x%02x\n",
1123 i2c_rd16(sd, CHIPID) & MASK_REVID);
1124 v4l2_info(sd, "Reset: IR: %d, CEC: %d, CSI TX: %d, HDMI: %d\n",
1125 !!(sysctl & MASK_IRRST),
1126 !!(sysctl & MASK_CECRST),
1127 !!(sysctl & MASK_CTXRST),
1128 !!(sysctl & MASK_HDMIRST));
1129 v4l2_info(sd, "Sleep mode: %s\n", sysctl & MASK_SLEEP ? "on" : "off");
1130 v4l2_info(sd, "Cable detected (+5V power): %s\n",
1131 hdmi_sys_status & MASK_S_DDC5V ? "yes" : "no");
1132 v4l2_info(sd, "DDC lines enabled: %s\n",
1133 (i2c_rd8(sd, EDID_MODE) & MASK_EDID_MODE_E_DDC) ?
1134 "yes" : "no");
1135 v4l2_info(sd, "Hotplug enabled: %s\n",
1136 (i2c_rd8(sd, HPD_CTL) & MASK_HPD_OUT0) ?
1137 "yes" : "no");
1138 v4l2_info(sd, "CEC enabled: %s\n",
1139 (i2c_rd16(sd, CECEN) & MASK_CECEN) ? "yes" : "no");
1140 v4l2_info(sd, "-----Signal status-----\n");
1141 v4l2_info(sd, "TMDS signal detected: %s\n",
1142 hdmi_sys_status & MASK_S_TMDS ? "yes" : "no");
1143 v4l2_info(sd, "Stable sync signal: %s\n",
1144 hdmi_sys_status & MASK_S_SYNC ? "yes" : "no");
1145 v4l2_info(sd, "PHY PLL locked: %s\n",
1146 hdmi_sys_status & MASK_S_PHY_PLL ? "yes" : "no");
1147 v4l2_info(sd, "PHY DE detected: %s\n",
1148 hdmi_sys_status & MASK_S_PHY_SCDT ? "yes" : "no");
1149
1150 if (tc358743_get_detected_timings(sd, &timings)) {
1151 v4l2_info(sd, "No video detected\n");
1152 } else {
1153 v4l2_print_dv_timings(sd->name, "Detected format: ", &timings,
1154 true);
1155 }
1156 v4l2_print_dv_timings(sd->name, "Configured format: ", &state->timings,
1157 true);
1158
1159 v4l2_info(sd, "-----CSI-TX status-----\n");
1160 v4l2_info(sd, "Lanes needed: %d\n",
1161 tc358743_num_csi_lanes_needed(sd));
1162 v4l2_info(sd, "Lanes in use: %d\n",
1163 tc358743_num_csi_lanes_in_use(sd));
1164 v4l2_info(sd, "Waiting for particular sync signal: %s\n",
1165 (i2c_rd16(sd, CSI_STATUS) & MASK_S_WSYNC) ?
1166 "yes" : "no");
1167 v4l2_info(sd, "Transmit mode: %s\n",
1168 (i2c_rd16(sd, CSI_STATUS) & MASK_S_TXACT) ?
1169 "yes" : "no");
1170 v4l2_info(sd, "Receive mode: %s\n",
1171 (i2c_rd16(sd, CSI_STATUS) & MASK_S_RXACT) ?
1172 "yes" : "no");
1173 v4l2_info(sd, "Stopped: %s\n",
1174 (i2c_rd16(sd, CSI_STATUS) & MASK_S_HLT) ?
1175 "yes" : "no");
1176 v4l2_info(sd, "Color space: %s\n",
1177 state->mbus_fmt_code == MEDIA_BUS_FMT_UYVY8_1X16 ?
1178 "YCbCr 422 16-bit" :
1179 state->mbus_fmt_code == MEDIA_BUS_FMT_RGB888_1X24 ?
1180 "RGB 888 24-bit" : "Unsupported");
1181
1182 v4l2_info(sd, "-----%s status-----\n", is_hdmi(sd) ? "HDMI" : "DVI-D");
1183 v4l2_info(sd, "HDCP encrypted content: %s\n",
1184 hdmi_sys_status & MASK_S_HDCP ? "yes" : "no");
1185 v4l2_info(sd, "Input color space: %s %s range\n",
1186 input_color_space[(vi_status3 & MASK_S_V_COLOR) >> 1],
1187 (vi_status3 & MASK_LIMITED) ? "limited" : "full");
1188 if (!is_hdmi(sd))
1189 return 0;
1190 v4l2_info(sd, "AV Mute: %s\n", hdmi_sys_status & MASK_S_AVMUTE ? "on" :
1191 "off");
1192 v4l2_info(sd, "Deep color mode: %d-bits per channel\n",
1193 deep_color_mode[(i2c_rd8(sd, VI_STATUS1) &
1194 MASK_S_DEEPCOLOR) >> 2]);
1195 print_avi_infoframe(sd);
1196
1197 return 0;
1198}
1199
1200#ifdef CONFIG_VIDEO_ADV_DEBUG
1201static void tc358743_print_register_map(struct v4l2_subdev *sd)
1202{
1203 v4l2_info(sd, "0x0000–0x00FF: Global Control Register\n");
1204 v4l2_info(sd, "0x0100–0x01FF: CSI2-TX PHY Register\n");
1205 v4l2_info(sd, "0x0200–0x03FF: CSI2-TX PPI Register\n");
1206 v4l2_info(sd, "0x0400–0x05FF: Reserved\n");
1207 v4l2_info(sd, "0x0600–0x06FF: CEC Register\n");
1208 v4l2_info(sd, "0x0700–0x84FF: Reserved\n");
1209 v4l2_info(sd, "0x8500–0x85FF: HDMIRX System Control Register\n");
1210 v4l2_info(sd, "0x8600–0x86FF: HDMIRX Audio Control Register\n");
1211 v4l2_info(sd, "0x8700–0x87FF: HDMIRX InfoFrame packet data Register\n");
1212 v4l2_info(sd, "0x8800–0x88FF: HDMIRX HDCP Port Register\n");
1213 v4l2_info(sd, "0x8900–0x89FF: HDMIRX Video Output Port & 3D Register\n");
1214 v4l2_info(sd, "0x8A00–0x8BFF: Reserved\n");
1215 v4l2_info(sd, "0x8C00–0x8FFF: HDMIRX EDID-RAM (1024bytes)\n");
1216 v4l2_info(sd, "0x9000–0x90FF: HDMIRX GBD Extraction Control\n");
1217 v4l2_info(sd, "0x9100–0x92FF: HDMIRX GBD RAM read\n");
1218 v4l2_info(sd, "0x9300- : Reserved\n");
1219}
1220
1221static int tc358743_get_reg_size(u16 address)
1222{
1223 /* REF_01 p. 66-72 */
1224 if (address <= 0x00ff)
1225 return 2;
1226 else if ((address >= 0x0100) && (address <= 0x06FF))
1227 return 4;
1228 else if ((address >= 0x0700) && (address <= 0x84ff))
1229 return 2;
1230 else
1231 return 1;
1232}
1233
1234static int tc358743_g_register(struct v4l2_subdev *sd,
1235 struct v4l2_dbg_register *reg)
1236{
1237 if (reg->reg > 0xffff) {
1238 tc358743_print_register_map(sd);
1239 return -EINVAL;
1240 }
1241
1242 reg->size = tc358743_get_reg_size(reg->reg);
1243
1244 i2c_rd(sd, reg->reg, (u8 *)&reg->val, reg->size);
1245
1246 return 0;
1247}
1248
1249static int tc358743_s_register(struct v4l2_subdev *sd,
1250 const struct v4l2_dbg_register *reg)
1251{
1252 if (reg->reg > 0xffff) {
1253 tc358743_print_register_map(sd);
1254 return -EINVAL;
1255 }
1256
1257 /* It should not be possible for the user to enable HDCP with a simple
1258 * v4l2-dbg command.
1259 *
1260 * DO NOT REMOVE THIS unless all other issues with HDCP have been
1261 * resolved.
1262 */
1263 if (reg->reg == HDCP_MODE ||
1264 reg->reg == HDCP_REG1 ||
1265 reg->reg == HDCP_REG2 ||
1266 reg->reg == HDCP_REG3 ||
1267 reg->reg == BCAPS)
1268 return 0;
1269
1270 i2c_wr(sd, (u16)reg->reg, (u8 *)&reg->val,
1271 tc358743_get_reg_size(reg->reg));
1272
1273 return 0;
1274}
1275#endif
1276
1277static int tc358743_isr(struct v4l2_subdev *sd, u32 status, bool *handled)
1278{
1279 u16 intstatus = i2c_rd16(sd, INTSTATUS);
1280
1281 v4l2_dbg(1, debug, sd, "%s: IntStatus = 0x%04x\n", __func__, intstatus);
1282
1283 if (intstatus & MASK_HDMI_INT) {
1284 u8 hdmi_int0 = i2c_rd8(sd, HDMI_INT0);
1285 u8 hdmi_int1 = i2c_rd8(sd, HDMI_INT1);
1286
1287 if (hdmi_int0 & MASK_I_MISC)
1288 tc358743_hdmi_misc_int_handler(sd, handled);
1289 if (hdmi_int1 & MASK_I_CBIT)
1290 tc358743_hdmi_cbit_int_handler(sd, handled);
1291 if (hdmi_int1 & MASK_I_CLK)
1292 tc358743_hdmi_clk_int_handler(sd, handled);
1293 if (hdmi_int1 & MASK_I_SYS)
1294 tc358743_hdmi_sys_int_handler(sd, handled);
1295 if (hdmi_int1 & MASK_I_AUD)
1296 tc358743_hdmi_audio_int_handler(sd, handled);
1297
1298 i2c_wr16(sd, INTSTATUS, MASK_HDMI_INT);
1299 intstatus &= ~MASK_HDMI_INT;
1300 }
1301
1302 if (intstatus & MASK_CSI_INT) {
1303 u32 csi_int = i2c_rd32(sd, CSI_INT);
1304
1305 if (csi_int & MASK_INTER)
1306 tc358743_csi_err_int_handler(sd, handled);
1307
1308 i2c_wr16(sd, INTSTATUS, MASK_CSI_INT);
1309 intstatus &= ~MASK_CSI_INT;
1310 }
1311
1312 intstatus = i2c_rd16(sd, INTSTATUS);
1313 if (intstatus) {
1314 v4l2_dbg(1, debug, sd,
1315 "%s: Unhandled IntStatus interrupts: 0x%02x\n",
1316 __func__, intstatus);
1317 }
1318
1319 return 0;
1320}
1321
d747b806
PZ		 1322static irqreturn_t tc358743_irq_handler(int irq, void *dev_id)
1323{
1324 struct tc358743_state *state = dev_id;
1325 bool handled;
1326
1327 tc358743_isr(&state->sd, 0, &handled);
1328
1329 return handled ? IRQ_HANDLED : IRQ_NONE;
1330}
1331
1140f919
PZ		 1332static int tc358743_subscribe_event(struct v4l2_subdev *sd, struct v4l2_fh *fh,
1333 struct v4l2_event_subscription *sub)
1334{
1335 switch (sub->type) {
1336 case V4L2_EVENT_SOURCE_CHANGE:
1337 return v4l2_src_change_event_subdev_subscribe(sd, fh, sub);
1338 case V4L2_EVENT_CTRL:
1339 return v4l2_ctrl_subdev_subscribe_event(sd, fh, sub);
1340 default:
1341 return -EINVAL;
1342 }
1343}
1344
d32d9864
MR		 1345/* --------------- VIDEO OPS --------------- */
1346
1347static int tc358743_g_input_status(struct v4l2_subdev *sd, u32 *status)
1348{
1349 *status = 0;
1350 *status |= no_signal(sd) ? V4L2_IN_ST_NO_SIGNAL : 0;
1351 *status |= no_sync(sd) ? V4L2_IN_ST_NO_SYNC : 0;
1352
1353 v4l2_dbg(1, debug, sd, "%s: status = 0x%x\n", __func__, *status);
1354
1355 return 0;
1356}
1357
1358static int tc358743_s_dv_timings(struct v4l2_subdev *sd,
1359 struct v4l2_dv_timings *timings)
1360{
1361 struct tc358743_state *state = to_state(sd);
d32d9864
MR		 1362
1363 if (!timings)
1364 return -EINVAL;
1365
1366 if (debug)
1367 v4l2_print_dv_timings(sd->name, "tc358743_s_dv_timings: ",
1368 timings, false);
1369
85f9e06c 1370 if (v4l2_match_dv_timings(&state->timings, timings, 0, false)) {
d32d9864
MR		 1371 v4l2_dbg(1, debug, sd, "%s: no change\n", __func__);
1372 return 0;
1373 }
1374
d32d9864
MR		 1375 if (!v4l2_valid_dv_timings(timings,
1376 &tc358743_timings_cap, NULL, NULL)) {
1377 v4l2_dbg(1, debug, sd, "%s: timings out of range\n", __func__);
1378 return -ERANGE;
1379 }
1380
1381 state->timings = *timings;
1382
1383 enable_stream(sd, false);
1384 tc358743_set_pll(sd);
1385 tc358743_set_csi(sd);
1386
1387 return 0;
1388}
1389
1390static int tc358743_g_dv_timings(struct v4l2_subdev *sd,
1391 struct v4l2_dv_timings *timings)
1392{
1393 struct tc358743_state *state = to_state(sd);
1394
1395 *timings = state->timings;
1396
1397 return 0;
1398}
1399
1400static int tc358743_enum_dv_timings(struct v4l2_subdev *sd,
1401 struct v4l2_enum_dv_timings *timings)
1402{
1403 if (timings->pad != 0)
1404 return -EINVAL;
1405
1406 return v4l2_enum_dv_timings_cap(timings,
1407 &tc358743_timings_cap, NULL, NULL);
1408}
1409
1410static int tc358743_query_dv_timings(struct v4l2_subdev *sd,
1411 struct v4l2_dv_timings *timings)
1412{
1413 int ret;
1414
1415 ret = tc358743_get_detected_timings(sd, timings);
1416 if (ret)
1417 return ret;
1418
1419 if (debug)
1420 v4l2_print_dv_timings(sd->name, "tc358743_query_dv_timings: ",
1421 timings, false);
1422
1423 if (!v4l2_valid_dv_timings(timings,
1424 &tc358743_timings_cap, NULL, NULL)) {
1425 v4l2_dbg(1, debug, sd, "%s: timings out of range\n", __func__);
1426 return -ERANGE;
1427 }
1428
1429 return 0;
1430}
1431
1432static int tc358743_dv_timings_cap(struct v4l2_subdev *sd,
1433 struct v4l2_dv_timings_cap *cap)
1434{
1435 if (cap->pad != 0)
1436 return -EINVAL;
1437
1438 *cap = tc358743_timings_cap;
1439
1440 return 0;
1441}
1442
1443static int tc358743_g_mbus_config(struct v4l2_subdev *sd,
1444 struct v4l2_mbus_config *cfg)
1445{
1446 cfg->type = V4L2_MBUS_CSI2;
1447
1448 /* Support for non-continuous CSI-2 clock is missing in the driver */
1449 cfg->flags = V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
1450
1451 switch (tc358743_num_csi_lanes_in_use(sd)) {
1452 case 1:
1453 cfg->flags |= V4L2_MBUS_CSI2_1_LANE;
1454 break;
1455 case 2:
1456 cfg->flags |= V4L2_MBUS_CSI2_2_LANE;
1457 break;
1458 case 3:
1459 cfg->flags |= V4L2_MBUS_CSI2_3_LANE;
1460 break;
1461 case 4:
1462 cfg->flags |= V4L2_MBUS_CSI2_4_LANE;
1463 break;
1464 default:
1465 return -EINVAL;
1466 }
1467
1468 return 0;
1469}
1470
1471static int tc358743_s_stream(struct v4l2_subdev *sd, int enable)
1472{
1473 enable_stream(sd, enable);
1474
1475 return 0;
1476}
1477
1478/* --------------- PAD OPS --------------- */
1479
1480static int tc358743_get_fmt(struct v4l2_subdev *sd,
1481 struct v4l2_subdev_pad_config *cfg,
1482 struct v4l2_subdev_format *format)
1483{
1484 struct tc358743_state *state = to_state(sd);
1485 u8 vi_rep = i2c_rd8(sd, VI_REP);
1486
1487 if (format->pad != 0)
1488 return -EINVAL;
1489
1490 format->format.code = state->mbus_fmt_code;
1491 format->format.width = state->timings.bt.width;
1492 format->format.height = state->timings.bt.height;
1493 format->format.field = V4L2_FIELD_NONE;
1494
1495 switch (vi_rep & MASK_VOUT_COLOR_SEL) {
1496 case MASK_VOUT_COLOR_RGB_FULL:
1497 case MASK_VOUT_COLOR_RGB_LIMITED:
1498 format->format.colorspace = V4L2_COLORSPACE_SRGB;
1499 break;
1500 case MASK_VOUT_COLOR_601_YCBCR_LIMITED:
1501 case MASK_VOUT_COLOR_601_YCBCR_FULL:
1502 format->format.colorspace = V4L2_COLORSPACE_SMPTE170M;
1503 break;
1504 case MASK_VOUT_COLOR_709_YCBCR_FULL:
1505 case MASK_VOUT_COLOR_709_YCBCR_LIMITED:
1506 format->format.colorspace = V4L2_COLORSPACE_REC709;
1507 break;
1508 default:
1509 format->format.colorspace = 0;
1510 break;
1511 }
1512
1513 return 0;
1514}
1515
1516static int tc358743_set_fmt(struct v4l2_subdev *sd,
1517 struct v4l2_subdev_pad_config *cfg,
1518 struct v4l2_subdev_format *format)
1519{
1520 struct tc358743_state *state = to_state(sd);
1521
1522 u32 code = format->format.code; /* is overwritten by get_fmt */
1523 int ret = tc358743_get_fmt(sd, cfg, format);
1524
1525 format->format.code = code;
1526
1527 if (ret)
1528 return ret;
1529
1530 switch (code) {
1531 case MEDIA_BUS_FMT_RGB888_1X24:
1532 case MEDIA_BUS_FMT_UYVY8_1X16:
1533 break;
1534 default:
1535 return -EINVAL;
1536 }
1537
1538 if (format->which == V4L2_SUBDEV_FORMAT_TRY)
1539 return 0;
1540
1541 state->mbus_fmt_code = format->format.code;
1542
1543 enable_stream(sd, false);
1544 tc358743_set_pll(sd);
1545 tc358743_set_csi(sd);
1546 tc358743_set_csi_color_space(sd);
1547
1548 return 0;
1549}
1550
1551static int tc358743_g_edid(struct v4l2_subdev *sd,
1552 struct v4l2_subdev_edid *edid)
1553{
1554 struct tc358743_state *state = to_state(sd);
1555
1556 if (edid->pad != 0)
1557 return -EINVAL;
1558
1559 if (edid->start_block == 0 && edid->blocks == 0) {
1560 edid->blocks = state->edid_blocks_written;
1561 return 0;
1562 }
1563
1564 if (state->edid_blocks_written == 0)
1565 return -ENODATA;
1566
1567 if (edid->start_block >= state->edid_blocks_written ||
1568 edid->blocks == 0)
1569 return -EINVAL;
1570
1571 if (edid->start_block + edid->blocks > state->edid_blocks_written)
1572 edid->blocks = state->edid_blocks_written - edid->start_block;
1573
1574 i2c_rd(sd, EDID_RAM + (edid->start_block * EDID_BLOCK_SIZE), edid->edid,
1575 edid->blocks * EDID_BLOCK_SIZE);
1576
1577 return 0;
1578}
1579
1580static int tc358743_s_edid(struct v4l2_subdev *sd,
1581 struct v4l2_subdev_edid *edid)
1582{
1583 struct tc358743_state *state = to_state(sd);
1584 u16 edid_len = edid->blocks * EDID_BLOCK_SIZE;
1585
1586 v4l2_dbg(2, debug, sd, "%s, pad %d, start block %d, blocks %d\n",
1587 __func__, edid->pad, edid->start_block, edid->blocks);
1588
1589 if (edid->pad != 0)
1590 return -EINVAL;
1591
1592 if (edid->start_block != 0)
1593 return -EINVAL;
1594
1595 if (edid->blocks > EDID_NUM_BLOCKS_MAX) {
1596 edid->blocks = EDID_NUM_BLOCKS_MAX;
1597 return -E2BIG;
1598 }
1599
1600 tc358743_disable_edid(sd);
1601
1602 i2c_wr8(sd, EDID_LEN1, edid_len & 0xff);
1603 i2c_wr8(sd, EDID_LEN2, edid_len >> 8);
1604
1605 if (edid->blocks == 0) {
1606 state->edid_blocks_written = 0;
1607 return 0;
1608 }
1609
1610 i2c_wr(sd, EDID_RAM, edid->edid, edid_len);
1611
1612 state->edid_blocks_written = edid->blocks;
1613
1614 if (tx_5v_power_present(sd))
1615 tc358743_enable_edid(sd);
1616
1617 return 0;
1618}
1619
1620/* -------------------------------------------------------------------------- */
1621
1622static const struct v4l2_subdev_core_ops tc358743_core_ops = {
1623 .log_status = tc358743_log_status,
1624#ifdef CONFIG_VIDEO_ADV_DEBUG
1625 .g_register = tc358743_g_register,
1626 .s_register = tc358743_s_register,
1627#endif
1628 .interrupt_service_routine = tc358743_isr,
1140f919
PZ		 1629 .subscribe_event = tc358743_subscribe_event,
1630 .unsubscribe_event = v4l2_event_subdev_unsubscribe,
d32d9864
MR		 1631};
1632
1633static const struct v4l2_subdev_video_ops tc358743_video_ops = {
1634 .g_input_status = tc358743_g_input_status,
1635 .s_dv_timings = tc358743_s_dv_timings,
1636 .g_dv_timings = tc358743_g_dv_timings,
1637 .query_dv_timings = tc358743_query_dv_timings,
1638 .g_mbus_config = tc358743_g_mbus_config,
1639 .s_stream = tc358743_s_stream,
1640};
1641
1642static const struct v4l2_subdev_pad_ops tc358743_pad_ops = {
1643 .set_fmt = tc358743_set_fmt,
1644 .get_fmt = tc358743_get_fmt,
1645 .get_edid = tc358743_g_edid,
1646 .set_edid = tc358743_s_edid,
1647 .enum_dv_timings = tc358743_enum_dv_timings,
1648 .dv_timings_cap = tc358743_dv_timings_cap,
1649};
1650
1651static const struct v4l2_subdev_ops tc358743_ops = {
1652 .core = &tc358743_core_ops,
1653 .video = &tc358743_video_ops,
1654 .pad = &tc358743_pad_ops,
1655};
1656
1657/* --------------- CUSTOM CTRLS --------------- */
1658
1659static const struct v4l2_ctrl_config tc358743_ctrl_audio_sampling_rate = {
1660 .id = TC358743_CID_AUDIO_SAMPLING_RATE,
1661 .name = "Audio sampling rate",
1662 .type = V4L2_CTRL_TYPE_INTEGER,
1663 .min = 0,
1664 .max = 768000,
1665 .step = 1,
1666 .def = 0,
1667 .flags = V4L2_CTRL_FLAG_READ_ONLY,
1668};
1669
1670static const struct v4l2_ctrl_config tc358743_ctrl_audio_present = {
1671 .id = TC358743_CID_AUDIO_PRESENT,
1672 .name = "Audio present",
1673 .type = V4L2_CTRL_TYPE_BOOLEAN,
1674 .min = 0,
1675 .max = 1,
1676 .step = 1,
1677 .def = 0,
1678 .flags = V4L2_CTRL_FLAG_READ_ONLY,
1679};
1680
1681/* --------------- PROBE / REMOVE --------------- */
1682
25614824
PZ		 1683#ifdef CONFIG_OF
1684static void tc358743_gpio_reset(struct tc358743_state *state)
1685{
25614824
PZ		 1686 usleep_range(5000, 10000);
1687 gpiod_set_value(state->reset_gpio, 1);
1688 usleep_range(1000, 2000);
1689 gpiod_set_value(state->reset_gpio, 0);
1690 msleep(20);
1691}
1692
1693static int tc358743_probe_of(struct tc358743_state *state)
1694{
1695 struct device *dev = &state->i2c_client->dev;
1696 struct v4l2_of_endpoint *endpoint;
1697 struct device_node *ep;
1698 struct clk *refclk;
1699 u32 bps_pr_lane;
1700 int ret = -EINVAL;
1701
1702 refclk = devm_clk_get(dev, "refclk");
1703 if (IS_ERR(refclk)) {
1704 if (PTR_ERR(refclk) != -EPROBE_DEFER)
1705 dev_err(dev, "failed to get refclk: %ld\n",
1706 PTR_ERR(refclk));
1707 return PTR_ERR(refclk);
1708 }
1709
1710 ep = of_graph_get_next_endpoint(dev->of_node, NULL);
1711 if (!ep) {
1712 dev_err(dev, "missing endpoint node\n");
1713 return -EINVAL;
1714 }
1715
1716 endpoint = v4l2_of_alloc_parse_endpoint(ep);
1717 if (IS_ERR(endpoint)) {
1718 dev_err(dev, "failed to parse endpoint\n");
1719 return PTR_ERR(endpoint);
1720 }
1721
1722 if (endpoint->bus_type != V4L2_MBUS_CSI2 ||
1723 endpoint->bus.mipi_csi2.num_data_lanes == 0 ||
1724 endpoint->nr_of_link_frequencies == 0) {
1725 dev_err(dev, "missing CSI-2 properties in endpoint\n");
1726 goto free_endpoint;
1727 }
1728
1729 state->bus = endpoint->bus.mipi_csi2;
1730
1731 clk_prepare_enable(refclk);
1732
1733 state->pdata.refclk_hz = clk_get_rate(refclk);
1734 state->pdata.ddc5v_delay = DDC5V_DELAY_100_MS;
1735 state->pdata.enable_hdcp = false;
1736 /* A FIFO level of 16 should be enough for 2-lane 720p60 at 594 MHz. */
1737 state->pdata.fifo_level = 16;
1738 /*
1739 * The PLL input clock is obtained by dividing refclk by pll_prd.
1740 * It must be between 6 MHz and 40 MHz, lower frequency is better.
1741 */
1742 switch (state->pdata.refclk_hz) {
1743 case 26000000:
1744 case 27000000:
1745 case 42000000:
1746 state->pdata.pll_prd = state->pdata.refclk_hz / 6000000;
1747 break;
1748 default:
1749 dev_err(dev, "unsupported refclk rate: %u Hz\n",
1750 state->pdata.refclk_hz);
1751 goto disable_clk;
1752 }
1753
1754 /*
1755 * The CSI bps per lane must be between 62.5 Mbps and 1 Gbps.
1756 * The default is 594 Mbps for 4-lane 1080p60 or 2-lane 720p60.
1757 */
1758 bps_pr_lane = 2 * endpoint->link_frequencies[0];
1759 if (bps_pr_lane < 62500000U || bps_pr_lane > 1000000000U) {
1760 dev_err(dev, "unsupported bps per lane: %u bps\n", bps_pr_lane);
1761 goto disable_clk;
1762 }
1763
1764 /* The CSI speed per lane is refclk / pll_prd * pll_fbd */
1765 state->pdata.pll_fbd = bps_pr_lane /
1766 state->pdata.refclk_hz * state->pdata.pll_prd;
1767
1768 /*
1769 * FIXME: These timings are from REF_02 for 594 Mbps per lane (297 MHz
1770 * link frequency). In principle it should be possible to calculate
1771 * them based on link frequency and resolution.
1772 */
1773 if (bps_pr_lane != 594000000U)
1774 dev_warn(dev, "untested bps per lane: %u bps\n", bps_pr_lane);
1775 state->pdata.lineinitcnt = 0xe80;
1776 state->pdata.lptxtimecnt = 0x003;
1777 /* tclk-preparecnt: 3, tclk-zerocnt: 20 */
1778 state->pdata.tclk_headercnt = 0x1403;
1779 state->pdata.tclk_trailcnt = 0x00;
1780 /* ths-preparecnt: 3, ths-zerocnt: 1 */
1781 state->pdata.ths_headercnt = 0x0103;
1782 state->pdata.twakeup = 0x4882;
1783 state->pdata.tclk_postcnt = 0x008;
1784 state->pdata.ths_trailcnt = 0x2;
1785 state->pdata.hstxvregcnt = 0;
1786
1e137d92
UKK		 1787 state->reset_gpio = devm_gpiod_get_optional(dev, "reset",
1788 GPIOD_OUT_LOW);
25614824
PZ		 1789 if (IS_ERR(state->reset_gpio)) {
1790 dev_err(dev, "failed to get reset gpio\n");
1791 ret = PTR_ERR(state->reset_gpio);
1792 goto disable_clk;
1793 }
1794
1e137d92
UKK		 1795 if (state->reset_gpio)
1796 tc358743_gpio_reset(state);
25614824
PZ		 1797
1798 ret = 0;
1799 goto free_endpoint;
1800
1801disable_clk:
1802 clk_disable_unprepare(refclk);
1803free_endpoint:
1804 v4l2_of_free_endpoint(endpoint);
1805 return ret;
1806}
1807#else
1808static inline int tc358743_probe_of(struct tc358743_state *state)
1809{
1810 return -ENODEV;
1811}
1812#endif
1813
d32d9864
MR		 1814static int tc358743_probe(struct i2c_client *client,
1815 const struct i2c_device_id *id)
1816{
1817 static struct v4l2_dv_timings default_timing =
1818 V4L2_DV_BT_CEA_640X480P59_94;
1819 struct tc358743_state *state;
1820 struct tc358743_platform_data *pdata = client->dev.platform_data;
1821 struct v4l2_subdev *sd;
1822 int err;
1823
1824 if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
1825 return -EIO;
1826 v4l_dbg(1, debug, client, "chip found @ 0x%x (%s)\n",
1827 client->addr << 1, client->adapter->name);
1828
1829 state = devm_kzalloc(&client->dev, sizeof(struct tc358743_state),
1830 GFP_KERNEL);
1831 if (!state)
1832 return -ENOMEM;
1833
25614824
PZ		 1834 state->i2c_client = client;
1835
d32d9864 1836 /* platform data */
25614824
PZ		 1837 if (pdata) {
1838 state->pdata = *pdata;
1839 state->bus.flags = V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
1840 } else {
1841 err = tc358743_probe_of(state);
1842 if (err == -ENODEV)
1843 v4l_err(client, "No platform data!\n");
1844 if (err)
1845 return err;
d32d9864 1846 }
d32d9864 1847
d32d9864
MR		 1848 sd = &state->sd;
1849 v4l2_i2c_subdev_init(sd, client, &tc358743_ops);
8ec23da7 1850 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS;
d32d9864
MR		 1851
1852 /* i2c access */
1853 if ((i2c_rd16(sd, CHIPID) & MASK_CHIPID) != 0) {
1854 v4l2_info(sd, "not a TC358743 on address 0x%x\n",
1855 client->addr << 1);
1856 return -ENODEV;
1857 }
1858
1859 /* control handlers */
1860 v4l2_ctrl_handler_init(&state->hdl, 3);
1861
1862 /* private controls */
1863 state->detect_tx_5v_ctrl = v4l2_ctrl_new_std(&state->hdl, NULL,
1864 V4L2_CID_DV_RX_POWER_PRESENT, 0, 1, 0, 0);
1865
1866 /* custom controls */
1867 state->audio_sampling_rate_ctrl = v4l2_ctrl_new_custom(&state->hdl,
1868 &tc358743_ctrl_audio_sampling_rate, NULL);
1869
1870 state->audio_present_ctrl = v4l2_ctrl_new_custom(&state->hdl,
1871 &tc358743_ctrl_audio_present, NULL);
1872
1873 sd->ctrl_handler = &state->hdl;
1874 if (state->hdl.error) {
1875 err = state->hdl.error;
1876 goto err_hdl;
1877 }
1878
1879 if (tc358743_update_controls(sd)) {
1880 err = -ENODEV;
1881 goto err_hdl;
1882 }
1883
1884 /* work queues */
1885 state->work_queues = create_singlethread_workqueue(client->name);
1886 if (!state->work_queues) {
1887 v4l2_err(sd, "Could not create work queue\n");
1888 err = -ENOMEM;
1889 goto err_hdl;
1890 }
1891
4c5211a1 1892 state->pad.flags = MEDIA_PAD_FL_SOURCE;
ab22e77c 1893 err = media_entity_pads_init(&sd->entity, 1, &state->pad);
4c5211a1
PZ		 1894 if (err < 0)
1895 goto err_hdl;
1896
1897 sd->dev = &client->dev;
1898 err = v4l2_async_register_subdev(sd);
1899 if (err < 0)
1900 goto err_hdl;
1901
d32d9864
MR		 1902 mutex_init(&state->confctl_mutex);
1903
1904 INIT_DELAYED_WORK(&state->delayed_work_enable_hotplug,
1905 tc358743_delayed_work_enable_hotplug);
1906
1907 tc358743_initial_setup(sd);
1908
1909 tc358743_s_dv_timings(sd, &default_timing);
1910
1911 state->mbus_fmt_code = MEDIA_BUS_FMT_RGB888_1X24;
1912 tc358743_set_csi_color_space(sd);
1913
1914 tc358743_init_interrupts(sd);
d747b806
PZ		 1915
1916 if (state->i2c_client->irq) {
1917 err = devm_request_threaded_irq(&client->dev,
1918 state->i2c_client->irq,
1919 NULL, tc358743_irq_handler,
1920 IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
1921 "tc358743", state);
1922 if (err)
1923 goto err_work_queues;
1924 }
1925
d32d9864
MR		 1926 tc358743_enable_interrupts(sd, tx_5v_power_present(sd));
1927 i2c_wr16(sd, INTMASK, ~(MASK_HDMI_MSK | MASK_CSI_MSK) & 0xffff);
1928
1929 err = v4l2_ctrl_handler_setup(sd->ctrl_handler);
1930 if (err)
1931 goto err_work_queues;
1932
1933 v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name,
1934 client->addr << 1, client->adapter->name);
1935
1936 return 0;
1937
1938err_work_queues:
1939 cancel_delayed_work(&state->delayed_work_enable_hotplug);
1940 destroy_workqueue(state->work_queues);
1941 mutex_destroy(&state->confctl_mutex);
1942err_hdl:
4c5211a1 1943 media_entity_cleanup(&sd->entity);
d32d9864
MR		 1944 v4l2_ctrl_handler_free(&state->hdl);
1945 return err;
1946}
1947
1948static int tc358743_remove(struct i2c_client *client)
1949{
1950 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1951 struct tc358743_state *state = to_state(sd);
1952
1953 cancel_delayed_work(&state->delayed_work_enable_hotplug);
1954 destroy_workqueue(state->work_queues);
4c5211a1 1955 v4l2_async_unregister_subdev(sd);
d32d9864
MR		 1956 v4l2_device_unregister_subdev(sd);
1957 mutex_destroy(&state->confctl_mutex);
4c5211a1 1958 media_entity_cleanup(&sd->entity);
d32d9864
MR		 1959 v4l2_ctrl_handler_free(&state->hdl);
1960
1961 return 0;
1962}
1963
1964static struct i2c_device_id tc358743_id[] = {
1965 {"tc358743", 0},
1966 {}
1967};
1968
1969MODULE_DEVICE_TABLE(i2c, tc358743_id);
1970
1971static struct i2c_driver tc358743_driver = {
1972 .driver = {
d32d9864
MR		 1973 .name = "tc358743",
1974 },
1975 .probe = tc358743_probe,
1976 .remove = tc358743_remove,
1977 .id_table = tc358743_id,
1978};
1979
1980module_i2c_driver(tc358743_driver);
Ubuntu Artful kernel mirror