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[mirror_ubuntu-artful-kernel.git] / drivers / media / i2c / tvp514x.c
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07b1747c 1/*
cb7a01ac 2 * drivers/media/i2c/tvp514x.c
07b1747c
VH
3 *
4 * TI TVP5146/47 decoder driver
5 *
6 * Copyright (C) 2008 Texas Instruments Inc
7 * Author: Vaibhav Hiremath <hvaibhav@ti.com>
8 *
9 * Contributors:
10 * Sivaraj R <sivaraj@ti.com>
11 * Brijesh R Jadav <brijesh.j@ti.com>
12 * Hardik Shah <hardik.shah@ti.com>
13 * Manjunath Hadli <mrh@ti.com>
14 * Karicheri Muralidharan <m-karicheri2@ti.com>
5b38b0f8 15 * Prabhakar Lad <prabhakar.lad@ti.com>
07b1747c
VH
16 *
17 * This package is free software; you can redistribute it and/or modify
18 * it under the terms of the GNU General Public License version 2 as
19 * published by the Free Software Foundation.
20 *
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; if not, write to the Free Software
28 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
29 *
30 */
31
32#include <linux/i2c.h>
5a0e3ad6 33#include <linux/slab.h>
07b1747c
VH
34#include <linux/delay.h>
35#include <linux/videodev2.h>
7a707b89 36#include <linux/module.h>
5b38b0f8 37#include <linux/v4l2-mediabus.h>
098bcba3 38#include <linux/of.h>
fd9fdb78 39#include <linux/of_graph.h>
62ef80a1 40
8f23acb5 41#include <media/v4l2-async.h>
62ef80a1
MK
42#include <media/v4l2-device.h>
43#include <media/v4l2-common.h>
83811913 44#include <media/v4l2-mediabus.h>
b610b592 45#include <media/v4l2-of.h>
cf6832af 46#include <media/v4l2-ctrls.h>
07b1747c 47#include <media/tvp514x.h>
5b38b0f8 48#include <media/media-entity.h>
07b1747c
VH
49
50#include "tvp514x_regs.h"
51
07b1747c
VH
52/* Private macros for TVP */
53#define I2C_RETRY_COUNT (5)
54#define LOCK_RETRY_COUNT (5)
55#define LOCK_RETRY_DELAY (200)
56
57/* Debug functions */
90ab5ee9 58static bool debug;
07b1747c
VH
59module_param(debug, bool, 0644);
60MODULE_PARM_DESC(debug, "Debug level (0-1)");
61
62ef80a1
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62MODULE_AUTHOR("Texas Instruments");
63MODULE_DESCRIPTION("TVP514X linux decoder driver");
64MODULE_LICENSE("GPL");
07b1747c 65
c1c9d09c 66/* enum tvp514x_std - enum for supported standards */
07b1747c
VH
67enum tvp514x_std {
68 STD_NTSC_MJ = 0,
69 STD_PAL_BDGHIN,
70 STD_INVALID
71};
72
c1c9d09c 73/**
07b1747c
VH
74 * struct tvp514x_std_info - Structure to store standard informations
75 * @width: Line width in pixels
76 * @height:Number of active lines
77 * @video_std: Value to write in REG_VIDEO_STD register
78 * @standard: v4l2 standard structure information
79 */
80struct tvp514x_std_info {
81 unsigned long width;
82 unsigned long height;
83 u8 video_std;
84 struct v4l2_standard standard;
85};
86
6722e0ef 87static struct tvp514x_reg tvp514x_reg_list_default[0x40];
63b59cec
VH
88
89static int tvp514x_s_stream(struct v4l2_subdev *sd, int enable);
c1c9d09c 90/**
6722e0ef 91 * struct tvp514x_decoder - TVP5146/47 decoder object
62ef80a1 92 * @sd: Subdevice Slave handle
6722e0ef 93 * @tvp514x_regs: copy of hw's regs with preset values.
07b1747c 94 * @pdata: Board specific
07b1747c 95 * @ver: Chip version
62ef80a1 96 * @streaming: TVP5146/47 decoder streaming - enabled or disabled.
5b38b0f8
MH
97 * @pix: Current pixel format
98 * @num_fmts: Number of formats
99 * @fmt_list: Format list
07b1747c
VH
100 * @current_std: Current standard
101 * @num_stds: Number of standards
102 * @std_list: Standards list
62ef80a1
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103 * @input: Input routing at chip level
104 * @output: Output routing at chip level
07b1747c
VH
105 */
106struct tvp514x_decoder {
62ef80a1 107 struct v4l2_subdev sd;
cf6832af 108 struct v4l2_ctrl_handler hdl;
6722e0ef 109 struct tvp514x_reg tvp514x_regs[ARRAY_SIZE(tvp514x_reg_list_default)];
07b1747c 110 const struct tvp514x_platform_data *pdata;
07b1747c
VH
111
112 int ver;
62ef80a1 113 int streaming;
07b1747c 114
5b38b0f8
MH
115 struct v4l2_pix_format pix;
116 int num_fmts;
117 const struct v4l2_fmtdesc *fmt_list;
118
07b1747c
VH
119 enum tvp514x_std current_std;
120 int num_stds;
a75ffc12 121 const struct tvp514x_std_info *std_list;
c1c9d09c 122 /* Input and Output Routing parameters */
62ef80a1
MK
123 u32 input;
124 u32 output;
5b38b0f8
MH
125
126 /* mc related members */
127 struct media_pad pad;
128 struct v4l2_mbus_framefmt format;
f0a12d0c
LPC
129
130 struct tvp514x_reg *int_seq;
07b1747c
VH
131};
132
133/* TVP514x default register values */
6722e0ef 134static struct tvp514x_reg tvp514x_reg_list_default[] = {
c1c9d09c
MK
135 /* Composite selected */
136 {TOK_WRITE, REG_INPUT_SEL, 0x05},
07b1747c 137 {TOK_WRITE, REG_AFE_GAIN_CTRL, 0x0F},
c1c9d09c
MK
138 /* Auto mode */
139 {TOK_WRITE, REG_VIDEO_STD, 0x00},
07b1747c
VH
140 {TOK_WRITE, REG_OPERATION_MODE, 0x00},
141 {TOK_SKIP, REG_AUTOSWITCH_MASK, 0x3F},
142 {TOK_WRITE, REG_COLOR_KILLER, 0x10},
143 {TOK_WRITE, REG_LUMA_CONTROL1, 0x00},
144 {TOK_WRITE, REG_LUMA_CONTROL2, 0x00},
145 {TOK_WRITE, REG_LUMA_CONTROL3, 0x02},
146 {TOK_WRITE, REG_BRIGHTNESS, 0x80},
147 {TOK_WRITE, REG_CONTRAST, 0x80},
148 {TOK_WRITE, REG_SATURATION, 0x80},
149 {TOK_WRITE, REG_HUE, 0x00},
150 {TOK_WRITE, REG_CHROMA_CONTROL1, 0x00},
151 {TOK_WRITE, REG_CHROMA_CONTROL2, 0x0E},
c1c9d09c
MK
152 /* Reserved */
153 {TOK_SKIP, 0x0F, 0x00},
07b1747c
VH
154 {TOK_WRITE, REG_COMP_PR_SATURATION, 0x80},
155 {TOK_WRITE, REG_COMP_Y_CONTRAST, 0x80},
156 {TOK_WRITE, REG_COMP_PB_SATURATION, 0x80},
c1c9d09c
MK
157 /* Reserved */
158 {TOK_SKIP, 0x13, 0x00},
07b1747c 159 {TOK_WRITE, REG_COMP_Y_BRIGHTNESS, 0x80},
c1c9d09c
MK
160 /* Reserved */
161 {TOK_SKIP, 0x15, 0x00},
162 /* NTSC timing */
163 {TOK_SKIP, REG_AVID_START_PIXEL_LSB, 0x55},
07b1747c
VH
164 {TOK_SKIP, REG_AVID_START_PIXEL_MSB, 0x00},
165 {TOK_SKIP, REG_AVID_STOP_PIXEL_LSB, 0x25},
166 {TOK_SKIP, REG_AVID_STOP_PIXEL_MSB, 0x03},
c1c9d09c
MK
167 /* NTSC timing */
168 {TOK_SKIP, REG_HSYNC_START_PIXEL_LSB, 0x00},
07b1747c
VH
169 {TOK_SKIP, REG_HSYNC_START_PIXEL_MSB, 0x00},
170 {TOK_SKIP, REG_HSYNC_STOP_PIXEL_LSB, 0x40},
171 {TOK_SKIP, REG_HSYNC_STOP_PIXEL_MSB, 0x00},
c1c9d09c
MK
172 /* NTSC timing */
173 {TOK_SKIP, REG_VSYNC_START_LINE_LSB, 0x04},
07b1747c
VH
174 {TOK_SKIP, REG_VSYNC_START_LINE_MSB, 0x00},
175 {TOK_SKIP, REG_VSYNC_STOP_LINE_LSB, 0x07},
176 {TOK_SKIP, REG_VSYNC_STOP_LINE_MSB, 0x00},
c1c9d09c
MK
177 /* NTSC timing */
178 {TOK_SKIP, REG_VBLK_START_LINE_LSB, 0x01},
07b1747c
VH
179 {TOK_SKIP, REG_VBLK_START_LINE_MSB, 0x00},
180 {TOK_SKIP, REG_VBLK_STOP_LINE_LSB, 0x15},
181 {TOK_SKIP, REG_VBLK_STOP_LINE_MSB, 0x00},
c1c9d09c
MK
182 /* Reserved */
183 {TOK_SKIP, 0x26, 0x00},
184 /* Reserved */
185 {TOK_SKIP, 0x27, 0x00},
07b1747c 186 {TOK_SKIP, REG_FAST_SWTICH_CONTROL, 0xCC},
c1c9d09c
MK
187 /* Reserved */
188 {TOK_SKIP, 0x29, 0x00},
07b1747c 189 {TOK_SKIP, REG_FAST_SWTICH_SCART_DELAY, 0x00},
c1c9d09c
MK
190 /* Reserved */
191 {TOK_SKIP, 0x2B, 0x00},
07b1747c
VH
192 {TOK_SKIP, REG_SCART_DELAY, 0x00},
193 {TOK_SKIP, REG_CTI_DELAY, 0x00},
194 {TOK_SKIP, REG_CTI_CONTROL, 0x00},
c1c9d09c
MK
195 /* Reserved */
196 {TOK_SKIP, 0x2F, 0x00},
197 /* Reserved */
198 {TOK_SKIP, 0x30, 0x00},
199 /* Reserved */
200 {TOK_SKIP, 0x31, 0x00},
201 /* HS, VS active high */
202 {TOK_WRITE, REG_SYNC_CONTROL, 0x00},
203 /* 10-bit BT.656 */
204 {TOK_WRITE, REG_OUTPUT_FORMATTER1, 0x00},
205 /* Enable clk & data */
206 {TOK_WRITE, REG_OUTPUT_FORMATTER2, 0x11},
207 /* Enable AVID & FLD */
208 {TOK_WRITE, REG_OUTPUT_FORMATTER3, 0xEE},
209 /* Enable VS & HS */
210 {TOK_WRITE, REG_OUTPUT_FORMATTER4, 0xAF},
07b1747c
VH
211 {TOK_WRITE, REG_OUTPUT_FORMATTER5, 0xFF},
212 {TOK_WRITE, REG_OUTPUT_FORMATTER6, 0xFF},
c1c9d09c
MK
213 /* Clear status */
214 {TOK_WRITE, REG_CLEAR_LOST_LOCK, 0x01},
07b1747c
VH
215 {TOK_TERM, 0, 0},
216};
217
5b38b0f8
MH
218/**
219 * List of image formats supported by TVP5146/47 decoder
220 * Currently we are using 8 bit mode only, but can be
221 * extended to 10/20 bit mode.
222 */
223static const struct v4l2_fmtdesc tvp514x_fmt_list[] = {
224 {
225 .index = 0,
226 .type = V4L2_BUF_TYPE_VIDEO_CAPTURE,
227 .flags = 0,
228 .description = "8-bit UYVY 4:2:2 Format",
229 .pixelformat = V4L2_PIX_FMT_UYVY,
230 },
231};
232
c1c9d09c 233/**
07b1747c
VH
234 * Supported standards -
235 *
236 * Currently supports two standards only, need to add support for rest of the
237 * modes, like SECAM, etc...
238 */
a75ffc12 239static const struct tvp514x_std_info tvp514x_std_list[] = {
07b1747c
VH
240 /* Standard: STD_NTSC_MJ */
241 [STD_NTSC_MJ] = {
242 .width = NTSC_NUM_ACTIVE_PIXELS,
243 .height = NTSC_NUM_ACTIVE_LINES,
244 .video_std = VIDEO_STD_NTSC_MJ_BIT,
245 .standard = {
246 .index = 0,
247 .id = V4L2_STD_NTSC,
248 .name = "NTSC",
249 .frameperiod = {1001, 30000},
250 .framelines = 525
251 },
252 /* Standard: STD_PAL_BDGHIN */
253 },
254 [STD_PAL_BDGHIN] = {
255 .width = PAL_NUM_ACTIVE_PIXELS,
256 .height = PAL_NUM_ACTIVE_LINES,
257 .video_std = VIDEO_STD_PAL_BDGHIN_BIT,
258 .standard = {
259 .index = 1,
260 .id = V4L2_STD_PAL,
261 .name = "PAL",
262 .frameperiod = {1, 25},
263 .framelines = 625
264 },
265 },
266 /* Standard: need to add for additional standard */
267};
62ef80a1
MK
268
269
270static inline struct tvp514x_decoder *to_decoder(struct v4l2_subdev *sd)
271{
272 return container_of(sd, struct tvp514x_decoder, sd);
273}
274
cf6832af
HV
275static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
276{
277 return &container_of(ctrl->handler, struct tvp514x_decoder, hdl)->sd;
278}
279
07b1747c 280
c1c9d09c
MK
281/**
282 * tvp514x_read_reg() - Read a value from a register in an TVP5146/47.
283 * @sd: ptr to v4l2_subdev struct
284 * @reg: TVP5146/47 register address
285 *
07b1747c
VH
286 * Returns value read if successful, or non-zero (-1) otherwise.
287 */
62ef80a1 288static int tvp514x_read_reg(struct v4l2_subdev *sd, u8 reg)
07b1747c 289{
62ef80a1
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290 int err, retry = 0;
291 struct i2c_client *client = v4l2_get_subdevdata(sd);
292
07b1747c
VH
293read_again:
294
295 err = i2c_smbus_read_byte_data(client, reg);
6f901a99 296 if (err < 0) {
07b1747c 297 if (retry <= I2C_RETRY_COUNT) {
62ef80a1 298 v4l2_warn(sd, "Read: retry ... %d\n", retry);
07b1747c
VH
299 retry++;
300 msleep_interruptible(10);
301 goto read_again;
302 }
303 }
304
305 return err;
306}
307
c1c9d09c
MK
308/**
309 * dump_reg() - dump the register content of TVP5146/47.
310 * @sd: ptr to v4l2_subdev struct
311 * @reg: TVP5146/47 register address
312 */
62ef80a1
MK
313static void dump_reg(struct v4l2_subdev *sd, u8 reg)
314{
315 u32 val;
316
317 val = tvp514x_read_reg(sd, reg);
318 v4l2_info(sd, "Reg(0x%.2X): 0x%.2X\n", reg, val);
319}
320
c1c9d09c
MK
321/**
322 * tvp514x_write_reg() - Write a value to a register in TVP5146/47
323 * @sd: ptr to v4l2_subdev struct
324 * @reg: TVP5146/47 register address
325 * @val: value to be written to the register
326 *
07b1747c
VH
327 * Write a value to a register in an TVP5146/47 decoder device.
328 * Returns zero if successful, or non-zero otherwise.
329 */
62ef80a1 330static int tvp514x_write_reg(struct v4l2_subdev *sd, u8 reg, u8 val)
07b1747c 331{
62ef80a1
MK
332 int err, retry = 0;
333 struct i2c_client *client = v4l2_get_subdevdata(sd);
334
07b1747c
VH
335write_again:
336
337 err = i2c_smbus_write_byte_data(client, reg, val);
338 if (err) {
339 if (retry <= I2C_RETRY_COUNT) {
62ef80a1 340 v4l2_warn(sd, "Write: retry ... %d\n", retry);
07b1747c
VH
341 retry++;
342 msleep_interruptible(10);
343 goto write_again;
344 }
345 }
346
347 return err;
348}
349
c1c9d09c
MK
350/**
351 * tvp514x_write_regs() : Initializes a list of TVP5146/47 registers
352 * @sd: ptr to v4l2_subdev struct
353 * @reglist: list of TVP5146/47 registers and values
354 *
355 * Initializes a list of TVP5146/47 registers:-
07b1747c
VH
356 * if token is TOK_TERM, then entire write operation terminates
357 * if token is TOK_DELAY, then a delay of 'val' msec is introduced
358 * if token is TOK_SKIP, then the register write is skipped
359 * if token is TOK_WRITE, then the register write is performed
07b1747c
VH
360 * Returns zero if successful, or non-zero otherwise.
361 */
62ef80a1 362static int tvp514x_write_regs(struct v4l2_subdev *sd,
07b1747c
VH
363 const struct tvp514x_reg reglist[])
364{
365 int err;
366 const struct tvp514x_reg *next = reglist;
367
368 for (; next->token != TOK_TERM; next++) {
369 if (next->token == TOK_DELAY) {
370 msleep(next->val);
371 continue;
372 }
373
374 if (next->token == TOK_SKIP)
375 continue;
376
62ef80a1 377 err = tvp514x_write_reg(sd, next->reg, (u8) next->val);
07b1747c 378 if (err) {
62ef80a1 379 v4l2_err(sd, "Write failed. Err[%d]\n", err);
07b1747c
VH
380 return err;
381 }
382 }
383 return 0;
384}
385
c1c9d09c 386/**
2db4e78f 387 * tvp514x_query_current_std() : Query the current standard detected by TVP5146/47
c1c9d09c
MK
388 * @sd: ptr to v4l2_subdev struct
389 *
2db4e78f 390 * Returns the current standard detected by TVP5146/47, STD_INVALID if there is no
c1c9d09c 391 * standard detected.
07b1747c 392 */
2db4e78f 393static enum tvp514x_std tvp514x_query_current_std(struct v4l2_subdev *sd)
07b1747c
VH
394{
395 u8 std, std_status;
396
62ef80a1
MK
397 std = tvp514x_read_reg(sd, REG_VIDEO_STD);
398 if ((std & VIDEO_STD_MASK) == VIDEO_STD_AUTO_SWITCH_BIT)
07b1747c 399 /* use the standard status register */
62ef80a1
MK
400 std_status = tvp514x_read_reg(sd, REG_VIDEO_STD_STATUS);
401 else
c1c9d09c
MK
402 /* use the standard register itself */
403 std_status = std;
07b1747c
VH
404
405 switch (std_status & VIDEO_STD_MASK) {
406 case VIDEO_STD_NTSC_MJ_BIT:
407 return STD_NTSC_MJ;
408
409 case VIDEO_STD_PAL_BDGHIN_BIT:
410 return STD_PAL_BDGHIN;
411
412 default:
413 return STD_INVALID;
414 }
415
416 return STD_INVALID;
417}
418
c1c9d09c 419/* TVP5146/47 register dump function */
62ef80a1 420static void tvp514x_reg_dump(struct v4l2_subdev *sd)
07b1747c 421{
62ef80a1
MK
422 dump_reg(sd, REG_INPUT_SEL);
423 dump_reg(sd, REG_AFE_GAIN_CTRL);
424 dump_reg(sd, REG_VIDEO_STD);
425 dump_reg(sd, REG_OPERATION_MODE);
426 dump_reg(sd, REG_COLOR_KILLER);
427 dump_reg(sd, REG_LUMA_CONTROL1);
428 dump_reg(sd, REG_LUMA_CONTROL2);
429 dump_reg(sd, REG_LUMA_CONTROL3);
430 dump_reg(sd, REG_BRIGHTNESS);
431 dump_reg(sd, REG_CONTRAST);
432 dump_reg(sd, REG_SATURATION);
433 dump_reg(sd, REG_HUE);
434 dump_reg(sd, REG_CHROMA_CONTROL1);
435 dump_reg(sd, REG_CHROMA_CONTROL2);
436 dump_reg(sd, REG_COMP_PR_SATURATION);
437 dump_reg(sd, REG_COMP_Y_CONTRAST);
438 dump_reg(sd, REG_COMP_PB_SATURATION);
439 dump_reg(sd, REG_COMP_Y_BRIGHTNESS);
440 dump_reg(sd, REG_AVID_START_PIXEL_LSB);
441 dump_reg(sd, REG_AVID_START_PIXEL_MSB);
442 dump_reg(sd, REG_AVID_STOP_PIXEL_LSB);
443 dump_reg(sd, REG_AVID_STOP_PIXEL_MSB);
444 dump_reg(sd, REG_HSYNC_START_PIXEL_LSB);
445 dump_reg(sd, REG_HSYNC_START_PIXEL_MSB);
446 dump_reg(sd, REG_HSYNC_STOP_PIXEL_LSB);
447 dump_reg(sd, REG_HSYNC_STOP_PIXEL_MSB);
448 dump_reg(sd, REG_VSYNC_START_LINE_LSB);
449 dump_reg(sd, REG_VSYNC_START_LINE_MSB);
450 dump_reg(sd, REG_VSYNC_STOP_LINE_LSB);
451 dump_reg(sd, REG_VSYNC_STOP_LINE_MSB);
452 dump_reg(sd, REG_VBLK_START_LINE_LSB);
453 dump_reg(sd, REG_VBLK_START_LINE_MSB);
454 dump_reg(sd, REG_VBLK_STOP_LINE_LSB);
455 dump_reg(sd, REG_VBLK_STOP_LINE_MSB);
456 dump_reg(sd, REG_SYNC_CONTROL);
457 dump_reg(sd, REG_OUTPUT_FORMATTER1);
458 dump_reg(sd, REG_OUTPUT_FORMATTER2);
459 dump_reg(sd, REG_OUTPUT_FORMATTER3);
460 dump_reg(sd, REG_OUTPUT_FORMATTER4);
461 dump_reg(sd, REG_OUTPUT_FORMATTER5);
462 dump_reg(sd, REG_OUTPUT_FORMATTER6);
463 dump_reg(sd, REG_CLEAR_LOST_LOCK);
07b1747c
VH
464}
465
c1c9d09c
MK
466/**
467 * tvp514x_configure() - Configure the TVP5146/47 registers
468 * @sd: ptr to v4l2_subdev struct
469 * @decoder: ptr to tvp514x_decoder structure
470 *
07b1747c
VH
471 * Returns zero if successful, or non-zero otherwise.
472 */
62ef80a1
MK
473static int tvp514x_configure(struct v4l2_subdev *sd,
474 struct tvp514x_decoder *decoder)
07b1747c
VH
475{
476 int err;
477
478 /* common register initialization */
479 err =
62ef80a1 480 tvp514x_write_regs(sd, decoder->tvp514x_regs);
07b1747c
VH
481 if (err)
482 return err;
483
484 if (debug)
62ef80a1 485 tvp514x_reg_dump(sd);
07b1747c
VH
486
487 return 0;
488}
489
c1c9d09c
MK
490/**
491 * tvp514x_detect() - Detect if an tvp514x is present, and if so which revision.
492 * @sd: pointer to standard V4L2 sub-device structure
493 * @decoder: pointer to tvp514x_decoder structure
494 *
07b1747c
VH
495 * A device is considered to be detected if the chip ID (LSB and MSB)
496 * registers match the expected values.
497 * Any value of the rom version register is accepted.
498 * Returns ENODEV error number if no device is detected, or zero
499 * if a device is detected.
500 */
62ef80a1
MK
501static int tvp514x_detect(struct v4l2_subdev *sd,
502 struct tvp514x_decoder *decoder)
07b1747c
VH
503{
504 u8 chip_id_msb, chip_id_lsb, rom_ver;
62ef80a1 505 struct i2c_client *client = v4l2_get_subdevdata(sd);
07b1747c 506
62ef80a1
MK
507 chip_id_msb = tvp514x_read_reg(sd, REG_CHIP_ID_MSB);
508 chip_id_lsb = tvp514x_read_reg(sd, REG_CHIP_ID_LSB);
509 rom_ver = tvp514x_read_reg(sd, REG_ROM_VERSION);
07b1747c 510
62ef80a1 511 v4l2_dbg(1, debug, sd,
07b1747c
VH
512 "chip id detected msb:0x%x lsb:0x%x rom version:0x%x\n",
513 chip_id_msb, chip_id_lsb, rom_ver);
514 if ((chip_id_msb != TVP514X_CHIP_ID_MSB)
515 || ((chip_id_lsb != TVP5146_CHIP_ID_LSB)
516 && (chip_id_lsb != TVP5147_CHIP_ID_LSB))) {
517 /* We didn't read the values we expected, so this must not be
518 * an TVP5146/47.
519 */
62ef80a1
MK
520 v4l2_err(sd, "chip id mismatch msb:0x%x lsb:0x%x\n",
521 chip_id_msb, chip_id_lsb);
07b1747c
VH
522 return -ENODEV;
523 }
524
525 decoder->ver = rom_ver;
07b1747c 526
62ef80a1
MK
527 v4l2_info(sd, "%s (Version - 0x%.2x) found at 0x%x (%s)\n",
528 client->name, decoder->ver,
529 client->addr << 1, client->adapter->name);
07b1747c
VH
530 return 0;
531}
532
c1c9d09c
MK
533/**
534 * tvp514x_querystd() - V4L2 decoder interface handler for querystd
62ef80a1 535 * @sd: pointer to standard V4L2 sub-device structure
07b1747c
VH
536 * @std_id: standard V4L2 std_id ioctl enum
537 *
538 * Returns the current standard detected by TVP5146/47. If no active input is
2db4e78f 539 * detected then *std_id is set to 0 and the function returns 0.
07b1747c 540 */
62ef80a1 541static int tvp514x_querystd(struct v4l2_subdev *sd, v4l2_std_id *std_id)
07b1747c 542{
62ef80a1 543 struct tvp514x_decoder *decoder = to_decoder(sd);
07b1747c
VH
544 enum tvp514x_std current_std;
545 enum tvp514x_input input_sel;
546 u8 sync_lock_status, lock_mask;
547
548 if (std_id == NULL)
549 return -EINVAL;
550
c389648a
HV
551 /* To query the standard the TVP514x must power on the ADCs. */
552 if (!decoder->streaming) {
553 tvp514x_s_stream(sd, 1);
554 msleep(LOCK_RETRY_DELAY);
555 }
556
2db4e78f
HV
557 /* query the current standard */
558 current_std = tvp514x_query_current_std(sd);
55852cbb
HV
559 if (current_std == STD_INVALID) {
560 *std_id = V4L2_STD_UNKNOWN;
2db4e78f 561 return 0;
55852cbb 562 }
07b1747c 563
62ef80a1 564 input_sel = decoder->input;
07b1747c
VH
565
566 switch (input_sel) {
567 case INPUT_CVBS_VI1A:
568 case INPUT_CVBS_VI1B:
569 case INPUT_CVBS_VI1C:
570 case INPUT_CVBS_VI2A:
571 case INPUT_CVBS_VI2B:
572 case INPUT_CVBS_VI2C:
573 case INPUT_CVBS_VI3A:
574 case INPUT_CVBS_VI3B:
575 case INPUT_CVBS_VI3C:
576 case INPUT_CVBS_VI4A:
577 lock_mask = STATUS_CLR_SUBCAR_LOCK_BIT |
578 STATUS_HORZ_SYNC_LOCK_BIT |
579 STATUS_VIRT_SYNC_LOCK_BIT;
580 break;
581
582 case INPUT_SVIDEO_VI2A_VI1A:
583 case INPUT_SVIDEO_VI2B_VI1B:
584 case INPUT_SVIDEO_VI2C_VI1C:
585 case INPUT_SVIDEO_VI2A_VI3A:
586 case INPUT_SVIDEO_VI2B_VI3B:
587 case INPUT_SVIDEO_VI2C_VI3C:
588 case INPUT_SVIDEO_VI4A_VI1A:
589 case INPUT_SVIDEO_VI4A_VI1B:
590 case INPUT_SVIDEO_VI4A_VI1C:
591 case INPUT_SVIDEO_VI4A_VI3A:
592 case INPUT_SVIDEO_VI4A_VI3B:
593 case INPUT_SVIDEO_VI4A_VI3C:
594 lock_mask = STATUS_HORZ_SYNC_LOCK_BIT |
595 STATUS_VIRT_SYNC_LOCK_BIT;
596 break;
597 /*Need to add other interfaces*/
598 default:
599 return -EINVAL;
600 }
601 /* check whether signal is locked */
62ef80a1 602 sync_lock_status = tvp514x_read_reg(sd, REG_STATUS1);
55852cbb
HV
603 if (lock_mask != (sync_lock_status & lock_mask)) {
604 *std_id = V4L2_STD_UNKNOWN;
2db4e78f 605 return 0; /* No input detected */
55852cbb 606 }
07b1747c 607
55852cbb 608 *std_id &= decoder->std_list[current_std].standard.id;
07b1747c 609
2db4e78f 610 v4l2_dbg(1, debug, sd, "Current STD: %s\n",
07b1747c
VH
611 decoder->std_list[current_std].standard.name);
612 return 0;
613}
614
c1c9d09c
MK
615/**
616 * tvp514x_s_std() - V4L2 decoder interface handler for s_std
62ef80a1 617 * @sd: pointer to standard V4L2 sub-device structure
07b1747c
VH
618 * @std_id: standard V4L2 v4l2_std_id ioctl enum
619 *
620 * If std_id is supported, sets the requested standard. Otherwise, returns
621 * -EINVAL
622 */
62ef80a1 623static int tvp514x_s_std(struct v4l2_subdev *sd, v4l2_std_id std_id)
07b1747c 624{
62ef80a1 625 struct tvp514x_decoder *decoder = to_decoder(sd);
07b1747c
VH
626 int err, i;
627
07b1747c 628 for (i = 0; i < decoder->num_stds; i++)
62ef80a1 629 if (std_id & decoder->std_list[i].standard.id)
07b1747c
VH
630 break;
631
632 if ((i == decoder->num_stds) || (i == STD_INVALID))
633 return -EINVAL;
634
62ef80a1 635 err = tvp514x_write_reg(sd, REG_VIDEO_STD,
07b1747c
VH
636 decoder->std_list[i].video_std);
637 if (err)
638 return err;
639
640 decoder->current_std = i;
6722e0ef
SAS
641 decoder->tvp514x_regs[REG_VIDEO_STD].val =
642 decoder->std_list[i].video_std;
07b1747c 643
3907b072 644 v4l2_dbg(1, debug, sd, "Standard set to: %s\n",
07b1747c
VH
645 decoder->std_list[i].standard.name);
646 return 0;
647}
648
c1c9d09c
MK
649/**
650 * tvp514x_s_routing() - V4L2 decoder interface handler for s_routing
62ef80a1 651 * @sd: pointer to standard V4L2 sub-device structure
c1c9d09c
MK
652 * @input: input selector for routing the signal
653 * @output: output selector for routing the signal
654 * @config: config value. Not used
07b1747c
VH
655 *
656 * If index is valid, selects the requested input. Otherwise, returns -EINVAL if
657 * the input is not supported or there is no active signal present in the
658 * selected input.
659 */
62ef80a1
MK
660static int tvp514x_s_routing(struct v4l2_subdev *sd,
661 u32 input, u32 output, u32 config)
07b1747c 662{
62ef80a1 663 struct tvp514x_decoder *decoder = to_decoder(sd);
07b1747c
VH
664 int err;
665 enum tvp514x_input input_sel;
666 enum tvp514x_output output_sel;
07b1747c 667
62ef80a1
MK
668 if ((input >= INPUT_INVALID) ||
669 (output >= OUTPUT_INVALID))
c1c9d09c
MK
670 /* Index out of bound */
671 return -EINVAL;
07b1747c 672
62ef80a1
MK
673 input_sel = input;
674 output_sel = output;
07b1747c 675
62ef80a1 676 err = tvp514x_write_reg(sd, REG_INPUT_SEL, input_sel);
07b1747c
VH
677 if (err)
678 return err;
679
62ef80a1 680 output_sel |= tvp514x_read_reg(sd,
07b1747c 681 REG_OUTPUT_FORMATTER1) & 0x7;
62ef80a1 682 err = tvp514x_write_reg(sd, REG_OUTPUT_FORMATTER1,
07b1747c
VH
683 output_sel);
684 if (err)
685 return err;
686
6722e0ef
SAS
687 decoder->tvp514x_regs[REG_INPUT_SEL].val = input_sel;
688 decoder->tvp514x_regs[REG_OUTPUT_FORMATTER1].val = output_sel;
62ef80a1
MK
689 decoder->input = input;
690 decoder->output = output;
07b1747c 691
2db4e78f 692 v4l2_dbg(1, debug, sd, "Input set to: %d\n", input_sel);
07b1747c
VH
693
694 return 0;
695}
696
c1c9d09c
MK
697/**
698 * tvp514x_s_ctrl() - V4L2 decoder interface handler for s_ctrl
cf6832af 699 * @ctrl: pointer to v4l2_ctrl structure
07b1747c
VH
700 *
701 * If the requested control is supported, sets the control's current
702 * value in HW. Otherwise, returns -EINVAL if the control is not supported.
703 */
cf6832af 704static int tvp514x_s_ctrl(struct v4l2_ctrl *ctrl)
07b1747c 705{
cf6832af 706 struct v4l2_subdev *sd = to_sd(ctrl);
62ef80a1 707 struct tvp514x_decoder *decoder = to_decoder(sd);
07b1747c
VH
708 int err = -EINVAL, value;
709
cf6832af 710 value = ctrl->val;
07b1747c
VH
711
712 switch (ctrl->id) {
713 case V4L2_CID_BRIGHTNESS:
cf6832af
HV
714 err = tvp514x_write_reg(sd, REG_BRIGHTNESS, value);
715 if (!err)
716 decoder->tvp514x_regs[REG_BRIGHTNESS].val = value;
07b1747c
VH
717 break;
718 case V4L2_CID_CONTRAST:
62ef80a1 719 err = tvp514x_write_reg(sd, REG_CONTRAST, value);
cf6832af
HV
720 if (!err)
721 decoder->tvp514x_regs[REG_CONTRAST].val = value;
07b1747c
VH
722 break;
723 case V4L2_CID_SATURATION:
62ef80a1 724 err = tvp514x_write_reg(sd, REG_SATURATION, value);
cf6832af
HV
725 if (!err)
726 decoder->tvp514x_regs[REG_SATURATION].val = value;
07b1747c
VH
727 break;
728 case V4L2_CID_HUE:
729 if (value == 180)
730 value = 0x7F;
731 else if (value == -180)
732 value = 0x80;
62ef80a1 733 err = tvp514x_write_reg(sd, REG_HUE, value);
cf6832af
HV
734 if (!err)
735 decoder->tvp514x_regs[REG_HUE].val = value;
07b1747c
VH
736 break;
737 case V4L2_CID_AUTOGAIN:
cf6832af
HV
738 err = tvp514x_write_reg(sd, REG_AFE_GAIN_CTRL, value ? 0x0f : 0x0c);
739 if (!err)
740 decoder->tvp514x_regs[REG_AFE_GAIN_CTRL].val = value;
07b1747c 741 break;
07b1747c
VH
742 }
743
3907b072 744 v4l2_dbg(1, debug, sd, "Set Control: ID - %d - %d\n",
cf6832af 745 ctrl->id, ctrl->val);
07b1747c
VH
746 return err;
747}
748
83811913
HV
749/**
750 * tvp514x_enum_mbus_fmt() - V4L2 decoder interface handler for enum_mbus_fmt
751 * @sd: pointer to standard V4L2 sub-device structure
752 * @index: index of pixelcode to retrieve
753 * @code: receives the pixelcode
754 *
755 * Enumerates supported mediabus formats
756 */
757static int
758tvp514x_enum_mbus_fmt(struct v4l2_subdev *sd, unsigned index,
759 enum v4l2_mbus_pixelcode *code)
760{
761 if (index)
762 return -EINVAL;
763
764 *code = V4L2_MBUS_FMT_YUYV10_2X10;
765 return 0;
766}
767
83811913 768/**
5b38b0f8 769 * tvp514x_mbus_fmt() - V4L2 decoder interface handler for try/s/g_mbus_fmt
83811913
HV
770 * @sd: pointer to standard V4L2 sub-device structure
771 * @f: pointer to the mediabus format structure
772 *
773 * Negotiates the image capture size and mediabus format.
774 */
775static int
776tvp514x_mbus_fmt(struct v4l2_subdev *sd, struct v4l2_mbus_framefmt *f)
777{
778 struct tvp514x_decoder *decoder = to_decoder(sd);
779 enum tvp514x_std current_std;
780
781 if (f == NULL)
782 return -EINVAL;
783
784 /* Calculate height and width based on current standard */
785 current_std = decoder->current_std;
786
5b38b0f8 787 f->code = V4L2_MBUS_FMT_YUYV8_2X8;
83811913
HV
788 f->width = decoder->std_list[current_std].width;
789 f->height = decoder->std_list[current_std].height;
790 f->field = V4L2_FIELD_INTERLACED;
791 f->colorspace = V4L2_COLORSPACE_SMPTE170M;
83811913
HV
792 v4l2_dbg(1, debug, sd, "MBUS_FMT: Width - %d, Height - %d\n",
793 f->width, f->height);
794 return 0;
795}
796
c1c9d09c
MK
797/**
798 * tvp514x_g_parm() - V4L2 decoder interface handler for g_parm
62ef80a1 799 * @sd: pointer to standard V4L2 sub-device structure
07b1747c
VH
800 * @a: pointer to standard V4L2 VIDIOC_G_PARM ioctl structure
801 *
802 * Returns the decoder's video CAPTURE parameters.
803 */
804static int
62ef80a1 805tvp514x_g_parm(struct v4l2_subdev *sd, struct v4l2_streamparm *a)
07b1747c 806{
62ef80a1 807 struct tvp514x_decoder *decoder = to_decoder(sd);
07b1747c
VH
808 struct v4l2_captureparm *cparm;
809 enum tvp514x_std current_std;
810
811 if (a == NULL)
812 return -EINVAL;
813
814 if (a->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
c1c9d09c
MK
815 /* only capture is supported */
816 return -EINVAL;
07b1747c 817
07b1747c 818 /* get the current standard */
2db4e78f 819 current_std = decoder->current_std;
07b1747c
VH
820
821 cparm = &a->parm.capture;
822 cparm->capability = V4L2_CAP_TIMEPERFRAME;
823 cparm->timeperframe =
824 decoder->std_list[current_std].standard.frameperiod;
825
826 return 0;
827}
828
c1c9d09c
MK
829/**
830 * tvp514x_s_parm() - V4L2 decoder interface handler for s_parm
62ef80a1 831 * @sd: pointer to standard V4L2 sub-device structure
07b1747c
VH
832 * @a: pointer to standard V4L2 VIDIOC_S_PARM ioctl structure
833 *
834 * Configures the decoder to use the input parameters, if possible. If
835 * not possible, returns the appropriate error code.
836 */
837static int
62ef80a1 838tvp514x_s_parm(struct v4l2_subdev *sd, struct v4l2_streamparm *a)
07b1747c 839{
62ef80a1 840 struct tvp514x_decoder *decoder = to_decoder(sd);
07b1747c
VH
841 struct v4l2_fract *timeperframe;
842 enum tvp514x_std current_std;
843
844 if (a == NULL)
845 return -EINVAL;
846
847 if (a->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
c1c9d09c
MK
848 /* only capture is supported */
849 return -EINVAL;
07b1747c
VH
850
851 timeperframe = &a->parm.capture.timeperframe;
852
853 /* get the current standard */
2db4e78f 854 current_std = decoder->current_std;
07b1747c
VH
855
856 *timeperframe =
857 decoder->std_list[current_std].standard.frameperiod;
858
859 return 0;
860}
861
c1c9d09c
MK
862/**
863 * tvp514x_s_stream() - V4L2 decoder i/f handler for s_stream
62ef80a1
MK
864 * @sd: pointer to standard V4L2 sub-device structure
865 * @enable: streaming enable or disable
07b1747c 866 *
62ef80a1 867 * Sets streaming to enable or disable, if possible.
07b1747c 868 */
62ef80a1 869static int tvp514x_s_stream(struct v4l2_subdev *sd, int enable)
07b1747c 870{
07b1747c 871 int err = 0;
62ef80a1 872 struct tvp514x_decoder *decoder = to_decoder(sd);
07b1747c 873
62ef80a1
MK
874 if (decoder->streaming == enable)
875 return 0;
07b1747c 876
62ef80a1
MK
877 switch (enable) {
878 case 0:
879 {
880 /* Power Down Sequence */
881 err = tvp514x_write_reg(sd, REG_OPERATION_MODE, 0x01);
882 if (err) {
883 v4l2_err(sd, "Unable to turn off decoder\n");
884 return err;
885 }
886 decoder->streaming = enable;
07b1747c 887 break;
62ef80a1
MK
888 }
889 case 1:
890 {
62ef80a1 891 /* Power Up Sequence */
f0a12d0c 892 err = tvp514x_write_regs(sd, decoder->int_seq);
62ef80a1
MK
893 if (err) {
894 v4l2_err(sd, "Unable to turn on decoder\n");
895 return err;
896 }
897 /* Detect if not already detected */
898 err = tvp514x_detect(sd, decoder);
899 if (err) {
900 v4l2_err(sd, "Unable to detect decoder\n");
901 return err;
07b1747c 902 }
62ef80a1
MK
903 err = tvp514x_configure(sd, decoder);
904 if (err) {
905 v4l2_err(sd, "Unable to configure decoder\n");
906 return err;
907 }
908 decoder->streaming = enable;
07b1747c 909 break;
62ef80a1 910 }
07b1747c
VH
911 default:
912 err = -ENODEV;
913 break;
914 }
915
916 return err;
917}
918
cf6832af 919static const struct v4l2_ctrl_ops tvp514x_ctrl_ops = {
62ef80a1 920 .s_ctrl = tvp514x_s_ctrl,
cf6832af
HV
921};
922
5b38b0f8
MH
923/**
924 * tvp514x_enum_mbus_code() - V4L2 decoder interface handler for enum_mbus_code
925 * @sd: pointer to standard V4L2 sub-device structure
926 * @fh: file handle
927 * @code: pointer to v4l2_subdev_mbus_code_enum structure
928 *
929 * Enumertaes mbus codes supported
930 */
931static int tvp514x_enum_mbus_code(struct v4l2_subdev *sd,
932 struct v4l2_subdev_fh *fh,
933 struct v4l2_subdev_mbus_code_enum *code)
934{
935 u32 pad = code->pad;
936 u32 index = code->index;
937
938 memset(code, 0, sizeof(*code));
939 code->index = index;
940 code->pad = pad;
941
942 if (index != 0)
943 return -EINVAL;
944
945 code->code = V4L2_MBUS_FMT_YUYV8_2X8;
946
947 return 0;
948}
949
950/**
951 * tvp514x_get_pad_format() - V4L2 decoder interface handler for get pad format
952 * @sd: pointer to standard V4L2 sub-device structure
953 * @fh: file handle
954 * @format: pointer to v4l2_subdev_format structure
955 *
956 * Retrieves pad format which is active or tried based on requirement
957 */
958static int tvp514x_get_pad_format(struct v4l2_subdev *sd,
959 struct v4l2_subdev_fh *fh,
960 struct v4l2_subdev_format *format)
961{
962 struct tvp514x_decoder *decoder = to_decoder(sd);
963 __u32 which = format->which;
964
965 if (which == V4L2_SUBDEV_FORMAT_ACTIVE) {
966 format->format = decoder->format;
967 return 0;
968 }
969
970 format->format.code = V4L2_MBUS_FMT_YUYV8_2X8;
971 format->format.width = tvp514x_std_list[decoder->current_std].width;
972 format->format.height = tvp514x_std_list[decoder->current_std].height;
973 format->format.colorspace = V4L2_COLORSPACE_SMPTE170M;
974 format->format.field = V4L2_FIELD_INTERLACED;
975
976 return 0;
977}
978
979/**
980 * tvp514x_set_pad_format() - V4L2 decoder interface handler for set pad format
981 * @sd: pointer to standard V4L2 sub-device structure
982 * @fh: file handle
983 * @format: pointer to v4l2_subdev_format structure
984 *
985 * Set pad format for the output pad
986 */
987static int tvp514x_set_pad_format(struct v4l2_subdev *sd,
988 struct v4l2_subdev_fh *fh,
989 struct v4l2_subdev_format *fmt)
990{
991 struct tvp514x_decoder *decoder = to_decoder(sd);
992
993 if (fmt->format.field != V4L2_FIELD_INTERLACED ||
994 fmt->format.code != V4L2_MBUS_FMT_YUYV8_2X8 ||
995 fmt->format.colorspace != V4L2_COLORSPACE_SMPTE170M ||
996 fmt->format.width != tvp514x_std_list[decoder->current_std].width ||
997 fmt->format.height != tvp514x_std_list[decoder->current_std].height)
998 return -EINVAL;
999
1000 decoder->format = fmt->format;
1001
1002 return 0;
1003}
1004
cf6832af
HV
1005static const struct v4l2_subdev_core_ops tvp514x_core_ops = {
1006 .g_ext_ctrls = v4l2_subdev_g_ext_ctrls,
1007 .try_ext_ctrls = v4l2_subdev_try_ext_ctrls,
1008 .s_ext_ctrls = v4l2_subdev_s_ext_ctrls,
1009 .g_ctrl = v4l2_subdev_g_ctrl,
1010 .s_ctrl = v4l2_subdev_s_ctrl,
1011 .queryctrl = v4l2_subdev_queryctrl,
1012 .querymenu = v4l2_subdev_querymenu,
62ef80a1 1013};
07b1747c 1014
62ef80a1 1015static const struct v4l2_subdev_video_ops tvp514x_video_ops = {
8774bed9 1016 .s_std = tvp514x_s_std,
62ef80a1
MK
1017 .s_routing = tvp514x_s_routing,
1018 .querystd = tvp514x_querystd,
83811913
HV
1019 .enum_mbus_fmt = tvp514x_enum_mbus_fmt,
1020 .g_mbus_fmt = tvp514x_mbus_fmt,
1021 .try_mbus_fmt = tvp514x_mbus_fmt,
1022 .s_mbus_fmt = tvp514x_mbus_fmt,
62ef80a1
MK
1023 .g_parm = tvp514x_g_parm,
1024 .s_parm = tvp514x_s_parm,
1025 .s_stream = tvp514x_s_stream,
1026};
07b1747c 1027
5b38b0f8
MH
1028static const struct v4l2_subdev_pad_ops tvp514x_pad_ops = {
1029 .enum_mbus_code = tvp514x_enum_mbus_code,
1030 .get_fmt = tvp514x_get_pad_format,
1031 .set_fmt = tvp514x_set_pad_format,
1032};
1033
62ef80a1
MK
1034static const struct v4l2_subdev_ops tvp514x_ops = {
1035 .core = &tvp514x_core_ops,
1036 .video = &tvp514x_video_ops,
5b38b0f8 1037 .pad = &tvp514x_pad_ops,
07b1747c
VH
1038};
1039
07b1747c 1040static struct tvp514x_decoder tvp514x_dev = {
62ef80a1 1041 .streaming = 0,
5b38b0f8
MH
1042 .fmt_list = tvp514x_fmt_list,
1043 .num_fmts = ARRAY_SIZE(tvp514x_fmt_list),
1044 .pix = {
1045 /* Default to NTSC 8-bit YUV 422 */
1046 .width = NTSC_NUM_ACTIVE_PIXELS,
1047 .height = NTSC_NUM_ACTIVE_LINES,
1048 .pixelformat = V4L2_PIX_FMT_UYVY,
1049 .field = V4L2_FIELD_INTERLACED,
1050 .bytesperline = NTSC_NUM_ACTIVE_PIXELS * 2,
1051 .sizeimage = NTSC_NUM_ACTIVE_PIXELS * 2 *
1052 NTSC_NUM_ACTIVE_LINES,
1053 .colorspace = V4L2_COLORSPACE_SMPTE170M,
1054 },
07b1747c
VH
1055 .current_std = STD_NTSC_MJ,
1056 .std_list = tvp514x_std_list,
1057 .num_stds = ARRAY_SIZE(tvp514x_std_list),
62ef80a1 1058
07b1747c
VH
1059};
1060
b610b592
LP
1061static struct tvp514x_platform_data *
1062tvp514x_get_pdata(struct i2c_client *client)
1063{
1064 struct tvp514x_platform_data *pdata;
1065 struct v4l2_of_endpoint bus_cfg;
1066 struct device_node *endpoint;
1067 unsigned int flags;
1068
1069 if (!IS_ENABLED(CONFIG_OF) || !client->dev.of_node)
1070 return client->dev.platform_data;
1071
fd9fdb78 1072 endpoint = of_graph_get_next_endpoint(client->dev.of_node, NULL);
b610b592
LP
1073 if (!endpoint)
1074 return NULL;
1075
1076 pdata = devm_kzalloc(&client->dev, sizeof(*pdata), GFP_KERNEL);
1077 if (!pdata)
1078 goto done;
1079
1080 v4l2_of_parse_endpoint(endpoint, &bus_cfg);
1081 flags = bus_cfg.bus.parallel.flags;
1082
1083 if (flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH)
1084 pdata->hs_polarity = 1;
1085
1086 if (flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH)
1087 pdata->vs_polarity = 1;
1088
1089 if (flags & V4L2_MBUS_PCLK_SAMPLE_RISING)
1090 pdata->clk_polarity = 1;
1091
1092done:
1093 of_node_put(endpoint);
1094 return pdata;
1095}
1096
c1c9d09c
MK
1097/**
1098 * tvp514x_probe() - decoder driver i2c probe handler
07b1747c 1099 * @client: i2c driver client device structure
62ef80a1 1100 * @id: i2c driver id table
07b1747c
VH
1101 *
1102 * Register decoder as an i2c client device and V4L2
1103 * device.
1104 */
1105static int
1106tvp514x_probe(struct i2c_client *client, const struct i2c_device_id *id)
1107{
b610b592 1108 struct tvp514x_platform_data *pdata = tvp514x_get_pdata(client);
6722e0ef 1109 struct tvp514x_decoder *decoder;
62ef80a1 1110 struct v4l2_subdev *sd;
5b38b0f8 1111 int ret;
07b1747c 1112
b610b592
LP
1113 if (pdata == NULL) {
1114 dev_err(&client->dev, "No platform data\n");
1115 return -EINVAL;
1116 }
1117
07b1747c
VH
1118 /* Check if the adapter supports the needed features */
1119 if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
1120 return -EIO;
1121
08754d31 1122 decoder = devm_kzalloc(&client->dev, sizeof(*decoder), GFP_KERNEL);
6722e0ef
SAS
1123 if (!decoder)
1124 return -ENOMEM;
1125
c1c9d09c 1126 /* Initialize the tvp514x_decoder with default configuration */
6722e0ef 1127 *decoder = tvp514x_dev;
62ef80a1 1128 /* Copy default register configuration */
6722e0ef
SAS
1129 memcpy(decoder->tvp514x_regs, tvp514x_reg_list_default,
1130 sizeof(tvp514x_reg_list_default));
62ef80a1 1131
f0a12d0c
LPC
1132 decoder->int_seq = (struct tvp514x_reg *)id->driver_data;
1133
c1c9d09c 1134 /* Copy board specific information here */
b610b592 1135 decoder->pdata = pdata;
62ef80a1 1136
c1c9d09c 1137 /**
07b1747c
VH
1138 * Fetch platform specific data, and configure the
1139 * tvp514x_reg_list[] accordingly. Since this is one
1140 * time configuration, no need to preserve.
1141 */
6722e0ef 1142 decoder->tvp514x_regs[REG_OUTPUT_FORMATTER2].val |=
62ef80a1 1143 (decoder->pdata->clk_polarity << 1);
6722e0ef 1144 decoder->tvp514x_regs[REG_SYNC_CONTROL].val |=
62ef80a1
MK
1145 ((decoder->pdata->hs_polarity << 2) |
1146 (decoder->pdata->vs_polarity << 3));
1147 /* Set default standard to auto */
1148 decoder->tvp514x_regs[REG_VIDEO_STD].val =
1149 VIDEO_STD_AUTO_SWITCH_BIT;
07b1747c
VH
1150
1151 /* Register with V4L2 layer as slave device */
62ef80a1
MK
1152 sd = &decoder->sd;
1153 v4l2_i2c_subdev_init(sd, client, &tvp514x_ops);
5b38b0f8
MH
1154
1155#if defined(CONFIG_MEDIA_CONTROLLER)
1156 decoder->pad.flags = MEDIA_PAD_FL_SOURCE;
1157 decoder->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1158 decoder->sd.entity.flags |= MEDIA_ENT_T_V4L2_SUBDEV_DECODER;
1159
1160 ret = media_entity_init(&decoder->sd.entity, 1, &decoder->pad, 0);
1161 if (ret < 0) {
1162 v4l2_err(sd, "%s decoder driver failed to register !!\n",
1163 sd->name);
5b38b0f8
MH
1164 return ret;
1165 }
1166#endif
cf6832af
HV
1167 v4l2_ctrl_handler_init(&decoder->hdl, 5);
1168 v4l2_ctrl_new_std(&decoder->hdl, &tvp514x_ctrl_ops,
1169 V4L2_CID_BRIGHTNESS, 0, 255, 1, 128);
1170 v4l2_ctrl_new_std(&decoder->hdl, &tvp514x_ctrl_ops,
1171 V4L2_CID_CONTRAST, 0, 255, 1, 128);
1172 v4l2_ctrl_new_std(&decoder->hdl, &tvp514x_ctrl_ops,
1173 V4L2_CID_SATURATION, 0, 255, 1, 128);
1174 v4l2_ctrl_new_std(&decoder->hdl, &tvp514x_ctrl_ops,
1175 V4L2_CID_HUE, -180, 180, 180, 0);
1176 v4l2_ctrl_new_std(&decoder->hdl, &tvp514x_ctrl_ops,
1177 V4L2_CID_AUTOGAIN, 0, 1, 1, 1);
1178 sd->ctrl_handler = &decoder->hdl;
1179 if (decoder->hdl.error) {
5b38b0f8 1180 ret = decoder->hdl.error;
8f23acb5 1181 goto done;
cf6832af
HV
1182 }
1183 v4l2_ctrl_handler_setup(&decoder->hdl);
1184
8f23acb5
LP
1185 ret = v4l2_async_register_subdev(&decoder->sd);
1186 if (!ret)
1187 v4l2_info(sd, "%s decoder driver registered !!\n", sd->name);
6722e0ef 1188
8f23acb5
LP
1189done:
1190 if (ret < 0) {
1191 v4l2_ctrl_handler_free(&decoder->hdl);
1192#if defined(CONFIG_MEDIA_CONTROLLER)
1193 media_entity_cleanup(&decoder->sd.entity);
1194#endif
1195 }
1196 return ret;
07b1747c
VH
1197}
1198
c1c9d09c
MK
1199/**
1200 * tvp514x_remove() - decoder driver i2c remove handler
07b1747c
VH
1201 * @client: i2c driver client device structure
1202 *
1203 * Unregister decoder as an i2c client device and V4L2
1204 * device. Complement of tvp514x_probe().
1205 */
62ef80a1 1206static int tvp514x_remove(struct i2c_client *client)
07b1747c 1207{
62ef80a1
MK
1208 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1209 struct tvp514x_decoder *decoder = to_decoder(sd);
07b1747c 1210
8f23acb5 1211 v4l2_async_unregister_subdev(&decoder->sd);
62ef80a1 1212 v4l2_device_unregister_subdev(sd);
5b38b0f8
MH
1213#if defined(CONFIG_MEDIA_CONTROLLER)
1214 media_entity_cleanup(&decoder->sd.entity);
1215#endif
cf6832af 1216 v4l2_ctrl_handler_free(&decoder->hdl);
07b1747c
VH
1217 return 0;
1218}
c1c9d09c 1219/* TVP5146 Init/Power on Sequence */
07b1747c
VH
1220static const struct tvp514x_reg tvp5146_init_reg_seq[] = {
1221 {TOK_WRITE, REG_VBUS_ADDRESS_ACCESS1, 0x02},
1222 {TOK_WRITE, REG_VBUS_ADDRESS_ACCESS2, 0x00},
1223 {TOK_WRITE, REG_VBUS_ADDRESS_ACCESS3, 0x80},
1224 {TOK_WRITE, REG_VBUS_DATA_ACCESS_NO_VBUS_ADDR_INCR, 0x01},
1225 {TOK_WRITE, REG_VBUS_ADDRESS_ACCESS1, 0x60},
1226 {TOK_WRITE, REG_VBUS_ADDRESS_ACCESS2, 0x00},
1227 {TOK_WRITE, REG_VBUS_ADDRESS_ACCESS3, 0xB0},
1228 {TOK_WRITE, REG_VBUS_DATA_ACCESS_NO_VBUS_ADDR_INCR, 0x01},
1229 {TOK_WRITE, REG_VBUS_DATA_ACCESS_NO_VBUS_ADDR_INCR, 0x00},
1230 {TOK_WRITE, REG_OPERATION_MODE, 0x01},
1231 {TOK_WRITE, REG_OPERATION_MODE, 0x00},
62ef80a1 1232 {TOK_TERM, 0, 0},
07b1747c 1233};
62ef80a1 1234
c1c9d09c 1235/* TVP5147 Init/Power on Sequence */
07b1747c
VH
1236static const struct tvp514x_reg tvp5147_init_reg_seq[] = {
1237 {TOK_WRITE, REG_VBUS_ADDRESS_ACCESS1, 0x02},
1238 {TOK_WRITE, REG_VBUS_ADDRESS_ACCESS2, 0x00},
1239 {TOK_WRITE, REG_VBUS_ADDRESS_ACCESS3, 0x80},
1240 {TOK_WRITE, REG_VBUS_DATA_ACCESS_NO_VBUS_ADDR_INCR, 0x01},
1241 {TOK_WRITE, REG_VBUS_ADDRESS_ACCESS1, 0x60},
1242 {TOK_WRITE, REG_VBUS_ADDRESS_ACCESS2, 0x00},
1243 {TOK_WRITE, REG_VBUS_ADDRESS_ACCESS3, 0xB0},
1244 {TOK_WRITE, REG_VBUS_DATA_ACCESS_NO_VBUS_ADDR_INCR, 0x01},
1245 {TOK_WRITE, REG_VBUS_ADDRESS_ACCESS1, 0x16},
1246 {TOK_WRITE, REG_VBUS_ADDRESS_ACCESS2, 0x00},
1247 {TOK_WRITE, REG_VBUS_ADDRESS_ACCESS3, 0xA0},
1248 {TOK_WRITE, REG_VBUS_DATA_ACCESS_NO_VBUS_ADDR_INCR, 0x16},
1249 {TOK_WRITE, REG_VBUS_ADDRESS_ACCESS1, 0x60},
1250 {TOK_WRITE, REG_VBUS_ADDRESS_ACCESS2, 0x00},
1251 {TOK_WRITE, REG_VBUS_ADDRESS_ACCESS3, 0xB0},
1252 {TOK_WRITE, REG_VBUS_DATA_ACCESS_NO_VBUS_ADDR_INCR, 0x00},
1253 {TOK_WRITE, REG_OPERATION_MODE, 0x01},
1254 {TOK_WRITE, REG_OPERATION_MODE, 0x00},
62ef80a1 1255 {TOK_TERM, 0, 0},
07b1747c 1256};
62ef80a1 1257
c1c9d09c 1258/* TVP5146M2/TVP5147M1 Init/Power on Sequence */
07b1747c
VH
1259static const struct tvp514x_reg tvp514xm_init_reg_seq[] = {
1260 {TOK_WRITE, REG_OPERATION_MODE, 0x01},
1261 {TOK_WRITE, REG_OPERATION_MODE, 0x00},
62ef80a1 1262 {TOK_TERM, 0, 0},
07b1747c 1263};
62ef80a1 1264
c1c9d09c 1265/**
07b1747c
VH
1266 * I2C Device Table -
1267 *
1268 * name - Name of the actual device/chip.
1269 * driver_data - Driver data
1270 */
1271static const struct i2c_device_id tvp514x_id[] = {
62ef80a1
MK
1272 {"tvp5146", (unsigned long)tvp5146_init_reg_seq},
1273 {"tvp5146m2", (unsigned long)tvp514xm_init_reg_seq},
1274 {"tvp5147", (unsigned long)tvp5147_init_reg_seq},
1275 {"tvp5147m1", (unsigned long)tvp514xm_init_reg_seq},
07b1747c
VH
1276 {},
1277};
1278
1279MODULE_DEVICE_TABLE(i2c, tvp514x_id);
1280
b610b592
LP
1281#if IS_ENABLED(CONFIG_OF)
1282static const struct of_device_id tvp514x_of_match[] = {
1283 { .compatible = "ti,tvp5146", },
1284 { .compatible = "ti,tvp5146m2", },
1285 { .compatible = "ti,tvp5147", },
1286 { .compatible = "ti,tvp5147m1", },
1287 { /* sentinel */ },
1288};
1289MODULE_DEVICE_TABLE(of, tvp514x_of_match);
1290#endif
1291
62ef80a1 1292static struct i2c_driver tvp514x_driver = {
07b1747c 1293 .driver = {
b610b592 1294 .of_match_table = of_match_ptr(tvp514x_of_match),
62ef80a1
MK
1295 .owner = THIS_MODULE,
1296 .name = TVP514X_MODULE_NAME,
1297 },
07b1747c 1298 .probe = tvp514x_probe,
62ef80a1 1299 .remove = tvp514x_remove,
07b1747c
VH
1300 .id_table = tvp514x_id,
1301};
1302
c6e8d86f 1303module_i2c_driver(tvp514x_driver);