[mirror_ubuntu-artful-kernel.git] / drivers / media / i2c / vpx3220.c

/*
 * vpx3220a, vpx3216b & vpx3214c video decoder driver version 0.0.1
 *
 * Copyright (C) 2001 Laurent Pinchart <lpinchart@freegates.be>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <linux/module.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/types.h>
#include <linux/slab.h>
#include <linux/uaccess.h>
#include <linux/i2c.h>
#include <linux/videodev2.h>
#include <media/v4l2-device.h>
#include <media/v4l2-ctrls.h>

MODULE_DESCRIPTION("vpx3220a/vpx3216b/vpx3214c video decoder driver");
MODULE_AUTHOR("Laurent Pinchart");
MODULE_LICENSE("GPL");

static int debug;
module_param(debug, int, 0);
MODULE_PARM_DESC(debug, "Debug level (0-1)");


#define VPX_TIMEOUT_COUNT  10

/* ----------------------------------------------------------------------- */

struct vpx3220 {
	struct v4l2_subdev sd;
	struct v4l2_ctrl_handler hdl;
	unsigned char reg[255];

	v4l2_std_id norm;
	int input;
	int enable;
};

static inline struct vpx3220 *to_vpx3220(struct v4l2_subdev *sd)
{
	return container_of(sd, struct vpx3220, sd);
}

static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
{
	return &container_of(ctrl->handler, struct vpx3220, hdl)->sd;
}

static char *inputs[] = { "internal", "composite", "svideo" };

/* ----------------------------------------------------------------------- */

static inline int vpx3220_write(struct v4l2_subdev *sd, u8 reg, u8 value)
{
	struct i2c_client *client = v4l2_get_subdevdata(sd);
	struct vpx3220 *decoder = i2c_get_clientdata(client);

	decoder->reg[reg] = value;
	return i2c_smbus_write_byte_data(client, reg, value);
}

static inline int vpx3220_read(struct v4l2_subdev *sd, u8 reg)
{
	struct i2c_client *client = v4l2_get_subdevdata(sd);

	return i2c_smbus_read_byte_data(client, reg);
}

static int vpx3220_fp_status(struct v4l2_subdev *sd)
{
	unsigned char status;
	unsigned int i;

	for (i = 0; i < VPX_TIMEOUT_COUNT; i++) {
		status = vpx3220_read(sd, 0x29);

		if (!(status & 4))
			return 0;

		udelay(10);

		if (need_resched())
			cond_resched();
	}

	return -1;
}

static int vpx3220_fp_write(struct v4l2_subdev *sd, u8 fpaddr, u16 data)
{
	struct i2c_client *client = v4l2_get_subdevdata(sd);

	/* Write the 16-bit address to the FPWR register */
	if (i2c_smbus_write_word_data(client, 0x27, swab16(fpaddr)) == -1) {
		v4l2_dbg(1, debug, sd, "%s: failed\n", __func__);
		return -1;
	}

	if (vpx3220_fp_status(sd) < 0)
		return -1;

	/* Write the 16-bit data to the FPDAT register */
	if (i2c_smbus_write_word_data(client, 0x28, swab16(data)) == -1) {
		v4l2_dbg(1, debug, sd, "%s: failed\n", __func__);
		return -1;
	}

	return 0;
}

static int vpx3220_fp_read(struct v4l2_subdev *sd, u16 fpaddr)
{
	struct i2c_client *client = v4l2_get_subdevdata(sd);
	s16 data;

	/* Write the 16-bit address to the FPRD register */
	if (i2c_smbus_write_word_data(client, 0x26, swab16(fpaddr)) == -1) {
		v4l2_dbg(1, debug, sd, "%s: failed\n", __func__);
		return -1;
	}

	if (vpx3220_fp_status(sd) < 0)
		return -1;

	/* Read the 16-bit data from the FPDAT register */
	data = i2c_smbus_read_word_data(client, 0x28);
	if (data == -1) {
		v4l2_dbg(1, debug, sd, "%s: failed\n", __func__);
		return -1;
	}

	return swab16(data);
}

static int vpx3220_write_block(struct v4l2_subdev *sd, const u8 *data, unsigned int len)
{
	u8 reg;
	int ret = -1;

	while (len >= 2) {
		reg = *data++;
		ret = vpx3220_write(sd, reg, *data++);
		if (ret < 0)
			break;
		len -= 2;
	}

	return ret;
}

static int vpx3220_write_fp_block(struct v4l2_subdev *sd,
		const u16 *data, unsigned int len)
{
	u8 reg;
	int ret = 0;

	while (len > 1) {
		reg = *data++;
		ret |= vpx3220_fp_write(sd, reg, *data++);
		len -= 2;
	}

	return ret;
}

/* ---------------------------------------------------------------------- */

static const unsigned short init_ntsc[] = {
	0x1c, 0x00,		/* NTSC tint angle */
	0x88, 17,		/* Window 1 vertical */
	0x89, 240,		/* Vertical lines in */
	0x8a, 240,		/* Vertical lines out */
	0x8b, 000,		/* Horizontal begin */
	0x8c, 640,		/* Horizontal length */
	0x8d, 640,		/* Number of pixels */
	0x8f, 0xc00,		/* Disable window 2 */
	0xf0, 0x73,		/* 13.5 MHz transport, Forced
				 * mode, latch windows */
	0xf2, 0x13,		/* NTSC M, composite input */
	0xe7, 0x1e1,		/* Enable vertical standard
				 * locking @ 240 lines */
};

static const unsigned short init_pal[] = {
	0x88, 23,		/* Window 1 vertical begin */
	0x89, 288,		/* Vertical lines in (16 lines
				 * skipped by the VFE) */
	0x8a, 288,		/* Vertical lines out (16 lines
				 * skipped by the VFE) */
	0x8b, 16,		/* Horizontal begin */
	0x8c, 768,		/* Horizontal length */
	0x8d, 784, 		/* Number of pixels
				 * Must be >= Horizontal begin + Horizontal length */
	0x8f, 0xc00,		/* Disable window 2 */
	0xf0, 0x77,		/* 13.5 MHz transport, Forced
				 * mode, latch windows */
	0xf2, 0x3d1,		/* PAL B,G,H,I, composite input */
	0xe7, 0x241,		/* PAL/SECAM set to 288 lines */
};

static const unsigned short init_secam[] = {
	0x88, 23,		/* Window 1 vertical begin */
	0x89, 288,		/* Vertical lines in (16 lines
				 * skipped by the VFE) */
	0x8a, 288,		/* Vertical lines out (16 lines
				 * skipped by the VFE) */
	0x8b, 16,		/* Horizontal begin */
	0x8c, 768,		/* Horizontal length */
	0x8d, 784,		/* Number of pixels
				 * Must be >= Horizontal begin + Horizontal length */
	0x8f, 0xc00,		/* Disable window 2 */
	0xf0, 0x77,		/* 13.5 MHz transport, Forced
				 * mode, latch windows */
	0xf2, 0x3d5,		/* SECAM, composite input */
	0xe7, 0x241,		/* PAL/SECAM set to 288 lines */
};

static const unsigned char init_common[] = {
	0xf2, 0x00,		/* Disable all outputs */
	0x33, 0x0d,		/* Luma : VIN2, Chroma : CIN
				 * (clamp off) */
	0xd8, 0xa8,		/* HREF/VREF active high, VREF
				 * pulse = 2, Odd/Even flag */
	0x20, 0x03,		/* IF compensation 0dB/oct */
	0xe0, 0xff,		/* Open up all comparators */
	0xe1, 0x00,
	0xe2, 0x7f,
	0xe3, 0x80,
	0xe4, 0x7f,
	0xe5, 0x80,
	0xe6, 0x00,		/* Brightness set to 0 */
	0xe7, 0xe0,		/* Contrast to 1.0, noise shaping
				 * 10 to 8 2-bit error diffusion */
	0xe8, 0xf8,		/* YUV422, CbCr binary offset,
				 * ... (p.32) */
	0xea, 0x18,		/* LLC2 connected, output FIFO
				 * reset with VACTintern */
	0xf0, 0x8a,		/* Half full level to 10, bus
				 * shuffler [7:0, 23:16, 15:8] */
	0xf1, 0x18,		/* Single clock, sync mode, no
				 * FE delay, no HLEN counter */
	0xf8, 0x12,		/* Port A, PIXCLK, HF# & FE#
				 * strength to 2 */
	0xf9, 0x24,		/* Port B, HREF, VREF, PREF &
				 * ALPHA strength to 4 */
};

static const unsigned short init_fp[] = {
	0x59, 0,
	0xa0, 2070,		/* ACC reference */
	0xa3, 0,
	0xa4, 0,
	0xa8, 30,
	0xb2, 768,
	0xbe, 27,
	0x58, 0,
	0x26, 0,
	0x4b, 0x298,		/* PLL gain */
};


static int vpx3220_init(struct v4l2_subdev *sd, u32 val)
{
	struct vpx3220 *decoder = to_vpx3220(sd);

	vpx3220_write_block(sd, init_common, sizeof(init_common));
	vpx3220_write_fp_block(sd, init_fp, sizeof(init_fp) >> 1);
	if (decoder->norm & V4L2_STD_NTSC)
		vpx3220_write_fp_block(sd, init_ntsc, sizeof(init_ntsc) >> 1);
	else if (decoder->norm & V4L2_STD_PAL)
		vpx3220_write_fp_block(sd, init_pal, sizeof(init_pal) >> 1);
	else if (decoder->norm & V4L2_STD_SECAM)
		vpx3220_write_fp_block(sd, init_secam, sizeof(init_secam) >> 1);
	else
		vpx3220_write_fp_block(sd, init_pal, sizeof(init_pal) >> 1);
	return 0;
}

static int vpx3220_status(struct v4l2_subdev *sd, u32 *pstatus, v4l2_std_id *pstd)
{
	int res = V4L2_IN_ST_NO_SIGNAL, status;
	v4l2_std_id std = pstd ? *pstd : V4L2_STD_ALL;

	status = vpx3220_fp_read(sd, 0x0f3);

	v4l2_dbg(1, debug, sd, "status: 0x%04x\n", status);

	if (status < 0)
		return status;

	if ((status & 0x20) == 0) {
		res = 0;

		switch (status & 0x18) {
		case 0x00:
		case 0x10:
		case 0x14:
		case 0x18:
			std &= V4L2_STD_PAL;
			break;

		case 0x08:
			std &= V4L2_STD_SECAM;
			break;

		case 0x04:
		case 0x0c:
		case 0x1c:
			std &= V4L2_STD_NTSC;
			break;
		}
	} else {
		std = V4L2_STD_UNKNOWN;
	}
	if (pstd)
		*pstd = std;
	if (pstatus)
		*pstatus = res;
	return 0;
}

static int vpx3220_querystd(struct v4l2_subdev *sd, v4l2_std_id *std)
{
	v4l2_dbg(1, debug, sd, "querystd\n");
	return vpx3220_status(sd, NULL, std);
}

static int vpx3220_g_input_status(struct v4l2_subdev *sd, u32 *status)
{
	v4l2_dbg(1, debug, sd, "g_input_status\n");
	return vpx3220_status(sd, status, NULL);
}

static int vpx3220_s_std(struct v4l2_subdev *sd, v4l2_std_id std)
{
	struct vpx3220 *decoder = to_vpx3220(sd);
	int temp_input;

	/* Here we back up the input selection because it gets
	   overwritten when we fill the registers with the
	   chosen video norm */
	temp_input = vpx3220_fp_read(sd, 0xf2);

	v4l2_dbg(1, debug, sd, "s_std %llx\n", (unsigned long long)std);
	if (std & V4L2_STD_NTSC) {
		vpx3220_write_fp_block(sd, init_ntsc, sizeof(init_ntsc) >> 1);
		v4l2_dbg(1, debug, sd, "norm switched to NTSC\n");
	} else if (std & V4L2_STD_PAL) {
		vpx3220_write_fp_block(sd, init_pal, sizeof(init_pal) >> 1);
		v4l2_dbg(1, debug, sd, "norm switched to PAL\n");
	} else if (std & V4L2_STD_SECAM) {
		vpx3220_write_fp_block(sd, init_secam, sizeof(init_secam) >> 1);
		v4l2_dbg(1, debug, sd, "norm switched to SECAM\n");
	} else {
		return -EINVAL;
	}

	decoder->norm = std;

	/* And here we set the backed up video input again */
	vpx3220_fp_write(sd, 0xf2, temp_input | 0x0010);
	udelay(10);
	return 0;
}

static int vpx3220_s_routing(struct v4l2_subdev *sd,
			     u32 input, u32 output, u32 config)
{
	int data;

	/* RJ:   input = 0: ST8 (PCTV) input
		 input = 1: COMPOSITE  input
		 input = 2: SVHS       input  */

	const int input_vals[3][2] = {
		{0x0c, 0},
		{0x0d, 0},
		{0x0e, 1}
	};

	if (input > 2)
		return -EINVAL;

	v4l2_dbg(1, debug, sd, "input switched to %s\n", inputs[input]);

	vpx3220_write(sd, 0x33, input_vals[input][0]);

	data = vpx3220_fp_read(sd, 0xf2) & ~(0x0020);
	if (data < 0)
		return data;
	/* 0x0010 is required to latch the setting */
	vpx3220_fp_write(sd, 0xf2,
			data | (input_vals[input][1] << 5) | 0x0010);

	udelay(10);
	return 0;
}

static int vpx3220_s_stream(struct v4l2_subdev *sd, int enable)
{
	v4l2_dbg(1, debug, sd, "s_stream %s\n", enable ? "on" : "off");

	vpx3220_write(sd, 0xf2, (enable ? 0x1b : 0x00));
	return 0;
}

static int vpx3220_s_ctrl(struct v4l2_ctrl *ctrl)
{
	struct v4l2_subdev *sd = to_sd(ctrl);

	switch (ctrl->id) {
	case V4L2_CID_BRIGHTNESS:
		vpx3220_write(sd, 0xe6, ctrl->val);
		return 0;
	case V4L2_CID_CONTRAST:
		/* Bit 7 and 8 is for noise shaping */
		vpx3220_write(sd, 0xe7, ctrl->val + 192);
		return 0;
	case V4L2_CID_SATURATION:
		vpx3220_fp_write(sd, 0xa0, ctrl->val);
		return 0;
	case V4L2_CID_HUE:
		vpx3220_fp_write(sd, 0x1c, ctrl->val);
		return 0;
	}
	return -EINVAL;
}

/* ----------------------------------------------------------------------- */

static const struct v4l2_ctrl_ops vpx3220_ctrl_ops = {
	.s_ctrl = vpx3220_s_ctrl,
};

static const struct v4l2_subdev_core_ops vpx3220_core_ops = {
	.init = vpx3220_init,
};

static const struct v4l2_subdev_video_ops vpx3220_video_ops = {
	.s_std = vpx3220_s_std,
	.s_routing = vpx3220_s_routing,
	.s_stream = vpx3220_s_stream,
	.querystd = vpx3220_querystd,
	.g_input_status = vpx3220_g_input_status,
};

static const struct v4l2_subdev_ops vpx3220_ops = {
	.core = &vpx3220_core_ops,
	.video = &vpx3220_video_ops,
};

/* -----------------------------------------------------------------------
 * Client management code
 */

static int vpx3220_probe(struct i2c_client *client,
			const struct i2c_device_id *id)
{
	struct vpx3220 *decoder;
	struct v4l2_subdev *sd;
	const char *name = NULL;
	u8 ver;
	u16 pn;

	/* Check if the adapter supports the needed features */
	if (!i2c_check_functionality(client->adapter,
		I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA))
		return -ENODEV;

	decoder = devm_kzalloc(&client->dev, sizeof(*decoder), GFP_KERNEL);
	if (decoder == NULL)
		return -ENOMEM;
	sd = &decoder->sd;
	v4l2_i2c_subdev_init(sd, client, &vpx3220_ops);
	decoder->norm = V4L2_STD_PAL;
	decoder->input = 0;
	decoder->enable = 1;
	v4l2_ctrl_handler_init(&decoder->hdl, 4);
	v4l2_ctrl_new_std(&decoder->hdl, &vpx3220_ctrl_ops,
		V4L2_CID_BRIGHTNESS, -128, 127, 1, 0);
	v4l2_ctrl_new_std(&decoder->hdl, &vpx3220_ctrl_ops,
		V4L2_CID_CONTRAST, 0, 63, 1, 32);
	v4l2_ctrl_new_std(&decoder->hdl, &vpx3220_ctrl_ops,
		V4L2_CID_SATURATION, 0, 4095, 1, 2048);
	v4l2_ctrl_new_std(&decoder->hdl, &vpx3220_ctrl_ops,
		V4L2_CID_HUE, -512, 511, 1, 0);
	sd->ctrl_handler = &decoder->hdl;
	if (decoder->hdl.error) {
		int err = decoder->hdl.error;

		v4l2_ctrl_handler_free(&decoder->hdl);
		return err;
	}
	v4l2_ctrl_handler_setup(&decoder->hdl);

	ver = i2c_smbus_read_byte_data(client, 0x00);
	pn = (i2c_smbus_read_byte_data(client, 0x02) << 8) +
		i2c_smbus_read_byte_data(client, 0x01);
	if (ver == 0xec) {
		switch (pn) {
		case 0x4680:
			name = "vpx3220a";
			break;
		case 0x4260:
			name = "vpx3216b";
			break;
		case 0x4280:
			name = "vpx3214c";
			break;
		}
	}
	if (name)
		v4l2_info(sd, "%s found @ 0x%x (%s)\n", name,
			client->addr << 1, client->adapter->name);
	else
		v4l2_info(sd, "chip (%02x:%04x) found @ 0x%x (%s)\n",
			ver, pn, client->addr << 1, client->adapter->name);

	vpx3220_write_block(sd, init_common, sizeof(init_common));
	vpx3220_write_fp_block(sd, init_fp, sizeof(init_fp) >> 1);
	/* Default to PAL */
	vpx3220_write_fp_block(sd, init_pal, sizeof(init_pal) >> 1);
	return 0;
}

static int vpx3220_remove(struct i2c_client *client)
{
	struct v4l2_subdev *sd = i2c_get_clientdata(client);
	struct vpx3220 *decoder = to_vpx3220(sd);

	v4l2_device_unregister_subdev(sd);
	v4l2_ctrl_handler_free(&decoder->hdl);

	return 0;
}

static const struct i2c_device_id vpx3220_id[] = {
	{ "vpx3220a", 0 },
	{ "vpx3216b", 0 },
	{ "vpx3214c", 0 },
	{ }
};
MODULE_DEVICE_TABLE(i2c, vpx3220_id);

static struct i2c_driver vpx3220_driver = {
	.driver = {
		.name	= "vpx3220",
	},
	.probe		= vpx3220_probe,
	.remove		= vpx3220_remove,
	.id_table	= vpx3220_id,
};

module_i2c_driver(vpx3220_driver);
Commit	Line	Data
d56410e0	1	/*
1da177e4 LT	2	* vpx3220a, vpx3216b & vpx3214c video decoder driver version 0.0.1
	3	*
	4	* Copyright (C) 2001 Laurent Pinchart <lpinchart@freegates.be>
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License, or
	9	* (at your option) any later version.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
1da177e4 LT	15	*/
	16
	17	#include <linux/module.h>
	18	#include <linux/init.h>
	19	#include <linux/delay.h>
	20	#include <linux/types.h>
5a0e3ad6	21	#include <linux/slab.h>
7c0f6ba6	22	#include <linux/uaccess.h>
1da177e4	23	#include <linux/i2c.h>
107063c6	24	#include <linux/videodev2.h>
7e5eaadc	25	#include <media/v4l2-device.h>
9a775323	26	#include <media/v4l2-ctrls.h>
1da177e4	27
23848b65 HV	28	MODULE_DESCRIPTION("vpx3220a/vpx3216b/vpx3214c video decoder driver");
	29	MODULE_AUTHOR("Laurent Pinchart");
	30	MODULE_LICENSE("GPL");
1da177e4	31
ff699e6b	32	static int debug;
1da177e4 LT	33	module_param(debug, int, 0);
	34	MODULE_PARM_DESC(debug, "Debug level (0-1)");
	35
7e5eaadc	36
1da177e4 LT	37	#define VPX_TIMEOUT_COUNT 10
	38
	39	/* ----------------------------------------------------------------------- */
	40
	41	struct vpx3220 {
7e5eaadc	42	struct v4l2_subdev sd;
9a775323	43	struct v4l2_ctrl_handler hdl;
1da177e4 LT	44	unsigned char reg[255];
1da177e4 LT	45
107063c6	46	v4l2_std_id norm;
1da177e4 LT	47	int input;
1da177e4 LT	48	int enable;
1da177e4 LT	49	};
1da177e4 LT	50
7e5eaadc HV	51	static inline struct vpx3220 to_vpx3220(struct v4l2_subdev sd)
	52	{
	53	return container_of(sd, struct vpx3220, sd);
	54	}
	55
9a775323 HV	56	static inline struct v4l2_subdev to_sd(struct v4l2_ctrl ctrl)
	57	{
	58	return &container_of(ctrl->handler, struct vpx3220, hdl)->sd;
	59	}
	60
1da177e4 LT	61	static char *inputs[] = { "internal", "composite", "svideo" };
	62
	63	/* ----------------------------------------------------------------------- */
23848b65	64
7e5eaadc	65	static inline int vpx3220_write(struct v4l2_subdev *sd, u8 reg, u8 value)
1da177e4	66	{
7e5eaadc	67	struct i2c_client *client = v4l2_get_subdevdata(sd);
1da177e4 LT	68	struct vpx3220 *decoder = i2c_get_clientdata(client);
	69
	70	decoder->reg[reg] = value;
	71	return i2c_smbus_write_byte_data(client, reg, value);
	72	}
	73
7e5eaadc	74	static inline int vpx3220_read(struct v4l2_subdev *sd, u8 reg)
1da177e4	75	{
7e5eaadc HV	76	struct i2c_client *client = v4l2_get_subdevdata(sd);
7e5eaadc HV	77
1da177e4 LT	78	return i2c_smbus_read_byte_data(client, reg);
	79	}
	80
7e5eaadc	81	static int vpx3220_fp_status(struct v4l2_subdev *sd)
1da177e4 LT	82	{
	83	unsigned char status;
	84	unsigned int i;
	85
	86	for (i = 0; i < VPX_TIMEOUT_COUNT; i++) {
7e5eaadc	87	status = vpx3220_read(sd, 0x29);
1da177e4 LT	88
	89	if (!(status & 4))
	90	return 0;
	91
	92	udelay(10);
	93
	94	if (need_resched())
	95	cond_resched();
	96	}
	97
	98	return -1;
	99	}
	100
7e5eaadc	101	static int vpx3220_fp_write(struct v4l2_subdev *sd, u8 fpaddr, u16 data)
1da177e4	102	{
7e5eaadc HV	103	struct i2c_client *client = v4l2_get_subdevdata(sd);
7e5eaadc HV	104
1da177e4 LT	105	/* Write the 16-bit address to the FPWR register */
1da177e4 LT	106	if (i2c_smbus_write_word_data(client, 0x27, swab16(fpaddr)) == -1) {
7e5eaadc	107	v4l2_dbg(1, debug, sd, "%s: failed\n", __func__);
1da177e4 LT	108	return -1;
	109	}
	110
7e5eaadc	111	if (vpx3220_fp_status(sd) < 0)
1da177e4 LT	112	return -1;
	113
	114	/* Write the 16-bit data to the FPDAT register */
	115	if (i2c_smbus_write_word_data(client, 0x28, swab16(data)) == -1) {
7e5eaadc	116	v4l2_dbg(1, debug, sd, "%s: failed\n", __func__);
1da177e4 LT	117	return -1;
	118	}
	119
	120	return 0;
	121	}
	122
39de7d95	123	static int vpx3220_fp_read(struct v4l2_subdev *sd, u16 fpaddr)
1da177e4	124	{
7e5eaadc	125	struct i2c_client *client = v4l2_get_subdevdata(sd);
1da177e4 LT	126	s16 data;
	127
	128	/* Write the 16-bit address to the FPRD register */
	129	if (i2c_smbus_write_word_data(client, 0x26, swab16(fpaddr)) == -1) {
7e5eaadc	130	v4l2_dbg(1, debug, sd, "%s: failed\n", __func__);
1da177e4 LT	131	return -1;
	132	}
	133
7e5eaadc	134	if (vpx3220_fp_status(sd) < 0)
1da177e4 LT	135	return -1;
	136
	137	/* Read the 16-bit data from the FPDAT register */
	138	data = i2c_smbus_read_word_data(client, 0x28);
	139	if (data == -1) {
7e5eaadc	140	v4l2_dbg(1, debug, sd, "%s: failed\n", __func__);
1da177e4 LT	141	return -1;
	142	}
	143
	144	return swab16(data);
	145	}
	146
7e5eaadc	147	static int vpx3220_write_block(struct v4l2_subdev sd, const u8 data, unsigned int len)
1da177e4 LT	148	{
	149	u8 reg;
	150	int ret = -1;
	151
	152	while (len >= 2) {
	153	reg = *data++;
7e5eaadc	154	ret = vpx3220_write(sd, reg, *data++);
23848b65	155	if (ret < 0)
1da177e4 LT	156	break;
	157	len -= 2;
	158	}
	159
	160	return ret;
	161	}
	162
7e5eaadc	163	static int vpx3220_write_fp_block(struct v4l2_subdev *sd,
23848b65	164	const u16 *data, unsigned int len)
1da177e4 LT	165	{
	166	u8 reg;
	167	int ret = 0;
	168
	169	while (len > 1) {
	170	reg = *data++;
7e5eaadc	171	ret \|= vpx3220_fp_write(sd, reg, *data++);
1da177e4 LT	172	len -= 2;
	173	}
	174
	175	return ret;
	176	}
	177
	178	/* ---------------------------------------------------------------------- */
	179
	180	static const unsigned short init_ntsc[] = {
	181	0x1c, 0x00, /* NTSC tint angle */
	182	0x88, 17, /* Window 1 vertical */
	183	0x89, 240, /* Vertical lines in */
	184	0x8a, 240, /* Vertical lines out */
	185	0x8b, 000, /* Horizontal begin */
	186	0x8c, 640, /* Horizontal length */
	187	0x8d, 640, /* Number of pixels */
	188	0x8f, 0xc00, /* Disable window 2 */
9b3acc21	189	0xf0, 0x73, /* 13.5 MHz transport, Forced
1da177e4 LT	190	* mode, latch windows */
	191	0xf2, 0x13, /* NTSC M, composite input */
	192	0xe7, 0x1e1, /* Enable vertical standard
	193	* locking @ 240 lines */
	194	};
	195
	196	static const unsigned short init_pal[] = {
	197	0x88, 23, /* Window 1 vertical begin */
9b3acc21	198	0x89, 288, /* Vertical lines in (16 lines
1da177e4	199	* skipped by the VFE) */
9b3acc21	200	0x8a, 288, /* Vertical lines out (16 lines
1da177e4 LT	201	* skipped by the VFE) */
	202	0x8b, 16, /* Horizontal begin */
	203	0x8c, 768, /* Horizontal length */
	204	0x8d, 784, /* Number of pixels
	205	* Must be >= Horizontal begin + Horizontal length */
	206	0x8f, 0xc00, /* Disable window 2 */
9b3acc21	207	0xf0, 0x77, /* 13.5 MHz transport, Forced
1da177e4 LT	208	* mode, latch windows */
1da177e4 LT	209	0xf2, 0x3d1, /* PAL B,G,H,I, composite input */
9b3acc21	210	0xe7, 0x241, /* PAL/SECAM set to 288 lines */
1da177e4 LT	211	};
	212
	213	static const unsigned short init_secam[] = {
9b3acc21 RB	214	0x88, 23, /* Window 1 vertical begin */
9b3acc21 RB	215	0x89, 288, /* Vertical lines in (16 lines
1da177e4	216	* skipped by the VFE) */
9b3acc21	217	0x8a, 288, /* Vertical lines out (16 lines
1da177e4 LT	218	* skipped by the VFE) */
	219	0x8b, 16, /* Horizontal begin */
	220	0x8c, 768, /* Horizontal length */
	221	0x8d, 784, /* Number of pixels
	222	* Must be >= Horizontal begin + Horizontal length */
	223	0x8f, 0xc00, /* Disable window 2 */
9b3acc21	224	0xf0, 0x77, /* 13.5 MHz transport, Forced
1da177e4 LT	225	* mode, latch windows */
1da177e4 LT	226	0xf2, 0x3d5, /* SECAM, composite input */
9b3acc21	227	0xe7, 0x241, /* PAL/SECAM set to 288 lines */
1da177e4 LT	228	};
	229
	230	static const unsigned char init_common[] = {
	231	0xf2, 0x00, /* Disable all outputs */
	232	0x33, 0x0d, /* Luma : VIN2, Chroma : CIN
	233	* (clamp off) */
	234	0xd8, 0xa8, /* HREF/VREF active high, VREF
	235	* pulse = 2, Odd/Even flag */
	236	0x20, 0x03, /* IF compensation 0dB/oct */
	237	0xe0, 0xff, /* Open up all comparators */
	238	0xe1, 0x00,
	239	0xe2, 0x7f,
	240	0xe3, 0x80,
	241	0xe4, 0x7f,
	242	0xe5, 0x80,
	243	0xe6, 0x00, /* Brightness set to 0 */
	244	0xe7, 0xe0, /* Contrast to 1.0, noise shaping
	245	* 10 to 8 2-bit error diffusion */
	246	0xe8, 0xf8, /* YUV422, CbCr binary offset,
	247	* ... (p.32) */
	248	0xea, 0x18, /* LLC2 connected, output FIFO
	249	* reset with VACTintern */
	250	0xf0, 0x8a, /* Half full level to 10, bus
	251	* shuffler [7:0, 23:16, 15:8] */
	252	0xf1, 0x18, /* Single clock, sync mode, no
	253	* FE delay, no HLEN counter */
	254	0xf8, 0x12, /* Port A, PIXCLK, HF# & FE#
	255	* strength to 2 */
	256	0xf9, 0x24, /* Port B, HREF, VREF, PREF &
	257	* ALPHA strength to 4 */
	258	};
	259
	260	static const unsigned short init_fp[] = {
	261	0x59, 0,
	262	0xa0, 2070, /* ACC reference */
	263	0xa3, 0,
	264	0xa4, 0,
	265	0xa8, 30,
	266	0xb2, 768,
	267	0xbe, 27,
	268	0x58, 0,
	269	0x26, 0,
	270	0x4b, 0x298, /* PLL gain */
	271	};
	272
1da177e4	273
7e5eaadc	274	static int vpx3220_init(struct v4l2_subdev *sd, u32 val)
1da177e4	275	{
7e5eaadc HV	276	struct vpx3220 *decoder = to_vpx3220(sd);
	277
	278	vpx3220_write_block(sd, init_common, sizeof(init_common));
	279	vpx3220_write_fp_block(sd, init_fp, sizeof(init_fp) >> 1);
	280	if (decoder->norm & V4L2_STD_NTSC)
	281	vpx3220_write_fp_block(sd, init_ntsc, sizeof(init_ntsc) >> 1);
	282	else if (decoder->norm & V4L2_STD_PAL)
	283	vpx3220_write_fp_block(sd, init_pal, sizeof(init_pal) >> 1);
	284	else if (decoder->norm & V4L2_STD_SECAM)
	285	vpx3220_write_fp_block(sd, init_secam, sizeof(init_secam) >> 1);
	286	else
	287	vpx3220_write_fp_block(sd, init_pal, sizeof(init_pal) >> 1);
	288	return 0;
	289	}
1da177e4	290
7e5eaadc HV	291	static int vpx3220_status(struct v4l2_subdev sd, u32 pstatus, v4l2_std_id *pstd)
	292	{
	293	int res = V4L2_IN_ST_NO_SIGNAL, status;
32cb3b09	294	v4l2_std_id std = pstd ? *pstd : V4L2_STD_ALL;
1da177e4	295
7e5eaadc	296	status = vpx3220_fp_read(sd, 0x0f3);
1da177e4	297
7e5eaadc	298	v4l2_dbg(1, debug, sd, "status: 0x%04x\n", status);
1da177e4	299
7e5eaadc HV	300	if (status < 0)
7e5eaadc HV	301	return status;
1da177e4	302
7e5eaadc HV	303	if ((status & 0x20) == 0) {
7e5eaadc HV	304	res = 0;
1da177e4	305
7e5eaadc HV	306	switch (status & 0x18) {
	307	case 0x00:
	308	case 0x10:
	309	case 0x14:
	310	case 0x18:
32cb3b09	311	std &= V4L2_STD_PAL;
7e5eaadc	312	break;
1da177e4	313
7e5eaadc	314	case 0x08:
32cb3b09	315	std &= V4L2_STD_SECAM;
7e5eaadc	316	break;
1da177e4	317
7e5eaadc HV	318	case 0x04:
	319	case 0x0c:
	320	case 0x1c:
32cb3b09	321	std &= V4L2_STD_NTSC;
7e5eaadc	322	break;
1da177e4	323	}
32cb3b09 HV	324	} else {
32cb3b09 HV	325	std = V4L2_STD_UNKNOWN;
23848b65	326	}
7e5eaadc HV	327	if (pstd)
	328	*pstd = std;
	329	if (pstatus)
ba08831b	330	*pstatus = res;
7e5eaadc HV	331	return 0;
7e5eaadc HV	332	}
1da177e4	333
7e5eaadc HV	334	static int vpx3220_querystd(struct v4l2_subdev sd, v4l2_std_id std)
7e5eaadc HV	335	{
bccfa449	336	v4l2_dbg(1, debug, sd, "querystd\n");
7e5eaadc HV	337	return vpx3220_status(sd, NULL, std);
7e5eaadc HV	338	}
107063c6	339
7e5eaadc HV	340	static int vpx3220_g_input_status(struct v4l2_subdev sd, u32 status)
7e5eaadc HV	341	{
bccfa449	342	v4l2_dbg(1, debug, sd, "g_input_status\n");
7e5eaadc HV	343	return vpx3220_status(sd, status, NULL);
7e5eaadc HV	344	}
de21eb63	345
7e5eaadc HV	346	static int vpx3220_s_std(struct v4l2_subdev *sd, v4l2_std_id std)
	347	{
	348	struct vpx3220 *decoder = to_vpx3220(sd);
	349	int temp_input;
	350
	351	/* Here we back up the input selection because it gets
	352	overwritten when we fill the registers with the
25985edc	353	chosen video norm */
7e5eaadc HV	354	temp_input = vpx3220_fp_read(sd, 0xf2);
7e5eaadc HV	355
bccfa449	356	v4l2_dbg(1, debug, sd, "s_std %llx\n", (unsigned long long)std);
7e5eaadc HV	357	if (std & V4L2_STD_NTSC) {
	358	vpx3220_write_fp_block(sd, init_ntsc, sizeof(init_ntsc) >> 1);
	359	v4l2_dbg(1, debug, sd, "norm switched to NTSC\n");
	360	} else if (std & V4L2_STD_PAL) {
	361	vpx3220_write_fp_block(sd, init_pal, sizeof(init_pal) >> 1);
	362	v4l2_dbg(1, debug, sd, "norm switched to PAL\n");
	363	} else if (std & V4L2_STD_SECAM) {
	364	vpx3220_write_fp_block(sd, init_secam, sizeof(init_secam) >> 1);
	365	v4l2_dbg(1, debug, sd, "norm switched to SECAM\n");
	366	} else {
	367	return -EINVAL;
23848b65	368	}
1da177e4	369
7e5eaadc	370	decoder->norm = std;
1da177e4	371
7e5eaadc HV	372	/* And here we set the backed up video input again */
	373	vpx3220_fp_write(sd, 0xf2, temp_input \| 0x0010);
	374	udelay(10);
	375	return 0;
	376	}
1da177e4	377
5325b427 HV	378	static int vpx3220_s_routing(struct v4l2_subdev *sd,
5325b427 HV	379	u32 input, u32 output, u32 config)
7e5eaadc HV	380	{
7e5eaadc HV	381	int data;
1da177e4	382
5325b427 HV	383	/* RJ: input = 0: ST8 (PCTV) input
	384	input = 1: COMPOSITE input
	385	input = 2: SVHS input */
1da177e4	386
5325b427	387	const int input_vals[3][2] = {
7e5eaadc HV	388	{0x0c, 0},
	389	{0x0d, 0},
	390	{0x0e, 1}
	391	};
1da177e4	392
f14a2972	393	if (input > 2)
7e5eaadc	394	return -EINVAL;
1da177e4	395
5325b427	396	v4l2_dbg(1, debug, sd, "input switched to %s\n", inputs[input]);
1da177e4	397
5325b427	398	vpx3220_write(sd, 0x33, input_vals[input][0]);
1da177e4	399
7e5eaadc HV	400	data = vpx3220_fp_read(sd, 0xf2) & ~(0x0020);
	401	if (data < 0)
	402	return data;
	403	/* 0x0010 is required to latch the setting */
	404	vpx3220_fp_write(sd, 0xf2,
5325b427	405	data \| (input_vals[input][1] << 5) \| 0x0010);
1da177e4	406
7e5eaadc HV	407	udelay(10);
	408	return 0;
	409	}
1da177e4	410
7e5eaadc HV	411	static int vpx3220_s_stream(struct v4l2_subdev *sd, int enable)
7e5eaadc HV	412	{
bccfa449	413	v4l2_dbg(1, debug, sd, "s_stream %s\n", enable ? "on" : "off");
1da177e4	414
7e5eaadc HV	415	vpx3220_write(sd, 0xf2, (enable ? 0x1b : 0x00));
	416	return 0;
	417	}
107063c6	418
9a775323	419	static int vpx3220_s_ctrl(struct v4l2_ctrl *ctrl)
7e5eaadc	420	{
9a775323	421	struct v4l2_subdev *sd = to_sd(ctrl);
1da177e4	422
7e5eaadc HV	423	switch (ctrl->id) {
7e5eaadc HV	424	case V4L2_CID_BRIGHTNESS:
9a775323 HV	425	vpx3220_write(sd, 0xe6, ctrl->val);
9a775323 HV	426	return 0;
7e5eaadc	427	case V4L2_CID_CONTRAST:
9a775323 HV	428	/* Bit 7 and 8 is for noise shaping */
	429	vpx3220_write(sd, 0xe7, ctrl->val + 192);
	430	return 0;
7e5eaadc	431	case V4L2_CID_SATURATION:
9a775323 HV	432	vpx3220_fp_write(sd, 0xa0, ctrl->val);
9a775323 HV	433	return 0;
7e5eaadc	434	case V4L2_CID_HUE:
9a775323 HV	435	vpx3220_fp_write(sd, 0x1c, ctrl->val);
9a775323 HV	436	return 0;
107063c6	437	}
9a775323	438	return -EINVAL;
1da177e4 LT	439	}
1da177e4 LT	440
7e5eaadc HV	441	/* ----------------------------------------------------------------------- */
7e5eaadc HV	442
9a775323 HV	443	static const struct v4l2_ctrl_ops vpx3220_ctrl_ops = {
	444	.s_ctrl = vpx3220_s_ctrl,
	445	};
	446
7e5eaadc	447	static const struct v4l2_subdev_core_ops vpx3220_core_ops = {
7e5eaadc	448	.init = vpx3220_init,
7e5eaadc HV	449	};
	450
	451	static const struct v4l2_subdev_video_ops vpx3220_video_ops = {
8774bed9	452	.s_std = vpx3220_s_std,
7e5eaadc HV	453	.s_routing = vpx3220_s_routing,
	454	.s_stream = vpx3220_s_stream,
	455	.querystd = vpx3220_querystd,
	456	.g_input_status = vpx3220_g_input_status,
	457	};
	458
	459	static const struct v4l2_subdev_ops vpx3220_ops = {
	460	.core = &vpx3220_core_ops,
7e5eaadc HV	461	.video = &vpx3220_video_ops,
	462	};
	463
1da177e4	464	/* -----------------------------------------------------------------------
c84e6036	465	* Client management code
1da177e4 LT	466	*/
1da177e4 LT	467
23848b65 HV	468	static int vpx3220_probe(struct i2c_client *client,
23848b65 HV	469	const struct i2c_device_id *id)
1da177e4	470	{
1da177e4	471	struct vpx3220 *decoder;
7e5eaadc	472	struct v4l2_subdev *sd;
23848b65 HV	473	const char *name = NULL;
	474	u8 ver;
	475	u16 pn;
1da177e4 LT	476
1da177e4 LT	477	/* Check if the adapter supports the needed features */
23848b65 HV	478	if (!i2c_check_functionality(client->adapter,
	479	I2C_FUNC_SMBUS_BYTE_DATA \| I2C_FUNC_SMBUS_WORD_DATA))
	480	return -ENODEV;
1da177e4	481
c02b211d	482	decoder = devm_kzalloc(&client->dev, sizeof(*decoder), GFP_KERNEL);
23848b65	483	if (decoder == NULL)
1da177e4	484	return -ENOMEM;
7e5eaadc HV	485	sd = &decoder->sd;
7e5eaadc HV	486	v4l2_i2c_subdev_init(sd, client, &vpx3220_ops);
107063c6	487	decoder->norm = V4L2_STD_PAL;
1da177e4 LT	488	decoder->input = 0;
1da177e4 LT	489	decoder->enable = 1;
9a775323 HV	490	v4l2_ctrl_handler_init(&decoder->hdl, 4);
	491	v4l2_ctrl_new_std(&decoder->hdl, &vpx3220_ctrl_ops,
	492	V4L2_CID_BRIGHTNESS, -128, 127, 1, 0);
	493	v4l2_ctrl_new_std(&decoder->hdl, &vpx3220_ctrl_ops,
	494	V4L2_CID_CONTRAST, 0, 63, 1, 32);
	495	v4l2_ctrl_new_std(&decoder->hdl, &vpx3220_ctrl_ops,
	496	V4L2_CID_SATURATION, 0, 4095, 1, 2048);
	497	v4l2_ctrl_new_std(&decoder->hdl, &vpx3220_ctrl_ops,
	498	V4L2_CID_HUE, -512, 511, 1, 0);
	499	sd->ctrl_handler = &decoder->hdl;
	500	if (decoder->hdl.error) {
	501	int err = decoder->hdl.error;
	502
	503	v4l2_ctrl_handler_free(&decoder->hdl);
9a775323 HV	504	return err;
	505	}
	506	v4l2_ctrl_handler_setup(&decoder->hdl);
1da177e4	507
23848b65 HV	508	ver = i2c_smbus_read_byte_data(client, 0x00);
	509	pn = (i2c_smbus_read_byte_data(client, 0x02) << 8) +
	510	i2c_smbus_read_byte_data(client, 0x01);
	511	if (ver == 0xec) {
	512	switch (pn) {
	513	case 0x4680:
	514	name = "vpx3220a";
	515	break;
	516	case 0x4260:
	517	name = "vpx3216b";
	518	break;
	519	case 0x4280:
	520	name = "vpx3214c";
	521	break;
	522	}
1da177e4	523	}
23848b65	524	if (name)
7e5eaadc	525	v4l2_info(sd, "%s found @ 0x%x (%s)\n", name,
23848b65 HV	526	client->addr << 1, client->adapter->name);
23848b65 HV	527	else
7e5eaadc	528	v4l2_info(sd, "chip (%02x:%04x) found @ 0x%x (%s)\n",
23848b65	529	ver, pn, client->addr << 1, client->adapter->name);
1da177e4	530
7e5eaadc HV	531	vpx3220_write_block(sd, init_common, sizeof(init_common));
	532	vpx3220_write_fp_block(sd, init_fp, sizeof(init_fp) >> 1);
	533	/* Default to PAL */
	534	vpx3220_write_fp_block(sd, init_pal, sizeof(init_pal) >> 1);
1da177e4 LT	535	return 0;
	536	}
	537
23848b65	538	static int vpx3220_remove(struct i2c_client *client)
1da177e4	539	{
7e5eaadc	540	struct v4l2_subdev *sd = i2c_get_clientdata(client);
9a775323	541	struct vpx3220 *decoder = to_vpx3220(sd);
7e5eaadc HV	542
7e5eaadc HV	543	v4l2_device_unregister_subdev(sd);
9a775323	544	v4l2_ctrl_handler_free(&decoder->hdl);
c02b211d	545
23848b65	546	return 0;
1da177e4 LT	547	}
1da177e4 LT	548
23848b65 HV	549	static const struct i2c_device_id vpx3220_id[] = {
	550	{ "vpx3220a", 0 },
	551	{ "vpx3216b", 0 },
	552	{ "vpx3214c", 0 },
	553	{ }
	554	};
	555	MODULE_DEVICE_TABLE(i2c, vpx3220_id);
1da177e4	556
c2d999f3 HV	557	static struct i2c_driver vpx3220_driver = {
c2d999f3 HV	558	.driver = {
c2d999f3 HV	559	.name = "vpx3220",
	560	},
	561	.probe = vpx3220_probe,
	562	.remove = vpx3220_remove,
	563	.id_table = vpx3220_id,
1da177e4	564	};
c2d999f3	565
c6e8d86f	566	module_i2c_driver(vpx3220_driver);