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Commit | Line | Data |
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1c1e45d1 HV |
1 | /* |
2 | * cx18 firmware functions | |
3 | * | |
4 | * Copyright (C) 2007 Hans Verkuil <hverkuil@xs4all.nl> | |
6afdeaf8 | 5 | * Copyright (C) 2008 Andy Walls <awalls@md.metrocast.net> |
1c1e45d1 HV |
6 | * |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; either version 2 of the License, or | |
10 | * (at your option) any later version. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
1c1e45d1 HV |
16 | */ |
17 | ||
18 | #include "cx18-driver.h" | |
b1526421 | 19 | #include "cx18-io.h" |
1c1e45d1 HV |
20 | #include "cx18-scb.h" |
21 | #include "cx18-irq.h" | |
22 | #include "cx18-firmware.h" | |
23 | #include "cx18-cards.h" | |
24 | #include <linux/firmware.h> | |
25 | ||
6e6a8b5a MCC |
26 | #define CX18_PROC_SOFT_RESET 0xc70010 |
27 | #define CX18_DDR_SOFT_RESET 0xc70014 | |
28 | #define CX18_CLOCK_SELECT1 0xc71000 | |
29 | #define CX18_CLOCK_SELECT2 0xc71004 | |
30 | #define CX18_HALF_CLOCK_SELECT1 0xc71008 | |
31 | #define CX18_HALF_CLOCK_SELECT2 0xc7100C | |
32 | #define CX18_CLOCK_POLARITY1 0xc71010 | |
33 | #define CX18_CLOCK_POLARITY2 0xc71014 | |
34 | #define CX18_ADD_DELAY_ENABLE1 0xc71018 | |
35 | #define CX18_ADD_DELAY_ENABLE2 0xc7101C | |
36 | #define CX18_CLOCK_ENABLE1 0xc71020 | |
37 | #define CX18_CLOCK_ENABLE2 0xc71024 | |
38 | ||
39 | #define CX18_REG_BUS_TIMEOUT_EN 0xc72024 | |
40 | ||
41 | #define CX18_FAST_CLOCK_PLL_INT 0xc78000 | |
42 | #define CX18_FAST_CLOCK_PLL_FRAC 0xc78004 | |
43 | #define CX18_FAST_CLOCK_PLL_POST 0xc78008 | |
44 | #define CX18_FAST_CLOCK_PLL_PRESCALE 0xc7800C | |
1c1e45d1 HV |
45 | #define CX18_FAST_CLOCK_PLL_ADJUST_BANDWIDTH 0xc78010 |
46 | ||
6e6a8b5a MCC |
47 | #define CX18_SLOW_CLOCK_PLL_INT 0xc78014 |
48 | #define CX18_SLOW_CLOCK_PLL_FRAC 0xc78018 | |
49 | #define CX18_SLOW_CLOCK_PLL_POST 0xc7801C | |
1c1e45d1 HV |
50 | #define CX18_MPEG_CLOCK_PLL_INT 0xc78040 |
51 | #define CX18_MPEG_CLOCK_PLL_FRAC 0xc78044 | |
52 | #define CX18_MPEG_CLOCK_PLL_POST 0xc78048 | |
6e6a8b5a | 53 | #define CX18_PLL_POWER_DOWN 0xc78088 |
1c1e45d1 HV |
54 | #define CX18_SW1_INT_STATUS 0xc73104 |
55 | #define CX18_SW1_INT_ENABLE_PCI 0xc7311C | |
56 | #define CX18_SW2_INT_SET 0xc73140 | |
57 | #define CX18_SW2_INT_STATUS 0xc73144 | |
6e6a8b5a | 58 | #define CX18_ADEC_CONTROL 0xc78120 |
1c1e45d1 | 59 | |
6e6a8b5a MCC |
60 | #define CX18_DDR_REQUEST_ENABLE 0xc80000 |
61 | #define CX18_DDR_CHIP_CONFIG 0xc80004 | |
62 | #define CX18_DDR_REFRESH 0xc80008 | |
63 | #define CX18_DDR_TIMING1 0xc8000C | |
64 | #define CX18_DDR_TIMING2 0xc80010 | |
1c1e45d1 HV |
65 | #define CX18_DDR_POWER_REG 0xc8001C |
66 | ||
6e6a8b5a MCC |
67 | #define CX18_DDR_TUNE_LANE 0xc80048 |
68 | #define CX18_DDR_INITIAL_EMRS 0xc80054 | |
69 | #define CX18_DDR_MB_PER_ROW_7 0xc8009C | |
70 | #define CX18_DDR_BASE_63_ADDR 0xc804FC | |
71 | ||
72 | #define CX18_WMB_CLIENT02 0xc90108 | |
73 | #define CX18_WMB_CLIENT05 0xc90114 | |
74 | #define CX18_WMB_CLIENT06 0xc90118 | |
75 | #define CX18_WMB_CLIENT07 0xc9011C | |
76 | #define CX18_WMB_CLIENT08 0xc90120 | |
77 | #define CX18_WMB_CLIENT09 0xc90124 | |
78 | #define CX18_WMB_CLIENT10 0xc90128 | |
79 | #define CX18_WMB_CLIENT11 0xc9012C | |
80 | #define CX18_WMB_CLIENT12 0xc90130 | |
81 | #define CX18_WMB_CLIENT13 0xc90134 | |
82 | #define CX18_WMB_CLIENT14 0xc90138 | |
83 | ||
84 | #define CX18_DSP0_INTERRUPT_MASK 0xd0004C | |
1c1e45d1 | 85 | |
1c1e45d1 HV |
86 | #define APU_ROM_SYNC1 0x6D676553 /* "mgeS" */ |
87 | #define APU_ROM_SYNC2 0x72646548 /* "rdeH" */ | |
88 | ||
89 | struct cx18_apu_rom_seghdr { | |
90 | u32 sync1; | |
91 | u32 sync2; | |
92 | u32 addr; | |
93 | u32 size; | |
94 | }; | |
95 | ||
82fc52a8 | 96 | static int load_cpu_fw_direct(const char *fn, u8 __iomem *mem, struct cx18 *cx) |
1c1e45d1 HV |
97 | { |
98 | const struct firmware *fw = NULL; | |
1c1e45d1 | 99 | int i, j; |
82fc52a8 | 100 | unsigned size; |
1c1e45d1 HV |
101 | u32 __iomem *dst = (u32 __iomem *)mem; |
102 | const u32 *src; | |
103 | ||
3d05913d | 104 | if (request_firmware(&fw, fn, &cx->pci_dev->dev)) { |
82fc52a8 | 105 | CX18_ERR("Unable to open firmware %s\n", fn); |
1c1e45d1 HV |
106 | CX18_ERR("Did you put the firmware in the hotplug firmware directory?\n"); |
107 | return -ENOMEM; | |
108 | } | |
109 | ||
110 | src = (const u32 *)fw->data; | |
111 | ||
1c1e45d1 | 112 | for (i = 0; i < fw->size; i += 4096) { |
b1526421 | 113 | cx18_setup_page(cx, i); |
1c1e45d1 HV |
114 | for (j = i; j < fw->size && j < i + 4096; j += 4) { |
115 | /* no need for endianness conversion on the ppc */ | |
b1526421 AW |
116 | cx18_raw_writel(cx, *src, dst); |
117 | if (cx18_raw_readl(cx, dst) != *src) { | |
1c1e45d1 HV |
118 | CX18_ERR("Mismatch at offset %x\n", i); |
119 | release_firmware(fw); | |
ee2d64f5 | 120 | cx18_setup_page(cx, 0); |
1c1e45d1 HV |
121 | return -EIO; |
122 | } | |
123 | dst++; | |
124 | src++; | |
125 | } | |
126 | } | |
127 | if (!test_bit(CX18_F_I_LOADED_FW, &cx->i_flags)) | |
339f06c5 | 128 | CX18_INFO("loaded %s firmware (%zu bytes)\n", fn, fw->size); |
82fc52a8 | 129 | size = fw->size; |
1c1e45d1 | 130 | release_firmware(fw); |
ee2d64f5 | 131 | cx18_setup_page(cx, SCB_OFFSET); |
1c1e45d1 HV |
132 | return size; |
133 | } | |
134 | ||
2d1a1b05 AW |
135 | static int load_apu_fw_direct(const char *fn, u8 __iomem *dst, struct cx18 *cx, |
136 | u32 *entry_addr) | |
1c1e45d1 HV |
137 | { |
138 | const struct firmware *fw = NULL; | |
1c1e45d1 | 139 | int i, j; |
82fc52a8 | 140 | unsigned size; |
1c1e45d1 HV |
141 | const u32 *src; |
142 | struct cx18_apu_rom_seghdr seghdr; | |
143 | const u8 *vers; | |
144 | u32 offset = 0; | |
145 | u32 apu_version = 0; | |
146 | int sz; | |
147 | ||
3d05913d | 148 | if (request_firmware(&fw, fn, &cx->pci_dev->dev)) { |
82fc52a8 | 149 | CX18_ERR("unable to open firmware %s\n", fn); |
1c1e45d1 | 150 | CX18_ERR("did you put the firmware in the hotplug firmware directory?\n"); |
ee2d64f5 | 151 | cx18_setup_page(cx, 0); |
1c1e45d1 HV |
152 | return -ENOMEM; |
153 | } | |
154 | ||
c7abfb47 | 155 | *entry_addr = 0; |
1c1e45d1 HV |
156 | src = (const u32 *)fw->data; |
157 | vers = fw->data + sizeof(seghdr); | |
158 | sz = fw->size; | |
159 | ||
1c1e45d1 | 160 | apu_version = (vers[0] << 24) | (vers[4] << 16) | vers[32]; |
82fc52a8 | 161 | while (offset + sizeof(seghdr) < fw->size) { |
39fd4460 | 162 | const __le32 *shptr = (__force __le32 *)src + offset / 4; |
42d0c3ad HV |
163 | |
164 | seghdr.sync1 = le32_to_cpu(shptr[0]); | |
165 | seghdr.sync2 = le32_to_cpu(shptr[1]); | |
166 | seghdr.addr = le32_to_cpu(shptr[2]); | |
167 | seghdr.size = le32_to_cpu(shptr[3]); | |
168 | ||
1c1e45d1 HV |
169 | offset += sizeof(seghdr); |
170 | if (seghdr.sync1 != APU_ROM_SYNC1 || | |
171 | seghdr.sync2 != APU_ROM_SYNC2) { | |
172 | offset += seghdr.size; | |
173 | continue; | |
174 | } | |
175 | CX18_DEBUG_INFO("load segment %x-%x\n", seghdr.addr, | |
176 | seghdr.addr + seghdr.size - 1); | |
c7abfb47 | 177 | if (*entry_addr == 0) |
2d1a1b05 | 178 | *entry_addr = seghdr.addr; |
1c1e45d1 HV |
179 | if (offset + seghdr.size > sz) |
180 | break; | |
181 | for (i = 0; i < seghdr.size; i += 4096) { | |
2d1a1b05 | 182 | cx18_setup_page(cx, seghdr.addr + i); |
1c1e45d1 HV |
183 | for (j = i; j < seghdr.size && j < i + 4096; j += 4) { |
184 | /* no need for endianness conversion on the ppc */ | |
b1526421 AW |
185 | cx18_raw_writel(cx, src[(offset + j) / 4], |
186 | dst + seghdr.addr + j); | |
187 | if (cx18_raw_readl(cx, dst + seghdr.addr + j) | |
188 | != src[(offset + j) / 4]) { | |
189 | CX18_ERR("Mismatch at offset %x\n", | |
190 | offset + j); | |
1c1e45d1 | 191 | release_firmware(fw); |
ee2d64f5 | 192 | cx18_setup_page(cx, 0); |
1c1e45d1 HV |
193 | return -EIO; |
194 | } | |
195 | } | |
196 | } | |
197 | offset += seghdr.size; | |
198 | } | |
199 | if (!test_bit(CX18_F_I_LOADED_FW, &cx->i_flags)) | |
339f06c5 | 200 | CX18_INFO("loaded %s firmware V%08x (%zu bytes)\n", |
1c1e45d1 | 201 | fn, apu_version, fw->size); |
82fc52a8 | 202 | size = fw->size; |
1c1e45d1 | 203 | release_firmware(fw); |
ee2d64f5 | 204 | cx18_setup_page(cx, 0); |
1c1e45d1 HV |
205 | return size; |
206 | } | |
207 | ||
208 | void cx18_halt_firmware(struct cx18 *cx) | |
209 | { | |
210 | CX18_DEBUG_INFO("Preparing for firmware halt.\n"); | |
ced07371 AW |
211 | cx18_write_reg_expect(cx, 0x000F000F, CX18_PROC_SOFT_RESET, |
212 | 0x0000000F, 0x000F000F); | |
213 | cx18_write_reg_expect(cx, 0x00020002, CX18_ADEC_CONTROL, | |
214 | 0x00000002, 0x00020002); | |
1c1e45d1 HV |
215 | } |
216 | ||
217 | void cx18_init_power(struct cx18 *cx, int lowpwr) | |
218 | { | |
219 | /* power-down Spare and AOM PLLs */ | |
220 | /* power-up fast, slow and mpeg PLLs */ | |
b1526421 | 221 | cx18_write_reg(cx, 0x00000008, CX18_PLL_POWER_DOWN); |
1c1e45d1 HV |
222 | |
223 | /* ADEC out of sleep */ | |
ced07371 AW |
224 | cx18_write_reg_expect(cx, 0x00020000, CX18_ADEC_CONTROL, |
225 | 0x00000000, 0x00020002); | |
1c1e45d1 | 226 | |
55d81aa5 AW |
227 | /* |
228 | * The PLL parameters are based on the external crystal frequency that | |
229 | * would ideally be: | |
230 | * | |
231 | * NTSC Color subcarrier freq * 8 = | |
6e6a8b5a | 232 | * 4.5 MHz/286 * 455/2 * 8 = 28.63636363... MHz |
55d81aa5 AW |
233 | * |
234 | * The accidents of history and rationale that explain from where this | |
235 | * combination of magic numbers originate can be found in: | |
236 | * | |
237 | * [1] Abrahams, I. C., "Choice of Chrominance Subcarrier Frequency in | |
238 | * the NTSC Standards", Proceedings of the I-R-E, January 1954, pp 79-80 | |
239 | * | |
240 | * [2] Abrahams, I. C., "The 'Frequency Interleaving' Principle in the | |
241 | * NTSC Standards", Proceedings of the I-R-E, January 1954, pp 81-83 | |
242 | * | |
243 | * As Mike Bradley has rightly pointed out, it's not the exact crystal | |
244 | * frequency that matters, only that all parts of the driver and | |
245 | * firmware are using the same value (close to the ideal value). | |
246 | * | |
247 | * Since I have a strong suspicion that, if the firmware ever assumes a | |
248 | * crystal value at all, it will assume 28.636360 MHz, the crystal | |
249 | * freq used in calculations in this driver will be: | |
250 | * | |
251 | * xtal_freq = 28.636360 MHz | |
252 | * | |
253 | * an error of less than 0.13 ppm which is way, way better than any off | |
254 | * the shelf crystal will have for accuracy anyway. | |
255 | * | |
256 | * Below I aim to run the PLLs' VCOs near 400 MHz to minimze errors. | |
257 | * | |
258 | * Many thanks to Jeff Campbell and Mike Bradley for their extensive | |
259 | * investigation, experimentation, testing, and suggested solutions of | |
260 | * of audio/video sync problems with SVideo and CVBS captures. | |
261 | */ | |
262 | ||
263 | /* the fast clock is at 200/245 MHz */ | |
264 | /* 1 * xtal_freq * 0x0d.f7df9b8 / 2 = 200 MHz: 400 MHz pre post-divide*/ | |
265 | /* 1 * xtal_freq * 0x11.1c71eb8 / 2 = 245 MHz: 490 MHz pre post-divide*/ | |
b1526421 AW |
266 | cx18_write_reg(cx, lowpwr ? 0xD : 0x11, CX18_FAST_CLOCK_PLL_INT); |
267 | cx18_write_reg(cx, lowpwr ? 0x1EFBF37 : 0x038E3D7, | |
268 | CX18_FAST_CLOCK_PLL_FRAC); | |
1c1e45d1 | 269 | |
b1526421 AW |
270 | cx18_write_reg(cx, 2, CX18_FAST_CLOCK_PLL_POST); |
271 | cx18_write_reg(cx, 1, CX18_FAST_CLOCK_PLL_PRESCALE); | |
272 | cx18_write_reg(cx, 4, CX18_FAST_CLOCK_PLL_ADJUST_BANDWIDTH); | |
1c1e45d1 HV |
273 | |
274 | /* set slow clock to 125/120 MHz */ | |
55d81aa5 AW |
275 | /* xtal_freq * 0x0d.1861a20 / 3 = 125 MHz: 375 MHz before post-divide */ |
276 | /* xtal_freq * 0x0c.92493f8 / 3 = 120 MHz: 360 MHz before post-divide */ | |
277 | cx18_write_reg(cx, lowpwr ? 0xD : 0xC, CX18_SLOW_CLOCK_PLL_INT); | |
278 | cx18_write_reg(cx, lowpwr ? 0x30C344 : 0x124927F, | |
b1526421 | 279 | CX18_SLOW_CLOCK_PLL_FRAC); |
55d81aa5 | 280 | cx18_write_reg(cx, 3, CX18_SLOW_CLOCK_PLL_POST); |
1c1e45d1 HV |
281 | |
282 | /* mpeg clock pll 54MHz */ | |
55d81aa5 | 283 | /* xtal_freq * 0xf.15f17f0 / 8 = 54 MHz: 432 MHz before post-divide */ |
b1526421 | 284 | cx18_write_reg(cx, 0xF, CX18_MPEG_CLOCK_PLL_INT); |
55d81aa5 | 285 | cx18_write_reg(cx, 0x2BE2FE, CX18_MPEG_CLOCK_PLL_FRAC); |
b1526421 | 286 | cx18_write_reg(cx, 8, CX18_MPEG_CLOCK_PLL_POST); |
1c1e45d1 HV |
287 | |
288 | /* Defaults */ | |
289 | /* APU = SC or SC/2 = 125/62.5 */ | |
290 | /* EPU = SC = 125 */ | |
291 | /* DDR = FC = 180 */ | |
292 | /* ENC = SC = 125 */ | |
293 | /* AI1 = SC = 125 */ | |
294 | /* VIM2 = disabled */ | |
295 | /* PCI = FC/2 = 90 */ | |
296 | /* AI2 = disabled */ | |
297 | /* DEMUX = disabled */ | |
298 | /* AO = SC/2 = 62.5 */ | |
299 | /* SER = 54MHz */ | |
300 | /* VFC = disabled */ | |
301 | /* USB = disabled */ | |
302 | ||
ced07371 AW |
303 | if (lowpwr) { |
304 | cx18_write_reg_expect(cx, 0xFFFF0020, CX18_CLOCK_SELECT1, | |
305 | 0x00000020, 0xFFFFFFFF); | |
306 | cx18_write_reg_expect(cx, 0xFFFF0004, CX18_CLOCK_SELECT2, | |
307 | 0x00000004, 0xFFFFFFFF); | |
308 | } else { | |
309 | /* This doesn't explicitly set every clock select */ | |
310 | cx18_write_reg_expect(cx, 0x00060004, CX18_CLOCK_SELECT1, | |
311 | 0x00000004, 0x00060006); | |
312 | cx18_write_reg_expect(cx, 0x00060006, CX18_CLOCK_SELECT2, | |
313 | 0x00000006, 0x00060006); | |
314 | } | |
1c1e45d1 | 315 | |
ced07371 AW |
316 | cx18_write_reg_expect(cx, 0xFFFF0002, CX18_HALF_CLOCK_SELECT1, |
317 | 0x00000002, 0xFFFFFFFF); | |
318 | cx18_write_reg_expect(cx, 0xFFFF0104, CX18_HALF_CLOCK_SELECT2, | |
319 | 0x00000104, 0xFFFFFFFF); | |
320 | cx18_write_reg_expect(cx, 0xFFFF9026, CX18_CLOCK_ENABLE1, | |
321 | 0x00009026, 0xFFFFFFFF); | |
322 | cx18_write_reg_expect(cx, 0xFFFF3105, CX18_CLOCK_ENABLE2, | |
323 | 0x00003105, 0xFFFFFFFF); | |
1c1e45d1 HV |
324 | } |
325 | ||
326 | void cx18_init_memory(struct cx18 *cx) | |
327 | { | |
328 | cx18_msleep_timeout(10, 0); | |
ced07371 AW |
329 | cx18_write_reg_expect(cx, 0x00010000, CX18_DDR_SOFT_RESET, |
330 | 0x00000000, 0x00010001); | |
1c1e45d1 HV |
331 | cx18_msleep_timeout(10, 0); |
332 | ||
b1526421 | 333 | cx18_write_reg(cx, cx->card->ddr.chip_config, CX18_DDR_CHIP_CONFIG); |
1c1e45d1 HV |
334 | |
335 | cx18_msleep_timeout(10, 0); | |
336 | ||
b1526421 AW |
337 | cx18_write_reg(cx, cx->card->ddr.refresh, CX18_DDR_REFRESH); |
338 | cx18_write_reg(cx, cx->card->ddr.timing1, CX18_DDR_TIMING1); | |
339 | cx18_write_reg(cx, cx->card->ddr.timing2, CX18_DDR_TIMING2); | |
1c1e45d1 HV |
340 | |
341 | cx18_msleep_timeout(10, 0); | |
342 | ||
343 | /* Initialize DQS pad time */ | |
b1526421 AW |
344 | cx18_write_reg(cx, cx->card->ddr.tune_lane, CX18_DDR_TUNE_LANE); |
345 | cx18_write_reg(cx, cx->card->ddr.initial_emrs, CX18_DDR_INITIAL_EMRS); | |
1c1e45d1 HV |
346 | |
347 | cx18_msleep_timeout(10, 0); | |
348 | ||
ced07371 AW |
349 | cx18_write_reg_expect(cx, 0x00020000, CX18_DDR_SOFT_RESET, |
350 | 0x00000000, 0x00020002); | |
1c1e45d1 HV |
351 | cx18_msleep_timeout(10, 0); |
352 | ||
353 | /* use power-down mode when idle */ | |
b1526421 AW |
354 | cx18_write_reg(cx, 0x00000010, CX18_DDR_POWER_REG); |
355 | ||
ced07371 AW |
356 | cx18_write_reg_expect(cx, 0x00010001, CX18_REG_BUS_TIMEOUT_EN, |
357 | 0x00000001, 0x00010001); | |
b1526421 AW |
358 | |
359 | cx18_write_reg(cx, 0x48, CX18_DDR_MB_PER_ROW_7); | |
360 | cx18_write_reg(cx, 0xE0000, CX18_DDR_BASE_63_ADDR); | |
361 | ||
362 | cx18_write_reg(cx, 0x00000101, CX18_WMB_CLIENT02); /* AO */ | |
363 | cx18_write_reg(cx, 0x00000101, CX18_WMB_CLIENT09); /* AI2 */ | |
364 | cx18_write_reg(cx, 0x00000101, CX18_WMB_CLIENT05); /* VIM1 */ | |
365 | cx18_write_reg(cx, 0x00000101, CX18_WMB_CLIENT06); /* AI1 */ | |
366 | cx18_write_reg(cx, 0x00000101, CX18_WMB_CLIENT07); /* 3D comb */ | |
367 | cx18_write_reg(cx, 0x00000101, CX18_WMB_CLIENT10); /* ME */ | |
368 | cx18_write_reg(cx, 0x00000101, CX18_WMB_CLIENT12); /* ENC */ | |
369 | cx18_write_reg(cx, 0x00000101, CX18_WMB_CLIENT13); /* PK */ | |
370 | cx18_write_reg(cx, 0x00000101, CX18_WMB_CLIENT11); /* RC */ | |
371 | cx18_write_reg(cx, 0x00000101, CX18_WMB_CLIENT14); /* AVO */ | |
1c1e45d1 HV |
372 | } |
373 | ||
8a7bf1d4 TG |
374 | #define CX18_CPU_FIRMWARE "v4l-cx23418-cpu.fw" |
375 | #define CX18_APU_FIRMWARE "v4l-cx23418-apu.fw" | |
376 | ||
1c1e45d1 HV |
377 | int cx18_firmware_init(struct cx18 *cx) |
378 | { | |
fd6b9c97 AW |
379 | u32 fw_entry_addr; |
380 | int sz, retries; | |
381 | u32 api_args[MAX_MB_ARGUMENTS]; | |
382 | ||
1c1e45d1 | 383 | /* Allow chip to control CLKRUN */ |
b1526421 | 384 | cx18_write_reg(cx, 0x5, CX18_DSP0_INTERRUPT_MASK); |
1c1e45d1 | 385 | |
ced07371 AW |
386 | /* Stop the firmware */ |
387 | cx18_write_reg_expect(cx, 0x000F000F, CX18_PROC_SOFT_RESET, | |
388 | 0x0000000F, 0x000F000F); | |
1c1e45d1 HV |
389 | |
390 | cx18_msleep_timeout(1, 0); | |
391 | ||
fd6b9c97 AW |
392 | /* If the CPU is still running */ |
393 | if ((cx18_read_reg(cx, CX18_PROC_SOFT_RESET) & 8) == 0) { | |
394 | CX18_ERR("%s: couldn't stop CPU to load firmware\n", __func__); | |
395 | return -EIO; | |
396 | } | |
397 | ||
b1526421 AW |
398 | cx18_sw1_irq_enable(cx, IRQ_CPU_TO_EPU | IRQ_APU_TO_EPU); |
399 | cx18_sw2_irq_enable(cx, IRQ_CPU_TO_EPU_ACK | IRQ_APU_TO_EPU_ACK); | |
1c1e45d1 | 400 | |
8a7bf1d4 | 401 | sz = load_cpu_fw_direct(CX18_CPU_FIRMWARE, cx->enc_mem, cx); |
fd6b9c97 AW |
402 | if (sz <= 0) |
403 | return sz; | |
404 | ||
405 | /* The SCB & IPC area *must* be correct before starting the firmwares */ | |
406 | cx18_init_scb(cx); | |
407 | ||
408 | fw_entry_addr = 0; | |
8a7bf1d4 | 409 | sz = load_apu_fw_direct(CX18_APU_FIRMWARE, cx->enc_mem, cx, |
fd6b9c97 AW |
410 | &fw_entry_addr); |
411 | if (sz <= 0) | |
412 | return sz; | |
413 | ||
414 | /* Start the CPU. The CPU will take care of the APU for us. */ | |
415 | cx18_write_reg_expect(cx, 0x00080000, CX18_PROC_SOFT_RESET, | |
416 | 0x00000000, 0x00080008); | |
417 | ||
418 | /* Wait up to 500 ms for the APU to come out of reset */ | |
419 | for (retries = 0; | |
420 | retries < 50 && (cx18_read_reg(cx, CX18_PROC_SOFT_RESET) & 1) == 1; | |
421 | retries++) | |
422 | cx18_msleep_timeout(10, 0); | |
423 | ||
424 | cx18_msleep_timeout(200, 0); | |
425 | ||
426 | if (retries == 50 && | |
427 | (cx18_read_reg(cx, CX18_PROC_SOFT_RESET) & 1) == 1) { | |
428 | CX18_ERR("Could not start the CPU\n"); | |
429 | return -EIO; | |
1c1e45d1 | 430 | } |
d20ceecd AW |
431 | |
432 | /* | |
fd6b9c97 AW |
433 | * The CPU had once before set up to receive an interrupt for it's |
434 | * outgoing IRQ_CPU_TO_EPU_ACK to us. If it ever does this, we get an | |
435 | * interrupt when it sends us an ack, but by the time we process it, | |
436 | * that flag in the SW2 status register has been cleared by the CPU | |
437 | * firmware. We'll prevent that not so useful condition from happening | |
438 | * by clearing the CPU's interrupt enables for Ack IRQ's we want to | |
439 | * process. | |
d20ceecd AW |
440 | */ |
441 | cx18_sw2_irq_disable_cpu(cx, IRQ_CPU_TO_EPU_ACK | IRQ_APU_TO_EPU_ACK); | |
442 | ||
fd6b9c97 AW |
443 | /* Try a benign command to see if the CPU is alive and well */ |
444 | sz = cx18_vapi_result(cx, api_args, CX18_CPU_DEBUG_PEEK32, 1, 0); | |
445 | if (sz < 0) | |
446 | return sz; | |
447 | ||
1c1e45d1 | 448 | /* initialize GPIO */ |
ced07371 | 449 | cx18_write_reg_expect(cx, 0x14001400, 0xc78110, 0x00001400, 0x14001400); |
1c1e45d1 HV |
450 | return 0; |
451 | } | |
8a7bf1d4 TG |
452 | |
453 | MODULE_FIRMWARE(CX18_CPU_FIRMWARE); | |
454 | MODULE_FIRMWARE(CX18_APU_FIRMWARE); |