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b1526421 AW |
1 | /* |
2 | * cx18 driver PCI memory mapped IO access routines | |
3 | * | |
4 | * Copyright (C) 2007 Hans Verkuil <hverkuil@xs4all.nl> | |
6afdeaf8 | 5 | * Copyright (C) 2008 Andy Walls <awalls@md.metrocast.net> |
b1526421 AW |
6 | * |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; either version 2 of the License, or | |
10 | * (at your option) any later version. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
b1526421 AW |
16 | */ |
17 | ||
18 | #include "cx18-driver.h" | |
c641d09c | 19 | #include "cx18-io.h" |
b1526421 AW |
20 | #include "cx18-irq.h" |
21 | ||
b1526421 AW |
22 | void cx18_memset_io(struct cx18 *cx, void __iomem *addr, int val, size_t count) |
23 | { | |
2796073a | 24 | u8 __iomem *dst = addr; |
c641d09c AW |
25 | u16 val2 = val | (val << 8); |
26 | u32 val4 = val2 | (val2 << 16); | |
27 | ||
28 | /* Align writes on the CX23418's addresses */ | |
ac2b97b1 AW |
29 | if ((count > 0) && ((unsigned long)dst & 1)) { |
30 | cx18_writeb(cx, (u8) val, dst); | |
c641d09c | 31 | count--; |
ac2b97b1 | 32 | dst++; |
c641d09c | 33 | } |
ac2b97b1 AW |
34 | if ((count > 1) && ((unsigned long)dst & 2)) { |
35 | cx18_writew(cx, val2, dst); | |
c641d09c | 36 | count -= 2; |
ac2b97b1 | 37 | dst += 2; |
c641d09c AW |
38 | } |
39 | while (count > 3) { | |
ac2b97b1 | 40 | cx18_writel(cx, val4, dst); |
c641d09c | 41 | count -= 4; |
ac2b97b1 | 42 | dst += 4; |
c641d09c AW |
43 | } |
44 | if (count > 1) { | |
ac2b97b1 | 45 | cx18_writew(cx, val2, dst); |
c641d09c | 46 | count -= 2; |
ac2b97b1 | 47 | dst += 2; |
c641d09c AW |
48 | } |
49 | if (count > 0) | |
ac2b97b1 | 50 | cx18_writeb(cx, (u8) val, dst); |
b1526421 AW |
51 | } |
52 | ||
53 | void cx18_sw1_irq_enable(struct cx18 *cx, u32 val) | |
54 | { | |
f056d29e | 55 | cx18_write_reg_expect(cx, val, SW1_INT_STATUS, ~val, val); |
d6c7e5f8 AW |
56 | cx->sw1_irq_mask = cx18_read_reg(cx, SW1_INT_ENABLE_PCI) | val; |
57 | cx18_write_reg(cx, cx->sw1_irq_mask, SW1_INT_ENABLE_PCI); | |
b1526421 AW |
58 | } |
59 | ||
60 | void cx18_sw1_irq_disable(struct cx18 *cx, u32 val) | |
61 | { | |
d6c7e5f8 AW |
62 | cx->sw1_irq_mask = cx18_read_reg(cx, SW1_INT_ENABLE_PCI) & ~val; |
63 | cx18_write_reg(cx, cx->sw1_irq_mask, SW1_INT_ENABLE_PCI); | |
b1526421 AW |
64 | } |
65 | ||
66 | void cx18_sw2_irq_enable(struct cx18 *cx, u32 val) | |
67 | { | |
f056d29e | 68 | cx18_write_reg_expect(cx, val, SW2_INT_STATUS, ~val, val); |
d6c7e5f8 AW |
69 | cx->sw2_irq_mask = cx18_read_reg(cx, SW2_INT_ENABLE_PCI) | val; |
70 | cx18_write_reg(cx, cx->sw2_irq_mask, SW2_INT_ENABLE_PCI); | |
b1526421 AW |
71 | } |
72 | ||
73 | void cx18_sw2_irq_disable(struct cx18 *cx, u32 val) | |
74 | { | |
d6c7e5f8 AW |
75 | cx->sw2_irq_mask = cx18_read_reg(cx, SW2_INT_ENABLE_PCI) & ~val; |
76 | cx18_write_reg(cx, cx->sw2_irq_mask, SW2_INT_ENABLE_PCI); | |
b1526421 AW |
77 | } |
78 | ||
d20ceecd AW |
79 | void cx18_sw2_irq_disable_cpu(struct cx18 *cx, u32 val) |
80 | { | |
81 | u32 r; | |
82 | r = cx18_read_reg(cx, SW2_INT_ENABLE_CPU); | |
83 | cx18_write_reg(cx, r & ~val, SW2_INT_ENABLE_CPU); | |
84 | } | |
85 | ||
b1526421 AW |
86 | void cx18_setup_page(struct cx18 *cx, u32 addr) |
87 | { | |
88 | u32 val; | |
89 | val = cx18_read_reg(cx, 0xD000F8); | |
90 | val = (val & ~0x1f00) | ((addr >> 17) & 0x1f00); | |
91 | cx18_write_reg(cx, val, 0xD000F8); | |
92 | } |