[mirror_ubuntu-hirsute-kernel.git] / drivers / media / pci / cx18 / cx18-io.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 *  cx18 driver PCI memory mapped IO access routines
 *
 *  Copyright (C) 2007  Hans Verkuil <hverkuil@xs4all.nl>
 *  Copyright (C) 2008  Andy Walls <awalls@md.metrocast.net>
 */

#include "cx18-driver.h"
#include "cx18-io.h"
#include "cx18-irq.h"

void cx18_memset_io(struct cx18 *cx, void __iomem *addr, int val, size_t count)
{
	u8 __iomem *dst = addr;
	u16 val2 = val | (val << 8);
	u32 val4 = val2 | (val2 << 16);

	/* Align writes on the CX23418's addresses */
	if ((count > 0) && ((unsigned long)dst & 1)) {
		cx18_writeb(cx, (u8) val, dst);
		count--;
		dst++;
	}
	if ((count > 1) && ((unsigned long)dst & 2)) {
		cx18_writew(cx, val2, dst);
		count -= 2;
		dst += 2;
	}
	while (count > 3) {
		cx18_writel(cx, val4, dst);
		count -= 4;
		dst += 4;
	}
	if (count > 1) {
		cx18_writew(cx, val2, dst);
		count -= 2;
		dst += 2;
	}
	if (count > 0)
		cx18_writeb(cx, (u8) val, dst);
}

void cx18_sw1_irq_enable(struct cx18 *cx, u32 val)
{
	cx18_write_reg_expect(cx, val, SW1_INT_STATUS, ~val, val);
	cx->sw1_irq_mask = cx18_read_reg(cx, SW1_INT_ENABLE_PCI) | val;
	cx18_write_reg(cx, cx->sw1_irq_mask, SW1_INT_ENABLE_PCI);
}

void cx18_sw1_irq_disable(struct cx18 *cx, u32 val)
{
	cx->sw1_irq_mask = cx18_read_reg(cx, SW1_INT_ENABLE_PCI) & ~val;
	cx18_write_reg(cx, cx->sw1_irq_mask, SW1_INT_ENABLE_PCI);
}

void cx18_sw2_irq_enable(struct cx18 *cx, u32 val)
{
	cx18_write_reg_expect(cx, val, SW2_INT_STATUS, ~val, val);
	cx->sw2_irq_mask = cx18_read_reg(cx, SW2_INT_ENABLE_PCI) | val;
	cx18_write_reg(cx, cx->sw2_irq_mask, SW2_INT_ENABLE_PCI);
}

void cx18_sw2_irq_disable(struct cx18 *cx, u32 val)
{
	cx->sw2_irq_mask = cx18_read_reg(cx, SW2_INT_ENABLE_PCI) & ~val;
	cx18_write_reg(cx, cx->sw2_irq_mask, SW2_INT_ENABLE_PCI);
}

void cx18_sw2_irq_disable_cpu(struct cx18 *cx, u32 val)
{
	u32 r;
	r = cx18_read_reg(cx, SW2_INT_ENABLE_CPU);
	cx18_write_reg(cx, r & ~val, SW2_INT_ENABLE_CPU);
}

void cx18_setup_page(struct cx18 *cx, u32 addr)
{
	u32 val;
	val = cx18_read_reg(cx, 0xD000F8);
	val = (val & ~0x1f00) | ((addr >> 17) & 0x1f00);
	cx18_write_reg(cx, val, 0xD000F8);
}
Commit	Line	Data
c942fddf	1	// SPDX-License-Identifier: GPL-2.0-or-later
b1526421 AW	2	/*
	3	* cx18 driver PCI memory mapped IO access routines
	4	*
	5	* Copyright (C) 2007 Hans Verkuil <hverkuil@xs4all.nl>
6afdeaf8	6	* Copyright (C) 2008 Andy Walls <awalls@md.metrocast.net>
b1526421 AW	7	*/
	8
	9	#include "cx18-driver.h"
c641d09c	10	#include "cx18-io.h"
b1526421 AW	11	#include "cx18-irq.h"
b1526421 AW	12
b1526421 AW	13	void cx18_memset_io(struct cx18 cx, void __iomem addr, int val, size_t count)
b1526421 AW	14	{
2796073a	15	u8 __iomem *dst = addr;
c641d09c AW	16	u16 val2 = val \| (val << 8);
	17	u32 val4 = val2 \| (val2 << 16);
	18
	19	/* Align writes on the CX23418's addresses */
ac2b97b1 AW	20	if ((count > 0) && ((unsigned long)dst & 1)) {
ac2b97b1 AW	21	cx18_writeb(cx, (u8) val, dst);
c641d09c	22	count--;
ac2b97b1	23	dst++;
c641d09c	24	}
ac2b97b1 AW	25	if ((count > 1) && ((unsigned long)dst & 2)) {
ac2b97b1 AW	26	cx18_writew(cx, val2, dst);
c641d09c	27	count -= 2;
ac2b97b1	28	dst += 2;
c641d09c AW	29	}
c641d09c AW	30	while (count > 3) {
ac2b97b1	31	cx18_writel(cx, val4, dst);
c641d09c	32	count -= 4;
ac2b97b1	33	dst += 4;
c641d09c AW	34	}
c641d09c AW	35	if (count > 1) {
ac2b97b1	36	cx18_writew(cx, val2, dst);
c641d09c	37	count -= 2;
ac2b97b1	38	dst += 2;
c641d09c AW	39	}
c641d09c AW	40	if (count > 0)
ac2b97b1	41	cx18_writeb(cx, (u8) val, dst);
b1526421 AW	42	}
	43
	44	void cx18_sw1_irq_enable(struct cx18 *cx, u32 val)
	45	{
f056d29e	46	cx18_write_reg_expect(cx, val, SW1_INT_STATUS, ~val, val);
d6c7e5f8 AW	47	cx->sw1_irq_mask = cx18_read_reg(cx, SW1_INT_ENABLE_PCI) \| val;
d6c7e5f8 AW	48	cx18_write_reg(cx, cx->sw1_irq_mask, SW1_INT_ENABLE_PCI);
b1526421 AW	49	}
	50
	51	void cx18_sw1_irq_disable(struct cx18 *cx, u32 val)
	52	{
d6c7e5f8 AW	53	cx->sw1_irq_mask = cx18_read_reg(cx, SW1_INT_ENABLE_PCI) & ~val;
d6c7e5f8 AW	54	cx18_write_reg(cx, cx->sw1_irq_mask, SW1_INT_ENABLE_PCI);
b1526421 AW	55	}
	56
	57	void cx18_sw2_irq_enable(struct cx18 *cx, u32 val)
	58	{
f056d29e	59	cx18_write_reg_expect(cx, val, SW2_INT_STATUS, ~val, val);
d6c7e5f8 AW	60	cx->sw2_irq_mask = cx18_read_reg(cx, SW2_INT_ENABLE_PCI) \| val;
d6c7e5f8 AW	61	cx18_write_reg(cx, cx->sw2_irq_mask, SW2_INT_ENABLE_PCI);
b1526421 AW	62	}
	63
	64	void cx18_sw2_irq_disable(struct cx18 *cx, u32 val)
	65	{
d6c7e5f8 AW	66	cx->sw2_irq_mask = cx18_read_reg(cx, SW2_INT_ENABLE_PCI) & ~val;
d6c7e5f8 AW	67	cx18_write_reg(cx, cx->sw2_irq_mask, SW2_INT_ENABLE_PCI);
b1526421 AW	68	}
b1526421 AW	69
d20ceecd AW	70	void cx18_sw2_irq_disable_cpu(struct cx18 *cx, u32 val)
	71	{
	72	u32 r;
	73	r = cx18_read_reg(cx, SW2_INT_ENABLE_CPU);
	74	cx18_write_reg(cx, r & ~val, SW2_INT_ENABLE_CPU);
	75	}
	76
b1526421 AW	77	void cx18_setup_page(struct cx18 *cx, u32 addr)
	78	{
	79	u32 val;
	80	val = cx18_read_reg(cx, 0xD000F8);
	81	val = (val & ~0x1f00) \| ((addr >> 17) & 0x1f00);
	82	cx18_write_reg(cx, val, 0xD000F8);
	83	}