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Commit | Line | Data |
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b1b81f1d ST |
1 | /* |
2 | * | |
3 | * Support for a cx23417 mpeg encoder via cx23885 host port. | |
4 | * | |
f8de18d4 | 5 | * (c) 2004 Jelle Foks <jelle@foks.us> |
b1b81f1d | 6 | * (c) 2004 Gerd Knorr <kraxel@bytesex.org> |
6d897616 | 7 | * (c) 2008 Steven Toth <stoth@linuxtv.org> |
b1b81f1d ST |
8 | * - CX23885/7/8 support |
9 | * | |
631dd1a8 | 10 | * Includes parts from the ivtv driver <http://sourceforge.net/projects/ivtv/> |
b1b81f1d ST |
11 | * |
12 | * This program is free software; you can redistribute it and/or modify | |
13 | * it under the terms of the GNU General Public License as published by | |
14 | * the Free Software Foundation; either version 2 of the License, or | |
15 | * (at your option) any later version. | |
16 | * | |
17 | * This program is distributed in the hope that it will be useful, | |
18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | * GNU General Public License for more details. | |
b1b81f1d ST |
21 | */ |
22 | ||
23 | #include <linux/module.h> | |
24 | #include <linux/moduleparam.h> | |
25 | #include <linux/init.h> | |
26 | #include <linux/fs.h> | |
27 | #include <linux/delay.h> | |
28 | #include <linux/device.h> | |
29 | #include <linux/firmware.h> | |
5a0e3ad6 | 30 | #include <linux/slab.h> |
b1b81f1d | 31 | #include <media/v4l2-common.h> |
35ea11ff | 32 | #include <media/v4l2-ioctl.h> |
d647f0b7 | 33 | #include <media/drv-intf/cx2341x.h> |
b1b81f1d ST |
34 | |
35 | #include "cx23885.h" | |
74618244 | 36 | #include "cx23885-ioctl.h" |
b1b81f1d ST |
37 | |
38 | #define CX23885_FIRM_IMAGE_SIZE 376836 | |
39 | #define CX23885_FIRM_IMAGE_NAME "v4l-cx23885-enc.fw" | |
40 | ||
41 | static unsigned int mpegbufs = 32; | |
42 | module_param(mpegbufs, int, 0644); | |
43 | MODULE_PARM_DESC(mpegbufs, "number of mpeg buffers, range 2-32"); | |
44 | static unsigned int mpeglines = 32; | |
45 | module_param(mpeglines, int, 0644); | |
46 | MODULE_PARM_DESC(mpeglines, "number of lines in an MPEG buffer, range 2-32"); | |
47 | static unsigned int mpeglinesize = 512; | |
48 | module_param(mpeglinesize, int, 0644); | |
49 | MODULE_PARM_DESC(mpeglinesize, | |
50 | "number of bytes in each line of an MPEG buffer, range 512-1024"); | |
51 | ||
52 | static unsigned int v4l_debug; | |
53 | module_param(v4l_debug, int, 0644); | |
54 | MODULE_PARM_DESC(v4l_debug, "enable V4L debug messages"); | |
55 | ||
56 | #define dprintk(level, fmt, arg...)\ | |
57 | do { if (v4l_debug >= level) \ | |
ca4e771f MK |
58 | printk(KERN_DEBUG "%s: " fmt, \ |
59 | (dev) ? dev->name : "cx23885[?]", ## arg); \ | |
b1b81f1d ST |
60 | } while (0) |
61 | ||
62 | static struct cx23885_tvnorm cx23885_tvnorms[] = { | |
63 | { | |
64 | .name = "NTSC-M", | |
65 | .id = V4L2_STD_NTSC_M, | |
66 | }, { | |
67 | .name = "NTSC-JP", | |
68 | .id = V4L2_STD_NTSC_M_JP, | |
69 | }, { | |
70 | .name = "PAL-BG", | |
71 | .id = V4L2_STD_PAL_BG, | |
72 | }, { | |
73 | .name = "PAL-DK", | |
74 | .id = V4L2_STD_PAL_DK, | |
75 | }, { | |
76 | .name = "PAL-I", | |
77 | .id = V4L2_STD_PAL_I, | |
78 | }, { | |
79 | .name = "PAL-M", | |
80 | .id = V4L2_STD_PAL_M, | |
81 | }, { | |
82 | .name = "PAL-N", | |
83 | .id = V4L2_STD_PAL_N, | |
84 | }, { | |
85 | .name = "PAL-Nc", | |
86 | .id = V4L2_STD_PAL_Nc, | |
87 | }, { | |
88 | .name = "PAL-60", | |
89 | .id = V4L2_STD_PAL_60, | |
90 | }, { | |
91 | .name = "SECAM-L", | |
92 | .id = V4L2_STD_SECAM_L, | |
93 | }, { | |
94 | .name = "SECAM-DK", | |
95 | .id = V4L2_STD_SECAM_DK, | |
96 | } | |
97 | }; | |
98 | ||
99 | /* ------------------------------------------------------------------ */ | |
100 | enum cx23885_capture_type { | |
101 | CX23885_MPEG_CAPTURE, | |
102 | CX23885_RAW_CAPTURE, | |
103 | CX23885_RAW_PASSTHRU_CAPTURE | |
104 | }; | |
105 | enum cx23885_capture_bits { | |
106 | CX23885_RAW_BITS_NONE = 0x00, | |
107 | CX23885_RAW_BITS_YUV_CAPTURE = 0x01, | |
108 | CX23885_RAW_BITS_PCM_CAPTURE = 0x02, | |
109 | CX23885_RAW_BITS_VBI_CAPTURE = 0x04, | |
110 | CX23885_RAW_BITS_PASSTHRU_CAPTURE = 0x08, | |
111 | CX23885_RAW_BITS_TO_HOST_CAPTURE = 0x10 | |
112 | }; | |
113 | enum cx23885_capture_end { | |
114 | CX23885_END_AT_GOP, /* stop at the end of gop, generate irq */ | |
115 | CX23885_END_NOW, /* stop immediately, no irq */ | |
116 | }; | |
117 | enum cx23885_framerate { | |
118 | CX23885_FRAMERATE_NTSC_30, /* NTSC: 30fps */ | |
119 | CX23885_FRAMERATE_PAL_25 /* PAL: 25fps */ | |
120 | }; | |
121 | enum cx23885_stream_port { | |
122 | CX23885_OUTPUT_PORT_MEMORY, | |
123 | CX23885_OUTPUT_PORT_STREAMING, | |
124 | CX23885_OUTPUT_PORT_SERIAL | |
125 | }; | |
126 | enum cx23885_data_xfer_status { | |
127 | CX23885_MORE_BUFFERS_FOLLOW, | |
128 | CX23885_LAST_BUFFER, | |
129 | }; | |
130 | enum cx23885_picture_mask { | |
131 | CX23885_PICTURE_MASK_NONE, | |
132 | CX23885_PICTURE_MASK_I_FRAMES, | |
133 | CX23885_PICTURE_MASK_I_P_FRAMES = 0x3, | |
134 | CX23885_PICTURE_MASK_ALL_FRAMES = 0x7, | |
135 | }; | |
136 | enum cx23885_vbi_mode_bits { | |
137 | CX23885_VBI_BITS_SLICED, | |
138 | CX23885_VBI_BITS_RAW, | |
139 | }; | |
140 | enum cx23885_vbi_insertion_bits { | |
141 | CX23885_VBI_BITS_INSERT_IN_XTENSION_USR_DATA, | |
142 | CX23885_VBI_BITS_INSERT_IN_PRIVATE_PACKETS = 0x1 << 1, | |
143 | CX23885_VBI_BITS_SEPARATE_STREAM = 0x2 << 1, | |
144 | CX23885_VBI_BITS_SEPARATE_STREAM_USR_DATA = 0x4 << 1, | |
145 | CX23885_VBI_BITS_SEPARATE_STREAM_PRV_DATA = 0x5 << 1, | |
146 | }; | |
147 | enum cx23885_dma_unit { | |
148 | CX23885_DMA_BYTES, | |
149 | CX23885_DMA_FRAMES, | |
150 | }; | |
151 | enum cx23885_dma_transfer_status_bits { | |
152 | CX23885_DMA_TRANSFER_BITS_DONE = 0x01, | |
153 | CX23885_DMA_TRANSFER_BITS_ERROR = 0x04, | |
154 | CX23885_DMA_TRANSFER_BITS_LL_ERROR = 0x10, | |
155 | }; | |
156 | enum cx23885_pause { | |
157 | CX23885_PAUSE_ENCODING, | |
158 | CX23885_RESUME_ENCODING, | |
159 | }; | |
160 | enum cx23885_copyright { | |
161 | CX23885_COPYRIGHT_OFF, | |
162 | CX23885_COPYRIGHT_ON, | |
163 | }; | |
164 | enum cx23885_notification_type { | |
165 | CX23885_NOTIFICATION_REFRESH, | |
166 | }; | |
167 | enum cx23885_notification_status { | |
168 | CX23885_NOTIFICATION_OFF, | |
169 | CX23885_NOTIFICATION_ON, | |
170 | }; | |
171 | enum cx23885_notification_mailbox { | |
172 | CX23885_NOTIFICATION_NO_MAILBOX = -1, | |
173 | }; | |
174 | enum cx23885_field1_lines { | |
175 | CX23885_FIELD1_SAA7114 = 0x00EF, /* 239 */ | |
176 | CX23885_FIELD1_SAA7115 = 0x00F0, /* 240 */ | |
177 | CX23885_FIELD1_MICRONAS = 0x0105, /* 261 */ | |
178 | }; | |
179 | enum cx23885_field2_lines { | |
180 | CX23885_FIELD2_SAA7114 = 0x00EF, /* 239 */ | |
181 | CX23885_FIELD2_SAA7115 = 0x00F0, /* 240 */ | |
182 | CX23885_FIELD2_MICRONAS = 0x0106, /* 262 */ | |
183 | }; | |
184 | enum cx23885_custom_data_type { | |
185 | CX23885_CUSTOM_EXTENSION_USR_DATA, | |
186 | CX23885_CUSTOM_PRIVATE_PACKET, | |
187 | }; | |
188 | enum cx23885_mute { | |
189 | CX23885_UNMUTE, | |
190 | CX23885_MUTE, | |
191 | }; | |
192 | enum cx23885_mute_video_mask { | |
193 | CX23885_MUTE_VIDEO_V_MASK = 0x0000FF00, | |
194 | CX23885_MUTE_VIDEO_U_MASK = 0x00FF0000, | |
195 | CX23885_MUTE_VIDEO_Y_MASK = 0xFF000000, | |
196 | }; | |
197 | enum cx23885_mute_video_shift { | |
198 | CX23885_MUTE_VIDEO_V_SHIFT = 8, | |
199 | CX23885_MUTE_VIDEO_U_SHIFT = 16, | |
200 | CX23885_MUTE_VIDEO_Y_SHIFT = 24, | |
201 | }; | |
202 | ||
203 | /* defines below are from ivtv-driver.h */ | |
204 | #define IVTV_CMD_HW_BLOCKS_RST 0xFFFFFFFF | |
205 | ||
206 | /* Firmware API commands */ | |
207 | #define IVTV_API_STD_TIMEOUT 500 | |
208 | ||
209 | /* Registers */ | |
210 | /* IVTV_REG_OFFSET */ | |
211 | #define IVTV_REG_ENC_SDRAM_REFRESH (0x07F8) | |
212 | #define IVTV_REG_ENC_SDRAM_PRECHARGE (0x07FC) | |
213 | #define IVTV_REG_SPU (0x9050) | |
214 | #define IVTV_REG_HW_BLOCKS (0x9054) | |
215 | #define IVTV_REG_VPU (0x9058) | |
216 | #define IVTV_REG_APU (0xA064) | |
217 | ||
218 | /**** Bit definitions for MC417_RWD and MC417_OEN registers *** | |
219 | bits 31-16 | |
220 | +-----------+ | |
221 | | Reserved | | |
222 | +-----------+ | |
223 | bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 | |
224 | +-------+-------+-------+-------+-------+-------+-------+-------+ | |
225 | | MIWR# | MIRD# | MICS# |MIRDY# |MIADDR3|MIADDR2|MIADDR1|MIADDR0| | |
226 | +-------+-------+-------+-------+-------+-------+-------+-------+ | |
227 | bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 | |
228 | +-------+-------+-------+-------+-------+-------+-------+-------+ | |
229 | |MIDATA7|MIDATA6|MIDATA5|MIDATA4|MIDATA3|MIDATA2|MIDATA1|MIDATA0| | |
230 | +-------+-------+-------+-------+-------+-------+-------+-------+ | |
231 | ***/ | |
232 | #define MC417_MIWR 0x8000 | |
233 | #define MC417_MIRD 0x4000 | |
234 | #define MC417_MICS 0x2000 | |
235 | #define MC417_MIRDY 0x1000 | |
236 | #define MC417_MIADDR 0x0F00 | |
237 | #define MC417_MIDATA 0x00FF | |
238 | ||
239 | /* MIADDR* nibble definitions */ | |
240 | #define MCI_MEMORY_DATA_BYTE0 0x000 | |
241 | #define MCI_MEMORY_DATA_BYTE1 0x100 | |
242 | #define MCI_MEMORY_DATA_BYTE2 0x200 | |
243 | #define MCI_MEMORY_DATA_BYTE3 0x300 | |
244 | #define MCI_MEMORY_ADDRESS_BYTE2 0x400 | |
245 | #define MCI_MEMORY_ADDRESS_BYTE1 0x500 | |
246 | #define MCI_MEMORY_ADDRESS_BYTE0 0x600 | |
247 | #define MCI_REGISTER_DATA_BYTE0 0x800 | |
248 | #define MCI_REGISTER_DATA_BYTE1 0x900 | |
249 | #define MCI_REGISTER_DATA_BYTE2 0xA00 | |
250 | #define MCI_REGISTER_DATA_BYTE3 0xB00 | |
251 | #define MCI_REGISTER_ADDRESS_BYTE0 0xC00 | |
252 | #define MCI_REGISTER_ADDRESS_BYTE1 0xD00 | |
253 | #define MCI_REGISTER_MODE 0xE00 | |
254 | ||
255 | /* Read and write modes */ | |
256 | #define MCI_MODE_REGISTER_READ 0 | |
257 | #define MCI_MODE_REGISTER_WRITE 1 | |
258 | #define MCI_MODE_MEMORY_READ 0 | |
259 | #define MCI_MODE_MEMORY_WRITE 0x40 | |
260 | ||
261 | /*** Bit definitions for MC417_CTL register **** | |
262 | bits 31-6 bits 5-4 bit 3 bits 2-1 Bit 0 | |
263 | +--------+-------------+--------+--------------+------------+ | |
264 | |Reserved|MC417_SPD_CTL|Reserved|MC417_GPIO_SEL|UART_GPIO_EN| | |
265 | +--------+-------------+--------+--------------+------------+ | |
266 | ***/ | |
267 | #define MC417_SPD_CTL(x) (((x) << 4) & 0x00000030) | |
268 | #define MC417_GPIO_SEL(x) (((x) << 1) & 0x00000006) | |
269 | #define MC417_UART_GPIO_EN 0x00000001 | |
270 | ||
271 | /* Values for speed control */ | |
272 | #define MC417_SPD_CTL_SLOW 0x1 | |
273 | #define MC417_SPD_CTL_MEDIUM 0x0 | |
274 | #define MC417_SPD_CTL_FAST 0x3 /* b'1x, but we use b'11 */ | |
275 | ||
276 | /* Values for GPIO select */ | |
277 | #define MC417_GPIO_SEL_GPIO3 0x3 | |
278 | #define MC417_GPIO_SEL_GPIO2 0x2 | |
279 | #define MC417_GPIO_SEL_GPIO1 0x1 | |
280 | #define MC417_GPIO_SEL_GPIO0 0x0 | |
281 | ||
282 | void cx23885_mc417_init(struct cx23885_dev *dev) | |
283 | { | |
284 | u32 regval; | |
285 | ||
286 | dprintk(2, "%s()\n", __func__); | |
287 | ||
288 | /* Configure MC417_CTL register to defaults. */ | |
289 | regval = MC417_SPD_CTL(MC417_SPD_CTL_FAST) | | |
290 | MC417_GPIO_SEL(MC417_GPIO_SEL_GPIO3) | | |
291 | MC417_UART_GPIO_EN; | |
292 | cx_write(MC417_CTL, regval); | |
293 | ||
294 | /* Configure MC417_OEN to defaults. */ | |
295 | regval = MC417_MIRDY; | |
296 | cx_write(MC417_OEN, regval); | |
297 | ||
298 | /* Configure MC417_RWD to defaults. */ | |
299 | regval = MC417_MIWR | MC417_MIRD | MC417_MICS; | |
300 | cx_write(MC417_RWD, regval); | |
301 | } | |
302 | ||
303 | static int mc417_wait_ready(struct cx23885_dev *dev) | |
304 | { | |
305 | u32 mi_ready; | |
306 | unsigned long timeout = jiffies + msecs_to_jiffies(1); | |
307 | ||
308 | for (;;) { | |
309 | mi_ready = cx_read(MC417_RWD) & MC417_MIRDY; | |
310 | if (mi_ready != 0) | |
311 | return 0; | |
312 | if (time_after(jiffies, timeout)) | |
313 | return -1; | |
314 | udelay(1); | |
315 | } | |
316 | } | |
317 | ||
74618244 | 318 | int mc417_register_write(struct cx23885_dev *dev, u16 address, u32 value) |
b1b81f1d ST |
319 | { |
320 | u32 regval; | |
321 | ||
322 | /* Enable MC417 GPIO outputs except for MC417_MIRDY, | |
323 | * which is an input. | |
324 | */ | |
325 | cx_write(MC417_OEN, MC417_MIRDY); | |
326 | ||
327 | /* Write data byte 0 */ | |
328 | regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_DATA_BYTE0 | | |
329 | (value & 0x000000FF); | |
330 | cx_write(MC417_RWD, regval); | |
331 | ||
332 | /* Transition CS/WR to effect write transaction across bus. */ | |
333 | regval |= MC417_MICS | MC417_MIWR; | |
334 | cx_write(MC417_RWD, regval); | |
335 | ||
336 | /* Write data byte 1 */ | |
337 | regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_DATA_BYTE1 | | |
338 | ((value >> 8) & 0x000000FF); | |
339 | cx_write(MC417_RWD, regval); | |
340 | regval |= MC417_MICS | MC417_MIWR; | |
341 | cx_write(MC417_RWD, regval); | |
342 | ||
343 | /* Write data byte 2 */ | |
344 | regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_DATA_BYTE2 | | |
345 | ((value >> 16) & 0x000000FF); | |
346 | cx_write(MC417_RWD, regval); | |
347 | regval |= MC417_MICS | MC417_MIWR; | |
348 | cx_write(MC417_RWD, regval); | |
349 | ||
350 | /* Write data byte 3 */ | |
351 | regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_DATA_BYTE3 | | |
352 | ((value >> 24) & 0x000000FF); | |
353 | cx_write(MC417_RWD, regval); | |
354 | regval |= MC417_MICS | MC417_MIWR; | |
355 | cx_write(MC417_RWD, regval); | |
356 | ||
357 | /* Write address byte 0 */ | |
358 | regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_ADDRESS_BYTE0 | | |
359 | (address & 0xFF); | |
360 | cx_write(MC417_RWD, regval); | |
361 | regval |= MC417_MICS | MC417_MIWR; | |
362 | cx_write(MC417_RWD, regval); | |
363 | ||
364 | /* Write address byte 1 */ | |
365 | regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_ADDRESS_BYTE1 | | |
366 | ((address >> 8) & 0xFF); | |
367 | cx_write(MC417_RWD, regval); | |
368 | regval |= MC417_MICS | MC417_MIWR; | |
369 | cx_write(MC417_RWD, regval); | |
370 | ||
371 | /* Indicate that this is a write. */ | |
372 | regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_MODE | | |
373 | MCI_MODE_REGISTER_WRITE; | |
374 | cx_write(MC417_RWD, regval); | |
375 | regval |= MC417_MICS | MC417_MIWR; | |
376 | cx_write(MC417_RWD, regval); | |
377 | ||
378 | /* Wait for the trans to complete (MC417_MIRDY asserted). */ | |
379 | return mc417_wait_ready(dev); | |
380 | } | |
381 | ||
74618244 | 382 | int mc417_register_read(struct cx23885_dev *dev, u16 address, u32 *value) |
b1b81f1d ST |
383 | { |
384 | int retval; | |
385 | u32 regval; | |
386 | u32 tempval; | |
387 | u32 dataval; | |
388 | ||
389 | /* Enable MC417 GPIO outputs except for MC417_MIRDY, | |
390 | * which is an input. | |
391 | */ | |
392 | cx_write(MC417_OEN, MC417_MIRDY); | |
393 | ||
394 | /* Write address byte 0 */ | |
395 | regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_ADDRESS_BYTE0 | | |
396 | ((address & 0x00FF)); | |
397 | cx_write(MC417_RWD, regval); | |
398 | regval |= MC417_MICS | MC417_MIWR; | |
399 | cx_write(MC417_RWD, regval); | |
400 | ||
401 | /* Write address byte 1 */ | |
402 | regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_ADDRESS_BYTE1 | | |
403 | ((address >> 8) & 0xFF); | |
404 | cx_write(MC417_RWD, regval); | |
405 | regval |= MC417_MICS | MC417_MIWR; | |
406 | cx_write(MC417_RWD, regval); | |
407 | ||
408 | /* Indicate that this is a register read. */ | |
409 | regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_MODE | | |
410 | MCI_MODE_REGISTER_READ; | |
411 | cx_write(MC417_RWD, regval); | |
412 | regval |= MC417_MICS | MC417_MIWR; | |
413 | cx_write(MC417_RWD, regval); | |
414 | ||
415 | /* Wait for the trans to complete (MC417_MIRDY asserted). */ | |
416 | retval = mc417_wait_ready(dev); | |
417 | ||
418 | /* switch the DAT0-7 GPIO[10:3] to input mode */ | |
419 | cx_write(MC417_OEN, MC417_MIRDY | MC417_MIDATA); | |
420 | ||
421 | /* Read data byte 0 */ | |
422 | regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_DATA_BYTE0; | |
423 | cx_write(MC417_RWD, regval); | |
424 | ||
425 | /* Transition RD to effect read transaction across bus. | |
39c1cb2b | 426 | * Transition 0x5000 -> 0x9000 correct (RD/RDY -> WR/RDY)? |
b1b81f1d ST |
427 | * Should it be 0x9000 -> 0xF000 (also why is RDY being set, its |
428 | * input only...) | |
429 | */ | |
430 | regval = MC417_MIWR | MC417_MIRDY | MCI_REGISTER_DATA_BYTE0; | |
431 | cx_write(MC417_RWD, regval); | |
432 | ||
433 | /* Collect byte */ | |
434 | tempval = cx_read(MC417_RWD); | |
435 | dataval = tempval & 0x000000FF; | |
436 | ||
437 | /* Bring CS and RD high. */ | |
438 | regval = MC417_MIWR | MC417_MIRD | MC417_MICS | MC417_MIRDY; | |
439 | cx_write(MC417_RWD, regval); | |
440 | ||
441 | /* Read data byte 1 */ | |
442 | regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_DATA_BYTE1; | |
443 | cx_write(MC417_RWD, regval); | |
444 | regval = MC417_MIWR | MC417_MIRDY | MCI_REGISTER_DATA_BYTE1; | |
445 | cx_write(MC417_RWD, regval); | |
446 | tempval = cx_read(MC417_RWD); | |
447 | dataval |= ((tempval & 0x000000FF) << 8); | |
448 | regval = MC417_MIWR | MC417_MIRD | MC417_MICS | MC417_MIRDY; | |
449 | cx_write(MC417_RWD, regval); | |
450 | ||
451 | /* Read data byte 2 */ | |
452 | regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_DATA_BYTE2; | |
453 | cx_write(MC417_RWD, regval); | |
454 | regval = MC417_MIWR | MC417_MIRDY | MCI_REGISTER_DATA_BYTE2; | |
455 | cx_write(MC417_RWD, regval); | |
456 | tempval = cx_read(MC417_RWD); | |
457 | dataval |= ((tempval & 0x000000FF) << 16); | |
458 | regval = MC417_MIWR | MC417_MIRD | MC417_MICS | MC417_MIRDY; | |
459 | cx_write(MC417_RWD, regval); | |
460 | ||
461 | /* Read data byte 3 */ | |
462 | regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_DATA_BYTE3; | |
463 | cx_write(MC417_RWD, regval); | |
464 | regval = MC417_MIWR | MC417_MIRDY | MCI_REGISTER_DATA_BYTE3; | |
465 | cx_write(MC417_RWD, regval); | |
466 | tempval = cx_read(MC417_RWD); | |
467 | dataval |= ((tempval & 0x000000FF) << 24); | |
468 | regval = MC417_MIWR | MC417_MIRD | MC417_MICS | MC417_MIRDY; | |
469 | cx_write(MC417_RWD, regval); | |
470 | ||
471 | *value = dataval; | |
472 | ||
473 | return retval; | |
474 | } | |
475 | ||
476 | int mc417_memory_write(struct cx23885_dev *dev, u32 address, u32 value) | |
477 | { | |
478 | u32 regval; | |
479 | ||
480 | /* Enable MC417 GPIO outputs except for MC417_MIRDY, | |
481 | * which is an input. | |
482 | */ | |
483 | cx_write(MC417_OEN, MC417_MIRDY); | |
484 | ||
485 | /* Write data byte 0 */ | |
486 | regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_DATA_BYTE0 | | |
487 | (value & 0x000000FF); | |
488 | cx_write(MC417_RWD, regval); | |
489 | ||
490 | /* Transition CS/WR to effect write transaction across bus. */ | |
491 | regval |= MC417_MICS | MC417_MIWR; | |
492 | cx_write(MC417_RWD, regval); | |
493 | ||
494 | /* Write data byte 1 */ | |
495 | regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_DATA_BYTE1 | | |
496 | ((value >> 8) & 0x000000FF); | |
497 | cx_write(MC417_RWD, regval); | |
498 | regval |= MC417_MICS | MC417_MIWR; | |
499 | cx_write(MC417_RWD, regval); | |
500 | ||
501 | /* Write data byte 2 */ | |
502 | regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_DATA_BYTE2 | | |
503 | ((value >> 16) & 0x000000FF); | |
504 | cx_write(MC417_RWD, regval); | |
505 | regval |= MC417_MICS | MC417_MIWR; | |
506 | cx_write(MC417_RWD, regval); | |
507 | ||
508 | /* Write data byte 3 */ | |
509 | regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_DATA_BYTE3 | | |
510 | ((value >> 24) & 0x000000FF); | |
511 | cx_write(MC417_RWD, regval); | |
512 | regval |= MC417_MICS | MC417_MIWR; | |
513 | cx_write(MC417_RWD, regval); | |
514 | ||
515 | /* Write address byte 2 */ | |
516 | regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_ADDRESS_BYTE2 | | |
517 | MCI_MODE_MEMORY_WRITE | ((address >> 16) & 0x3F); | |
518 | cx_write(MC417_RWD, regval); | |
519 | regval |= MC417_MICS | MC417_MIWR; | |
520 | cx_write(MC417_RWD, regval); | |
521 | ||
522 | /* Write address byte 1 */ | |
523 | regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_ADDRESS_BYTE1 | | |
524 | ((address >> 8) & 0xFF); | |
525 | cx_write(MC417_RWD, regval); | |
526 | regval |= MC417_MICS | MC417_MIWR; | |
527 | cx_write(MC417_RWD, regval); | |
528 | ||
529 | /* Write address byte 0 */ | |
530 | regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_ADDRESS_BYTE0 | | |
531 | (address & 0xFF); | |
532 | cx_write(MC417_RWD, regval); | |
533 | regval |= MC417_MICS | MC417_MIWR; | |
534 | cx_write(MC417_RWD, regval); | |
535 | ||
536 | /* Wait for the trans to complete (MC417_MIRDY asserted). */ | |
537 | return mc417_wait_ready(dev); | |
538 | } | |
539 | ||
540 | int mc417_memory_read(struct cx23885_dev *dev, u32 address, u32 *value) | |
541 | { | |
542 | int retval; | |
543 | u32 regval; | |
544 | u32 tempval; | |
545 | u32 dataval; | |
546 | ||
547 | /* Enable MC417 GPIO outputs except for MC417_MIRDY, | |
548 | * which is an input. | |
549 | */ | |
550 | cx_write(MC417_OEN, MC417_MIRDY); | |
551 | ||
552 | /* Write address byte 2 */ | |
553 | regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_ADDRESS_BYTE2 | | |
554 | MCI_MODE_MEMORY_READ | ((address >> 16) & 0x3F); | |
555 | cx_write(MC417_RWD, regval); | |
556 | regval |= MC417_MICS | MC417_MIWR; | |
557 | cx_write(MC417_RWD, regval); | |
558 | ||
559 | /* Write address byte 1 */ | |
560 | regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_ADDRESS_BYTE1 | | |
561 | ((address >> 8) & 0xFF); | |
562 | cx_write(MC417_RWD, regval); | |
563 | regval |= MC417_MICS | MC417_MIWR; | |
564 | cx_write(MC417_RWD, regval); | |
565 | ||
566 | /* Write address byte 0 */ | |
567 | regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_ADDRESS_BYTE0 | | |
568 | (address & 0xFF); | |
569 | cx_write(MC417_RWD, regval); | |
570 | regval |= MC417_MICS | MC417_MIWR; | |
571 | cx_write(MC417_RWD, regval); | |
572 | ||
573 | /* Wait for the trans to complete (MC417_MIRDY asserted). */ | |
574 | retval = mc417_wait_ready(dev); | |
575 | ||
576 | /* switch the DAT0-7 GPIO[10:3] to input mode */ | |
577 | cx_write(MC417_OEN, MC417_MIRDY | MC417_MIDATA); | |
578 | ||
579 | /* Read data byte 3 */ | |
580 | regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_DATA_BYTE3; | |
581 | cx_write(MC417_RWD, regval); | |
582 | ||
583 | /* Transition RD to effect read transaction across bus. */ | |
584 | regval = MC417_MIWR | MC417_MIRDY | MCI_MEMORY_DATA_BYTE3; | |
585 | cx_write(MC417_RWD, regval); | |
586 | ||
587 | /* Collect byte */ | |
588 | tempval = cx_read(MC417_RWD); | |
589 | dataval = ((tempval & 0x000000FF) << 24); | |
590 | ||
591 | /* Bring CS and RD high. */ | |
592 | regval = MC417_MIWR | MC417_MIRD | MC417_MICS | MC417_MIRDY; | |
593 | cx_write(MC417_RWD, regval); | |
594 | ||
595 | /* Read data byte 2 */ | |
596 | regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_DATA_BYTE2; | |
597 | cx_write(MC417_RWD, regval); | |
598 | regval = MC417_MIWR | MC417_MIRDY | MCI_MEMORY_DATA_BYTE2; | |
599 | cx_write(MC417_RWD, regval); | |
600 | tempval = cx_read(MC417_RWD); | |
601 | dataval |= ((tempval & 0x000000FF) << 16); | |
602 | regval = MC417_MIWR | MC417_MIRD | MC417_MICS | MC417_MIRDY; | |
603 | cx_write(MC417_RWD, regval); | |
604 | ||
605 | /* Read data byte 1 */ | |
606 | regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_DATA_BYTE1; | |
607 | cx_write(MC417_RWD, regval); | |
608 | regval = MC417_MIWR | MC417_MIRDY | MCI_MEMORY_DATA_BYTE1; | |
609 | cx_write(MC417_RWD, regval); | |
610 | tempval = cx_read(MC417_RWD); | |
611 | dataval |= ((tempval & 0x000000FF) << 8); | |
612 | regval = MC417_MIWR | MC417_MIRD | MC417_MICS | MC417_MIRDY; | |
613 | cx_write(MC417_RWD, regval); | |
614 | ||
615 | /* Read data byte 0 */ | |
616 | regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_DATA_BYTE0; | |
617 | cx_write(MC417_RWD, regval); | |
618 | regval = MC417_MIWR | MC417_MIRDY | MCI_MEMORY_DATA_BYTE0; | |
619 | cx_write(MC417_RWD, regval); | |
620 | tempval = cx_read(MC417_RWD); | |
621 | dataval |= (tempval & 0x000000FF); | |
622 | regval = MC417_MIWR | MC417_MIRD | MC417_MICS | MC417_MIRDY; | |
623 | cx_write(MC417_RWD, regval); | |
624 | ||
625 | *value = dataval; | |
626 | ||
627 | return retval; | |
628 | } | |
629 | ||
f659c513 ST |
630 | void mc417_gpio_set(struct cx23885_dev *dev, u32 mask) |
631 | { | |
632 | u32 val; | |
633 | ||
634 | /* Set the gpio value */ | |
635 | mc417_register_read(dev, 0x900C, &val); | |
636 | val |= (mask & 0x000ffff); | |
637 | mc417_register_write(dev, 0x900C, val); | |
638 | } | |
639 | ||
640 | void mc417_gpio_clear(struct cx23885_dev *dev, u32 mask) | |
641 | { | |
642 | u32 val; | |
643 | ||
644 | /* Clear the gpio value */ | |
645 | mc417_register_read(dev, 0x900C, &val); | |
646 | val &= ~(mask & 0x0000ffff); | |
647 | mc417_register_write(dev, 0x900C, val); | |
648 | } | |
649 | ||
650 | void mc417_gpio_enable(struct cx23885_dev *dev, u32 mask, int asoutput) | |
651 | { | |
652 | u32 val; | |
653 | ||
654 | /* Enable GPIO direction bits */ | |
655 | mc417_register_read(dev, 0x9020, &val); | |
656 | if (asoutput) | |
657 | val |= (mask & 0x0000ffff); | |
658 | else | |
659 | val &= ~(mask & 0x0000ffff); | |
660 | ||
661 | mc417_register_write(dev, 0x9020, val); | |
662 | } | |
b1b81f1d ST |
663 | /* ------------------------------------------------------------------ */ |
664 | ||
665 | /* MPEG encoder API */ | |
d45b9b8a | 666 | static char *cmd_to_str(int cmd) |
b1b81f1d ST |
667 | { |
668 | switch (cmd) { | |
669 | case CX2341X_ENC_PING_FW: | |
670 | return "PING_FW"; | |
671 | case CX2341X_ENC_START_CAPTURE: | |
672 | return "START_CAPTURE"; | |
673 | case CX2341X_ENC_STOP_CAPTURE: | |
674 | return "STOP_CAPTURE"; | |
675 | case CX2341X_ENC_SET_AUDIO_ID: | |
676 | return "SET_AUDIO_ID"; | |
677 | case CX2341X_ENC_SET_VIDEO_ID: | |
678 | return "SET_VIDEO_ID"; | |
679 | case CX2341X_ENC_SET_PCR_ID: | |
26ee91ef | 680 | return "SET_PCR_ID"; |
b1b81f1d ST |
681 | case CX2341X_ENC_SET_FRAME_RATE: |
682 | return "SET_FRAME_RATE"; | |
683 | case CX2341X_ENC_SET_FRAME_SIZE: | |
684 | return "SET_FRAME_SIZE"; | |
685 | case CX2341X_ENC_SET_BIT_RATE: | |
686 | return "SET_BIT_RATE"; | |
687 | case CX2341X_ENC_SET_GOP_PROPERTIES: | |
688 | return "SET_GOP_PROPERTIES"; | |
689 | case CX2341X_ENC_SET_ASPECT_RATIO: | |
690 | return "SET_ASPECT_RATIO"; | |
691 | case CX2341X_ENC_SET_DNR_FILTER_MODE: | |
26ee91ef | 692 | return "SET_DNR_FILTER_MODE"; |
b1b81f1d ST |
693 | case CX2341X_ENC_SET_DNR_FILTER_PROPS: |
694 | return "SET_DNR_FILTER_PROPS"; | |
695 | case CX2341X_ENC_SET_CORING_LEVELS: | |
696 | return "SET_CORING_LEVELS"; | |
697 | case CX2341X_ENC_SET_SPATIAL_FILTER_TYPE: | |
698 | return "SET_SPATIAL_FILTER_TYPE"; | |
699 | case CX2341X_ENC_SET_VBI_LINE: | |
700 | return "SET_VBI_LINE"; | |
701 | case CX2341X_ENC_SET_STREAM_TYPE: | |
702 | return "SET_STREAM_TYPE"; | |
703 | case CX2341X_ENC_SET_OUTPUT_PORT: | |
704 | return "SET_OUTPUT_PORT"; | |
705 | case CX2341X_ENC_SET_AUDIO_PROPERTIES: | |
706 | return "SET_AUDIO_PROPERTIES"; | |
707 | case CX2341X_ENC_HALT_FW: | |
708 | return "HALT_FW"; | |
709 | case CX2341X_ENC_GET_VERSION: | |
710 | return "GET_VERSION"; | |
711 | case CX2341X_ENC_SET_GOP_CLOSURE: | |
712 | return "SET_GOP_CLOSURE"; | |
713 | case CX2341X_ENC_GET_SEQ_END: | |
714 | return "GET_SEQ_END"; | |
715 | case CX2341X_ENC_SET_PGM_INDEX_INFO: | |
716 | return "SET_PGM_INDEX_INFO"; | |
717 | case CX2341X_ENC_SET_VBI_CONFIG: | |
718 | return "SET_VBI_CONFIG"; | |
719 | case CX2341X_ENC_SET_DMA_BLOCK_SIZE: | |
720 | return "SET_DMA_BLOCK_SIZE"; | |
721 | case CX2341X_ENC_GET_PREV_DMA_INFO_MB_10: | |
722 | return "GET_PREV_DMA_INFO_MB_10"; | |
723 | case CX2341X_ENC_GET_PREV_DMA_INFO_MB_9: | |
724 | return "GET_PREV_DMA_INFO_MB_9"; | |
725 | case CX2341X_ENC_SCHED_DMA_TO_HOST: | |
726 | return "SCHED_DMA_TO_HOST"; | |
727 | case CX2341X_ENC_INITIALIZE_INPUT: | |
728 | return "INITIALIZE_INPUT"; | |
729 | case CX2341X_ENC_SET_FRAME_DROP_RATE: | |
730 | return "SET_FRAME_DROP_RATE"; | |
731 | case CX2341X_ENC_PAUSE_ENCODER: | |
732 | return "PAUSE_ENCODER"; | |
733 | case CX2341X_ENC_REFRESH_INPUT: | |
734 | return "REFRESH_INPUT"; | |
735 | case CX2341X_ENC_SET_COPYRIGHT: | |
736 | return "SET_COPYRIGHT"; | |
737 | case CX2341X_ENC_SET_EVENT_NOTIFICATION: | |
738 | return "SET_EVENT_NOTIFICATION"; | |
739 | case CX2341X_ENC_SET_NUM_VSYNC_LINES: | |
740 | return "SET_NUM_VSYNC_LINES"; | |
741 | case CX2341X_ENC_SET_PLACEHOLDER: | |
742 | return "SET_PLACEHOLDER"; | |
743 | case CX2341X_ENC_MUTE_VIDEO: | |
744 | return "MUTE_VIDEO"; | |
745 | case CX2341X_ENC_MUTE_AUDIO: | |
746 | return "MUTE_AUDIO"; | |
747 | case CX2341X_ENC_MISC: | |
748 | return "MISC"; | |
749 | default: | |
750 | return "UNKNOWN"; | |
751 | } | |
752 | } | |
753 | ||
754 | static int cx23885_mbox_func(void *priv, | |
755 | u32 command, | |
756 | int in, | |
757 | int out, | |
758 | u32 data[CX2341X_MBOX_MAX_DATA]) | |
759 | { | |
760 | struct cx23885_dev *dev = priv; | |
761 | unsigned long timeout; | |
762 | u32 value, flag, retval = 0; | |
763 | int i; | |
764 | ||
765 | dprintk(3, "%s: command(0x%X) = %s\n", __func__, command, | |
766 | cmd_to_str(command)); | |
767 | ||
768 | /* this may not be 100% safe if we can't read any memory location | |
769 | without side effects */ | |
770 | mc417_memory_read(dev, dev->cx23417_mailbox - 4, &value); | |
771 | if (value != 0x12345678) { | |
772 | printk(KERN_ERR | |
773 | "Firmware and/or mailbox pointer not initialized " | |
774 | "or corrupted, signature = 0x%x, cmd = %s\n", value, | |
775 | cmd_to_str(command)); | |
776 | return -1; | |
777 | } | |
778 | ||
779 | /* This read looks at 32 bits, but flag is only 8 bits. | |
780 | * Seems we also bail if CMD or TIMEOUT bytes are set??? | |
781 | */ | |
782 | mc417_memory_read(dev, dev->cx23417_mailbox, &flag); | |
783 | if (flag) { | |
784 | printk(KERN_ERR "ERROR: Mailbox appears to be in use " | |
785 | "(%x), cmd = %s\n", flag, cmd_to_str(command)); | |
786 | return -1; | |
787 | } | |
788 | ||
789 | flag |= 1; /* tell 'em we're working on it */ | |
790 | mc417_memory_write(dev, dev->cx23417_mailbox, flag); | |
791 | ||
792 | /* write command + args + fill remaining with zeros */ | |
793 | /* command code */ | |
794 | mc417_memory_write(dev, dev->cx23417_mailbox + 1, command); | |
795 | mc417_memory_write(dev, dev->cx23417_mailbox + 3, | |
796 | IVTV_API_STD_TIMEOUT); /* timeout */ | |
797 | for (i = 0; i < in; i++) { | |
798 | mc417_memory_write(dev, dev->cx23417_mailbox + 4 + i, data[i]); | |
799 | dprintk(3, "API Input %d = %d\n", i, data[i]); | |
800 | } | |
801 | for (; i < CX2341X_MBOX_MAX_DATA; i++) | |
802 | mc417_memory_write(dev, dev->cx23417_mailbox + 4 + i, 0); | |
803 | ||
804 | flag |= 3; /* tell 'em we're done writing */ | |
805 | mc417_memory_write(dev, dev->cx23417_mailbox, flag); | |
806 | ||
807 | /* wait for firmware to handle the API command */ | |
808 | timeout = jiffies + msecs_to_jiffies(10); | |
809 | for (;;) { | |
810 | mc417_memory_read(dev, dev->cx23417_mailbox, &flag); | |
811 | if (0 != (flag & 4)) | |
812 | break; | |
813 | if (time_after(jiffies, timeout)) { | |
814 | printk(KERN_ERR "ERROR: API Mailbox timeout\n"); | |
815 | return -1; | |
816 | } | |
817 | udelay(10); | |
818 | } | |
819 | ||
820 | /* read output values */ | |
821 | for (i = 0; i < out; i++) { | |
822 | mc417_memory_read(dev, dev->cx23417_mailbox + 4 + i, data + i); | |
823 | dprintk(3, "API Output %d = %d\n", i, data[i]); | |
824 | } | |
825 | ||
826 | mc417_memory_read(dev, dev->cx23417_mailbox + 2, &retval); | |
827 | dprintk(3, "API result = %d\n", retval); | |
828 | ||
829 | flag = 0; | |
830 | mc417_memory_write(dev, dev->cx23417_mailbox, flag); | |
831 | ||
832 | return retval; | |
833 | } | |
834 | ||
835 | /* We don't need to call the API often, so using just one | |
836 | * mailbox will probably suffice | |
837 | */ | |
838 | static int cx23885_api_cmd(struct cx23885_dev *dev, | |
839 | u32 command, | |
840 | u32 inputcnt, | |
841 | u32 outputcnt, | |
842 | ...) | |
843 | { | |
844 | u32 data[CX2341X_MBOX_MAX_DATA]; | |
845 | va_list vargs; | |
846 | int i, err; | |
847 | ||
848 | dprintk(3, "%s() cmds = 0x%08x\n", __func__, command); | |
849 | ||
850 | va_start(vargs, outputcnt); | |
851 | for (i = 0; i < inputcnt; i++) | |
852 | data[i] = va_arg(vargs, int); | |
853 | ||
854 | err = cx23885_mbox_func(dev, command, inputcnt, outputcnt, data); | |
855 | for (i = 0; i < outputcnt; i++) { | |
856 | int *vptr = va_arg(vargs, int *); | |
857 | *vptr = data[i]; | |
858 | } | |
859 | va_end(vargs); | |
860 | ||
861 | return err; | |
862 | } | |
863 | ||
5150392c HV |
864 | static int cx23885_api_func(void *priv, u32 cmd, int in, int out, u32 data[CX2341X_MBOX_MAX_DATA]) |
865 | { | |
866 | return cx23885_mbox_func(priv, cmd, in, out, data); | |
867 | } | |
868 | ||
b1b81f1d ST |
869 | static int cx23885_find_mailbox(struct cx23885_dev *dev) |
870 | { | |
871 | u32 signature[4] = { | |
872 | 0x12345678, 0x34567812, 0x56781234, 0x78123456 | |
873 | }; | |
874 | int signaturecnt = 0; | |
875 | u32 value; | |
876 | int i; | |
877 | ||
878 | dprintk(2, "%s()\n", __func__); | |
879 | ||
880 | for (i = 0; i < CX23885_FIRM_IMAGE_SIZE; i++) { | |
881 | mc417_memory_read(dev, i, &value); | |
882 | if (value == signature[signaturecnt]) | |
883 | signaturecnt++; | |
884 | else | |
885 | signaturecnt = 0; | |
886 | if (4 == signaturecnt) { | |
887 | dprintk(1, "Mailbox signature found at 0x%x\n", i+1); | |
888 | return i+1; | |
889 | } | |
890 | } | |
891 | printk(KERN_ERR "Mailbox signature values not found!\n"); | |
892 | return -1; | |
893 | } | |
894 | ||
895 | static int cx23885_load_firmware(struct cx23885_dev *dev) | |
896 | { | |
897 | static const unsigned char magic[8] = { | |
898 | 0xa7, 0x0d, 0x00, 0x00, 0x66, 0xbb, 0x55, 0xaa | |
899 | }; | |
900 | const struct firmware *firmware; | |
901 | int i, retval = 0; | |
902 | u32 value = 0; | |
903 | u32 gpio_output = 0; | |
182d29f3 | 904 | u32 gpio_value; |
b1b81f1d ST |
905 | u32 checksum = 0; |
906 | u32 *dataptr; | |
907 | ||
908 | dprintk(2, "%s()\n", __func__); | |
909 | ||
910 | /* Save GPIO settings before reset of APU */ | |
911 | retval |= mc417_memory_read(dev, 0x9020, &gpio_output); | |
182d29f3 | 912 | retval |= mc417_memory_read(dev, 0x900C, &gpio_value); |
b1b81f1d ST |
913 | |
914 | retval = mc417_register_write(dev, | |
915 | IVTV_REG_VPU, 0xFFFFFFED); | |
916 | retval |= mc417_register_write(dev, | |
917 | IVTV_REG_HW_BLOCKS, IVTV_CMD_HW_BLOCKS_RST); | |
918 | retval |= mc417_register_write(dev, | |
919 | IVTV_REG_ENC_SDRAM_REFRESH, 0x80000800); | |
920 | retval |= mc417_register_write(dev, | |
921 | IVTV_REG_ENC_SDRAM_PRECHARGE, 0x1A); | |
922 | retval |= mc417_register_write(dev, | |
923 | IVTV_REG_APU, 0); | |
924 | ||
925 | if (retval != 0) { | |
926 | printk(KERN_ERR "%s: Error with mc417_register_write\n", | |
927 | __func__); | |
928 | return -1; | |
929 | } | |
930 | ||
931 | retval = request_firmware(&firmware, CX23885_FIRM_IMAGE_NAME, | |
932 | &dev->pci->dev); | |
933 | ||
934 | if (retval != 0) { | |
935 | printk(KERN_ERR | |
936 | "ERROR: Hotplug firmware request failed (%s).\n", | |
d35ed627 | 937 | CX23885_FIRM_IMAGE_NAME); |
b1b81f1d ST |
938 | printk(KERN_ERR "Please fix your hotplug setup, the board will " |
939 | "not work without firmware loaded!\n"); | |
940 | return -1; | |
941 | } | |
942 | ||
943 | if (firmware->size != CX23885_FIRM_IMAGE_SIZE) { | |
944 | printk(KERN_ERR "ERROR: Firmware size mismatch " | |
339f06c5 | 945 | "(have %zu, expected %d)\n", |
b1b81f1d ST |
946 | firmware->size, CX23885_FIRM_IMAGE_SIZE); |
947 | release_firmware(firmware); | |
948 | return -1; | |
949 | } | |
950 | ||
951 | if (0 != memcmp(firmware->data, magic, 8)) { | |
952 | printk(KERN_ERR | |
953 | "ERROR: Firmware magic mismatch, wrong file?\n"); | |
954 | release_firmware(firmware); | |
955 | return -1; | |
956 | } | |
957 | ||
958 | /* transfer to the chip */ | |
959 | dprintk(2, "Loading firmware ...\n"); | |
960 | dataptr = (u32 *)firmware->data; | |
961 | for (i = 0; i < (firmware->size >> 2); i++) { | |
962 | value = *dataptr; | |
963 | checksum += ~value; | |
964 | if (mc417_memory_write(dev, i, value) != 0) { | |
965 | printk(KERN_ERR "ERROR: Loading firmware failed!\n"); | |
966 | release_firmware(firmware); | |
967 | return -1; | |
968 | } | |
969 | dataptr++; | |
970 | } | |
971 | ||
972 | /* read back to verify with the checksum */ | |
973 | dprintk(1, "Verifying firmware ...\n"); | |
974 | for (i--; i >= 0; i--) { | |
975 | if (mc417_memory_read(dev, i, &value) != 0) { | |
976 | printk(KERN_ERR "ERROR: Reading firmware failed!\n"); | |
977 | release_firmware(firmware); | |
978 | return -1; | |
979 | } | |
980 | checksum -= ~value; | |
981 | } | |
982 | if (checksum) { | |
983 | printk(KERN_ERR | |
984 | "ERROR: Firmware load failed (checksum mismatch).\n"); | |
985 | release_firmware(firmware); | |
986 | return -1; | |
987 | } | |
988 | release_firmware(firmware); | |
989 | dprintk(1, "Firmware upload successful.\n"); | |
990 | ||
991 | retval |= mc417_register_write(dev, IVTV_REG_HW_BLOCKS, | |
992 | IVTV_CMD_HW_BLOCKS_RST); | |
993 | ||
f659c513 ST |
994 | /* F/W power up disturbs the GPIOs, restore state */ |
995 | retval |= mc417_register_write(dev, 0x9020, gpio_output); | |
182d29f3 | 996 | retval |= mc417_register_write(dev, 0x900C, gpio_value); |
b1b81f1d ST |
997 | |
998 | retval |= mc417_register_read(dev, IVTV_REG_VPU, &value); | |
999 | retval |= mc417_register_write(dev, IVTV_REG_VPU, value & 0xFFFFFFE8); | |
1000 | ||
182d29f3 ST |
1001 | /* Hardcoded GPIO's here */ |
1002 | retval |= mc417_register_write(dev, 0x9020, 0x4000); | |
1003 | retval |= mc417_register_write(dev, 0x900C, 0x4000); | |
1004 | ||
1005 | mc417_register_read(dev, 0x9020, &gpio_output); | |
1006 | mc417_register_read(dev, 0x900C, &gpio_value); | |
1007 | ||
b1b81f1d ST |
1008 | if (retval < 0) |
1009 | printk(KERN_ERR "%s: Error with mc417_register_write\n", | |
1010 | __func__); | |
1011 | return 0; | |
1012 | } | |
1013 | ||
1014 | void cx23885_417_check_encoder(struct cx23885_dev *dev) | |
1015 | { | |
1016 | u32 status, seq; | |
1017 | ||
1018 | status = seq = 0; | |
1019 | cx23885_api_cmd(dev, CX2341X_ENC_GET_SEQ_END, 0, 2, &status, &seq); | |
1020 | dprintk(1, "%s() status = %d, seq = %d\n", __func__, status, seq); | |
1021 | } | |
1022 | ||
1023 | static void cx23885_codec_settings(struct cx23885_dev *dev) | |
1024 | { | |
1025 | dprintk(1, "%s()\n", __func__); | |
1026 | ||
38e3d7ce ST |
1027 | /* Dynamically change the height based on video standard */ |
1028 | if (dev->encodernorm.id & V4L2_STD_525_60) | |
1029 | dev->ts1.height = 480; | |
1030 | else | |
1031 | dev->ts1.height = 576; | |
1032 | ||
b1b81f1d ST |
1033 | /* assign frame size */ |
1034 | cx23885_api_cmd(dev, CX2341X_ENC_SET_FRAME_SIZE, 2, 0, | |
1035 | dev->ts1.height, dev->ts1.width); | |
1036 | ||
5150392c HV |
1037 | dev->cxhdl.width = dev->ts1.width; |
1038 | dev->cxhdl.height = dev->ts1.height; | |
1039 | dev->cxhdl.is_50hz = | |
b1b81f1d ST |
1040 | (dev->encodernorm.id & V4L2_STD_625_50) != 0; |
1041 | ||
5150392c | 1042 | cx2341x_handler_setup(&dev->cxhdl); |
b1b81f1d ST |
1043 | |
1044 | cx23885_api_cmd(dev, CX2341X_ENC_MISC, 2, 0, 3, 1); | |
1045 | cx23885_api_cmd(dev, CX2341X_ENC_MISC, 2, 0, 4, 1); | |
1046 | } | |
1047 | ||
9c9c3d07 | 1048 | static int cx23885_initialize_codec(struct cx23885_dev *dev, int startencoder) |
b1b81f1d ST |
1049 | { |
1050 | int version; | |
1051 | int retval; | |
1052 | u32 i, data[7]; | |
1053 | ||
1054 | dprintk(1, "%s()\n", __func__); | |
1055 | ||
1056 | retval = cx23885_api_cmd(dev, CX2341X_ENC_PING_FW, 0, 0); /* ping */ | |
1057 | if (retval < 0) { | |
1058 | dprintk(2, "%s() PING OK\n", __func__); | |
1059 | retval = cx23885_load_firmware(dev); | |
1060 | if (retval < 0) { | |
1061 | printk(KERN_ERR "%s() f/w load failed\n", __func__); | |
1062 | return retval; | |
1063 | } | |
f347535a | 1064 | retval = cx23885_find_mailbox(dev); |
1065 | if (retval < 0) { | |
b1b81f1d ST |
1066 | printk(KERN_ERR "%s() mailbox < 0, error\n", |
1067 | __func__); | |
1068 | return -1; | |
1069 | } | |
f347535a | 1070 | dev->cx23417_mailbox = retval; |
b1b81f1d ST |
1071 | retval = cx23885_api_cmd(dev, CX2341X_ENC_PING_FW, 0, 0); |
1072 | if (retval < 0) { | |
1073 | printk(KERN_ERR | |
1074 | "ERROR: cx23417 firmware ping failed!\n"); | |
1075 | return -1; | |
1076 | } | |
1077 | retval = cx23885_api_cmd(dev, CX2341X_ENC_GET_VERSION, 0, 1, | |
1078 | &version); | |
1079 | if (retval < 0) { | |
1080 | printk(KERN_ERR "ERROR: cx23417 firmware get encoder :" | |
1081 | "version failed!\n"); | |
1082 | return -1; | |
1083 | } | |
1084 | dprintk(1, "cx23417 firmware version is 0x%08x\n", version); | |
1085 | msleep(200); | |
1086 | } | |
1087 | ||
1088 | cx23885_codec_settings(dev); | |
1089 | msleep(60); | |
1090 | ||
1091 | cx23885_api_cmd(dev, CX2341X_ENC_SET_NUM_VSYNC_LINES, 2, 0, | |
1092 | CX23885_FIELD1_SAA7115, CX23885_FIELD2_SAA7115); | |
1093 | cx23885_api_cmd(dev, CX2341X_ENC_SET_PLACEHOLDER, 12, 0, | |
1094 | CX23885_CUSTOM_EXTENSION_USR_DATA, 0, 0, 0, 0, 0, 0, 0, 0, 0, | |
1095 | 0, 0); | |
1096 | ||
1097 | /* Setup to capture VBI */ | |
1098 | data[0] = 0x0001BD00; | |
1099 | data[1] = 1; /* frames per interrupt */ | |
1100 | data[2] = 4; /* total bufs */ | |
1101 | data[3] = 0x91559155; /* start codes */ | |
1102 | data[4] = 0x206080C0; /* stop codes */ | |
1103 | data[5] = 6; /* lines */ | |
1104 | data[6] = 64; /* BPL */ | |
1105 | ||
1106 | cx23885_api_cmd(dev, CX2341X_ENC_SET_VBI_CONFIG, 7, 0, data[0], data[1], | |
1107 | data[2], data[3], data[4], data[5], data[6]); | |
1108 | ||
1109 | for (i = 2; i <= 24; i++) { | |
1110 | int valid; | |
1111 | ||
1112 | valid = ((i >= 19) && (i <= 21)); | |
1113 | cx23885_api_cmd(dev, CX2341X_ENC_SET_VBI_LINE, 5, 0, i, | |
1114 | valid, 0 , 0, 0); | |
1115 | cx23885_api_cmd(dev, CX2341X_ENC_SET_VBI_LINE, 5, 0, | |
1116 | i | 0x80000000, valid, 0, 0, 0); | |
1117 | } | |
1118 | ||
1119 | cx23885_api_cmd(dev, CX2341X_ENC_MUTE_AUDIO, 1, 0, CX23885_UNMUTE); | |
1120 | msleep(60); | |
1121 | ||
1122 | /* initialize the video input */ | |
1123 | cx23885_api_cmd(dev, CX2341X_ENC_INITIALIZE_INPUT, 0, 0); | |
1124 | msleep(60); | |
1125 | ||
1126 | /* Enable VIP style pixel invalidation so we work with scaled mode */ | |
1127 | mc417_memory_write(dev, 2120, 0x00000080); | |
1128 | ||
1129 | /* start capturing to the host interface */ | |
9c9c3d07 ST |
1130 | if (startencoder) { |
1131 | cx23885_api_cmd(dev, CX2341X_ENC_START_CAPTURE, 2, 0, | |
1132 | CX23885_MPEG_CAPTURE, CX23885_RAW_BITS_NONE); | |
1133 | msleep(10); | |
1134 | } | |
b1b81f1d ST |
1135 | |
1136 | return 0; | |
1137 | } | |
1138 | ||
1139 | /* ------------------------------------------------------------------ */ | |
1140 | ||
df9ecb0c | 1141 | static int queue_setup(struct vb2_queue *q, |
453afdd9 | 1142 | unsigned int *num_buffers, unsigned int *num_planes, |
36c0f8b3 | 1143 | unsigned int sizes[], struct device *alloc_devs[]) |
b1b81f1d | 1144 | { |
453afdd9 | 1145 | struct cx23885_dev *dev = q->drv_priv; |
b1b81f1d | 1146 | |
453afdd9 HV |
1147 | dev->ts1.ts_packet_size = mpeglinesize; |
1148 | dev->ts1.ts_packet_count = mpeglines; | |
1149 | *num_planes = 1; | |
1150 | sizes[0] = mpeglinesize * mpeglines; | |
1151 | *num_buffers = mpegbufs; | |
1152 | return 0; | |
1153 | } | |
b1b81f1d | 1154 | |
453afdd9 HV |
1155 | static int buffer_prepare(struct vb2_buffer *vb) |
1156 | { | |
2d700715 | 1157 | struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); |
453afdd9 HV |
1158 | struct cx23885_dev *dev = vb->vb2_queue->drv_priv; |
1159 | struct cx23885_buffer *buf = | |
2d700715 | 1160 | container_of(vbuf, struct cx23885_buffer, vb); |
b1b81f1d | 1161 | |
453afdd9 | 1162 | return cx23885_buf_prepare(buf, &dev->ts1); |
b1b81f1d ST |
1163 | } |
1164 | ||
453afdd9 | 1165 | static void buffer_finish(struct vb2_buffer *vb) |
b1b81f1d | 1166 | { |
2d700715 | 1167 | struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); |
453afdd9 | 1168 | struct cx23885_dev *dev = vb->vb2_queue->drv_priv; |
2d700715 | 1169 | struct cx23885_buffer *buf = container_of(vbuf, |
453afdd9 | 1170 | struct cx23885_buffer, vb); |
453afdd9 HV |
1171 | |
1172 | cx23885_free_buffer(dev, buf); | |
b1b81f1d ST |
1173 | } |
1174 | ||
453afdd9 | 1175 | static void buffer_queue(struct vb2_buffer *vb) |
b1b81f1d | 1176 | { |
2d700715 | 1177 | struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); |
453afdd9 | 1178 | struct cx23885_dev *dev = vb->vb2_queue->drv_priv; |
2d700715 | 1179 | struct cx23885_buffer *buf = container_of(vbuf, |
453afdd9 HV |
1180 | struct cx23885_buffer, vb); |
1181 | ||
1182 | cx23885_buf_queue(&dev->ts1, buf); | |
1183 | } | |
1184 | ||
1185 | static int cx23885_start_streaming(struct vb2_queue *q, unsigned int count) | |
1186 | { | |
1187 | struct cx23885_dev *dev = q->drv_priv; | |
1188 | struct cx23885_dmaqueue *dmaq = &dev->ts1.mpegq; | |
1189 | unsigned long flags; | |
1190 | int ret; | |
1191 | ||
1192 | ret = cx23885_initialize_codec(dev, 1); | |
1193 | if (ret == 0) { | |
1194 | struct cx23885_buffer *buf = list_entry(dmaq->active.next, | |
1195 | struct cx23885_buffer, queue); | |
1196 | ||
1197 | cx23885_start_dma(&dev->ts1, dmaq, buf); | |
1198 | return 0; | |
1199 | } | |
1200 | spin_lock_irqsave(&dev->slock, flags); | |
1201 | while (!list_empty(&dmaq->active)) { | |
1202 | struct cx23885_buffer *buf = list_entry(dmaq->active.next, | |
1203 | struct cx23885_buffer, queue); | |
1204 | ||
1205 | list_del(&buf->queue); | |
2d700715 | 1206 | vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_QUEUED); |
453afdd9 HV |
1207 | } |
1208 | spin_unlock_irqrestore(&dev->slock, flags); | |
1209 | return ret; | |
b1b81f1d ST |
1210 | } |
1211 | ||
453afdd9 | 1212 | static void cx23885_stop_streaming(struct vb2_queue *q) |
b1b81f1d | 1213 | { |
453afdd9 HV |
1214 | struct cx23885_dev *dev = q->drv_priv; |
1215 | ||
1216 | /* stop mpeg capture */ | |
1217 | cx23885_api_cmd(dev, CX2341X_ENC_STOP_CAPTURE, 3, 0, | |
1218 | CX23885_END_NOW, CX23885_MPEG_CAPTURE, | |
1219 | CX23885_RAW_BITS_NONE); | |
1220 | ||
1221 | msleep(500); | |
1222 | cx23885_417_check_encoder(dev); | |
1223 | cx23885_cancel_buffers(&dev->ts1); | |
b1b81f1d ST |
1224 | } |
1225 | ||
453afdd9 HV |
1226 | static struct vb2_ops cx23885_qops = { |
1227 | .queue_setup = queue_setup, | |
1228 | .buf_prepare = buffer_prepare, | |
1229 | .buf_finish = buffer_finish, | |
1230 | .buf_queue = buffer_queue, | |
1231 | .wait_prepare = vb2_ops_wait_prepare, | |
1232 | .wait_finish = vb2_ops_wait_finish, | |
1233 | .start_streaming = cx23885_start_streaming, | |
1234 | .stop_streaming = cx23885_stop_streaming, | |
b1b81f1d ST |
1235 | }; |
1236 | ||
1237 | /* ------------------------------------------------------------------ */ | |
1238 | ||
09b3bc22 ST |
1239 | static int vidioc_g_std(struct file *file, void *priv, v4l2_std_id *id) |
1240 | { | |
568f44a1 | 1241 | struct cx23885_dev *dev = video_drvdata(file); |
09b3bc22 | 1242 | |
9c1f5df8 | 1243 | *id = dev->tvnorm; |
09b3bc22 ST |
1244 | return 0; |
1245 | } | |
1246 | ||
314527ac | 1247 | static int vidioc_s_std(struct file *file, void *priv, v4l2_std_id id) |
b1b81f1d | 1248 | { |
568f44a1 | 1249 | struct cx23885_dev *dev = video_drvdata(file); |
305519c9 | 1250 | unsigned int i; |
f1b6a735 | 1251 | int ret; |
b1b81f1d | 1252 | |
305519c9 | 1253 | for (i = 0; i < ARRAY_SIZE(cx23885_tvnorms); i++) |
314527ac | 1254 | if (id & cx23885_tvnorms[i].id) |
305519c9 DSL |
1255 | break; |
1256 | if (i == ARRAY_SIZE(cx23885_tvnorms)) | |
1257 | return -EINVAL; | |
09b3bc22 | 1258 | |
f1b6a735 HV |
1259 | ret = cx23885_set_tvnorm(dev, id); |
1260 | if (!ret) | |
1261 | dev->encodernorm = cx23885_tvnorms[i]; | |
1262 | return ret; | |
305519c9 | 1263 | } |
b1b81f1d | 1264 | |
305519c9 | 1265 | static int vidioc_enum_input(struct file *file, void *priv, |
09b3bc22 | 1266 | struct v4l2_input *i) |
305519c9 | 1267 | { |
568f44a1 | 1268 | struct cx23885_dev *dev = video_drvdata(file); |
09b3bc22 ST |
1269 | dprintk(1, "%s()\n", __func__); |
1270 | return cx23885_enum_input(dev, i); | |
305519c9 | 1271 | } |
b1b81f1d | 1272 | |
305519c9 DSL |
1273 | static int vidioc_g_input(struct file *file, void *priv, unsigned int *i) |
1274 | { | |
09b3bc22 | 1275 | return cx23885_get_input(file, priv, i); |
305519c9 | 1276 | } |
b1b81f1d | 1277 | |
305519c9 DSL |
1278 | static int vidioc_s_input(struct file *file, void *priv, unsigned int i) |
1279 | { | |
09b3bc22 | 1280 | return cx23885_set_input(file, priv, i); |
305519c9 | 1281 | } |
b1b81f1d | 1282 | |
305519c9 DSL |
1283 | static int vidioc_g_tuner(struct file *file, void *priv, |
1284 | struct v4l2_tuner *t) | |
1285 | { | |
568f44a1 | 1286 | struct cx23885_dev *dev = video_drvdata(file); |
b1b81f1d | 1287 | |
0f3bf3dc | 1288 | if (dev->tuner_type == TUNER_ABSENT) |
305519c9 DSL |
1289 | return -EINVAL; |
1290 | if (0 != t->index) | |
1291 | return -EINVAL; | |
305519c9 | 1292 | strcpy(t->name, "Television"); |
0d5a19f1 | 1293 | call_all(dev, tuner, g_tuner, t); |
b1b81f1d | 1294 | |
305519c9 | 1295 | dprintk(1, "VIDIOC_G_TUNER: tuner type %d\n", t->type); |
b1b81f1d | 1296 | |
305519c9 DSL |
1297 | return 0; |
1298 | } | |
b1b81f1d | 1299 | |
305519c9 | 1300 | static int vidioc_s_tuner(struct file *file, void *priv, |
2f73c7c5 | 1301 | const struct v4l2_tuner *t) |
305519c9 | 1302 | { |
568f44a1 | 1303 | struct cx23885_dev *dev = video_drvdata(file); |
305519c9 | 1304 | |
0f3bf3dc | 1305 | if (dev->tuner_type == TUNER_ABSENT) |
305519c9 DSL |
1306 | return -EINVAL; |
1307 | ||
1308 | /* Update the A/V core */ | |
0d5a19f1 | 1309 | call_all(dev, tuner, s_tuner, t); |
305519c9 DSL |
1310 | |
1311 | return 0; | |
1312 | } | |
1313 | ||
1314 | static int vidioc_g_frequency(struct file *file, void *priv, | |
1315 | struct v4l2_frequency *f) | |
1316 | { | |
568f44a1 | 1317 | struct cx23885_dev *dev = video_drvdata(file); |
305519c9 | 1318 | |
0f3bf3dc | 1319 | if (dev->tuner_type == TUNER_ABSENT) |
305519c9 DSL |
1320 | return -EINVAL; |
1321 | f->type = V4L2_TUNER_ANALOG_TV; | |
1322 | f->frequency = dev->freq; | |
1323 | ||
0d5a19f1 | 1324 | call_all(dev, tuner, g_frequency, f); |
305519c9 DSL |
1325 | |
1326 | return 0; | |
1327 | } | |
1328 | ||
1329 | static int vidioc_s_frequency(struct file *file, void *priv, | |
b530a447 | 1330 | const struct v4l2_frequency *f) |
305519c9 | 1331 | { |
09b3bc22 ST |
1332 | return cx23885_set_frequency(file, priv, f); |
1333 | } | |
305519c9 | 1334 | |
305519c9 DSL |
1335 | static int vidioc_querycap(struct file *file, void *priv, |
1336 | struct v4l2_capability *cap) | |
b1b81f1d | 1337 | { |
568f44a1 | 1338 | struct cx23885_dev *dev = video_drvdata(file); |
b1b81f1d ST |
1339 | struct cx23885_tsport *tsport = &dev->ts1; |
1340 | ||
b084307c | 1341 | strlcpy(cap->driver, dev->name, sizeof(cap->driver)); |
305519c9 DSL |
1342 | strlcpy(cap->card, cx23885_boards[tsport->dev->board].name, |
1343 | sizeof(cap->card)); | |
6b46211f HV |
1344 | sprintf(cap->bus_info, "PCIe:%s", pci_name(dev->pci)); |
1345 | cap->device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_READWRITE | | |
1346 | V4L2_CAP_STREAMING; | |
0f3bf3dc | 1347 | if (dev->tuner_type != TUNER_ABSENT) |
6b46211f HV |
1348 | cap->device_caps |= V4L2_CAP_TUNER; |
1349 | cap->capabilities = cap->device_caps | V4L2_CAP_VBI_CAPTURE | | |
1350 | V4L2_CAP_AUDIO | V4L2_CAP_DEVICE_CAPS; | |
b1b81f1d | 1351 | |
305519c9 DSL |
1352 | return 0; |
1353 | } | |
b1b81f1d | 1354 | |
305519c9 DSL |
1355 | static int vidioc_enum_fmt_vid_cap(struct file *file, void *priv, |
1356 | struct v4l2_fmtdesc *f) | |
1357 | { | |
f29816bc | 1358 | if (f->index != 0) |
305519c9 | 1359 | return -EINVAL; |
b1b81f1d | 1360 | |
305519c9 | 1361 | strlcpy(f->description, "MPEG", sizeof(f->description)); |
305519c9 | 1362 | f->pixelformat = V4L2_PIX_FMT_MPEG; |
b1b81f1d | 1363 | |
305519c9 DSL |
1364 | return 0; |
1365 | } | |
b1b81f1d | 1366 | |
305519c9 DSL |
1367 | static int vidioc_g_fmt_vid_cap(struct file *file, void *priv, |
1368 | struct v4l2_format *f) | |
1369 | { | |
568f44a1 | 1370 | struct cx23885_dev *dev = video_drvdata(file); |
b1b81f1d | 1371 | |
305519c9 DSL |
1372 | f->fmt.pix.pixelformat = V4L2_PIX_FMT_MPEG; |
1373 | f->fmt.pix.bytesperline = 0; | |
1374 | f->fmt.pix.sizeimage = | |
1375 | dev->ts1.ts_packet_size * dev->ts1.ts_packet_count; | |
1376 | f->fmt.pix.colorspace = 0; | |
1377 | f->fmt.pix.width = dev->ts1.width; | |
1378 | f->fmt.pix.height = dev->ts1.height; | |
453afdd9 HV |
1379 | f->fmt.pix.field = V4L2_FIELD_INTERLACED; |
1380 | dprintk(1, "VIDIOC_G_FMT: w: %d, h: %d\n", | |
1381 | dev->ts1.width, dev->ts1.height); | |
305519c9 DSL |
1382 | return 0; |
1383 | } | |
b1b81f1d | 1384 | |
305519c9 DSL |
1385 | static int vidioc_try_fmt_vid_cap(struct file *file, void *priv, |
1386 | struct v4l2_format *f) | |
1387 | { | |
568f44a1 | 1388 | struct cx23885_dev *dev = video_drvdata(file); |
b1b81f1d | 1389 | |
305519c9 DSL |
1390 | f->fmt.pix.pixelformat = V4L2_PIX_FMT_MPEG; |
1391 | f->fmt.pix.bytesperline = 0; | |
1392 | f->fmt.pix.sizeimage = | |
1393 | dev->ts1.ts_packet_size * dev->ts1.ts_packet_count; | |
305519c9 | 1394 | f->fmt.pix.colorspace = 0; |
453afdd9 HV |
1395 | f->fmt.pix.field = V4L2_FIELD_INTERLACED; |
1396 | dprintk(1, "VIDIOC_TRY_FMT: w: %d, h: %d\n", | |
1397 | dev->ts1.width, dev->ts1.height); | |
305519c9 DSL |
1398 | return 0; |
1399 | } | |
b1b81f1d | 1400 | |
305519c9 DSL |
1401 | static int vidioc_s_fmt_vid_cap(struct file *file, void *priv, |
1402 | struct v4l2_format *f) | |
1403 | { | |
568f44a1 | 1404 | struct cx23885_dev *dev = video_drvdata(file); |
b1b81f1d | 1405 | |
305519c9 DSL |
1406 | f->fmt.pix.pixelformat = V4L2_PIX_FMT_MPEG; |
1407 | f->fmt.pix.bytesperline = 0; | |
1408 | f->fmt.pix.sizeimage = | |
1409 | dev->ts1.ts_packet_size * dev->ts1.ts_packet_count; | |
1410 | f->fmt.pix.colorspace = 0; | |
453afdd9 | 1411 | f->fmt.pix.field = V4L2_FIELD_INTERLACED; |
305519c9 DSL |
1412 | dprintk(1, "VIDIOC_S_FMT: w: %d, h: %d, f: %d\n", |
1413 | f->fmt.pix.width, f->fmt.pix.height, f->fmt.pix.field); | |
1414 | return 0; | |
1415 | } | |
b1b81f1d | 1416 | |
305519c9 DSL |
1417 | static int vidioc_log_status(struct file *file, void *priv) |
1418 | { | |
568f44a1 | 1419 | struct cx23885_dev *dev = video_drvdata(file); |
305519c9 DSL |
1420 | char name[32 + 2]; |
1421 | ||
1422 | snprintf(name, sizeof(name), "%s/2", dev->name); | |
0d5a19f1 | 1423 | call_all(dev, core, log_status); |
5150392c | 1424 | v4l2_ctrl_handler_log_status(&dev->cxhdl.hdl, name); |
b1b81f1d ST |
1425 | return 0; |
1426 | } | |
1427 | ||
bec43661 | 1428 | static struct v4l2_file_operations mpeg_fops = { |
b1b81f1d | 1429 | .owner = THIS_MODULE, |
453afdd9 HV |
1430 | .open = v4l2_fh_open, |
1431 | .release = vb2_fop_release, | |
1432 | .read = vb2_fop_read, | |
1433 | .poll = vb2_fop_poll, | |
24a8f7b5 | 1434 | .unlocked_ioctl = video_ioctl2, |
453afdd9 | 1435 | .mmap = vb2_fop_mmap, |
b1b81f1d ST |
1436 | }; |
1437 | ||
a399810c | 1438 | static const struct v4l2_ioctl_ops mpeg_ioctl_ops = { |
09b3bc22 | 1439 | .vidioc_g_std = vidioc_g_std, |
305519c9 DSL |
1440 | .vidioc_s_std = vidioc_s_std, |
1441 | .vidioc_enum_input = vidioc_enum_input, | |
1442 | .vidioc_g_input = vidioc_g_input, | |
1443 | .vidioc_s_input = vidioc_s_input, | |
1444 | .vidioc_g_tuner = vidioc_g_tuner, | |
1445 | .vidioc_s_tuner = vidioc_s_tuner, | |
1446 | .vidioc_g_frequency = vidioc_g_frequency, | |
1447 | .vidioc_s_frequency = vidioc_s_frequency, | |
305519c9 DSL |
1448 | .vidioc_querycap = vidioc_querycap, |
1449 | .vidioc_enum_fmt_vid_cap = vidioc_enum_fmt_vid_cap, | |
1450 | .vidioc_g_fmt_vid_cap = vidioc_g_fmt_vid_cap, | |
1451 | .vidioc_try_fmt_vid_cap = vidioc_try_fmt_vid_cap, | |
1452 | .vidioc_s_fmt_vid_cap = vidioc_s_fmt_vid_cap, | |
453afdd9 HV |
1453 | .vidioc_reqbufs = vb2_ioctl_reqbufs, |
1454 | .vidioc_prepare_buf = vb2_ioctl_prepare_buf, | |
1455 | .vidioc_querybuf = vb2_ioctl_querybuf, | |
1456 | .vidioc_qbuf = vb2_ioctl_qbuf, | |
1457 | .vidioc_dqbuf = vb2_ioctl_dqbuf, | |
1458 | .vidioc_streamon = vb2_ioctl_streamon, | |
1459 | .vidioc_streamoff = vb2_ioctl_streamoff, | |
305519c9 | 1460 | .vidioc_log_status = vidioc_log_status, |
74618244 | 1461 | #ifdef CONFIG_VIDEO_ADV_DEBUG |
80f8568f | 1462 | .vidioc_g_chip_info = cx23885_g_chip_info, |
74618244 AW |
1463 | .vidioc_g_register = cx23885_g_register, |
1464 | .vidioc_s_register = cx23885_s_register, | |
1465 | #endif | |
b1b81f1d ST |
1466 | }; |
1467 | ||
a399810c HV |
1468 | static struct video_device cx23885_mpeg_template = { |
1469 | .name = "cx23885", | |
a399810c HV |
1470 | .fops = &mpeg_fops, |
1471 | .ioctl_ops = &mpeg_ioctl_ops, | |
6655be0f | 1472 | .tvnorms = CX23885_NORMS, |
a399810c HV |
1473 | }; |
1474 | ||
b1b81f1d ST |
1475 | void cx23885_417_unregister(struct cx23885_dev *dev) |
1476 | { | |
1477 | dprintk(1, "%s()\n", __func__); | |
1478 | ||
1479 | if (dev->v4l_device) { | |
f0813b4c | 1480 | if (video_is_registered(dev->v4l_device)) |
b1b81f1d ST |
1481 | video_unregister_device(dev->v4l_device); |
1482 | else | |
1483 | video_device_release(dev->v4l_device); | |
5150392c | 1484 | v4l2_ctrl_handler_free(&dev->cxhdl.hdl); |
b1b81f1d ST |
1485 | dev->v4l_device = NULL; |
1486 | } | |
1487 | } | |
1488 | ||
1489 | static struct video_device *cx23885_video_dev_alloc( | |
1490 | struct cx23885_tsport *tsport, | |
1491 | struct pci_dev *pci, | |
1492 | struct video_device *template, | |
1493 | char *type) | |
1494 | { | |
1495 | struct video_device *vfd; | |
1496 | struct cx23885_dev *dev = tsport->dev; | |
1497 | ||
1498 | dprintk(1, "%s()\n", __func__); | |
1499 | ||
1500 | vfd = video_device_alloc(); | |
1501 | if (NULL == vfd) | |
1502 | return NULL; | |
1503 | *vfd = *template; | |
9def5ed7 ST |
1504 | snprintf(vfd->name, sizeof(vfd->name), "%s (%s)", |
1505 | cx23885_boards[tsport->dev->board].name, type); | |
874d91db | 1506 | vfd->v4l2_dev = &dev->v4l2_dev; |
b1b81f1d ST |
1507 | vfd->release = video_device_release; |
1508 | return vfd; | |
1509 | } | |
1510 | ||
1511 | int cx23885_417_register(struct cx23885_dev *dev) | |
1512 | { | |
1513 | /* FIXME: Port1 hardcoded here */ | |
1514 | int err = -ENODEV; | |
1515 | struct cx23885_tsport *tsport = &dev->ts1; | |
453afdd9 | 1516 | struct vb2_queue *q; |
b1b81f1d ST |
1517 | |
1518 | dprintk(1, "%s()\n", __func__); | |
1519 | ||
1520 | if (cx23885_boards[dev->board].portb != CX23885_MPEG_ENCODER) | |
1521 | return err; | |
1522 | ||
1523 | /* Set default TV standard */ | |
1524 | dev->encodernorm = cx23885_tvnorms[0]; | |
1525 | ||
1526 | if (dev->encodernorm.id & V4L2_STD_525_60) | |
1527 | tsport->height = 480; | |
1528 | else | |
1529 | tsport->height = 576; | |
1530 | ||
1531 | tsport->width = 720; | |
5150392c HV |
1532 | dev->cxhdl.port = CX2341X_PORT_SERIAL; |
1533 | err = cx2341x_handler_init(&dev->cxhdl, 50); | |
1534 | if (err) | |
1535 | return err; | |
1536 | dev->cxhdl.priv = dev; | |
1537 | dev->cxhdl.func = cx23885_api_func; | |
1538 | cx2341x_handler_set_50hz(&dev->cxhdl, tsport->height == 576); | |
1539 | v4l2_ctrl_add_handler(&dev->ctrl_handler, &dev->cxhdl.hdl, NULL); | |
b1b81f1d ST |
1540 | |
1541 | /* Allocate and initialize V4L video device */ | |
1542 | dev->v4l_device = cx23885_video_dev_alloc(tsport, | |
1543 | dev->pci, &cx23885_mpeg_template, "mpeg"); | |
453afdd9 HV |
1544 | q = &dev->vb2_mpegq; |
1545 | q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; | |
1546 | q->io_modes = VB2_MMAP | VB2_USERPTR | VB2_DMABUF | VB2_READ; | |
1547 | q->gfp_flags = GFP_DMA32; | |
1548 | q->min_buffers_needed = 2; | |
1549 | q->drv_priv = dev; | |
1550 | q->buf_struct_size = sizeof(struct cx23885_buffer); | |
1551 | q->ops = &cx23885_qops; | |
1552 | q->mem_ops = &vb2_dma_sg_memops; | |
1553 | q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; | |
1554 | q->lock = &dev->lock; | |
d8feef9b | 1555 | q->dev = &dev->pci->dev; |
453afdd9 HV |
1556 | |
1557 | err = vb2_queue_init(q); | |
1558 | if (err < 0) | |
1559 | return err; | |
63b0d5ad | 1560 | video_set_drvdata(dev->v4l_device, dev); |
24a8f7b5 | 1561 | dev->v4l_device->lock = &dev->lock; |
453afdd9 | 1562 | dev->v4l_device->queue = q; |
b1b81f1d ST |
1563 | err = video_register_device(dev->v4l_device, |
1564 | VFL_TYPE_GRABBER, -1); | |
1565 | if (err < 0) { | |
1566 | printk(KERN_INFO "%s: can't register mpeg device\n", dev->name); | |
1567 | return err; | |
1568 | } | |
1569 | ||
38c7c036 LP |
1570 | printk(KERN_INFO "%s: registered device %s [mpeg]\n", |
1571 | dev->name, video_device_node_name(dev->v4l_device)); | |
b1b81f1d | 1572 | |
9c9c3d07 ST |
1573 | /* ST: Configure the encoder paramaters, but don't begin |
1574 | * encoding, this resolves an issue where the first time the | |
1575 | * encoder is started video can be choppy. | |
1576 | */ | |
1577 | cx23885_initialize_codec(dev, 0); | |
1578 | ||
b1b81f1d ST |
1579 | return 0; |
1580 | } | |
583087f5 TG |
1581 | |
1582 | MODULE_FIRMWARE(CX23885_FIRM_IMAGE_NAME); |