[mirror_ubuntu-focal-kernel.git] / drivers / media / pci / cx23885 / cx23885-vbi.c

/*
 *  Driver for the Conexant CX23885 PCIe bridge
 *
 *  Copyright (c) 2007 Steven Toth <stoth@linuxtv.org>
 *
 *  This program is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License as published by
 *  the Free Software Foundation; either version 2 of the License, or
 *  (at your option) any later version.
 *
 *  This program is distributed in the hope that it will be useful,
 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *
 *  GNU General Public License for more details.
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>

#include "cx23885.h"

static unsigned int vbibufs = 4;
module_param(vbibufs, int, 0644);
MODULE_PARM_DESC(vbibufs, "number of vbi buffers, range 2-32");

static unsigned int vbi_debug;
module_param(vbi_debug, int, 0644);
MODULE_PARM_DESC(vbi_debug, "enable debug messages [vbi]");

#define dprintk(level, fmt, arg...)\
	do { if (vbi_debug >= level)\
		printk(KERN_DEBUG "%s/0: " fmt, dev->name, ## arg);\
	} while (0)

/* ------------------------------------------------------------------ */

#define VBI_LINE_LENGTH 1440
#define VBI_NTSC_LINE_COUNT 12
#define VBI_PAL_LINE_COUNT 18


int cx23885_vbi_fmt(struct file *file, void *priv,
	struct v4l2_format *f)
{
	struct cx23885_dev *dev = video_drvdata(file);

	f->fmt.vbi.sampling_rate = 27000000;
	f->fmt.vbi.samples_per_line = VBI_LINE_LENGTH;
	f->fmt.vbi.sample_format = V4L2_PIX_FMT_GREY;
	f->fmt.vbi.offset = 0;
	f->fmt.vbi.flags = 0;
	if (dev->tvnorm & V4L2_STD_525_60) {
		/* ntsc */
		f->fmt.vbi.start[0] = V4L2_VBI_ITU_525_F1_START + 9;
		f->fmt.vbi.start[1] = V4L2_VBI_ITU_525_F2_START + 9;
		f->fmt.vbi.count[0] = VBI_NTSC_LINE_COUNT;
		f->fmt.vbi.count[1] = VBI_NTSC_LINE_COUNT;
	} else if (dev->tvnorm & V4L2_STD_625_50) {
		/* pal */
		f->fmt.vbi.start[0] = V4L2_VBI_ITU_625_F1_START + 5;
		f->fmt.vbi.start[1] = V4L2_VBI_ITU_625_F2_START + 5;
		f->fmt.vbi.count[0] = VBI_PAL_LINE_COUNT;
		f->fmt.vbi.count[1] = VBI_PAL_LINE_COUNT;
	}

	return 0;
}

/* We're given the Video Interrupt status register.
 * The cx23885_video_irq() func has already validated
 * the potential error bits, we just need to
 * deal with vbi payload and return indication if
 * we actually processed any payload.
 */
int cx23885_vbi_irq(struct cx23885_dev *dev, u32 status)
{
	u32 count;
	int handled = 0;

	if (status & VID_BC_MSK_VBI_RISCI1) {
		dprintk(1, "%s() VID_BC_MSK_VBI_RISCI1\n", __func__);
		spin_lock(&dev->slock);
		count = cx_read(VID_A_GPCNT);
		cx23885_video_wakeup(dev, &dev->vbiq, count);
		spin_unlock(&dev->slock);
		handled++;
	}

	return handled;
}

static int cx23885_start_vbi_dma(struct cx23885_dev    *dev,
			 struct cx23885_dmaqueue *q,
			 struct cx23885_buffer   *buf)
{
	dprintk(1, "%s()\n", __func__);

	/* setup fifo + format */
	cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH02],
				VBI_LINE_LENGTH, buf->risc.dma);

	/* reset counter */
	cx_write(VID_A_GPCNT_CTL, 3);
	cx_write(VID_A_VBI_CTRL, 3);
	cx_write(VBI_A_GPCNT_CTL, 3);
	q->count = 0;

	/* enable irq */
	cx23885_irq_add_enable(dev, 0x01);
	cx_set(VID_A_INT_MSK, 0x000022);

	/* start dma */
	cx_set(DEV_CNTRL2, (1<<5));
	cx_set(VID_A_DMA_CTL, 0x22); /* FIFO and RISC enable */

	return 0;
}

/* ------------------------------------------------------------------ */

static int queue_setup(struct vb2_queue *q, const struct v4l2_format *fmt,
			   unsigned int *num_buffers, unsigned int *num_planes,
			   unsigned int sizes[], void *alloc_ctxs[])
{
	struct cx23885_dev *dev = q->drv_priv;
	unsigned lines = VBI_PAL_LINE_COUNT;

	if (dev->tvnorm & V4L2_STD_525_60)
		lines = VBI_NTSC_LINE_COUNT;
	*num_planes = 1;
	sizes[0] = lines * VBI_LINE_LENGTH * 2;
	alloc_ctxs[0] = dev->alloc_ctx;
	return 0;
}

static int buffer_prepare(struct vb2_buffer *vb)
{
	struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
	struct cx23885_dev *dev = vb->vb2_queue->drv_priv;
	struct cx23885_buffer *buf = container_of(vbuf,
		struct cx23885_buffer, vb);
	struct sg_table *sgt = vb2_dma_sg_plane_desc(vb, 0);
	unsigned lines = VBI_PAL_LINE_COUNT;

	if (dev->tvnorm & V4L2_STD_525_60)
		lines = VBI_NTSC_LINE_COUNT;

	if (vb2_plane_size(vb, 0) < lines * VBI_LINE_LENGTH * 2)
		return -EINVAL;
	vb2_set_plane_payload(vb, 0, lines * VBI_LINE_LENGTH * 2);

	cx23885_risc_vbibuffer(dev->pci, &buf->risc,
			 sgt->sgl,
			 0, VBI_LINE_LENGTH * lines,
			 VBI_LINE_LENGTH, 0,
			 lines);
	return 0;
}

static void buffer_finish(struct vb2_buffer *vb)
{
	struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
	struct cx23885_buffer *buf = container_of(vbuf,
		struct cx23885_buffer, vb);

	cx23885_free_buffer(vb->vb2_queue->drv_priv, buf);
}

/*
 * The risc program for each buffer works as follows: it starts with a simple
 * 'JUMP to addr + 12', which is effectively a NOP. Then the code to DMA the
 * buffer follows and at the end we have a JUMP back to the start + 12 (skipping
 * the initial JUMP).
 *
 * This is the risc program of the first buffer to be queued if the active list
 * is empty and it just keeps DMAing this buffer without generating any
 * interrupts.
 *
 * If a new buffer is added then the initial JUMP in the code for that buffer
 * will generate an interrupt which signals that the previous buffer has been
 * DMAed successfully and that it can be returned to userspace.
 *
 * It also sets the final jump of the previous buffer to the start of the new
 * buffer, thus chaining the new buffer into the DMA chain. This is a single
 * atomic u32 write, so there is no race condition.
 *
 * The end-result of all this that you only get an interrupt when a buffer
 * is ready, so the control flow is very easy.
 */
static void buffer_queue(struct vb2_buffer *vb)
{
	struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
	struct cx23885_dev *dev = vb->vb2_queue->drv_priv;
	struct cx23885_buffer *buf = container_of(vbuf,
			struct cx23885_buffer, vb);
	struct cx23885_buffer *prev;
	struct cx23885_dmaqueue *q = &dev->vbiq;
	unsigned long flags;

	buf->risc.cpu[1] = cpu_to_le32(buf->risc.dma + 12);
	buf->risc.jmp[0] = cpu_to_le32(RISC_JUMP | RISC_CNT_INC);
	buf->risc.jmp[1] = cpu_to_le32(buf->risc.dma + 12);
	buf->risc.jmp[2] = cpu_to_le32(0); /* bits 63-32 */

	if (list_empty(&q->active)) {
		spin_lock_irqsave(&dev->slock, flags);
		list_add_tail(&buf->queue, &q->active);
		spin_unlock_irqrestore(&dev->slock, flags);
		dprintk(2, "[%p/%d] vbi_queue - first active\n",
			buf, buf->vb.vb2_buf.index);

	} else {
		buf->risc.cpu[0] |= cpu_to_le32(RISC_IRQ1);
		prev = list_entry(q->active.prev, struct cx23885_buffer,
			queue);
		spin_lock_irqsave(&dev->slock, flags);
		list_add_tail(&buf->queue, &q->active);
		spin_unlock_irqrestore(&dev->slock, flags);
		prev->risc.jmp[1] = cpu_to_le32(buf->risc.dma);
		dprintk(2, "[%p/%d] buffer_queue - append to active\n",
			buf, buf->vb.vb2_buf.index);
	}
}

static int cx23885_start_streaming(struct vb2_queue *q, unsigned int count)
{
	struct cx23885_dev *dev = q->drv_priv;
	struct cx23885_dmaqueue *dmaq = &dev->vbiq;
	struct cx23885_buffer *buf = list_entry(dmaq->active.next,
			struct cx23885_buffer, queue);

	cx23885_start_vbi_dma(dev, dmaq, buf);
	return 0;
}

static void cx23885_stop_streaming(struct vb2_queue *q)
{
	struct cx23885_dev *dev = q->drv_priv;
	struct cx23885_dmaqueue *dmaq = &dev->vbiq;
	unsigned long flags;

	cx_clear(VID_A_DMA_CTL, 0x22); /* FIFO and RISC enable */
	spin_lock_irqsave(&dev->slock, flags);
	while (!list_empty(&dmaq->active)) {
		struct cx23885_buffer *buf = list_entry(dmaq->active.next,
			struct cx23885_buffer, queue);

		list_del(&buf->queue);
		vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR);
	}
	spin_unlock_irqrestore(&dev->slock, flags);
}


struct vb2_ops cx23885_vbi_qops = {
	.queue_setup    = queue_setup,
	.buf_prepare  = buffer_prepare,
	.buf_finish = buffer_finish,
	.buf_queue    = buffer_queue,
	.wait_prepare = vb2_ops_wait_prepare,
	.wait_finish = vb2_ops_wait_finish,
	.start_streaming = cx23885_start_streaming,
	.stop_streaming = cx23885_stop_streaming,
};
Commit	Line	Data
e47f30b1 ST	1	/*
	2	* Driver for the Conexant CX23885 PCIe bridge
	3	*
6d897616	4	* Copyright (c) 2007 Steven Toth <stoth@linuxtv.org>
e47f30b1 ST	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License, or
	9	* (at your option) any later version.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	*
	15	* GNU General Public License for more details.
e47f30b1 ST	16	*/
	17
	18	#include <linux/kernel.h>
	19	#include <linux/module.h>
	20	#include <linux/moduleparam.h>
	21	#include <linux/init.h>
e47f30b1 ST	22
	23	#include "cx23885.h"
	24
	25	static unsigned int vbibufs = 4;
	26	module_param(vbibufs, int, 0644);
	27	MODULE_PARM_DESC(vbibufs, "number of vbi buffers, range 2-32");
	28
4513fc69	29	static unsigned int vbi_debug;
e47f30b1 ST	30	module_param(vbi_debug, int, 0644);
	31	MODULE_PARM_DESC(vbi_debug, "enable debug messages [vbi]");
	32
4513fc69 ST	33	#define dprintk(level, fmt, arg...)\
	34	do { if (vbi_debug >= level)\
	35	printk(KERN_DEBUG "%s/0: " fmt, dev->name, ## arg);\
	36	} while (0)
e47f30b1 ST	37
	38	/* ------------------------------------------------------------------ */
	39
4f9c4143	40	#define VBI_LINE_LENGTH 1440
453afdd9 HV	41	#define VBI_NTSC_LINE_COUNT 12
453afdd9 HV	42	#define VBI_PAL_LINE_COUNT 18
4f9c4143 ST	43
4f9c4143 ST	44
e47f30b1 ST	45	int cx23885_vbi_fmt(struct file file, void priv,
	46	struct v4l2_format *f)
	47	{
568f44a1	48	struct cx23885_dev *dev = video_drvdata(file);
e47f30b1	49
453afdd9 HV	50	f->fmt.vbi.sampling_rate = 27000000;
	51	f->fmt.vbi.samples_per_line = VBI_LINE_LENGTH;
	52	f->fmt.vbi.sample_format = V4L2_PIX_FMT_GREY;
	53	f->fmt.vbi.offset = 0;
	54	f->fmt.vbi.flags = 0;
e47f30b1 ST	55	if (dev->tvnorm & V4L2_STD_525_60) {
e47f30b1 ST	56	/* ntsc */
420b2176 HV	57	f->fmt.vbi.start[0] = V4L2_VBI_ITU_525_F1_START + 9;
420b2176 HV	58	f->fmt.vbi.start[1] = V4L2_VBI_ITU_525_F2_START + 9;
453afdd9 HV	59	f->fmt.vbi.count[0] = VBI_NTSC_LINE_COUNT;
453afdd9 HV	60	f->fmt.vbi.count[1] = VBI_NTSC_LINE_COUNT;
e47f30b1 ST	61	} else if (dev->tvnorm & V4L2_STD_625_50) {
e47f30b1 ST	62	/* pal */
420b2176 HV	63	f->fmt.vbi.start[0] = V4L2_VBI_ITU_625_F1_START + 5;
420b2176 HV	64	f->fmt.vbi.start[1] = V4L2_VBI_ITU_625_F2_START + 5;
453afdd9 HV	65	f->fmt.vbi.count[0] = VBI_PAL_LINE_COUNT;
453afdd9 HV	66	f->fmt.vbi.count[1] = VBI_PAL_LINE_COUNT;
e47f30b1	67	}
4f9c4143	68
e47f30b1 ST	69	return 0;
	70	}
	71
b5f74050 ST	72	/* We're given the Video Interrupt status register.
	73	* The cx23885_video_irq() func has already validated
	74	* the potential error bits, we just need to
	75	* deal with vbi payload and return indication if
	76	* we actually processed any payload.
	77	*/
	78	int cx23885_vbi_irq(struct cx23885_dev *dev, u32 status)
	79	{
	80	u32 count;
	81	int handled = 0;
	82
	83	if (status & VID_BC_MSK_VBI_RISCI1) {
	84	dprintk(1, "%s() VID_BC_MSK_VBI_RISCI1\n", __func__);
	85	spin_lock(&dev->slock);
	86	count = cx_read(VID_A_GPCNT);
	87	cx23885_video_wakeup(dev, &dev->vbiq, count);
	88	spin_unlock(&dev->slock);
	89	handled++;
	90	}
	91
b5f74050 ST	92	return handled;
	93	}
	94
e47f30b1 ST	95	static int cx23885_start_vbi_dma(struct cx23885_dev *dev,
	96	struct cx23885_dmaqueue *q,
	97	struct cx23885_buffer *buf)
	98	{
b5f74050 ST	99	dprintk(1, "%s()\n", __func__);
b5f74050 ST	100
e47f30b1 ST	101	/* setup fifo + format */
e47f30b1 ST	102	cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH02],
453afdd9	103	VBI_LINE_LENGTH, buf->risc.dma);
e47f30b1 ST	104
e47f30b1 ST	105	/* reset counter */
b5f74050	106	cx_write(VID_A_GPCNT_CTL, 3);
4f9c4143 ST	107	cx_write(VID_A_VBI_CTRL, 3);
4f9c4143 ST	108	cx_write(VBI_A_GPCNT_CTL, 3);
453afdd9	109	q->count = 0;
e47f30b1	110
b5f74050	111	/* enable irq */
dbe83a3b	112	cx23885_irq_add_enable(dev, 0x01);
e47f30b1 ST	113	cx_set(VID_A_INT_MSK, 0x000022);
	114
	115	/* start dma */
	116	cx_set(DEV_CNTRL2, (1<<5));
b5f74050	117	cx_set(VID_A_DMA_CTL, 0x22); /* FIFO and RISC enable */
e47f30b1 ST	118
	119	return 0;
	120	}
	121
453afdd9	122	/* ------------------------------------------------------------------ */
e47f30b1	123
453afdd9 HV	124	static int queue_setup(struct vb2_queue q, const struct v4l2_format fmt,
	125	unsigned int num_buffers, unsigned int num_planes,
	126	unsigned int sizes[], void *alloc_ctxs[])
e47f30b1	127	{
453afdd9 HV	128	struct cx23885_dev *dev = q->drv_priv;
	129	unsigned lines = VBI_PAL_LINE_COUNT;
	130
	131	if (dev->tvnorm & V4L2_STD_525_60)
	132	lines = VBI_NTSC_LINE_COUNT;
	133	*num_planes = 1;
	134	sizes[0] = lines * VBI_LINE_LENGTH * 2;
0c3a14c1	135	alloc_ctxs[0] = dev->alloc_ctx;
e47f30b1 ST	136	return 0;
	137	}
	138
453afdd9	139	static int buffer_prepare(struct vb2_buffer *vb)
e47f30b1	140	{
2d700715	141	struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
453afdd9	142	struct cx23885_dev *dev = vb->vb2_queue->drv_priv;
2d700715	143	struct cx23885_buffer *buf = container_of(vbuf,
453afdd9 HV	144	struct cx23885_buffer, vb);
	145	struct sg_table *sgt = vb2_dma_sg_plane_desc(vb, 0);
	146	unsigned lines = VBI_PAL_LINE_COUNT;
e47f30b1	147
453afdd9 HV	148	if (dev->tvnorm & V4L2_STD_525_60)
453afdd9 HV	149	lines = VBI_NTSC_LINE_COUNT;
e47f30b1	150
453afdd9 HV	151	if (vb2_plane_size(vb, 0) < lines * VBI_LINE_LENGTH * 2)
	152	return -EINVAL;
	153	vb2_set_plane_payload(vb, 0, lines * VBI_LINE_LENGTH * 2);
e47f30b1	154
453afdd9 HV	155	cx23885_risc_vbibuffer(dev->pci, &buf->risc,
	156	sgt->sgl,
	157	0, VBI_LINE_LENGTH * lines,
	158	VBI_LINE_LENGTH, 0,
	159	lines);
e47f30b1 ST	160	return 0;
	161	}
	162
453afdd9	163	static void buffer_finish(struct vb2_buffer *vb)
e47f30b1	164	{
2d700715 JS	165	struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
2d700715 JS	166	struct cx23885_buffer *buf = container_of(vbuf,
e47f30b1	167	struct cx23885_buffer, vb);
e47f30b1	168
453afdd9	169	cx23885_free_buffer(vb->vb2_queue->drv_priv, buf);
e47f30b1 ST	170	}
e47f30b1 ST	171
453afdd9 HV	172	/*
	173	* The risc program for each buffer works as follows: it starts with a simple
	174	* 'JUMP to addr + 12', which is effectively a NOP. Then the code to DMA the
	175	* buffer follows and at the end we have a JUMP back to the start + 12 (skipping
	176	* the initial JUMP).
	177	*
	178	* This is the risc program of the first buffer to be queued if the active list
	179	* is empty and it just keeps DMAing this buffer without generating any
	180	* interrupts.
	181	*
	182	* If a new buffer is added then the initial JUMP in the code for that buffer
	183	* will generate an interrupt which signals that the previous buffer has been
	184	* DMAed successfully and that it can be returned to userspace.
	185	*
	186	* It also sets the final jump of the previous buffer to the start of the new
	187	* buffer, thus chaining the new buffer into the DMA chain. This is a single
	188	* atomic u32 write, so there is no race condition.
	189	*
	190	* The end-result of all this that you only get an interrupt when a buffer
	191	* is ready, so the control flow is very easy.
	192	*/
	193	static void buffer_queue(struct vb2_buffer *vb)
e47f30b1	194	{
2d700715	195	struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
453afdd9	196	struct cx23885_dev *dev = vb->vb2_queue->drv_priv;
2d700715 JS	197	struct cx23885_buffer *buf = container_of(vbuf,
2d700715 JS	198	struct cx23885_buffer, vb);
453afdd9 HV	199	struct cx23885_buffer *prev;
	200	struct cx23885_dmaqueue *q = &dev->vbiq;
	201	unsigned long flags;
	202
	203	buf->risc.cpu[1] = cpu_to_le32(buf->risc.dma + 12);
	204	buf->risc.jmp[0] = cpu_to_le32(RISC_JUMP \| RISC_CNT_INC);
	205	buf->risc.jmp[1] = cpu_to_le32(buf->risc.dma + 12);
e47f30b1 ST	206	buf->risc.jmp[2] = cpu_to_le32(0); /* bits 63-32 */
	207
	208	if (list_empty(&q->active)) {
453afdd9 HV	209	spin_lock_irqsave(&dev->slock, flags);
	210	list_add_tail(&buf->queue, &q->active);
	211	spin_unlock_irqrestore(&dev->slock, flags);
e47f30b1	212	dprintk(2, "[%p/%d] vbi_queue - first active\n",
2d700715	213	buf, buf->vb.vb2_buf.index);
e47f30b1 ST	214
e47f30b1 ST	215	} else {
453afdd9	216	buf->risc.cpu[0] \|= cpu_to_le32(RISC_IRQ1);
e47f30b1	217	prev = list_entry(q->active.prev, struct cx23885_buffer,
453afdd9 HV	218	queue);
	219	spin_lock_irqsave(&dev->slock, flags);
	220	list_add_tail(&buf->queue, &q->active);
	221	spin_unlock_irqrestore(&dev->slock, flags);
e47f30b1	222	prev->risc.jmp[1] = cpu_to_le32(buf->risc.dma);
e47f30b1	223	dprintk(2, "[%p/%d] buffer_queue - append to active\n",
2d700715	224	buf, buf->vb.vb2_buf.index);
e47f30b1 ST	225	}
	226	}
	227
453afdd9	228	static int cx23885_start_streaming(struct vb2_queue *q, unsigned int count)
e47f30b1	229	{
453afdd9 HV	230	struct cx23885_dev *dev = q->drv_priv;
	231	struct cx23885_dmaqueue *dmaq = &dev->vbiq;
	232	struct cx23885_buffer *buf = list_entry(dmaq->active.next,
	233	struct cx23885_buffer, queue);
e47f30b1	234
453afdd9 HV	235	cx23885_start_vbi_dma(dev, dmaq, buf);
453afdd9 HV	236	return 0;
e47f30b1 ST	237	}
e47f30b1 ST	238
453afdd9 HV	239	static void cx23885_stop_streaming(struct vb2_queue *q)
	240	{
	241	struct cx23885_dev *dev = q->drv_priv;
	242	struct cx23885_dmaqueue *dmaq = &dev->vbiq;
	243	unsigned long flags;
e47f30b1	244
453afdd9 HV	245	cx_clear(VID_A_DMA_CTL, 0x22); /* FIFO and RISC enable */
	246	spin_lock_irqsave(&dev->slock, flags);
	247	while (!list_empty(&dmaq->active)) {
	248	struct cx23885_buffer *buf = list_entry(dmaq->active.next,
	249	struct cx23885_buffer, queue);
	250
	251	list_del(&buf->queue);
2d700715	252	vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR);
453afdd9 HV	253	}
	254	spin_unlock_irqrestore(&dev->slock, flags);
	255	}
	256
	257
	258	struct vb2_ops cx23885_vbi_qops = {
	259	.queue_setup = queue_setup,
	260	.buf_prepare = buffer_prepare,
	261	.buf_finish = buffer_finish,
	262	.buf_queue = buffer_queue,
	263	.wait_prepare = vb2_ops_wait_prepare,
	264	.wait_finish = vb2_ops_wait_finish,
	265	.start_streaming = cx23885_start_streaming,
	266	.stop_streaming = cx23885_stop_streaming,
	267	};