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[mirror_ubuntu-kernels.git] / drivers / media / pci / cx23885 / cx23885.h
CommitLineData
d19770e5
ST		 1/*
2 * Driver for the Conexant CX23885 PCIe bridge
3 *
6d897616 4 * Copyright (c) 2006 Steven Toth <stoth@linuxtv.org>
d19770e5
ST		 5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 *
15 * GNU General Public License for more details.
d19770e5
ST		 16 */
17
e39682b5
MCC		 18#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
19
d19770e5
ST		 20#include <linux/pci.h>
21#include <linux/i2c.h>
d19770e5 22#include <linux/kdev_t.h>
5a0e3ad6 23#include <linux/slab.h>
d19770e5 24
c0714f6c 25#include <media/v4l2-device.h>
86dd9831 26#include <media/v4l2-fh.h>
da59a4de 27#include <media/v4l2-ctrls.h>
d19770e5
ST		 28#include <media/tuner.h>
29#include <media/tveeprom.h>
453afdd9
HV		 30#include <media/videobuf2-dma-sg.h>
31#include <media/videobuf2-dvb.h>
6bda9644 32#include <media/rc-core.h>
d19770e5 33
d19770e5 34#include "cx23885-reg.h"
d647f0b7 35#include "media/drv-intf/cx2341x.h"
d19770e5 36
d19770e5
ST		 37#include <linux/mutex.h>
38
453afdd9 39#define CX23885_VERSION "0.0.4"
d19770e5
ST		 40
41#define UNSET (-1U)
42
43#define CX23885_MAXBOARDS 8
44
d19770e5
ST		 45/* Max number of inputs by card */
46#define MAX_CX23885_INPUT 8
7b888014 47#define INPUT(nr) (&cx23885_boards[dev->board].input[nr])
d19770e5 48
d19770e5
ST		 49#define BUFFER_TIMEOUT (HZ) /* 0.5 seconds */
50
51#define CX23885_BOARD_NOAUTO UNSET
52#define CX23885_BOARD_UNKNOWN 0
53#define CX23885_BOARD_HAUPPAUGE_HVR1800lp 1
54#define CX23885_BOARD_HAUPPAUGE_HVR1800 2
a77743bc 55#define CX23885_BOARD_HAUPPAUGE_HVR1250 3
9bc37caa 56#define CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP 4
d1987d55 57#define CX23885_BOARD_HAUPPAUGE_HVR1500Q 5
07b4a835 58#define CX23885_BOARD_HAUPPAUGE_HVR1500 6
b3ea0166 59#define CX23885_BOARD_HAUPPAUGE_HVR1200 7
a780a31c 60#define CX23885_BOARD_HAUPPAUGE_HVR1700 8
66762373 61#define CX23885_BOARD_HAUPPAUGE_HVR1400 9
335377b7 62#define CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP 10
aef2d186 63#define CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP 11
4c56b04a 64#define CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H 12
9bb1b7e8 65#define CX23885_BOARD_COMPRO_VIDEOMATE_E650F 13
96318d0c 66#define CX23885_BOARD_TBS_6920 14
579943f5 67#define CX23885_BOARD_TEVII_S470 15
c9b8b04b 68#define CX23885_BOARD_DVBWORLD_2005 16
5a23b076 69#define CX23885_BOARD_NETUP_DUAL_DVBS2_CI 17
2074dffa 70#define CX23885_BOARD_HAUPPAUGE_HVR1270 18
d099becb 71#define CX23885_BOARD_HAUPPAUGE_HVR1275 19
19bc5796 72#define CX23885_BOARD_HAUPPAUGE_HVR1255 20
6b926eca 73#define CX23885_BOARD_HAUPPAUGE_HVR1210 21
493b7127 74#define CX23885_BOARD_MYGICA_X8506 22
2365b2d3 75#define CX23885_BOARD_MAGICPRO_PROHDTVE2 23
13697380 76#define CX23885_BOARD_HAUPPAUGE_HVR1850 24
34e383dd 77#define CX23885_BOARD_COMPRO_VIDEOMATE_E800 25
aee0b24c 78#define CX23885_BOARD_HAUPPAUGE_HVR1290 26
ea5697fe 79#define CX23885_BOARD_MYGICA_X8558PRO 27
0b32d65c 80#define CX23885_BOARD_LEADTEK_WINFAST_PXTV1200 28
9028f58f 81#define CX23885_BOARD_GOTVIEW_X5_3D_HYBRID 29
78db8547 82#define CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF 30
0cf8af57 83#define CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000 31
2cb9ccd4 84#define CX23885_BOARD_MPX885 32
87988753 85#define CX23885_BOARD_MYGICA_X8507 33
722c90eb 86#define CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL 34
7b134e85 87#define CX23885_BOARD_TEVII_S471 35
0ac60acb 88#define CX23885_BOARD_HAUPPAUGE_HVR1255_22111 36
f667190b 89#define CX23885_BOARD_PROF_8000 37
7c62f5a1 90#define CX23885_BOARD_HAUPPAUGE_HVR4400 38
e8d42373 91#define CX23885_BOARD_AVERMEDIA_HC81R 39
e6001482
LA		 92#define CX23885_BOARD_TBS_6981 40
93#define CX23885_BOARD_TBS_6980 41
642ca1a0 94#define CX23885_BOARD_LEADTEK_WINFAST_PXPVR2200 42
cce11b09 95#define CX23885_BOARD_HAUPPAUGE_IMPACTVCBE 43
46b21bba 96#define CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP2 44
29442266 97#define CX23885_BOARD_DVBSKY_T9580 45
82c10276 98#define CX23885_BOARD_DVBSKY_T980C 46
0e6c7b01 99#define CX23885_BOARD_DVBSKY_S950C 47
61b103e8 100#define CX23885_BOARD_TT_CT2_4500_CI 48
cba5480c 101#define CX23885_BOARD_DVBSKY_S950 49
c29d6a83 102#define CX23885_BOARD_DVBSKY_S952 50
c02ef64a 103#define CX23885_BOARD_DVBSKY_T982 51
1fc77d01 104#define CX23885_BOARD_HAUPPAUGE_HVR5525 52
4a8ba331 105#define CX23885_BOARD_HAUPPAUGE_STARBURST 53
6c43a217
HV		 106#define CX23885_BOARD_VIEWCAST_260E 54
107#define CX23885_BOARD_VIEWCAST_460E 55
dd9ad4fb
SB		 108#define CX23885_BOARD_HAUPPAUGE_QUADHD_DVB 56
109#define CX23885_BOARD_HAUPPAUGE_QUADHD_ATSC 57
94f11518 110#define CX23885_BOARD_HAUPPAUGE_HVR1265_K4 58
16fad674 111#define CX23885_BOARD_HAUPPAUGE_STARBURST2 59
c00ba2c1
BL		 112#define CX23885_BOARD_HAUPPAUGE_QUADHD_DVB_885 60
113#define CX23885_BOARD_HAUPPAUGE_QUADHD_ATSC_885 61
d19770e5 114
6f8bee9b
ST		 115#define GPIO_0 0x00000001
116#define GPIO_1 0x00000002
117#define GPIO_2 0x00000004
118#define GPIO_3 0x00000008
119#define GPIO_4 0x00000010
120#define GPIO_5 0x00000020
121#define GPIO_6 0x00000040
122#define GPIO_7 0x00000080
123#define GPIO_8 0x00000100
124#define GPIO_9 0x00000200
f659c513
ST		 125#define GPIO_10 0x00000400
126#define GPIO_11 0x00000800
127#define GPIO_12 0x00001000
128#define GPIO_13 0x00002000
129#define GPIO_14 0x00004000
130#define GPIO_15 0x00008000
6f8bee9b 131
7b888014
ST		 132/* Currently unsupported by the driver: PAL/H, NTSC/Kr, SECAM B/G/H/LC */
133#define CX23885_NORMS (\
134 V4L2_STD_NTSC_M | V4L2_STD_NTSC_M_JP | V4L2_STD_NTSC_443 | \
135 V4L2_STD_PAL_BG | V4L2_STD_PAL_DK | V4L2_STD_PAL_I | \
136 V4L2_STD_PAL_M | V4L2_STD_PAL_N | V4L2_STD_PAL_Nc | \
137 V4L2_STD_PAL_60 | V4L2_STD_SECAM_L | V4L2_STD_SECAM_DK)
138
139struct cx23885_fmt {
140 char *name;
141 u32 fourcc; /* v4l2 format id */
142 int depth;
143 int flags;
144 u32 cxformat;
145};
146
7b888014
ST		 147struct cx23885_tvnorm {
148 char *name;
149 v4l2_std_id id;
150 u32 cxiformat;
151 u32 cxoformat;
152};
153
d19770e5
ST		 154enum cx23885_itype {
155 CX23885_VMUX_COMPOSITE1 = 1,
156 CX23885_VMUX_COMPOSITE2,
157 CX23885_VMUX_COMPOSITE3,
158 CX23885_VMUX_COMPOSITE4,
159 CX23885_VMUX_SVIDEO,
dac65fa1 160 CX23885_VMUX_COMPONENT,
d19770e5
ST		 161 CX23885_VMUX_TELEVISION,
162 CX23885_VMUX_CABLE,
163 CX23885_VMUX_DVB,
164 CX23885_VMUX_DEBUG,
165 CX23885_RADIO,
166};
167
579f1163
ST		 168enum cx23885_src_sel_type {
169 CX23885_SRC_SEL_EXT_656_VIDEO = 0,
170 CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO
171};
172
4d63a25c
HV		 173struct cx23885_riscmem {
174 unsigned int size;
175 __le32 *cpu;
176 __le32 *jmp;
177 dma_addr_t dma;
178};
179
d19770e5
ST		 180/* buffer for one video frame */
181struct cx23885_buffer {
182 /* common v4l buffer stuff -- must be first */
2d700715 183 struct vb2_v4l2_buffer vb;
453afdd9 184 struct list_head queue;
d19770e5
ST		 185
186 /* cx23885 specific */
187 unsigned int bpl;
4d63a25c 188 struct cx23885_riscmem risc;
d19770e5
ST		 189 struct cx23885_fmt *fmt;
190 u32 count;
191};
192
193struct cx23885_input {
194 enum cx23885_itype type;
195 unsigned int vmux;
8304be88 196 unsigned int amux;
d19770e5
ST		 197 u32 gpio0, gpio1, gpio2, gpio3;
198};
199
661c7e44
ST		 200typedef enum {
201 CX23885_MPEG_UNDEFINED = 0,
7b888014
ST		 202 CX23885_MPEG_DVB,
203 CX23885_ANALOG_VIDEO,
b1b81f1d 204 CX23885_MPEG_ENCODER,
661c7e44
ST		 205} port_t;
206
d19770e5
ST		 207struct cx23885_board {
208 char *name;
7b888014 209 port_t porta, portb, portc;
10d0dcd7 210 int num_fds_portb, num_fds_portc;
7b888014
ST		 211 unsigned int tuner_type;
212 unsigned int radio_type;
213 unsigned char tuner_addr;
214 unsigned char radio_addr;
557f48d5 215 unsigned int tuner_bus;
c7712613
ST		 216
217 /* Vendors can and do run the PCIe bridge at different
218 * clock rates, driven physically by crystals on the PCBs.
25985edc 219 * The core has to accommodate this. This allows the user
c7712613
ST		 220 * to add new boards with new frequencys. The value is
221 * expressed in Hz.
222 *
223 * The core framework will default this value based on
224 * current designs, but it can vary.
225 */
226 u32 clk_freq;
d19770e5 227 struct cx23885_input input[MAX_CX23885_INPUT];
78db8547 228 int ci_type; /* for NetUP */
35045137
ST		 229 /* Force bottom field first during DMA (888 workaround) */
230 u32 force_bff;
d19770e5
ST		 231};
232
233struct cx23885_subid {
234 u16 subvendor;
235 u16 subdevice;
236 u32 card;
237};
238
239struct cx23885_i2c {
240 struct cx23885_dev *dev;
241
242 int nr;
243
244 /* i2c i/o */
245 struct i2c_adapter i2c_adap;
d19770e5
ST		 246 struct i2c_client i2c_client;
247 u32 i2c_rc;
248
16790554 249 /* 885 registers used for raw address */
d19770e5
ST		 250 u32 i2c_period;
251 u32 reg_ctrl;
252 u32 reg_stat;
253 u32 reg_addr;
254 u32 reg_rdata;
255 u32 reg_wdata;
256};
257
258struct cx23885_dmaqueue {
259 struct list_head active;
d19770e5
ST		 260 u32 count;
261};
262
263struct cx23885_tsport {
264 struct cx23885_dev *dev;
265
e837d85c 266 unsigned nr;
d19770e5
ST		 267 int sram_chno;
268
453afdd9 269 struct vb2_dvb_frontends frontends;
d19770e5
ST		 270
271 /* dma queues */
272 struct cx23885_dmaqueue mpegq;
273 u32 ts_packet_size;
274 u32 ts_packet_count;
275
276 int width;
277 int height;
278
279 spinlock_t slock;
280
281 /* registers */
282 u32 reg_gpcnt;
283 u32 reg_gpcnt_ctl;
284 u32 reg_dma_ctl;
285 u32 reg_lngth;
286 u32 reg_hw_sop_ctrl;
287 u32 reg_gen_ctrl;
288 u32 reg_bd_pkt_status;
289 u32 reg_sop_status;
290 u32 reg_fifo_ovfl_stat;
291 u32 reg_vld_misc;
292 u32 reg_ts_clk_en;
293 u32 reg_ts_int_msk;
a6a3f140 294 u32 reg_ts_int_stat;
579f1163 295 u32 reg_src_sel;
d19770e5
ST		 296
297 /* Default register vals */
298 int pci_irqmask;
299 u32 dma_ctl_val;
300 u32 ts_int_msk_val;
301 u32 gen_ctrl_val;
302 u32 ts_clk_en_val;
579f1163 303 u32 src_sel_val;
b1b81f1d
ST		 304 u32 vld_misc_val;
305 u32 hw_sop_ctrl_val;
a739a7e4
ST		 306
307 /* Allow a single tsport to have multiple frontends */
308 u32 num_frontends;
78db8547 309 void (*gate_ctrl)(struct cx23885_tsport *port, int open);
5a23b076 310 void *port_priv;
35045137
ST		 311
312 /* Workaround for a temp dvb_frontend that the tuner can attached to */
313 struct dvb_frontend analog_fe;
15472faf 314
b0b12e63
OS		 315 struct i2c_client *i2c_client_demod;
316 struct i2c_client *i2c_client_tuner;
bf5e3ef0 317 struct i2c_client *i2c_client_sec;
e450de45 318 struct i2c_client *i2c_client_ci;
b0b12e63 319
15472faf 320 int (*set_frontend)(struct dvb_frontend *fe);
5cd3b6b4 321 int (*fe_set_voltage)(struct dvb_frontend *fe,
0df289a2 322 enum fe_sec_voltage voltage);
d19770e5
ST		 323};
324
43c24078
AW		 325struct cx23885_kernel_ir {
326 struct cx23885_dev *cx;
eeefae53
AW		 327 char *name;
328 char *phys;
329
d8b4b582 330 struct rc_dev *rc;
eeefae53
AW		 331};
332
9e44d632
MM		 333struct cx23885_audio_buffer {
334 unsigned int bpl;
4d63a25c 335 struct cx23885_riscmem risc;
9529a4b0
HV		 336 void *vaddr;
337 struct scatterlist *sglist;
338 int sglen;
339 int nr_pages;
9e44d632
MM		 340};
341
342struct cx23885_audio_dev {
343 struct cx23885_dev *dev;
344
345 struct pci_dev *pci;
346
347 struct snd_card *card;
348
349 spinlock_t lock;
350
351 atomic_t count;
352
353 unsigned int dma_size;
354 unsigned int period_size;
355 unsigned int num_periods;
356
9e44d632
MM		 357 struct cx23885_audio_buffer *buf;
358
359 struct snd_pcm_substream *substream;
360};
361
d19770e5 362struct cx23885_dev {
d19770e5 363 atomic_t refcount;
6e6a8b5a 364 struct v4l2_device v4l2_dev;
da59a4de 365 struct v4l2_ctrl_handler ctrl_handler;
d19770e5
ST		 366
367 /* pci stuff */
368 struct pci_dev *pci;
369 unsigned char pci_rev, pci_lat;
370 int pci_bus, pci_slot;
371 u32 __iomem *lmmio;
372 u8 __iomem *bmmio;
d19770e5 373 int pci_irqmask;
dbe83a3b 374 spinlock_t pci_irqmask_lock; /* protects mask reg too */
0ac5881a 375 int hwrevision;
d19770e5 376
c7712613
ST		 377 /* This valud is board specific and is used to configure the
378 * AV core so we see nice clean and stable video and audio. */
379 u32 clk_freq;
380
44a6481d 381 /* I2C adapters: Master 1 & 2 (External) & Master 3 (Internal only) */
d19770e5
ST		 382 struct cx23885_i2c i2c_bus[3];
383
384 int nr;
385 struct mutex lock;
8386c27f 386 struct mutex gpio_lock;
d19770e5
ST		 387
388 /* board details */
389 unsigned int board;
390 char name[32];
391
a6a3f140 392 struct cx23885_tsport ts1, ts2;
d19770e5
ST		 393
394 /* sram configuration */
395 struct sram_channel *sram_channels;
e133be0f
ST		 396
397 enum {
398 CX23885_BRIDGE_UNDEFINED = 0,
399 CX23885_BRIDGE_885 = 885,
400 CX23885_BRIDGE_887 = 887,
25ea66e2 401 CX23885_BRIDGE_888 = 888,
e133be0f 402 } bridge;
7b888014
ST		 403
404 /* Analog video */
7b888014 405 unsigned int input;
fc1a889d 406 unsigned int audinput; /* Selectable audio input */
7b888014
ST		 407 u32 tvaudio;
408 v4l2_std_id tvnorm;
409 unsigned int tuner_type;
410 unsigned char tuner_addr;
557f48d5 411 unsigned int tuner_bus;
7b888014
ST		 412 unsigned int radio_type;
413 unsigned char radio_addr;
6e6a8b5a 414 struct v4l2_subdev *sd_cx25840;
e5514f10 415 struct work_struct cx25840_work;
f59ad611
AW		 416
417 /* Infrared */
418 struct v4l2_subdev *sd_ir;
419 struct work_struct ir_rx_work;
420 unsigned long ir_rx_notifications;
421 struct work_struct ir_tx_work;
422 unsigned long ir_tx_notifications;
7b888014 423
43c24078 424 struct cx23885_kernel_ir *kernel_ir;
dbda8f70
AW		 425 atomic_t ir_input_stopping;
426
7b888014
ST		 427 /* V4l */
428 u32 freq;
429 struct video_device *video_dev;
430 struct video_device *vbi_dev;
7b888014 431
91d2d674
HV		 432 /* video capture */
433 struct cx23885_fmt *fmt;
434 unsigned int width, height;
453afdd9 435 unsigned field;
91d2d674 436
7b888014 437 struct cx23885_dmaqueue vidq;
453afdd9 438 struct vb2_queue vb2_vidq;
7b888014 439 struct cx23885_dmaqueue vbiq;
453afdd9
HV		 440 struct vb2_queue vb2_vbiq;
441
7b888014 442 spinlock_t slock;
b1b81f1d
ST		 443
444 /* MPEG Encoder ONLY settings */
445 u32 cx23417_mailbox;
5150392c 446 struct cx2341x_handler cxhdl;
b1b81f1d 447 struct video_device *v4l_device;
453afdd9 448 struct vb2_queue vb2_mpegq;
b1b81f1d
ST		 449 struct cx23885_tvnorm encodernorm;
450
9e44d632
MM		 451 /* Analog raw audio */
452 struct cx23885_audio_dev *audio_dev;
453
4bd46aa0
BL		 454 /* Does the system require periodic DMA resets? */
455 unsigned int need_dma_reset:1;
d19770e5
ST		 456};
457
c0714f6c
HV		 458static inline struct cx23885_dev *to_cx23885(struct v4l2_device *v4l2_dev)
459{
460 return container_of(v4l2_dev, struct cx23885_dev, v4l2_dev);
461}
462
0d5a19f1
HV		 463#define call_all(dev, o, f, args...) \
464 v4l2_device_call_all(&dev->v4l2_dev, 0, o, f, ##args)
465
d6b1850d
AW		 466#define CX23885_HW_888_IR (1 << 0)
467#define CX23885_HW_AV_CORE (1 << 1)
29f8a0a5
AW		 468
469#define call_hw(dev, grpid, o, f, args...) \
470 v4l2_device_call_all(&dev->v4l2_dev, grpid, o, f, ##args)
471
472extern struct v4l2_subdev *cx23885_find_hw(struct cx23885_dev *dev, u32 hw);
473
d19770e5
ST		 474#define SRAM_CH01 0 /* Video A */
475#define SRAM_CH02 1 /* VBI A */
476#define SRAM_CH03 2 /* Video B */
477#define SRAM_CH04 3 /* Transport via B */
478#define SRAM_CH05 4 /* VBI B */
479#define SRAM_CH06 5 /* Video C */
480#define SRAM_CH07 6 /* Transport via C */
481#define SRAM_CH08 7 /* Audio Internal A */
482#define SRAM_CH09 8 /* Audio Internal B */
483#define SRAM_CH10 9 /* Audio External */
484#define SRAM_CH11 10 /* COMB_3D_N */
485#define SRAM_CH12 11 /* Comb 3D N1 */
486#define SRAM_CH13 12 /* Comb 3D N2 */
487#define SRAM_CH14 13 /* MOE Vid */
488#define SRAM_CH15 14 /* MOE RSLT */
489
490struct sram_channel {
491 char *name;
492 u32 cmds_start;
493 u32 ctrl_start;
494 u32 cdt;
1ebcad77 495 u32 fifo_start;
d19770e5
ST		 496 u32 fifo_size;
497 u32 ptr1_reg;
498 u32 ptr2_reg;
499 u32 cnt1_reg;
500 u32 cnt2_reg;
501 u32 jumponly;
502};
503
504/* ----------------------------------------------------------- */
505
506#define cx_read(reg) readl(dev->lmmio + ((reg)>>2))
9c8ced51 507#define cx_write(reg, value) writel((value), dev->lmmio + ((reg)>>2))
d19770e5 508
9c8ced51 509#define cx_andor(reg, mask, value) \
d19770e5
ST		 510 writel((readl(dev->lmmio+((reg)>>2)) & ~(mask)) |\
511 ((value) & (mask)), dev->lmmio+((reg)>>2))
512
9c8ced51
ST		 513#define cx_set(reg, bit) cx_andor((reg), (bit), (bit))
514#define cx_clear(reg, bit) cx_andor((reg), (bit), 0)
d19770e5 515
d19770e5 516/* ----------------------------------------------------------- */
7b888014
ST		 517/* cx23885-core.c */
518
519extern int cx23885_sram_channel_setup(struct cx23885_dev *dev,
520 struct sram_channel *ch,
521 unsigned int bpl, u32 risc);
522
523extern void cx23885_sram_channel_dump(struct cx23885_dev *dev,
524 struct sram_channel *ch);
d19770e5 525
4d63a25c 526extern int cx23885_risc_buffer(struct pci_dev *pci, struct cx23885_riscmem *risc,
7b888014
ST		 527 struct scatterlist *sglist,
528 unsigned int top_offset, unsigned int bottom_offset,
529 unsigned int bpl, unsigned int padding, unsigned int lines);
530
5ab27e6d 531extern int cx23885_risc_vbibuffer(struct pci_dev *pci,
4d63a25c 532 struct cx23885_riscmem *risc, struct scatterlist *sglist,
5ab27e6d
ST		 533 unsigned int top_offset, unsigned int bottom_offset,
534 unsigned int bpl, unsigned int padding, unsigned int lines);
535
453afdd9
HV		 536int cx23885_start_dma(struct cx23885_tsport *port,
537 struct cx23885_dmaqueue *q,
538 struct cx23885_buffer *buf);
7b888014
ST		 539void cx23885_cancel_buffers(struct cx23885_tsport *port);
540
7b888014 541
6f8bee9b
ST		 542extern void cx23885_gpio_set(struct cx23885_dev *dev, u32 mask);
543extern void cx23885_gpio_clear(struct cx23885_dev *dev, u32 mask);
09ea33e5 544extern u32 cx23885_gpio_get(struct cx23885_dev *dev, u32 mask);
6f8bee9b
ST		 545extern void cx23885_gpio_enable(struct cx23885_dev *dev, u32 mask,
546 int asoutput);
547
dbe83a3b
AW		 548extern void cx23885_irq_add_enable(struct cx23885_dev *dev, u32 mask);
549extern void cx23885_irq_enable(struct cx23885_dev *dev, u32 mask);
550extern void cx23885_irq_disable(struct cx23885_dev *dev, u32 mask);
551extern void cx23885_irq_remove(struct cx23885_dev *dev, u32 mask);
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ST		 552
553/* ----------------------------------------------------------- */
554/* cx23885-cards.c */
d19770e5
ST		 555extern struct cx23885_board cx23885_boards[];
556extern const unsigned int cx23885_bcount;
557
558extern struct cx23885_subid cx23885_subids[];
559extern const unsigned int cx23885_idcount;
560
9c8ced51
ST		 561extern int cx23885_tuner_callback(void *priv, int component,
562 int command, int arg);
d19770e5 563extern void cx23885_card_list(struct cx23885_dev *dev);
a6a3f140 564extern int cx23885_ir_init(struct cx23885_dev *dev);
f59ad611
AW		 565extern void cx23885_ir_pci_int_enable(struct cx23885_dev *dev);
566extern void cx23885_ir_fini(struct cx23885_dev *dev);
a6a3f140 567extern void cx23885_gpio_setup(struct cx23885_dev *dev);
d19770e5
ST		 568extern void cx23885_card_setup(struct cx23885_dev *dev);
569extern void cx23885_card_setup_pre_i2c(struct cx23885_dev *dev);
570
571extern int cx23885_dvb_register(struct cx23885_tsport *port);
572extern int cx23885_dvb_unregister(struct cx23885_tsport *port);
573
453afdd9
HV		 574extern int cx23885_buf_prepare(struct cx23885_buffer *buf,
575 struct cx23885_tsport *port);
44a6481d
MK		 576extern void cx23885_buf_queue(struct cx23885_tsport *port,
577 struct cx23885_buffer *buf);
453afdd9 578extern void cx23885_free_buffer(struct cx23885_dev *dev,
44a6481d 579 struct cx23885_buffer *buf);
d19770e5
ST		 580
581/* ----------------------------------------------------------- */
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ST		 582/* cx23885-video.c */
583/* Video */
584extern int cx23885_video_register(struct cx23885_dev *dev);
585extern void cx23885_video_unregister(struct cx23885_dev *dev);
586extern int cx23885_video_irq(struct cx23885_dev *dev, u32 status);
b5f74050
ST		 587extern void cx23885_video_wakeup(struct cx23885_dev *dev,
588 struct cx23885_dmaqueue *q, u32 count);
35045137
ST		 589int cx23885_enum_input(struct cx23885_dev *dev, struct v4l2_input *i);
590int cx23885_set_input(struct file *file, void *priv, unsigned int i);
591int cx23885_get_input(struct file *file, void *priv, unsigned int *i);
b530a447 592int cx23885_set_frequency(struct file *file, void *priv, const struct v4l2_frequency *f);
35045137 593int cx23885_set_tvnorm(struct cx23885_dev *dev, v4l2_std_id norm);
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ST		 594
595/* ----------------------------------------------------------- */
596/* cx23885-vbi.c */
597extern int cx23885_vbi_fmt(struct file *file, void *priv,
598 struct v4l2_format *f);
599extern void cx23885_vbi_timeout(unsigned long data);
0e2d9a9d 600extern const struct vb2_ops cx23885_vbi_qops;
b5f74050 601extern int cx23885_vbi_irq(struct cx23885_dev *dev, u32 status);
7b888014 602
d19770e5
ST		 603/* cx23885-i2c.c */
604extern int cx23885_i2c_register(struct cx23885_i2c *bus);
605extern int cx23885_i2c_unregister(struct cx23885_i2c *bus);
a589b665 606extern void cx23885_av_clk(struct cx23885_dev *dev, int enable);
d19770e5 607
b1b81f1d
ST		 608/* ----------------------------------------------------------- */
609/* cx23885-417.c */
610extern int cx23885_417_register(struct cx23885_dev *dev);
611extern void cx23885_417_unregister(struct cx23885_dev *dev);
612extern int cx23885_irq_417(struct cx23885_dev *dev, u32 status);
613extern void cx23885_417_check_encoder(struct cx23885_dev *dev);
614extern void cx23885_mc417_init(struct cx23885_dev *dev);
615extern int mc417_memory_read(struct cx23885_dev *dev, u32 address, u32 *value);
616extern int mc417_memory_write(struct cx23885_dev *dev, u32 address, u32 value);
74618244
AW		 617extern int mc417_register_read(struct cx23885_dev *dev,
618 u16 address, u32 *value);
619extern int mc417_register_write(struct cx23885_dev *dev,
620 u16 address, u32 value);
f659c513
ST		 621extern void mc417_gpio_set(struct cx23885_dev *dev, u32 mask);
622extern void mc417_gpio_clear(struct cx23885_dev *dev, u32 mask);
623extern void mc417_gpio_enable(struct cx23885_dev *dev, u32 mask, int asoutput);
b1b81f1d 624
9e44d632
MM		 625/* ----------------------------------------------------------- */
626/* cx23885-alsa.c */
efa762f5
ST		 627extern struct cx23885_audio_dev *cx23885_audio_register(
628 struct cx23885_dev *dev);
629extern void cx23885_audio_unregister(struct cx23885_dev *dev);
9e44d632
MM		 630extern int cx23885_audio_irq(struct cx23885_dev *dev, u32 status, u32 mask);
631extern int cx23885_risc_databuffer(struct pci_dev *pci,
4d63a25c 632 struct cx23885_riscmem *risc,
9e44d632
MM		 633 struct scatterlist *sglist,
634 unsigned int bpl,
635 unsigned int lines,
636 unsigned int lpi);
b1b81f1d 637
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ST		 638/* ----------------------------------------------------------- */
639/* tv norms */
640
7b888014
ST		 641static inline unsigned int norm_maxh(v4l2_std_id norm)
642{
1c5eaa23 643 return (norm & V4L2_STD_525_60) ? 480 : 576;
7b888014 644}
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