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Commit | Line | Data |
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29f8a0a5 AW |
1 | /* |
2 | * Driver for the Conexant CX23885/7/8 PCIe bridge | |
3 | * | |
4 | * CX23888 Integrated Consumer Infrared Controller | |
5 | * | |
6afdeaf8 | 6 | * Copyright (C) 2009 Andy Walls <awalls@md.metrocast.net> |
29f8a0a5 AW |
7 | * |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License | |
10 | * as published by the Free Software Foundation; either version 2 | |
11 | * of the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA | |
21 | * 02110-1301, USA. | |
22 | */ | |
23 | ||
1a0b9d89 | 24 | #include <linux/kfifo.h> |
5a0e3ad6 | 25 | #include <linux/slab.h> |
1a0b9d89 | 26 | |
29f8a0a5 | 27 | #include <media/v4l2-device.h> |
6bda9644 | 28 | #include <media/rc-core.h> |
29f8a0a5 AW |
29 | |
30 | #include "cx23885.h" | |
ada73eee | 31 | #include "cx23888-ir.h" |
29f8a0a5 | 32 | |
1a0b9d89 AW |
33 | static unsigned int ir_888_debug; |
34 | module_param(ir_888_debug, int, 0644); | |
35 | MODULE_PARM_DESC(ir_888_debug, "enable debug messages [CX23888 IR controller]"); | |
36 | ||
29f8a0a5 AW |
37 | #define CX23888_IR_REG_BASE 0x170000 |
38 | /* | |
39 | * These CX23888 register offsets have a straightforward one to one mapping | |
40 | * to the CX23885 register offsets of 0x200 through 0x218 | |
41 | */ | |
42 | #define CX23888_IR_CNTRL_REG 0x170000 | |
1a0b9d89 AW |
43 | #define CNTRL_WIN_3_3 0x00000000 |
44 | #define CNTRL_WIN_4_3 0x00000001 | |
45 | #define CNTRL_WIN_3_4 0x00000002 | |
46 | #define CNTRL_WIN_4_4 0x00000003 | |
47 | #define CNTRL_WIN 0x00000003 | |
48 | #define CNTRL_EDG_NONE 0x00000000 | |
49 | #define CNTRL_EDG_FALL 0x00000004 | |
50 | #define CNTRL_EDG_RISE 0x00000008 | |
51 | #define CNTRL_EDG_BOTH 0x0000000C | |
52 | #define CNTRL_EDG 0x0000000C | |
53 | #define CNTRL_DMD 0x00000010 | |
54 | #define CNTRL_MOD 0x00000020 | |
55 | #define CNTRL_RFE 0x00000040 | |
56 | #define CNTRL_TFE 0x00000080 | |
57 | #define CNTRL_RXE 0x00000100 | |
58 | #define CNTRL_TXE 0x00000200 | |
59 | #define CNTRL_RIC 0x00000400 | |
60 | #define CNTRL_TIC 0x00000800 | |
61 | #define CNTRL_CPL 0x00001000 | |
62 | #define CNTRL_LBM 0x00002000 | |
63 | #define CNTRL_R 0x00004000 | |
5a28d9a3 AW |
64 | /* CX23888 specific control flag */ |
65 | #define CNTRL_IVO 0x00008000 | |
1a0b9d89 | 66 | |
29f8a0a5 | 67 | #define CX23888_IR_TXCLK_REG 0x170004 |
1a0b9d89 AW |
68 | #define TXCLK_TCD 0x0000FFFF |
69 | ||
29f8a0a5 | 70 | #define CX23888_IR_RXCLK_REG 0x170008 |
1a0b9d89 AW |
71 | #define RXCLK_RCD 0x0000FFFF |
72 | ||
29f8a0a5 | 73 | #define CX23888_IR_CDUTY_REG 0x17000C |
1a0b9d89 AW |
74 | #define CDUTY_CDC 0x0000000F |
75 | ||
29f8a0a5 | 76 | #define CX23888_IR_STATS_REG 0x170010 |
1a0b9d89 AW |
77 | #define STATS_RTO 0x00000001 |
78 | #define STATS_ROR 0x00000002 | |
79 | #define STATS_RBY 0x00000004 | |
80 | #define STATS_TBY 0x00000008 | |
81 | #define STATS_RSR 0x00000010 | |
82 | #define STATS_TSR 0x00000020 | |
83 | ||
29f8a0a5 | 84 | #define CX23888_IR_IRQEN_REG 0x170014 |
1a0b9d89 AW |
85 | #define IRQEN_RTE 0x00000001 |
86 | #define IRQEN_ROE 0x00000002 | |
87 | #define IRQEN_RSE 0x00000010 | |
88 | #define IRQEN_TSE 0x00000020 | |
89 | ||
29f8a0a5 | 90 | #define CX23888_IR_FILTR_REG 0x170018 |
1a0b9d89 AW |
91 | #define FILTR_LPF 0x0000FFFF |
92 | ||
29f8a0a5 AW |
93 | /* This register doesn't follow the pattern; it's 0x23C on a CX23885 */ |
94 | #define CX23888_IR_FIFO_REG 0x170040 | |
1a0b9d89 AW |
95 | #define FIFO_RXTX 0x0000FFFF |
96 | #define FIFO_RXTX_LVL 0x00010000 | |
97 | #define FIFO_RXTX_RTO 0x0001FFFF | |
98 | #define FIFO_RX_NDV 0x00020000 | |
99 | #define FIFO_RX_DEPTH 8 | |
100 | #define FIFO_TX_DEPTH 8 | |
29f8a0a5 AW |
101 | |
102 | /* CX23888 unique registers */ | |
103 | #define CX23888_IR_SEEDP_REG 0x17001C | |
104 | #define CX23888_IR_TIMOL_REG 0x170020 | |
105 | #define CX23888_IR_WAKE0_REG 0x170024 | |
106 | #define CX23888_IR_WAKE1_REG 0x170028 | |
107 | #define CX23888_IR_WAKE2_REG 0x17002C | |
108 | #define CX23888_IR_MASK0_REG 0x170030 | |
109 | #define CX23888_IR_MASK1_REG 0x170034 | |
110 | #define CX23888_IR_MAKS2_REG 0x170038 | |
111 | #define CX23888_IR_DPIPG_REG 0x17003C | |
112 | #define CX23888_IR_LEARN_REG 0x170044 | |
113 | ||
1a0b9d89 | 114 | #define CX23888_VIDCLK_FREQ 108000000 /* 108 MHz, BT.656 */ |
928213aa | 115 | #define CX23888_IR_REFCLK_FREQ (CX23888_VIDCLK_FREQ / 2) |
1a0b9d89 | 116 | |
c02e0d12 AW |
117 | /* |
118 | * We use this union internally for convenience, but callers to tx_write | |
119 | * and rx_read will be expecting records of type struct ir_raw_event. | |
120 | * Always ensure the size of this union is dictated by struct ir_raw_event. | |
121 | */ | |
122 | union cx23888_ir_fifo_rec { | |
123 | u32 hw_fifo_data; | |
124 | struct ir_raw_event ir_core_data; | |
125 | }; | |
126 | ||
127 | #define CX23888_IR_RX_KFIFO_SIZE (256 * sizeof(union cx23888_ir_fifo_rec)) | |
128 | #define CX23888_IR_TX_KFIFO_SIZE (256 * sizeof(union cx23888_ir_fifo_rec)) | |
29f8a0a5 AW |
129 | |
130 | struct cx23888_ir_state { | |
131 | struct v4l2_subdev sd; | |
132 | struct cx23885_dev *dev; | |
1a0b9d89 AW |
133 | |
134 | struct v4l2_subdev_ir_parameters rx_params; | |
135 | struct mutex rx_params_lock; | |
136 | atomic_t rxclk_divider; | |
137 | atomic_t rx_invert; | |
138 | ||
7801edb0 | 139 | struct kfifo rx_kfifo; |
1a0b9d89 AW |
140 | spinlock_t rx_kfifo_lock; |
141 | ||
142 | struct v4l2_subdev_ir_parameters tx_params; | |
143 | struct mutex tx_params_lock; | |
144 | atomic_t txclk_divider; | |
29f8a0a5 AW |
145 | }; |
146 | ||
147 | static inline struct cx23888_ir_state *to_state(struct v4l2_subdev *sd) | |
148 | { | |
149 | return v4l2_get_subdevdata(sd); | |
150 | } | |
151 | ||
1a0b9d89 AW |
152 | /* |
153 | * IR register block read and write functions | |
154 | */ | |
155 | static | |
156 | inline int cx23888_ir_write4(struct cx23885_dev *dev, u32 addr, u32 value) | |
29f8a0a5 | 157 | { |
1a0b9d89 AW |
158 | cx_write(addr, value); |
159 | return 0; | |
160 | } | |
161 | ||
162 | static inline u32 cx23888_ir_read4(struct cx23885_dev *dev, u32 addr) | |
163 | { | |
164 | return cx_read(addr); | |
165 | } | |
29f8a0a5 | 166 | |
1a0b9d89 AW |
167 | static inline int cx23888_ir_and_or4(struct cx23885_dev *dev, u32 addr, |
168 | u32 and_mask, u32 or_value) | |
169 | { | |
170 | cx_andor(addr, ~and_mask, or_value); | |
29f8a0a5 AW |
171 | return 0; |
172 | } | |
173 | ||
1a0b9d89 AW |
174 | /* |
175 | * Rx and Tx Clock Divider register computations | |
176 | * | |
177 | * Note the largest clock divider value of 0xffff corresponds to: | |
178 | * (0xffff + 1) * 1000 / 108/2 MHz = 1,213,629.629... ns | |
179 | * which fits in 21 bits, so we'll use unsigned int for time arguments. | |
180 | */ | |
181 | static inline u16 count_to_clock_divider(unsigned int d) | |
29f8a0a5 | 182 | { |
928213aa | 183 | if (d > RXCLK_RCD + 1) |
1a0b9d89 AW |
184 | d = RXCLK_RCD; |
185 | else if (d < 2) | |
186 | d = 1; | |
187 | else | |
188 | d--; | |
189 | return (u16) d; | |
190 | } | |
191 | ||
192 | static inline u16 ns_to_clock_divider(unsigned int ns) | |
193 | { | |
194 | return count_to_clock_divider( | |
928213aa | 195 | DIV_ROUND_CLOSEST(CX23888_IR_REFCLK_FREQ / 1000000 * ns, 1000)); |
1a0b9d89 AW |
196 | } |
197 | ||
198 | static inline unsigned int clock_divider_to_ns(unsigned int divider) | |
199 | { | |
200 | /* Period of the Rx or Tx clock in ns */ | |
201 | return DIV_ROUND_CLOSEST((divider + 1) * 1000, | |
928213aa | 202 | CX23888_IR_REFCLK_FREQ / 1000000); |
1a0b9d89 AW |
203 | } |
204 | ||
205 | static inline u16 carrier_freq_to_clock_divider(unsigned int freq) | |
206 | { | |
207 | return count_to_clock_divider( | |
208 | DIV_ROUND_CLOSEST(CX23888_IR_REFCLK_FREQ, freq * 16)); | |
209 | } | |
210 | ||
211 | static inline unsigned int clock_divider_to_carrier_freq(unsigned int divider) | |
212 | { | |
213 | return DIV_ROUND_CLOSEST(CX23888_IR_REFCLK_FREQ, (divider + 1) * 16); | |
214 | } | |
215 | ||
216 | static inline u16 freq_to_clock_divider(unsigned int freq, | |
217 | unsigned int rollovers) | |
218 | { | |
219 | return count_to_clock_divider( | |
220 | DIV_ROUND_CLOSEST(CX23888_IR_REFCLK_FREQ, freq * rollovers)); | |
221 | } | |
222 | ||
223 | static inline unsigned int clock_divider_to_freq(unsigned int divider, | |
224 | unsigned int rollovers) | |
225 | { | |
226 | return DIV_ROUND_CLOSEST(CX23888_IR_REFCLK_FREQ, | |
227 | (divider + 1) * rollovers); | |
228 | } | |
229 | ||
230 | /* | |
231 | * Low Pass Filter register calculations | |
232 | * | |
233 | * Note the largest count value of 0xffff corresponds to: | |
234 | * 0xffff * 1000 / 108/2 MHz = 1,213,611.11... ns | |
235 | * which fits in 21 bits, so we'll use unsigned int for time arguments. | |
236 | */ | |
237 | static inline u16 count_to_lpf_count(unsigned int d) | |
238 | { | |
239 | if (d > FILTR_LPF) | |
240 | d = FILTR_LPF; | |
241 | else if (d < 4) | |
242 | d = 0; | |
243 | return (u16) d; | |
244 | } | |
245 | ||
246 | static inline u16 ns_to_lpf_count(unsigned int ns) | |
247 | { | |
248 | return count_to_lpf_count( | |
928213aa | 249 | DIV_ROUND_CLOSEST(CX23888_IR_REFCLK_FREQ / 1000000 * ns, 1000)); |
1a0b9d89 AW |
250 | } |
251 | ||
252 | static inline unsigned int lpf_count_to_ns(unsigned int count) | |
253 | { | |
254 | /* Duration of the Low Pass Filter rejection window in ns */ | |
928213aa AW |
255 | return DIV_ROUND_CLOSEST(count * 1000, |
256 | CX23888_IR_REFCLK_FREQ / 1000000); | |
1a0b9d89 AW |
257 | } |
258 | ||
259 | static inline unsigned int lpf_count_to_us(unsigned int count) | |
260 | { | |
261 | /* Duration of the Low Pass Filter rejection window in us */ | |
928213aa | 262 | return DIV_ROUND_CLOSEST(count, CX23888_IR_REFCLK_FREQ / 1000000); |
1a0b9d89 AW |
263 | } |
264 | ||
265 | /* | |
266 | * FIFO register pulse width count compuations | |
267 | */ | |
268 | static u32 clock_divider_to_resolution(u16 divider) | |
269 | { | |
270 | /* | |
271 | * Resolution is the duration of 1 tick of the readable portion of | |
272 | * of the pulse width counter as read from the FIFO. The two lsb's are | |
273 | * not readable, hence the << 2. This function returns ns. | |
274 | */ | |
275 | return DIV_ROUND_CLOSEST((1 << 2) * ((u32) divider + 1) * 1000, | |
928213aa | 276 | CX23888_IR_REFCLK_FREQ / 1000000); |
1a0b9d89 AW |
277 | } |
278 | ||
279 | static u64 pulse_width_count_to_ns(u16 count, u16 divider) | |
280 | { | |
281 | u64 n; | |
282 | u32 rem; | |
283 | ||
284 | /* | |
285 | * The 2 lsb's of the pulse width timer count are not readable, hence | |
286 | * the (count << 2) | 0x3 | |
287 | */ | |
288 | n = (((u64) count << 2) | 0x3) * (divider + 1) * 1000; /* millicycles */ | |
928213aa AW |
289 | rem = do_div(n, CX23888_IR_REFCLK_FREQ / 1000000); /* / MHz => ns */ |
290 | if (rem >= CX23888_IR_REFCLK_FREQ / 1000000 / 2) | |
1a0b9d89 AW |
291 | n++; |
292 | return n; | |
293 | } | |
294 | ||
295 | static unsigned int pulse_width_count_to_us(u16 count, u16 divider) | |
296 | { | |
297 | u64 n; | |
298 | u32 rem; | |
299 | ||
300 | /* | |
301 | * The 2 lsb's of the pulse width timer count are not readable, hence | |
302 | * the (count << 2) | 0x3 | |
303 | */ | |
928213aa AW |
304 | n = (((u64) count << 2) | 0x3) * (divider + 1); /* cycles */ |
305 | rem = do_div(n, CX23888_IR_REFCLK_FREQ / 1000000); /* / MHz => us */ | |
306 | if (rem >= CX23888_IR_REFCLK_FREQ / 1000000 / 2) | |
1a0b9d89 AW |
307 | n++; |
308 | return (unsigned int) n; | |
309 | } | |
310 | ||
311 | /* | |
312 | * Pulse Clocks computations: Combined Pulse Width Count & Rx Clock Counts | |
313 | * | |
314 | * The total pulse clock count is an 18 bit pulse width timer count as the most | |
315 | * significant part and (up to) 16 bit clock divider count as a modulus. | |
316 | * When the Rx clock divider ticks down to 0, it increments the 18 bit pulse | |
317 | * width timer count's least significant bit. | |
318 | */ | |
319 | static u64 ns_to_pulse_clocks(u32 ns) | |
320 | { | |
321 | u64 clocks; | |
322 | u32 rem; | |
928213aa | 323 | clocks = CX23888_IR_REFCLK_FREQ / 1000000 * (u64) ns; /* millicycles */ |
1a0b9d89 | 324 | rem = do_div(clocks, 1000); /* /1000 = cycles */ |
928213aa | 325 | if (rem >= 1000 / 2) |
1a0b9d89 AW |
326 | clocks++; |
327 | return clocks; | |
328 | } | |
329 | ||
330 | static u16 pulse_clocks_to_clock_divider(u64 count) | |
331 | { | |
e92ba283 | 332 | do_div(count, (FIFO_RXTX << 2) | 0x3); |
1a0b9d89 AW |
333 | |
334 | /* net result needs to be rounded down and decremented by 1 */ | |
928213aa | 335 | if (count > RXCLK_RCD + 1) |
1a0b9d89 AW |
336 | count = RXCLK_RCD; |
337 | else if (count < 2) | |
338 | count = 1; | |
339 | else | |
340 | count--; | |
341 | return (u16) count; | |
342 | } | |
343 | ||
344 | /* | |
345 | * IR Control Register helpers | |
346 | */ | |
347 | enum tx_fifo_watermark { | |
348 | TX_FIFO_HALF_EMPTY = 0, | |
349 | TX_FIFO_EMPTY = CNTRL_TIC, | |
350 | }; | |
351 | ||
352 | enum rx_fifo_watermark { | |
353 | RX_FIFO_HALF_FULL = 0, | |
354 | RX_FIFO_NOT_EMPTY = CNTRL_RIC, | |
355 | }; | |
356 | ||
357 | static inline void control_tx_irq_watermark(struct cx23885_dev *dev, | |
358 | enum tx_fifo_watermark level) | |
359 | { | |
360 | cx23888_ir_and_or4(dev, CX23888_IR_CNTRL_REG, ~CNTRL_TIC, level); | |
361 | } | |
362 | ||
363 | static inline void control_rx_irq_watermark(struct cx23885_dev *dev, | |
364 | enum rx_fifo_watermark level) | |
365 | { | |
366 | cx23888_ir_and_or4(dev, CX23888_IR_CNTRL_REG, ~CNTRL_RIC, level); | |
367 | } | |
368 | ||
369 | static inline void control_tx_enable(struct cx23885_dev *dev, bool enable) | |
370 | { | |
371 | cx23888_ir_and_or4(dev, CX23888_IR_CNTRL_REG, ~(CNTRL_TXE | CNTRL_TFE), | |
372 | enable ? (CNTRL_TXE | CNTRL_TFE) : 0); | |
373 | } | |
374 | ||
375 | static inline void control_rx_enable(struct cx23885_dev *dev, bool enable) | |
376 | { | |
377 | cx23888_ir_and_or4(dev, CX23888_IR_CNTRL_REG, ~(CNTRL_RXE | CNTRL_RFE), | |
378 | enable ? (CNTRL_RXE | CNTRL_RFE) : 0); | |
379 | } | |
380 | ||
381 | static inline void control_tx_modulation_enable(struct cx23885_dev *dev, | |
382 | bool enable) | |
383 | { | |
384 | cx23888_ir_and_or4(dev, CX23888_IR_CNTRL_REG, ~CNTRL_MOD, | |
385 | enable ? CNTRL_MOD : 0); | |
386 | } | |
387 | ||
388 | static inline void control_rx_demodulation_enable(struct cx23885_dev *dev, | |
389 | bool enable) | |
390 | { | |
391 | cx23888_ir_and_or4(dev, CX23888_IR_CNTRL_REG, ~CNTRL_DMD, | |
392 | enable ? CNTRL_DMD : 0); | |
393 | } | |
394 | ||
395 | static inline void control_rx_s_edge_detection(struct cx23885_dev *dev, | |
396 | u32 edge_types) | |
397 | { | |
398 | cx23888_ir_and_or4(dev, CX23888_IR_CNTRL_REG, ~CNTRL_EDG_BOTH, | |
399 | edge_types & CNTRL_EDG_BOTH); | |
400 | } | |
401 | ||
402 | static void control_rx_s_carrier_window(struct cx23885_dev *dev, | |
403 | unsigned int carrier, | |
404 | unsigned int *carrier_range_low, | |
405 | unsigned int *carrier_range_high) | |
406 | { | |
407 | u32 v; | |
408 | unsigned int c16 = carrier * 16; | |
409 | ||
410 | if (*carrier_range_low < DIV_ROUND_CLOSEST(c16, 16 + 3)) { | |
411 | v = CNTRL_WIN_3_4; | |
412 | *carrier_range_low = DIV_ROUND_CLOSEST(c16, 16 + 4); | |
413 | } else { | |
414 | v = CNTRL_WIN_3_3; | |
415 | *carrier_range_low = DIV_ROUND_CLOSEST(c16, 16 + 3); | |
416 | } | |
417 | ||
418 | if (*carrier_range_high > DIV_ROUND_CLOSEST(c16, 16 - 3)) { | |
419 | v |= CNTRL_WIN_4_3; | |
420 | *carrier_range_high = DIV_ROUND_CLOSEST(c16, 16 - 4); | |
421 | } else { | |
422 | v |= CNTRL_WIN_3_3; | |
423 | *carrier_range_high = DIV_ROUND_CLOSEST(c16, 16 - 3); | |
424 | } | |
425 | cx23888_ir_and_or4(dev, CX23888_IR_CNTRL_REG, ~CNTRL_WIN, v); | |
426 | } | |
427 | ||
428 | static inline void control_tx_polarity_invert(struct cx23885_dev *dev, | |
429 | bool invert) | |
430 | { | |
431 | cx23888_ir_and_or4(dev, CX23888_IR_CNTRL_REG, ~CNTRL_CPL, | |
432 | invert ? CNTRL_CPL : 0); | |
433 | } | |
434 | ||
5a28d9a3 AW |
435 | static inline void control_tx_level_invert(struct cx23885_dev *dev, |
436 | bool invert) | |
437 | { | |
438 | cx23888_ir_and_or4(dev, CX23888_IR_CNTRL_REG, ~CNTRL_IVO, | |
439 | invert ? CNTRL_IVO : 0); | |
440 | } | |
441 | ||
1a0b9d89 AW |
442 | /* |
443 | * IR Rx & Tx Clock Register helpers | |
444 | */ | |
445 | static unsigned int txclk_tx_s_carrier(struct cx23885_dev *dev, | |
446 | unsigned int freq, | |
447 | u16 *divider) | |
448 | { | |
449 | *divider = carrier_freq_to_clock_divider(freq); | |
450 | cx23888_ir_write4(dev, CX23888_IR_TXCLK_REG, *divider); | |
451 | return clock_divider_to_carrier_freq(*divider); | |
452 | } | |
453 | ||
454 | static unsigned int rxclk_rx_s_carrier(struct cx23885_dev *dev, | |
455 | unsigned int freq, | |
456 | u16 *divider) | |
457 | { | |
458 | *divider = carrier_freq_to_clock_divider(freq); | |
459 | cx23888_ir_write4(dev, CX23888_IR_RXCLK_REG, *divider); | |
460 | return clock_divider_to_carrier_freq(*divider); | |
461 | } | |
462 | ||
463 | static u32 txclk_tx_s_max_pulse_width(struct cx23885_dev *dev, u32 ns, | |
464 | u16 *divider) | |
465 | { | |
466 | u64 pulse_clocks; | |
467 | ||
c02e0d12 AW |
468 | if (ns > IR_MAX_DURATION) |
469 | ns = IR_MAX_DURATION; | |
1a0b9d89 AW |
470 | pulse_clocks = ns_to_pulse_clocks(ns); |
471 | *divider = pulse_clocks_to_clock_divider(pulse_clocks); | |
472 | cx23888_ir_write4(dev, CX23888_IR_TXCLK_REG, *divider); | |
473 | return (u32) pulse_width_count_to_ns(FIFO_RXTX, *divider); | |
474 | } | |
475 | ||
476 | static u32 rxclk_rx_s_max_pulse_width(struct cx23885_dev *dev, u32 ns, | |
477 | u16 *divider) | |
478 | { | |
479 | u64 pulse_clocks; | |
480 | ||
c02e0d12 AW |
481 | if (ns > IR_MAX_DURATION) |
482 | ns = IR_MAX_DURATION; | |
1a0b9d89 AW |
483 | pulse_clocks = ns_to_pulse_clocks(ns); |
484 | *divider = pulse_clocks_to_clock_divider(pulse_clocks); | |
485 | cx23888_ir_write4(dev, CX23888_IR_RXCLK_REG, *divider); | |
486 | return (u32) pulse_width_count_to_ns(FIFO_RXTX, *divider); | |
487 | } | |
488 | ||
489 | /* | |
490 | * IR Tx Carrier Duty Cycle register helpers | |
491 | */ | |
492 | static unsigned int cduty_tx_s_duty_cycle(struct cx23885_dev *dev, | |
493 | unsigned int duty_cycle) | |
494 | { | |
495 | u32 n; | |
496 | n = DIV_ROUND_CLOSEST(duty_cycle * 100, 625); /* 16ths of 100% */ | |
497 | if (n != 0) | |
498 | n--; | |
499 | if (n > 15) | |
500 | n = 15; | |
501 | cx23888_ir_write4(dev, CX23888_IR_CDUTY_REG, n); | |
928213aa | 502 | return DIV_ROUND_CLOSEST((n + 1) * 100, 16); |
1a0b9d89 AW |
503 | } |
504 | ||
505 | /* | |
506 | * IR Filter Register helpers | |
507 | */ | |
508 | static u32 filter_rx_s_min_width(struct cx23885_dev *dev, u32 min_width_ns) | |
509 | { | |
510 | u32 count = ns_to_lpf_count(min_width_ns); | |
511 | cx23888_ir_write4(dev, CX23888_IR_FILTR_REG, count); | |
512 | return lpf_count_to_ns(count); | |
513 | } | |
514 | ||
515 | /* | |
516 | * IR IRQ Enable Register helpers | |
517 | */ | |
518 | static inline void irqenable_rx(struct cx23885_dev *dev, u32 mask) | |
519 | { | |
520 | mask &= (IRQEN_RTE | IRQEN_ROE | IRQEN_RSE); | |
521 | cx23888_ir_and_or4(dev, CX23888_IR_IRQEN_REG, | |
522 | ~(IRQEN_RTE | IRQEN_ROE | IRQEN_RSE), mask); | |
523 | } | |
524 | ||
525 | static inline void irqenable_tx(struct cx23885_dev *dev, u32 mask) | |
526 | { | |
527 | mask &= IRQEN_TSE; | |
528 | cx23888_ir_and_or4(dev, CX23888_IR_IRQEN_REG, ~IRQEN_TSE, mask); | |
529 | } | |
530 | ||
531 | /* | |
532 | * V4L2 Subdevice IR Ops | |
533 | */ | |
534 | static int cx23888_ir_irq_handler(struct v4l2_subdev *sd, u32 status, | |
535 | bool *handled) | |
536 | { | |
537 | struct cx23888_ir_state *state = to_state(sd); | |
538 | struct cx23885_dev *dev = state->dev; | |
7801edb0 | 539 | unsigned long flags; |
1a0b9d89 AW |
540 | |
541 | u32 cntrl = cx23888_ir_read4(dev, CX23888_IR_CNTRL_REG); | |
542 | u32 irqen = cx23888_ir_read4(dev, CX23888_IR_IRQEN_REG); | |
543 | u32 stats = cx23888_ir_read4(dev, CX23888_IR_STATS_REG); | |
544 | ||
c02e0d12 AW |
545 | union cx23888_ir_fifo_rec rx_data[FIFO_RX_DEPTH]; |
546 | unsigned int i, j, k; | |
1a0b9d89 AW |
547 | u32 events, v; |
548 | int tsr, rsr, rto, ror, tse, rse, rte, roe, kror; | |
549 | ||
550 | tsr = stats & STATS_TSR; /* Tx FIFO Service Request */ | |
551 | rsr = stats & STATS_RSR; /* Rx FIFO Service Request */ | |
552 | rto = stats & STATS_RTO; /* Rx Pulse Width Timer Time Out */ | |
553 | ror = stats & STATS_ROR; /* Rx FIFO Over Run */ | |
554 | ||
555 | tse = irqen & IRQEN_TSE; /* Tx FIFO Service Request IRQ Enable */ | |
556 | rse = irqen & IRQEN_RSE; /* Rx FIFO Service Reuqest IRQ Enable */ | |
557 | rte = irqen & IRQEN_RTE; /* Rx Pulse Width Timer Time Out IRQ Enable */ | |
558 | roe = irqen & IRQEN_ROE; /* Rx FIFO Over Run IRQ Enable */ | |
559 | ||
560 | *handled = false; | |
561 | v4l2_dbg(2, ir_888_debug, sd, "IRQ Status: %s %s %s %s %s %s\n", | |
562 | tsr ? "tsr" : " ", rsr ? "rsr" : " ", | |
563 | rto ? "rto" : " ", ror ? "ror" : " ", | |
564 | stats & STATS_TBY ? "tby" : " ", | |
565 | stats & STATS_RBY ? "rby" : " "); | |
566 | ||
567 | v4l2_dbg(2, ir_888_debug, sd, "IRQ Enables: %s %s %s %s\n", | |
568 | tse ? "tse" : " ", rse ? "rse" : " ", | |
569 | rte ? "rte" : " ", roe ? "roe" : " "); | |
570 | ||
571 | /* | |
572 | * Transmitter interrupt service | |
573 | */ | |
574 | if (tse && tsr) { | |
575 | /* | |
576 | * TODO: | |
577 | * Check the watermark threshold setting | |
578 | * Pull FIFO_TX_DEPTH or FIFO_TX_DEPTH/2 entries from tx_kfifo | |
579 | * Push the data to the hardware FIFO. | |
580 | * If there was nothing more to send in the tx_kfifo, disable | |
581 | * the TSR IRQ and notify the v4l2_device. | |
582 | * If there was something in the tx_kfifo, check the tx_kfifo | |
583 | * level and notify the v4l2_device, if it is low. | |
584 | */ | |
585 | /* For now, inhibit TSR interrupt until Tx is implemented */ | |
586 | irqenable_tx(dev, 0); | |
587 | events = V4L2_SUBDEV_IR_TX_FIFO_SERVICE_REQ; | |
588 | v4l2_subdev_notify(sd, V4L2_SUBDEV_IR_TX_NOTIFY, &events); | |
589 | *handled = true; | |
590 | } | |
591 | ||
592 | /* | |
593 | * Receiver interrupt service | |
594 | */ | |
595 | kror = 0; | |
596 | if ((rse && rsr) || (rte && rto)) { | |
597 | /* | |
598 | * Receive data on RSR to clear the STATS_RSR. | |
599 | * Receive data on RTO, since we may not have yet hit the RSR | |
600 | * watermark when we receive the RTO. | |
601 | */ | |
602 | for (i = 0, v = FIFO_RX_NDV; | |
603 | (v & FIFO_RX_NDV) && !kror; i = 0) { | |
604 | for (j = 0; | |
605 | (v & FIFO_RX_NDV) && j < FIFO_RX_DEPTH; j++) { | |
606 | v = cx23888_ir_read4(dev, CX23888_IR_FIFO_REG); | |
c02e0d12 AW |
607 | rx_data[i].hw_fifo_data = v & ~FIFO_RX_NDV; |
608 | i++; | |
1a0b9d89 AW |
609 | } |
610 | if (i == 0) | |
611 | break; | |
c02e0d12 | 612 | j = i * sizeof(union cx23888_ir_fifo_rec); |
7801edb0 SS |
613 | k = kfifo_in_locked(&state->rx_kfifo, |
614 | (unsigned char *) rx_data, j, | |
615 | &state->rx_kfifo_lock); | |
1a0b9d89 AW |
616 | if (k != j) |
617 | kror++; /* rx_kfifo over run */ | |
618 | } | |
619 | *handled = true; | |
620 | } | |
621 | ||
622 | events = 0; | |
623 | v = 0; | |
624 | if (kror) { | |
625 | events |= V4L2_SUBDEV_IR_RX_SW_FIFO_OVERRUN; | |
626 | v4l2_err(sd, "IR receiver software FIFO overrun\n"); | |
627 | } | |
628 | if (roe && ror) { | |
629 | /* | |
630 | * The RX FIFO Enable (CNTRL_RFE) must be toggled to clear | |
631 | * the Rx FIFO Over Run status (STATS_ROR) | |
632 | */ | |
633 | v |= CNTRL_RFE; | |
634 | events |= V4L2_SUBDEV_IR_RX_HW_FIFO_OVERRUN; | |
635 | v4l2_err(sd, "IR receiver hardware FIFO overrun\n"); | |
636 | } | |
637 | if (rte && rto) { | |
638 | /* | |
639 | * The IR Receiver Enable (CNTRL_RXE) must be toggled to clear | |
640 | * the Rx Pulse Width Timer Time Out (STATS_RTO) | |
641 | */ | |
642 | v |= CNTRL_RXE; | |
643 | events |= V4L2_SUBDEV_IR_RX_END_OF_RX_DETECTED; | |
644 | } | |
645 | if (v) { | |
646 | /* Clear STATS_ROR & STATS_RTO as needed by reseting hardware */ | |
647 | cx23888_ir_write4(dev, CX23888_IR_CNTRL_REG, cntrl & ~v); | |
648 | cx23888_ir_write4(dev, CX23888_IR_CNTRL_REG, cntrl); | |
649 | *handled = true; | |
650 | } | |
7801edb0 SS |
651 | |
652 | spin_lock_irqsave(&state->rx_kfifo_lock, flags); | |
653 | if (kfifo_len(&state->rx_kfifo) >= CX23888_IR_RX_KFIFO_SIZE / 2) | |
1a0b9d89 | 654 | events |= V4L2_SUBDEV_IR_RX_FIFO_SERVICE_REQ; |
7801edb0 | 655 | spin_unlock_irqrestore(&state->rx_kfifo_lock, flags); |
1a0b9d89 AW |
656 | |
657 | if (events) | |
658 | v4l2_subdev_notify(sd, V4L2_SUBDEV_IR_RX_NOTIFY, &events); | |
29f8a0a5 AW |
659 | return 0; |
660 | } | |
661 | ||
1a0b9d89 AW |
662 | /* Receiver */ |
663 | static int cx23888_ir_rx_read(struct v4l2_subdev *sd, u8 *buf, size_t count, | |
664 | ssize_t *num) | |
29f8a0a5 | 665 | { |
1a0b9d89 AW |
666 | struct cx23888_ir_state *state = to_state(sd); |
667 | bool invert = (bool) atomic_read(&state->rx_invert); | |
668 | u16 divider = (u16) atomic_read(&state->rxclk_divider); | |
669 | ||
670 | unsigned int i, n; | |
c02e0d12 | 671 | union cx23888_ir_fifo_rec *p; |
bd829e9d | 672 | unsigned u, v, w; |
1a0b9d89 | 673 | |
c02e0d12 AW |
674 | n = count / sizeof(union cx23888_ir_fifo_rec) |
675 | * sizeof(union cx23888_ir_fifo_rec); | |
1a0b9d89 AW |
676 | if (n == 0) { |
677 | *num = 0; | |
678 | return 0; | |
679 | } | |
680 | ||
7801edb0 | 681 | n = kfifo_out_locked(&state->rx_kfifo, buf, n, &state->rx_kfifo_lock); |
1a0b9d89 | 682 | |
c02e0d12 AW |
683 | n /= sizeof(union cx23888_ir_fifo_rec); |
684 | *num = n * sizeof(union cx23888_ir_fifo_rec); | |
1a0b9d89 | 685 | |
c02e0d12 | 686 | for (p = (union cx23888_ir_fifo_rec *) buf, i = 0; i < n; p++, i++) { |
2560d94e | 687 | |
c02e0d12 | 688 | if ((p->hw_fifo_data & FIFO_RXTX_RTO) == FIFO_RXTX_RTO) { |
2560d94e AW |
689 | /* Assume RTO was because of no IR light input */ |
690 | u = 0; | |
bd829e9d | 691 | w = 1; |
2560d94e | 692 | } else { |
c02e0d12 | 693 | u = (p->hw_fifo_data & FIFO_RXTX_LVL) ? 1 : 0; |
2560d94e | 694 | if (invert) |
c02e0d12 | 695 | u = u ? 0 : 1; |
bd829e9d | 696 | w = 0; |
1a0b9d89 AW |
697 | } |
698 | ||
c02e0d12 AW |
699 | v = (unsigned) pulse_width_count_to_ns( |
700 | (u16) (p->hw_fifo_data & FIFO_RXTX), divider); | |
701 | if (v > IR_MAX_DURATION) | |
702 | v = IR_MAX_DURATION; | |
1a0b9d89 | 703 | |
dc697984 | 704 | init_ir_raw_event(&p->ir_core_data); |
c02e0d12 AW |
705 | p->ir_core_data.pulse = u; |
706 | p->ir_core_data.duration = v; | |
bd829e9d | 707 | p->ir_core_data.timeout = w; |
1a0b9d89 | 708 | |
bd829e9d AW |
709 | v4l2_dbg(2, ir_888_debug, sd, "rx read: %10u ns %s %s\n", |
710 | v, u ? "mark" : "space", w ? "(timed out)" : ""); | |
711 | if (w) | |
712 | v4l2_dbg(2, ir_888_debug, sd, "rx read: end of rx\n"); | |
1a0b9d89 AW |
713 | } |
714 | return 0; | |
29f8a0a5 AW |
715 | } |
716 | ||
1a0b9d89 AW |
717 | static int cx23888_ir_rx_g_parameters(struct v4l2_subdev *sd, |
718 | struct v4l2_subdev_ir_parameters *p) | |
29f8a0a5 | 719 | { |
1a0b9d89 AW |
720 | struct cx23888_ir_state *state = to_state(sd); |
721 | mutex_lock(&state->rx_params_lock); | |
722 | memcpy(p, &state->rx_params, sizeof(struct v4l2_subdev_ir_parameters)); | |
723 | mutex_unlock(&state->rx_params_lock); | |
724 | return 0; | |
29f8a0a5 AW |
725 | } |
726 | ||
1a0b9d89 | 727 | static int cx23888_ir_rx_shutdown(struct v4l2_subdev *sd) |
29f8a0a5 | 728 | { |
1a0b9d89 AW |
729 | struct cx23888_ir_state *state = to_state(sd); |
730 | struct cx23885_dev *dev = state->dev; | |
731 | ||
732 | mutex_lock(&state->rx_params_lock); | |
733 | ||
734 | /* Disable or slow down all IR Rx circuits and counters */ | |
735 | irqenable_rx(dev, 0); | |
736 | control_rx_enable(dev, false); | |
737 | control_rx_demodulation_enable(dev, false); | |
738 | control_rx_s_edge_detection(dev, CNTRL_EDG_NONE); | |
739 | filter_rx_s_min_width(dev, 0); | |
740 | cx23888_ir_write4(dev, CX23888_IR_RXCLK_REG, RXCLK_RCD); | |
741 | ||
742 | state->rx_params.shutdown = true; | |
743 | ||
744 | mutex_unlock(&state->rx_params_lock); | |
745 | return 0; | |
29f8a0a5 AW |
746 | } |
747 | ||
1a0b9d89 AW |
748 | static int cx23888_ir_rx_s_parameters(struct v4l2_subdev *sd, |
749 | struct v4l2_subdev_ir_parameters *p) | |
29f8a0a5 | 750 | { |
1a0b9d89 AW |
751 | struct cx23888_ir_state *state = to_state(sd); |
752 | struct cx23885_dev *dev = state->dev; | |
753 | struct v4l2_subdev_ir_parameters *o = &state->rx_params; | |
754 | u16 rxclk_divider; | |
755 | ||
756 | if (p->shutdown) | |
757 | return cx23888_ir_rx_shutdown(sd); | |
758 | ||
759 | if (p->mode != V4L2_SUBDEV_IR_MODE_PULSE_WIDTH) | |
760 | return -ENOSYS; | |
761 | ||
762 | mutex_lock(&state->rx_params_lock); | |
763 | ||
764 | o->shutdown = p->shutdown; | |
765 | ||
766 | o->mode = p->mode = V4L2_SUBDEV_IR_MODE_PULSE_WIDTH; | |
767 | ||
c02e0d12 AW |
768 | o->bytes_per_data_element = p->bytes_per_data_element |
769 | = sizeof(union cx23888_ir_fifo_rec); | |
1a0b9d89 AW |
770 | |
771 | /* Before we tweak the hardware, we have to disable the receiver */ | |
772 | irqenable_rx(dev, 0); | |
773 | control_rx_enable(dev, false); | |
774 | ||
775 | control_rx_demodulation_enable(dev, p->modulation); | |
776 | o->modulation = p->modulation; | |
777 | ||
778 | if (p->modulation) { | |
779 | p->carrier_freq = rxclk_rx_s_carrier(dev, p->carrier_freq, | |
780 | &rxclk_divider); | |
781 | ||
782 | o->carrier_freq = p->carrier_freq; | |
783 | ||
784 | o->duty_cycle = p->duty_cycle = 50; | |
785 | ||
786 | control_rx_s_carrier_window(dev, p->carrier_freq, | |
787 | &p->carrier_range_lower, | |
788 | &p->carrier_range_upper); | |
789 | o->carrier_range_lower = p->carrier_range_lower; | |
790 | o->carrier_range_upper = p->carrier_range_upper; | |
ceb152ad AW |
791 | |
792 | p->max_pulse_width = | |
793 | (u32) pulse_width_count_to_ns(FIFO_RXTX, rxclk_divider); | |
1a0b9d89 AW |
794 | } else { |
795 | p->max_pulse_width = | |
796 | rxclk_rx_s_max_pulse_width(dev, p->max_pulse_width, | |
797 | &rxclk_divider); | |
1a0b9d89 | 798 | } |
ceb152ad | 799 | o->max_pulse_width = p->max_pulse_width; |
1a0b9d89 AW |
800 | atomic_set(&state->rxclk_divider, rxclk_divider); |
801 | ||
802 | p->noise_filter_min_width = | |
803 | filter_rx_s_min_width(dev, p->noise_filter_min_width); | |
804 | o->noise_filter_min_width = p->noise_filter_min_width; | |
805 | ||
806 | p->resolution = clock_divider_to_resolution(rxclk_divider); | |
807 | o->resolution = p->resolution; | |
808 | ||
809 | /* FIXME - make this dependent on resolution for better performance */ | |
810 | control_rx_irq_watermark(dev, RX_FIFO_HALF_FULL); | |
811 | ||
812 | control_rx_s_edge_detection(dev, CNTRL_EDG_BOTH); | |
813 | ||
5a28d9a3 AW |
814 | o->invert_level = p->invert_level; |
815 | atomic_set(&state->rx_invert, p->invert_level); | |
1a0b9d89 AW |
816 | |
817 | o->interrupt_enable = p->interrupt_enable; | |
818 | o->enable = p->enable; | |
819 | if (p->enable) { | |
7801edb0 SS |
820 | unsigned long flags; |
821 | ||
822 | spin_lock_irqsave(&state->rx_kfifo_lock, flags); | |
823 | kfifo_reset(&state->rx_kfifo); | |
824 | /* reset tx_fifo too if there is one... */ | |
825 | spin_unlock_irqrestore(&state->rx_kfifo_lock, flags); | |
1a0b9d89 AW |
826 | if (p->interrupt_enable) |
827 | irqenable_rx(dev, IRQEN_RSE | IRQEN_RTE | IRQEN_ROE); | |
828 | control_rx_enable(dev, p->enable); | |
829 | } | |
830 | ||
831 | mutex_unlock(&state->rx_params_lock); | |
832 | return 0; | |
833 | } | |
834 | ||
835 | /* Transmitter */ | |
836 | static int cx23888_ir_tx_write(struct v4l2_subdev *sd, u8 *buf, size_t count, | |
837 | ssize_t *num) | |
838 | { | |
839 | struct cx23888_ir_state *state = to_state(sd); | |
840 | struct cx23885_dev *dev = state->dev; | |
841 | /* For now enable the Tx FIFO Service interrupt & pretend we did work */ | |
842 | irqenable_tx(dev, IRQEN_TSE); | |
843 | *num = count; | |
844 | return 0; | |
845 | } | |
846 | ||
847 | static int cx23888_ir_tx_g_parameters(struct v4l2_subdev *sd, | |
848 | struct v4l2_subdev_ir_parameters *p) | |
849 | { | |
850 | struct cx23888_ir_state *state = to_state(sd); | |
851 | mutex_lock(&state->tx_params_lock); | |
852 | memcpy(p, &state->tx_params, sizeof(struct v4l2_subdev_ir_parameters)); | |
853 | mutex_unlock(&state->tx_params_lock); | |
29f8a0a5 AW |
854 | return 0; |
855 | } | |
856 | ||
1a0b9d89 AW |
857 | static int cx23888_ir_tx_shutdown(struct v4l2_subdev *sd) |
858 | { | |
859 | struct cx23888_ir_state *state = to_state(sd); | |
860 | struct cx23885_dev *dev = state->dev; | |
861 | ||
862 | mutex_lock(&state->tx_params_lock); | |
863 | ||
864 | /* Disable or slow down all IR Tx circuits and counters */ | |
865 | irqenable_tx(dev, 0); | |
866 | control_tx_enable(dev, false); | |
867 | control_tx_modulation_enable(dev, false); | |
868 | cx23888_ir_write4(dev, CX23888_IR_TXCLK_REG, TXCLK_TCD); | |
869 | ||
870 | state->tx_params.shutdown = true; | |
871 | ||
872 | mutex_unlock(&state->tx_params_lock); | |
873 | return 0; | |
874 | } | |
875 | ||
876 | static int cx23888_ir_tx_s_parameters(struct v4l2_subdev *sd, | |
877 | struct v4l2_subdev_ir_parameters *p) | |
878 | { | |
879 | struct cx23888_ir_state *state = to_state(sd); | |
880 | struct cx23885_dev *dev = state->dev; | |
881 | struct v4l2_subdev_ir_parameters *o = &state->tx_params; | |
882 | u16 txclk_divider; | |
883 | ||
884 | if (p->shutdown) | |
885 | return cx23888_ir_tx_shutdown(sd); | |
886 | ||
887 | if (p->mode != V4L2_SUBDEV_IR_MODE_PULSE_WIDTH) | |
888 | return -ENOSYS; | |
889 | ||
890 | mutex_lock(&state->tx_params_lock); | |
891 | ||
892 | o->shutdown = p->shutdown; | |
893 | ||
894 | o->mode = p->mode = V4L2_SUBDEV_IR_MODE_PULSE_WIDTH; | |
895 | ||
c02e0d12 AW |
896 | o->bytes_per_data_element = p->bytes_per_data_element |
897 | = sizeof(union cx23888_ir_fifo_rec); | |
1a0b9d89 AW |
898 | |
899 | /* Before we tweak the hardware, we have to disable the transmitter */ | |
900 | irqenable_tx(dev, 0); | |
901 | control_tx_enable(dev, false); | |
902 | ||
903 | control_tx_modulation_enable(dev, p->modulation); | |
904 | o->modulation = p->modulation; | |
905 | ||
906 | if (p->modulation) { | |
907 | p->carrier_freq = txclk_tx_s_carrier(dev, p->carrier_freq, | |
908 | &txclk_divider); | |
909 | o->carrier_freq = p->carrier_freq; | |
910 | ||
911 | p->duty_cycle = cduty_tx_s_duty_cycle(dev, p->duty_cycle); | |
912 | o->duty_cycle = p->duty_cycle; | |
ceb152ad AW |
913 | |
914 | p->max_pulse_width = | |
915 | (u32) pulse_width_count_to_ns(FIFO_RXTX, txclk_divider); | |
1a0b9d89 AW |
916 | } else { |
917 | p->max_pulse_width = | |
918 | txclk_tx_s_max_pulse_width(dev, p->max_pulse_width, | |
919 | &txclk_divider); | |
1a0b9d89 | 920 | } |
ceb152ad | 921 | o->max_pulse_width = p->max_pulse_width; |
1a0b9d89 AW |
922 | atomic_set(&state->txclk_divider, txclk_divider); |
923 | ||
924 | p->resolution = clock_divider_to_resolution(txclk_divider); | |
925 | o->resolution = p->resolution; | |
926 | ||
927 | /* FIXME - make this dependent on resolution for better performance */ | |
928 | control_tx_irq_watermark(dev, TX_FIFO_HALF_EMPTY); | |
929 | ||
5a28d9a3 AW |
930 | control_tx_polarity_invert(dev, p->invert_carrier_sense); |
931 | o->invert_carrier_sense = p->invert_carrier_sense; | |
932 | ||
933 | control_tx_level_invert(dev, p->invert_level); | |
934 | o->invert_level = p->invert_level; | |
1a0b9d89 AW |
935 | |
936 | o->interrupt_enable = p->interrupt_enable; | |
937 | o->enable = p->enable; | |
938 | if (p->enable) { | |
1a0b9d89 AW |
939 | if (p->interrupt_enable) |
940 | irqenable_tx(dev, IRQEN_TSE); | |
941 | control_tx_enable(dev, p->enable); | |
942 | } | |
943 | ||
944 | mutex_unlock(&state->tx_params_lock); | |
945 | return 0; | |
946 | } | |
947 | ||
948 | ||
949 | /* | |
950 | * V4L2 Subdevice Core Ops | |
951 | */ | |
29f8a0a5 AW |
952 | static int cx23888_ir_log_status(struct v4l2_subdev *sd) |
953 | { | |
954 | struct cx23888_ir_state *state = to_state(sd); | |
955 | struct cx23885_dev *dev = state->dev; | |
1a0b9d89 AW |
956 | char *s; |
957 | int i, j; | |
958 | ||
959 | u32 cntrl = cx23888_ir_read4(dev, CX23888_IR_CNTRL_REG); | |
960 | u32 txclk = cx23888_ir_read4(dev, CX23888_IR_TXCLK_REG) & TXCLK_TCD; | |
961 | u32 rxclk = cx23888_ir_read4(dev, CX23888_IR_RXCLK_REG) & RXCLK_RCD; | |
962 | u32 cduty = cx23888_ir_read4(dev, CX23888_IR_CDUTY_REG) & CDUTY_CDC; | |
963 | u32 stats = cx23888_ir_read4(dev, CX23888_IR_STATS_REG); | |
964 | u32 irqen = cx23888_ir_read4(dev, CX23888_IR_IRQEN_REG); | |
965 | u32 filtr = cx23888_ir_read4(dev, CX23888_IR_FILTR_REG) & FILTR_LPF; | |
966 | ||
967 | v4l2_info(sd, "IR Receiver:\n"); | |
968 | v4l2_info(sd, "\tEnabled: %s\n", | |
969 | cntrl & CNTRL_RXE ? "yes" : "no"); | |
970 | v4l2_info(sd, "\tDemodulation from a carrier: %s\n", | |
971 | cntrl & CNTRL_DMD ? "enabled" : "disabled"); | |
972 | v4l2_info(sd, "\tFIFO: %s\n", | |
973 | cntrl & CNTRL_RFE ? "enabled" : "disabled"); | |
974 | switch (cntrl & CNTRL_EDG) { | |
975 | case CNTRL_EDG_NONE: | |
976 | s = "disabled"; | |
977 | break; | |
978 | case CNTRL_EDG_FALL: | |
979 | s = "falling edge"; | |
980 | break; | |
981 | case CNTRL_EDG_RISE: | |
982 | s = "rising edge"; | |
983 | break; | |
984 | case CNTRL_EDG_BOTH: | |
985 | s = "rising & falling edges"; | |
986 | break; | |
987 | default: | |
988 | s = "??? edge"; | |
989 | break; | |
990 | } | |
991 | v4l2_info(sd, "\tPulse timers' start/stop trigger: %s\n", s); | |
992 | v4l2_info(sd, "\tFIFO data on pulse timer overflow: %s\n", | |
993 | cntrl & CNTRL_R ? "not loaded" : "overflow marker"); | |
994 | v4l2_info(sd, "\tFIFO interrupt watermark: %s\n", | |
995 | cntrl & CNTRL_RIC ? "not empty" : "half full or greater"); | |
996 | v4l2_info(sd, "\tLoopback mode: %s\n", | |
997 | cntrl & CNTRL_LBM ? "loopback active" : "normal receive"); | |
998 | if (cntrl & CNTRL_DMD) { | |
999 | v4l2_info(sd, "\tExpected carrier (16 clocks): %u Hz\n", | |
1000 | clock_divider_to_carrier_freq(rxclk)); | |
1001 | switch (cntrl & CNTRL_WIN) { | |
1002 | case CNTRL_WIN_3_3: | |
1003 | i = 3; | |
1004 | j = 3; | |
1005 | break; | |
1006 | case CNTRL_WIN_4_3: | |
1007 | i = 4; | |
1008 | j = 3; | |
1009 | break; | |
1010 | case CNTRL_WIN_3_4: | |
1011 | i = 3; | |
1012 | j = 4; | |
1013 | break; | |
1014 | case CNTRL_WIN_4_4: | |
1015 | i = 4; | |
1016 | j = 4; | |
1017 | break; | |
1018 | default: | |
1019 | i = 0; | |
1020 | j = 0; | |
1021 | break; | |
1022 | } | |
1023 | v4l2_info(sd, "\tNext carrier edge window: 16 clocks " | |
1024 | "-%1d/+%1d, %u to %u Hz\n", i, j, | |
1025 | clock_divider_to_freq(rxclk, 16 + j), | |
1026 | clock_divider_to_freq(rxclk, 16 - i)); | |
1a0b9d89 | 1027 | } |
ceb152ad AW |
1028 | v4l2_info(sd, "\tMax measurable pulse width: %u us, %llu ns\n", |
1029 | pulse_width_count_to_us(FIFO_RXTX, rxclk), | |
1030 | pulse_width_count_to_ns(FIFO_RXTX, rxclk)); | |
1a0b9d89 AW |
1031 | v4l2_info(sd, "\tLow pass filter: %s\n", |
1032 | filtr ? "enabled" : "disabled"); | |
1033 | if (filtr) | |
1034 | v4l2_info(sd, "\tMin acceptable pulse width (LPF): %u us, " | |
1035 | "%u ns\n", | |
1036 | lpf_count_to_us(filtr), | |
1037 | lpf_count_to_ns(filtr)); | |
1038 | v4l2_info(sd, "\tPulse width timer timed-out: %s\n", | |
1039 | stats & STATS_RTO ? "yes" : "no"); | |
1040 | v4l2_info(sd, "\tPulse width timer time-out intr: %s\n", | |
1041 | irqen & IRQEN_RTE ? "enabled" : "disabled"); | |
1042 | v4l2_info(sd, "\tFIFO overrun: %s\n", | |
1043 | stats & STATS_ROR ? "yes" : "no"); | |
1044 | v4l2_info(sd, "\tFIFO overrun interrupt: %s\n", | |
1045 | irqen & IRQEN_ROE ? "enabled" : "disabled"); | |
1046 | v4l2_info(sd, "\tBusy: %s\n", | |
1047 | stats & STATS_RBY ? "yes" : "no"); | |
1048 | v4l2_info(sd, "\tFIFO service requested: %s\n", | |
1049 | stats & STATS_RSR ? "yes" : "no"); | |
1050 | v4l2_info(sd, "\tFIFO service request interrupt: %s\n", | |
1051 | irqen & IRQEN_RSE ? "enabled" : "disabled"); | |
1052 | ||
1053 | v4l2_info(sd, "IR Transmitter:\n"); | |
1054 | v4l2_info(sd, "\tEnabled: %s\n", | |
1055 | cntrl & CNTRL_TXE ? "yes" : "no"); | |
1056 | v4l2_info(sd, "\tModulation onto a carrier: %s\n", | |
1057 | cntrl & CNTRL_MOD ? "enabled" : "disabled"); | |
1058 | v4l2_info(sd, "\tFIFO: %s\n", | |
1059 | cntrl & CNTRL_TFE ? "enabled" : "disabled"); | |
1060 | v4l2_info(sd, "\tFIFO interrupt watermark: %s\n", | |
1061 | cntrl & CNTRL_TIC ? "not empty" : "half full or less"); | |
5a28d9a3 AW |
1062 | v4l2_info(sd, "\tOutput pin level inversion %s\n", |
1063 | cntrl & CNTRL_IVO ? "yes" : "no"); | |
1064 | v4l2_info(sd, "\tCarrier polarity: %s\n", | |
1065 | cntrl & CNTRL_CPL ? "space:burst mark:noburst" | |
1066 | : "space:noburst mark:burst"); | |
1a0b9d89 AW |
1067 | if (cntrl & CNTRL_MOD) { |
1068 | v4l2_info(sd, "\tCarrier (16 clocks): %u Hz\n", | |
1069 | clock_divider_to_carrier_freq(txclk)); | |
1070 | v4l2_info(sd, "\tCarrier duty cycle: %2u/16\n", | |
1071 | cduty + 1); | |
1a0b9d89 | 1072 | } |
ceb152ad AW |
1073 | v4l2_info(sd, "\tMax pulse width: %u us, %llu ns\n", |
1074 | pulse_width_count_to_us(FIFO_RXTX, txclk), | |
1075 | pulse_width_count_to_ns(FIFO_RXTX, txclk)); | |
1a0b9d89 AW |
1076 | v4l2_info(sd, "\tBusy: %s\n", |
1077 | stats & STATS_TBY ? "yes" : "no"); | |
1078 | v4l2_info(sd, "\tFIFO service requested: %s\n", | |
1079 | stats & STATS_TSR ? "yes" : "no"); | |
1080 | v4l2_info(sd, "\tFIFO service request interrupt: %s\n", | |
1081 | irqen & IRQEN_TSE ? "enabled" : "disabled"); | |
1082 | ||
29f8a0a5 AW |
1083 | return 0; |
1084 | } | |
1085 | ||
29f8a0a5 AW |
1086 | #ifdef CONFIG_VIDEO_ADV_DEBUG |
1087 | static int cx23888_ir_g_register(struct v4l2_subdev *sd, | |
1088 | struct v4l2_dbg_register *reg) | |
1089 | { | |
1090 | struct cx23888_ir_state *state = to_state(sd); | |
1091 | u32 addr = CX23888_IR_REG_BASE + (u32) reg->reg; | |
1092 | ||
29f8a0a5 AW |
1093 | if ((addr & 0x3) != 0) |
1094 | return -EINVAL; | |
1095 | if (addr < CX23888_IR_CNTRL_REG || addr > CX23888_IR_LEARN_REG) | |
1096 | return -EINVAL; | |
29f8a0a5 AW |
1097 | reg->size = 4; |
1098 | reg->val = cx23888_ir_read4(state->dev, addr); | |
1099 | return 0; | |
1100 | } | |
1101 | ||
1102 | static int cx23888_ir_s_register(struct v4l2_subdev *sd, | |
977ba3b1 | 1103 | const struct v4l2_dbg_register *reg) |
29f8a0a5 AW |
1104 | { |
1105 | struct cx23888_ir_state *state = to_state(sd); | |
1106 | u32 addr = CX23888_IR_REG_BASE + (u32) reg->reg; | |
1107 | ||
29f8a0a5 AW |
1108 | if ((addr & 0x3) != 0) |
1109 | return -EINVAL; | |
1110 | if (addr < CX23888_IR_CNTRL_REG || addr > CX23888_IR_LEARN_REG) | |
1111 | return -EINVAL; | |
29f8a0a5 AW |
1112 | cx23888_ir_write4(state->dev, addr, reg->val); |
1113 | return 0; | |
1114 | } | |
1115 | #endif | |
1116 | ||
1117 | static const struct v4l2_subdev_core_ops cx23888_ir_core_ops = { | |
29f8a0a5 AW |
1118 | .log_status = cx23888_ir_log_status, |
1119 | #ifdef CONFIG_VIDEO_ADV_DEBUG | |
1120 | .g_register = cx23888_ir_g_register, | |
1121 | .s_register = cx23888_ir_s_register, | |
1122 | #endif | |
260e689b | 1123 | .interrupt_service_routine = cx23888_ir_irq_handler, |
29f8a0a5 AW |
1124 | }; |
1125 | ||
1a0b9d89 | 1126 | static const struct v4l2_subdev_ir_ops cx23888_ir_ir_ops = { |
1a0b9d89 AW |
1127 | .rx_read = cx23888_ir_rx_read, |
1128 | .rx_g_parameters = cx23888_ir_rx_g_parameters, | |
1129 | .rx_s_parameters = cx23888_ir_rx_s_parameters, | |
1130 | ||
1131 | .tx_write = cx23888_ir_tx_write, | |
1132 | .tx_g_parameters = cx23888_ir_tx_g_parameters, | |
1133 | .tx_s_parameters = cx23888_ir_tx_s_parameters, | |
1134 | }; | |
1135 | ||
29f8a0a5 AW |
1136 | static const struct v4l2_subdev_ops cx23888_ir_controller_ops = { |
1137 | .core = &cx23888_ir_core_ops, | |
1a0b9d89 AW |
1138 | .ir = &cx23888_ir_ir_ops, |
1139 | }; | |
1140 | ||
1141 | static const struct v4l2_subdev_ir_parameters default_rx_params = { | |
c02e0d12 | 1142 | .bytes_per_data_element = sizeof(union cx23888_ir_fifo_rec), |
1a0b9d89 AW |
1143 | .mode = V4L2_SUBDEV_IR_MODE_PULSE_WIDTH, |
1144 | ||
1145 | .enable = false, | |
1146 | .interrupt_enable = false, | |
1147 | .shutdown = true, | |
1148 | ||
1149 | .modulation = true, | |
1150 | .carrier_freq = 36000, /* 36 kHz - RC-5, RC-6, and RC-6A carrier */ | |
1151 | ||
1152 | /* RC-5: 666,667 ns = 1/36 kHz * 32 cycles * 1 mark * 0.75 */ | |
1153 | /* RC-6A: 333,333 ns = 1/36 kHz * 16 cycles * 1 mark * 0.75 */ | |
1154 | .noise_filter_min_width = 333333, /* ns */ | |
1155 | .carrier_range_lower = 35000, | |
1156 | .carrier_range_upper = 37000, | |
5a28d9a3 | 1157 | .invert_level = false, |
1a0b9d89 AW |
1158 | }; |
1159 | ||
1160 | static const struct v4l2_subdev_ir_parameters default_tx_params = { | |
c02e0d12 | 1161 | .bytes_per_data_element = sizeof(union cx23888_ir_fifo_rec), |
1a0b9d89 AW |
1162 | .mode = V4L2_SUBDEV_IR_MODE_PULSE_WIDTH, |
1163 | ||
1164 | .enable = false, | |
1165 | .interrupt_enable = false, | |
1166 | .shutdown = true, | |
1167 | ||
1168 | .modulation = true, | |
1169 | .carrier_freq = 36000, /* 36 kHz - RC-5 carrier */ | |
1170 | .duty_cycle = 25, /* 25 % - RC-5 carrier */ | |
5a28d9a3 AW |
1171 | .invert_level = false, |
1172 | .invert_carrier_sense = false, | |
29f8a0a5 AW |
1173 | }; |
1174 | ||
1175 | int cx23888_ir_probe(struct cx23885_dev *dev) | |
1176 | { | |
1177 | struct cx23888_ir_state *state; | |
1178 | struct v4l2_subdev *sd; | |
1a0b9d89 AW |
1179 | struct v4l2_subdev_ir_parameters default_params; |
1180 | int ret; | |
29f8a0a5 AW |
1181 | |
1182 | state = kzalloc(sizeof(struct cx23888_ir_state), GFP_KERNEL); | |
1183 | if (state == NULL) | |
1184 | return -ENOMEM; | |
1185 | ||
1a0b9d89 | 1186 | spin_lock_init(&state->rx_kfifo_lock); |
7801edb0 | 1187 | if (kfifo_alloc(&state->rx_kfifo, CX23888_IR_RX_KFIFO_SIZE, GFP_KERNEL)) |
1a0b9d89 | 1188 | return -ENOMEM; |
1a0b9d89 | 1189 | |
29f8a0a5 | 1190 | state->dev = dev; |
29f8a0a5 AW |
1191 | sd = &state->sd; |
1192 | ||
1193 | v4l2_subdev_init(sd, &cx23888_ir_controller_ops); | |
1194 | v4l2_set_subdevdata(sd, state); | |
1195 | /* FIXME - fix the formatting of dev->v4l2_dev.name and use it */ | |
1196 | snprintf(sd->name, sizeof(sd->name), "%s/888-ir", dev->name); | |
1197 | sd->grp_id = CX23885_HW_888_IR; | |
1a0b9d89 AW |
1198 | |
1199 | ret = v4l2_device_register_subdev(&dev->v4l2_dev, sd); | |
1200 | if (ret == 0) { | |
1201 | /* | |
1202 | * Ensure no interrupts arrive from '888 specific conditions, | |
1203 | * since we ignore them in this driver to have commonality with | |
1204 | * similar IR controller cores. | |
1205 | */ | |
1206 | cx23888_ir_write4(dev, CX23888_IR_IRQEN_REG, 0); | |
1207 | ||
1208 | mutex_init(&state->rx_params_lock); | |
3618acab | 1209 | default_params = default_rx_params; |
1a0b9d89 AW |
1210 | v4l2_subdev_call(sd, ir, rx_s_parameters, &default_params); |
1211 | ||
1212 | mutex_init(&state->tx_params_lock); | |
3618acab | 1213 | default_params = default_tx_params; |
1a0b9d89 AW |
1214 | v4l2_subdev_call(sd, ir, tx_s_parameters, &default_params); |
1215 | } else { | |
7801edb0 | 1216 | kfifo_free(&state->rx_kfifo); |
1a0b9d89 AW |
1217 | } |
1218 | return ret; | |
29f8a0a5 AW |
1219 | } |
1220 | ||
1221 | int cx23888_ir_remove(struct cx23885_dev *dev) | |
1222 | { | |
1223 | struct v4l2_subdev *sd; | |
1224 | struct cx23888_ir_state *state; | |
1225 | ||
1226 | sd = cx23885_find_hw(dev, CX23885_HW_888_IR); | |
1227 | if (sd == NULL) | |
1228 | return -ENODEV; | |
1229 | ||
1a0b9d89 AW |
1230 | cx23888_ir_rx_shutdown(sd); |
1231 | cx23888_ir_tx_shutdown(sd); | |
29f8a0a5 AW |
1232 | |
1233 | state = to_state(sd); | |
1234 | v4l2_device_unregister_subdev(sd); | |
7801edb0 | 1235 | kfifo_free(&state->rx_kfifo); |
29f8a0a5 AW |
1236 | kfree(state); |
1237 | /* Nothing more to free() as state held the actual v4l2_subdev object */ | |
1238 | return 0; | |
1239 | } |