[mirror_ubuntu-artful-kernel.git] / drivers / media / pci / cx25821 / cx25821-medusa-reg.h

/*
 *  Driver for the Conexant CX25821 PCIe bridge
 *
 *  Copyright (C) 2009 Conexant Systems Inc.
 *  Authors  <shu.lin@conexant.com>, <hiep.huynh@conexant.com>
 *
 *  This program is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License as published by
 *  the Free Software Foundation; either version 2 of the License, or
 *  (at your option) any later version.
 *
 *  This program is distributed in the hope that it will be useful,
 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *
 *  GNU General Public License for more details.
 */

#ifndef __MEDUSA_REGISTERS__
#define __MEDUSA_REGISTERS__

/* Serial Slave Registers */
#define	HOST_REGISTER1				0x0000
#define	HOST_REGISTER2				0x0001

/* Chip Configuration Registers */
#define	CHIP_CTRL				0x0100
#define	AFE_AB_CTRL				0x0104
#define	AFE_CD_CTRL				0x0108
#define	AFE_EF_CTRL				0x010C
#define	AFE_GH_CTRL				0x0110
#define	DENC_AB_CTRL				0x0114
#define	BYP_AB_CTRL				0x0118
#define	MON_A_CTRL				0x011C
#define	DISP_SEQ_A				0x0120
#define	DISP_SEQ_B				0x0124
#define	DISP_AB_CNT				0x0128
#define	DISP_CD_CNT				0x012C
#define	DISP_EF_CNT				0x0130
#define	DISP_GH_CNT				0x0134
#define	DISP_IJ_CNT				0x0138
#define	PIN_OE_CTRL				0x013C
#define	PIN_SPD_CTRL				0x0140
#define	PIN_SPD_CTRL2				0x0144
#define	IRQ_STAT_CTRL				0x0148
#define	POWER_CTRL_AB				0x014C
#define	POWER_CTRL_CD				0x0150
#define	POWER_CTRL_EF				0x0154
#define	POWER_CTRL_GH				0x0158
#define	TUNE_CTRL				0x015C
#define	BIAS_CTRL				0x0160
#define	AFE_AB_DIAG_CTRL			0x0164
#define	AFE_CD_DIAG_CTRL			0x0168
#define	AFE_EF_DIAG_CTRL			0x016C
#define	AFE_GH_DIAG_CTRL			0x0170
#define	PLL_AB_DIAG_CTRL			0x0174
#define	PLL_CD_DIAG_CTRL			0x0178
#define	PLL_EF_DIAG_CTRL			0x017C
#define	PLL_GH_DIAG_CTRL			0x0180
#define	TEST_CTRL				0x0184
#define	BIST_STAT				0x0188
#define	BIST_STAT2				0x018C
#define	BIST_VID_PLL_AB_STAT			0x0190
#define	BIST_VID_PLL_CD_STAT			0x0194
#define	BIST_VID_PLL_EF_STAT			0x0198
#define	BIST_VID_PLL_GH_STAT			0x019C
#define	DLL_DIAG_CTRL				0x01A0
#define	DEV_CH_ID_CTRL				0x01A4
#define	ABIST_CTRL_STATUS			0x01A8
#define	ABIST_FREQ				0x01AC
#define	ABIST_GOERT_SHIFT			0x01B0
#define	ABIST_COEF12				0x01B4
#define	ABIST_COEF34				0x01B8
#define	ABIST_COEF56				0x01BC
#define	ABIST_COEF7_SNR				0x01C0
#define	ABIST_ADC_CAL				0x01C4
#define	ABIST_BIN1_VGA0				0x01C8
#define	ABIST_BIN2_VGA1				0x01CC
#define	ABIST_BIN3_VGA2				0x01D0
#define	ABIST_BIN4_VGA3				0x01D4
#define	ABIST_BIN5_VGA4				0x01D8
#define	ABIST_BIN6_VGA5				0x01DC
#define	ABIST_BIN7_VGA6				0x01E0
#define	ABIST_CLAMP_A				0x01E4
#define	ABIST_CLAMP_B				0x01E8
#define	ABIST_CLAMP_C				0x01EC
#define	ABIST_CLAMP_D				0x01F0
#define	ABIST_CLAMP_E				0x01F4
#define	ABIST_CLAMP_F				0x01F8

/* Digital Video Encoder A Registers */
#define	DENC_A_REG_1				0x0200
#define	DENC_A_REG_2				0x0204
#define	DENC_A_REG_3				0x0208
#define	DENC_A_REG_4				0x020C
#define	DENC_A_REG_5				0x0210
#define	DENC_A_REG_6				0x0214
#define	DENC_A_REG_7				0x0218
#define	DENC_A_REG_8				0x021C

/* Digital Video Encoder B Registers */
#define	DENC_B_REG_1				0x0300
#define	DENC_B_REG_2				0x0304
#define	DENC_B_REG_3				0x0308
#define	DENC_B_REG_4				0x030C
#define	DENC_B_REG_5				0x0310
#define	DENC_B_REG_6				0x0314
#define	DENC_B_REG_7				0x0318
#define	DENC_B_REG_8				0x031C

/* Video Decoder A Registers */
#define	MODE_CTRL				0x1000
#define	OUT_CTRL1				0x1004
#define	OUT_CTRL_NS				0x1008
#define	GEN_STAT				0x100C
#define	INT_STAT_MASK				0x1010
#define	LUMA_CTRL				0x1014
#define	CHROMA_CTRL				0x1018
#define	CRUSH_CTRL				0x101C
#define	HORIZ_TIM_CTRL				0x1020
#define	VERT_TIM_CTRL				0x1024
#define	MISC_TIM_CTRL				0x1028
#define	FIELD_COUNT				0x102C
#define	HSCALE_CTRL				0x1030
#define	VSCALE_CTRL				0x1034
#define	MAN_VGA_CTRL				0x1038
#define	MAN_AGC_CTRL				0x103C
#define	DFE_CTRL1				0x1040
#define	DFE_CTRL2				0x1044
#define	DFE_CTRL3				0x1048
#define	PLL_CTRL				0x104C
#define	PLL_CTRL_FAST				0x1050
#define	HTL_CTRL				0x1054
#define	SRC_CFG					0x1058
#define	SC_STEP_SIZE				0x105C
#define	SC_CONVERGE_CTRL			0x1060
#define	SC_LOOP_CTRL				0x1064
#define	COMB_2D_HFS_CFG				0x1068
#define	COMB_2D_HFD_CFG				0x106C
#define	COMB_2D_LF_CFG				0x1070
#define	COMB_2D_BLEND				0x1074
#define	COMB_MISC_CTRL				0x1078
#define	COMB_FLAT_THRESH_CTRL			0x107C
#define	COMB_TEST				0x1080
#define	BP_MISC_CTRL				0x1084
#define	VCR_DET_CTRL				0x1088
#define	NOISE_DET_CTRL				0x108C
#define	COMB_FLAT_NOISE_CTRL			0x1090
#define	VERSION					0x11F8
#define	SOFT_RST_CTRL				0x11FC

/* Video Decoder B Registers */
#define	VDEC_B_MODE_CTRL			0x1200
#define	VDEC_B_OUT_CTRL1			0x1204
#define	VDEC_B_OUT_CTRL_NS			0x1208
#define	VDEC_B_GEN_STAT				0x120C
#define	VDEC_B_INT_STAT_MASK			0x1210
#define	VDEC_B_LUMA_CTRL			0x1214
#define	VDEC_B_CHROMA_CTRL			0x1218
#define	VDEC_B_CRUSH_CTRL			0x121C
#define	VDEC_B_HORIZ_TIM_CTRL			0x1220
#define	VDEC_B_VERT_TIM_CTRL			0x1224
#define	VDEC_B_MISC_TIM_CTRL			0x1228
#define	VDEC_B_FIELD_COUNT			0x122C
#define	VDEC_B_HSCALE_CTRL			0x1230
#define	VDEC_B_VSCALE_CTRL			0x1234
#define	VDEC_B_MAN_VGA_CTRL			0x1238
#define	VDEC_B_MAN_AGC_CTRL			0x123C
#define	VDEC_B_DFE_CTRL1			0x1240
#define	VDEC_B_DFE_CTRL2			0x1244
#define	VDEC_B_DFE_CTRL3			0x1248
#define	VDEC_B_PLL_CTRL				0x124C
#define	VDEC_B_PLL_CTRL_FAST			0x1250
#define	VDEC_B_HTL_CTRL				0x1254
#define	VDEC_B_SRC_CFG				0x1258
#define	VDEC_B_SC_STEP_SIZE			0x125C
#define	VDEC_B_SC_CONVERGE_CTRL			0x1260
#define	VDEC_B_SC_LOOP_CTRL			0x1264
#define	VDEC_B_COMB_2D_HFS_CFG			0x1268
#define	VDEC_B_COMB_2D_HFD_CFG			0x126C
#define	VDEC_B_COMB_2D_LF_CFG			0x1270
#define	VDEC_B_COMB_2D_BLEND			0x1274
#define	VDEC_B_COMB_MISC_CTRL			0x1278
#define	VDEC_B_COMB_FLAT_THRESH_CTRL		0x127C
#define	VDEC_B_COMB_TEST			0x1280
#define	VDEC_B_BP_MISC_CTRL			0x1284
#define	VDEC_B_VCR_DET_CTRL			0x1288
#define	VDEC_B_NOISE_DET_CTRL			0x128C
#define	VDEC_B_COMB_FLAT_NOISE_CTRL		0x1290
#define	VDEC_B_VERSION				0x13F8
#define	VDEC_B_SOFT_RST_CTRL			0x13FC

/* Video Decoder C Registers */
#define	VDEC_C_MODE_CTRL			0x1400
#define	VDEC_C_OUT_CTRL1			0x1404
#define	VDEC_C_OUT_CTRL_NS			0x1408
#define	VDEC_C_GEN_STAT				0x140C
#define	VDEC_C_INT_STAT_MASK			0x1410
#define VDEC_C_LUMA_CTRL			0x1414
#define VDEC_C_CHROMA_CTRL			0x1418
#define	VDEC_C_CRUSH_CTRL			0x141C
#define	VDEC_C_HORIZ_TIM_CTRL			0x1420
#define	VDEC_C_VERT_TIM_CTRL			0x1424
#define	VDEC_C_MISC_TIM_CTRL			0x1428
#define	VDEC_C_FIELD_COUNT			0x142C
#define	VDEC_C_HSCALE_CTRL			0x1430
#define	VDEC_C_VSCALE_CTRL			0x1434
#define	VDEC_C_MAN_VGA_CTRL			0x1438
#define	VDEC_C_MAN_AGC_CTRL			0x143C
#define	VDEC_C_DFE_CTRL1			0x1440
#define	VDEC_C_DFE_CTRL2			0x1444
#define	VDEC_C_DFE_CTRL3			0x1448
#define	VDEC_C_PLL_CTRL				0x144C
#define	VDEC_C_PLL_CTRL_FAST			0x1450
#define	VDEC_C_HTL_CTRL				0x1454
#define	VDEC_C_SRC_CFG				0x1458
#define	VDEC_C_SC_STEP_SIZE			0x145C
#define	VDEC_C_SC_CONVERGE_CTRL			0x1460
#define	VDEC_C_SC_LOOP_CTRL			0x1464
#define	VDEC_C_COMB_2D_HFS_CFG			0x1468
#define	VDEC_C_COMB_2D_HFD_CFG			0x146C
#define	VDEC_C_COMB_2D_LF_CFG			0x1470
#define	VDEC_C_COMB_2D_BLEND			0x1474
#define	VDEC_C_COMB_MISC_CTRL			0x1478
#define	VDEC_C_COMB_FLAT_THRESH_CTRL		0x147C
#define	VDEC_C_COMB_TEST			0x1480
#define	VDEC_C_BP_MISC_CTRL			0x1484
#define	VDEC_C_VCR_DET_CTRL			0x1488
#define	VDEC_C_NOISE_DET_CTRL			0x148C
#define	VDEC_C_COMB_FLAT_NOISE_CTRL		0x1490
#define	VDEC_C_VERSION				0x15F8
#define	VDEC_C_SOFT_RST_CTRL			0x15FC

/* Video Decoder D Registers */
#define VDEC_D_MODE_CTRL			0x1600
#define VDEC_D_OUT_CTRL1			0x1604
#define VDEC_D_OUT_CTRL_NS			0x1608
#define VDEC_D_GEN_STAT				0x160C
#define VDEC_D_INT_STAT_MASK			0x1610
#define VDEC_D_LUMA_CTRL			0x1614
#define VDEC_D_CHROMA_CTRL			0x1618
#define VDEC_D_CRUSH_CTRL			0x161C
#define VDEC_D_HORIZ_TIM_CTRL			0x1620
#define VDEC_D_VERT_TIM_CTRL			0x1624
#define VDEC_D_MISC_TIM_CTRL			0x1628
#define VDEC_D_FIELD_COUNT			0x162C
#define VDEC_D_HSCALE_CTRL			0x1630
#define VDEC_D_VSCALE_CTRL			0x1634
#define VDEC_D_MAN_VGA_CTRL			0x1638
#define VDEC_D_MAN_AGC_CTRL			0x163C
#define VDEC_D_DFE_CTRL1			0x1640
#define VDEC_D_DFE_CTRL2			0x1644
#define VDEC_D_DFE_CTRL3			0x1648
#define VDEC_D_PLL_CTRL				0x164C
#define VDEC_D_PLL_CTRL_FAST			0x1650
#define VDEC_D_HTL_CTRL				0x1654
#define VDEC_D_SRC_CFG				0x1658
#define VDEC_D_SC_STEP_SIZE			0x165C
#define VDEC_D_SC_CONVERGE_CTRL			0x1660
#define VDEC_D_SC_LOOP_CTRL			0x1664
#define VDEC_D_COMB_2D_HFS_CFG			0x1668
#define VDEC_D_COMB_2D_HFD_CFG			0x166C
#define VDEC_D_COMB_2D_LF_CFG			0x1670
#define VDEC_D_COMB_2D_BLEND			0x1674
#define VDEC_D_COMB_MISC_CTRL			0x1678
#define VDEC_D_COMB_FLAT_THRESH_CTRL		0x167C
#define VDEC_D_COMB_TEST			0x1680
#define VDEC_D_BP_MISC_CTRL			0x1684
#define VDEC_D_VCR_DET_CTRL			0x1688
#define VDEC_D_NOISE_DET_CTRL			0x168C
#define VDEC_D_COMB_FLAT_NOISE_CTRL		0x1690
#define VDEC_D_VERSION				0x17F8
#define VDEC_D_SOFT_RST_CTRL			0x17FC

/* Video Decoder E Registers */
#define	VDEC_E_MODE_CTRL			0x1800
#define	VDEC_E_OUT_CTRL1			0x1804
#define	VDEC_E_OUT_CTRL_NS			0x1808
#define	VDEC_E_GEN_STAT				0x180C
#define	VDEC_E_INT_STAT_MASK			0x1810
#define	VDEC_E_LUMA_CTRL			0x1814
#define	VDEC_E_CHROMA_CTRL			0x1818
#define	VDEC_E_CRUSH_CTRL			0x181C
#define	VDEC_E_HORIZ_TIM_CTRL			0x1820
#define	VDEC_E_VERT_TIM_CTRL			0x1824
#define	VDEC_E_MISC_TIM_CTRL			0x1828
#define	VDEC_E_FIELD_COUNT			0x182C
#define	VDEC_E_HSCALE_CTRL			0x1830
#define	VDEC_E_VSCALE_CTRL			0x1834
#define	VDEC_E_MAN_VGA_CTRL			0x1838
#define	VDEC_E_MAN_AGC_CTRL			0x183C
#define	VDEC_E_DFE_CTRL1			0x1840
#define	VDEC_E_DFE_CTRL2			0x1844
#define	VDEC_E_DFE_CTRL3			0x1848
#define	VDEC_E_PLL_CTRL				0x184C
#define	VDEC_E_PLL_CTRL_FAST			0x1850
#define	VDEC_E_HTL_CTRL				0x1854
#define	VDEC_E_SRC_CFG				0x1858
#define	VDEC_E_SC_STEP_SIZE			0x185C
#define	VDEC_E_SC_CONVERGE_CTRL			0x1860
#define	VDEC_E_SC_LOOP_CTRL			0x1864
#define	VDEC_E_COMB_2D_HFS_CFG			0x1868
#define	VDEC_E_COMB_2D_HFD_CFG			0x186C
#define	VDEC_E_COMB_2D_LF_CFG			0x1870
#define	VDEC_E_COMB_2D_BLEND			0x1874
#define	VDEC_E_COMB_MISC_CTRL			0x1878
#define	VDEC_E_COMB_FLAT_THRESH_CTRL		0x187C
#define	VDEC_E_COMB_TEST			0x1880
#define	VDEC_E_BP_MISC_CTRL			0x1884
#define	VDEC_E_VCR_DET_CTRL			0x1888
#define	VDEC_E_NOISE_DET_CTRL			0x188C
#define	VDEC_E_COMB_FLAT_NOISE_CTRL		0x1890
#define	VDEC_E_VERSION				0x19F8
#define	VDEC_E_SOFT_RST_CTRL			0x19FC

/* Video Decoder F Registers */
#define	VDEC_F_MODE_CTRL			0x1A00
#define	VDEC_F_OUT_CTRL1			0x1A04
#define	VDEC_F_OUT_CTRL_NS			0x1A08
#define	VDEC_F_GEN_STAT				0x1A0C
#define	VDEC_F_INT_STAT_MASK			0x1A10
#define	VDEC_F_LUMA_CTRL			0x1A14
#define	VDEC_F_CHROMA_CTRL			0x1A18
#define	VDEC_F_CRUSH_CTRL			0x1A1C
#define	VDEC_F_HORIZ_TIM_CTRL			0x1A20
#define	VDEC_F_VERT_TIM_CTRL			0x1A24
#define	VDEC_F_MISC_TIM_CTRL			0x1A28
#define	VDEC_F_FIELD_COUNT			0x1A2C
#define	VDEC_F_HSCALE_CTRL			0x1A30
#define	VDEC_F_VSCALE_CTRL			0x1A34
#define	VDEC_F_MAN_VGA_CTRL			0x1A38
#define	VDEC_F_MAN_AGC_CTRL			0x1A3C
#define	VDEC_F_DFE_CTRL1			0x1A40
#define	VDEC_F_DFE_CTRL2			0x1A44
#define	VDEC_F_DFE_CTRL3			0x1A48
#define	VDEC_F_PLL_CTRL				0x1A4C
#define	VDEC_F_PLL_CTRL_FAST			0x1A50
#define	VDEC_F_HTL_CTRL				0x1A54
#define	VDEC_F_SRC_CFG				0x1A58
#define	VDEC_F_SC_STEP_SIZE			0x1A5C
#define	VDEC_F_SC_CONVERGE_CTRL			0x1A60
#define	VDEC_F_SC_LOOP_CTRL			0x1A64
#define	VDEC_F_COMB_2D_HFS_CFG			0x1A68
#define	VDEC_F_COMB_2D_HFD_CFG			0x1A6C
#define	VDEC_F_COMB_2D_LF_CFG			0x1A70
#define	VDEC_F_COMB_2D_BLEND			0x1A74
#define	VDEC_F_COMB_MISC_CTRL			0x1A78
#define	VDEC_F_COMB_FLAT_THRESH_CTRL		0x1A7C
#define	VDEC_F_COMB_TEST			0x1A80
#define	VDEC_F_BP_MISC_CTRL			0x1A84
#define	VDEC_F_VCR_DET_CTRL			0x1A88
#define	VDEC_F_NOISE_DET_CTRL			0x1A8C
#define	VDEC_F_COMB_FLAT_NOISE_CTRL		0x1A90
#define	VDEC_F_VERSION				0x1BF8
#define	VDEC_F_SOFT_RST_CTRL			0x1BFC

/* Video Decoder G Registers */
#define	VDEC_G_MODE_CTRL			0x1C00
#define	VDEC_G_OUT_CTRL1			0x1C04
#define	VDEC_G_OUT_CTRL_NS			0x1C08
#define	VDEC_G_GEN_STAT				0x1C0C
#define	VDEC_G_INT_STAT_MASK			0x1C10
#define	VDEC_G_LUMA_CTRL			0x1C14
#define	VDEC_G_CHROMA_CTRL			0x1C18
#define	VDEC_G_CRUSH_CTRL			0x1C1C
#define	VDEC_G_HORIZ_TIM_CTRL			0x1C20
#define	VDEC_G_VERT_TIM_CTRL			0x1C24
#define	VDEC_G_MISC_TIM_CTRL			0x1C28
#define	VDEC_G_FIELD_COUNT			0x1C2C
#define	VDEC_G_HSCALE_CTRL			0x1C30
#define	VDEC_G_VSCALE_CTRL			0x1C34
#define	VDEC_G_MAN_VGA_CTRL			0x1C38
#define	VDEC_G_MAN_AGC_CTRL			0x1C3C
#define	VDEC_G_DFE_CTRL1			0x1C40
#define	VDEC_G_DFE_CTRL2			0x1C44
#define	VDEC_G_DFE_CTRL3			0x1C48
#define	VDEC_G_PLL_CTRL				0x1C4C
#define	VDEC_G_PLL_CTRL_FAST			0x1C50
#define	VDEC_G_HTL_CTRL				0x1C54
#define	VDEC_G_SRC_CFG				0x1C58
#define	VDEC_G_SC_STEP_SIZE			0x1C5C
#define	VDEC_G_SC_CONVERGE_CTRL			0x1C60
#define	VDEC_G_SC_LOOP_CTRL			0x1C64
#define	VDEC_G_COMB_2D_HFS_CFG			0x1C68
#define	VDEC_G_COMB_2D_HFD_CFG			0x1C6C
#define	VDEC_G_COMB_2D_LF_CFG			0x1C70
#define	VDEC_G_COMB_2D_BLEND			0x1C74
#define	VDEC_G_COMB_MISC_CTRL			0x1C78
#define	VDEC_G_COMB_FLAT_THRESH_CTRL		0x1C7C
#define	VDEC_G_COMB_TEST			0x1C80
#define	VDEC_G_BP_MISC_CTRL			0x1C84
#define	VDEC_G_VCR_DET_CTRL			0x1C88
#define	VDEC_G_NOISE_DET_CTRL			0x1C8C
#define	VDEC_G_COMB_FLAT_NOISE_CTRL		0x1C90
#define	VDEC_G_VERSION				0x1DF8
#define	VDEC_G_SOFT_RST_CTRL			0x1DFC

/* Video Decoder H Registers  */
#define	VDEC_H_MODE_CTRL			0x1E00
#define	VDEC_H_OUT_CTRL1			0x1E04
#define	VDEC_H_OUT_CTRL_NS			0x1E08
#define	VDEC_H_GEN_STAT				0x1E0C
#define	VDEC_H_INT_STAT_MASK			0x1E1E
#define	VDEC_H_LUMA_CTRL			0x1E14
#define	VDEC_H_CHROMA_CTRL			0x1E18
#define	VDEC_H_CRUSH_CTRL			0x1E1C
#define	VDEC_H_HORIZ_TIM_CTRL			0x1E20
#define	VDEC_H_VERT_TIM_CTRL			0x1E24
#define	VDEC_H_MISC_TIM_CTRL			0x1E28
#define	VDEC_H_FIELD_COUNT			0x1E2C
#define	VDEC_H_HSCALE_CTRL			0x1E30
#define	VDEC_H_VSCALE_CTRL			0x1E34
#define	VDEC_H_MAN_VGA_CTRL			0x1E38
#define	VDEC_H_MAN_AGC_CTRL			0x1E3C
#define	VDEC_H_DFE_CTRL1			0x1E40
#define	VDEC_H_DFE_CTRL2			0x1E44
#define	VDEC_H_DFE_CTRL3			0x1E48
#define	VDEC_H_PLL_CTRL				0x1E4C
#define	VDEC_H_PLL_CTRL_FAST			0x1E50
#define	VDEC_H_HTL_CTRL				0x1E54
#define	VDEC_H_SRC_CFG				0x1E58
#define	VDEC_H_SC_STEP_SIZE			0x1E5C
#define	VDEC_H_SC_CONVERGE_CTRL			0x1E60
#define	VDEC_H_SC_LOOP_CTRL			0x1E64
#define	VDEC_H_COMB_2D_HFS_CFG			0x1E68
#define	VDEC_H_COMB_2D_HFD_CFG			0x1E6C
#define	VDEC_H_COMB_2D_LF_CFG			0x1E70
#define	VDEC_H_COMB_2D_BLEND			0x1E74
#define	VDEC_H_COMB_MISC_CTRL			0x1E78
#define	VDEC_H_COMB_FLAT_THRESH_CTRL		0x1E7C
#define	VDEC_H_COMB_TEST			0x1E80
#define	VDEC_H_BP_MISC_CTRL			0x1E84
#define	VDEC_H_VCR_DET_CTRL			0x1E88
#define	VDEC_H_NOISE_DET_CTRL			0x1E8C
#define	VDEC_H_COMB_FLAT_NOISE_CTRL		0x1E90
#define	VDEC_H_VERSION				0x1FF8
#define	VDEC_H_SOFT_RST_CTRL			0x1FFC

/*****************************************************************************/
/* LUMA_CTRL register fields */
#define VDEC_A_BRITE_CTRL			0x1014
#define VDEC_A_CNTRST_CTRL			0x1015
#define VDEC_A_PEAK_SEL				0x1016

/*****************************************************************************/
/* CHROMA_CTRL register fields */
#define VDEC_A_USAT_CTRL			0x1018
#define VDEC_A_VSAT_CTRL			0x1019
#define VDEC_A_HUE_CTRL				0x101A

#endif
Commit	Line	Data
1a9fc855 MCC	1	/*
	2	* Driver for the Conexant CX25821 PCIe bridge
	3	*
	4	* Copyright (C) 2009 Conexant Systems Inc.
	5	* Authors <shu.lin@conexant.com>, <hiep.huynh@conexant.com>
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License as published by
	9	* the Free Software Foundation; either version 2 of the License, or
	10	* (at your option) any later version.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	*
	16	* GNU General Public License for more details.
1a9fc855 MCC	17	*/
	18
	19	#ifndef __MEDUSA_REGISTERS__
	20	#define __MEDUSA_REGISTERS__
	21
6d8c2ba1	22	/* Serial Slave Registers */
1a9fc855 MCC	23	#define HOST_REGISTER1 0x0000
	24	#define HOST_REGISTER2 0x0001
	25
6d8c2ba1	26	/* Chip Configuration Registers */
f70a6566 LF	27	#define CHIP_CTRL 0x0100
	28	#define AFE_AB_CTRL 0x0104
	29	#define AFE_CD_CTRL 0x0108
	30	#define AFE_EF_CTRL 0x010C
	31	#define AFE_GH_CTRL 0x0110
1a9fc855	32	#define DENC_AB_CTRL 0x0114
f70a6566 LF	33	#define BYP_AB_CTRL 0x0118
	34	#define MON_A_CTRL 0x011C
	35	#define DISP_SEQ_A 0x0120
	36	#define DISP_SEQ_B 0x0124
	37	#define DISP_AB_CNT 0x0128
	38	#define DISP_CD_CNT 0x012C
	39	#define DISP_EF_CNT 0x0130
	40	#define DISP_GH_CNT 0x0134
	41	#define DISP_IJ_CNT 0x0138
	42	#define PIN_OE_CTRL 0x013C
1a9fc855 MCC	43	#define PIN_SPD_CTRL 0x0140
	44	#define PIN_SPD_CTRL2 0x0144
	45	#define IRQ_STAT_CTRL 0x0148
	46	#define POWER_CTRL_AB 0x014C
	47	#define POWER_CTRL_CD 0x0150
	48	#define POWER_CTRL_EF 0x0154
	49	#define POWER_CTRL_GH 0x0158
f70a6566 LF	50	#define TUNE_CTRL 0x015C
f70a6566 LF	51	#define BIAS_CTRL 0x0160
1a9fc855 MCC	52	#define AFE_AB_DIAG_CTRL 0x0164
	53	#define AFE_CD_DIAG_CTRL 0x0168
	54	#define AFE_EF_DIAG_CTRL 0x016C
	55	#define AFE_GH_DIAG_CTRL 0x0170
	56	#define PLL_AB_DIAG_CTRL 0x0174
	57	#define PLL_CD_DIAG_CTRL 0x0178
	58	#define PLL_EF_DIAG_CTRL 0x017C
	59	#define PLL_GH_DIAG_CTRL 0x0180
f70a6566 LF	60	#define TEST_CTRL 0x0184
	61	#define BIST_STAT 0x0188
	62	#define BIST_STAT2 0x018C
	63	#define BIST_VID_PLL_AB_STAT 0x0190
	64	#define BIST_VID_PLL_CD_STAT 0x0194
	65	#define BIST_VID_PLL_EF_STAT 0x0198
	66	#define BIST_VID_PLL_GH_STAT 0x019C
1a9fc855 MCC	67	#define DLL_DIAG_CTRL 0x01A0
	68	#define DEV_CH_ID_CTRL 0x01A4
	69	#define ABIST_CTRL_STATUS 0x01A8
f70a6566	70	#define ABIST_FREQ 0x01AC
1a9fc855 MCC	71	#define ABIST_GOERT_SHIFT 0x01B0
	72	#define ABIST_COEF12 0x01B4
	73	#define ABIST_COEF34 0x01B8
	74	#define ABIST_COEF56 0x01BC
	75	#define ABIST_COEF7_SNR 0x01C0
	76	#define ABIST_ADC_CAL 0x01C4
	77	#define ABIST_BIN1_VGA0 0x01C8
	78	#define ABIST_BIN2_VGA1 0x01CC
	79	#define ABIST_BIN3_VGA2 0x01D0
	80	#define ABIST_BIN4_VGA3 0x01D4
	81	#define ABIST_BIN5_VGA4 0x01D8
	82	#define ABIST_BIN6_VGA5 0x01DC
947b6f87 AO	83	#define ABIST_BIN7_VGA6 0x01E0
	84	#define ABIST_CLAMP_A 0x01E4
	85	#define ABIST_CLAMP_B 0x01E8
1a9fc855 MCC	86	#define ABIST_CLAMP_C 0x01EC
	87	#define ABIST_CLAMP_D 0x01F0
	88	#define ABIST_CLAMP_E 0x01F4
	89	#define ABIST_CLAMP_F 0x01F8
	90
f70a6566 LF	91	/* Digital Video Encoder A Registers */
	92	#define DENC_A_REG_1 0x0200
	93	#define DENC_A_REG_2 0x0204
	94	#define DENC_A_REG_3 0x0208
	95	#define DENC_A_REG_4 0x020C
	96	#define DENC_A_REG_5 0x0210
	97	#define DENC_A_REG_6 0x0214
	98	#define DENC_A_REG_7 0x0218
	99	#define DENC_A_REG_8 0x021C
1a9fc855	100
f70a6566 LF	101	/* Digital Video Encoder B Registers */
	102	#define DENC_B_REG_1 0x0300
	103	#define DENC_B_REG_2 0x0304
	104	#define DENC_B_REG_3 0x0308
	105	#define DENC_B_REG_4 0x030C
	106	#define DENC_B_REG_5 0x0310
	107	#define DENC_B_REG_6 0x0314
	108	#define DENC_B_REG_7 0x0318
	109	#define DENC_B_REG_8 0x031C
1a9fc855	110
f70a6566 LF	111	/* Video Decoder A Registers */
	112	#define MODE_CTRL 0x1000
	113	#define OUT_CTRL1 0x1004
	114	#define OUT_CTRL_NS 0x1008
	115	#define GEN_STAT 0x100C
	116	#define INT_STAT_MASK 0x1010
	117	#define LUMA_CTRL 0x1014
	118	#define CHROMA_CTRL 0x1018
	119	#define CRUSH_CTRL 0x101C
	120	#define HORIZ_TIM_CTRL 0x1020
	121	#define VERT_TIM_CTRL 0x1024
	122	#define MISC_TIM_CTRL 0x1028
	123	#define FIELD_COUNT 0x102C
	124	#define HSCALE_CTRL 0x1030
	125	#define VSCALE_CTRL 0x1034
	126	#define MAN_VGA_CTRL 0x1038
	127	#define MAN_AGC_CTRL 0x103C
	128	#define DFE_CTRL1 0x1040
	129	#define DFE_CTRL2 0x1044
	130	#define DFE_CTRL3 0x1048
	131	#define PLL_CTRL 0x104C
	132	#define PLL_CTRL_FAST 0x1050
	133	#define HTL_CTRL 0x1054
	134	#define SRC_CFG 0x1058
	135	#define SC_STEP_SIZE 0x105C
	136	#define SC_CONVERGE_CTRL 0x1060
	137	#define SC_LOOP_CTRL 0x1064
	138	#define COMB_2D_HFS_CFG 0x1068
	139	#define COMB_2D_HFD_CFG 0x106C
	140	#define COMB_2D_LF_CFG 0x1070
	141	#define COMB_2D_BLEND 0x1074
	142	#define COMB_MISC_CTRL 0x1078
1a9fc855	143	#define COMB_FLAT_THRESH_CTRL 0x107C
f70a6566 LF	144	#define COMB_TEST 0x1080
	145	#define BP_MISC_CTRL 0x1084
	146	#define VCR_DET_CTRL 0x1088
	147	#define NOISE_DET_CTRL 0x108C
1a9fc855	148	#define COMB_FLAT_NOISE_CTRL 0x1090
f70a6566 LF	149	#define VERSION 0x11F8
f70a6566 LF	150	#define SOFT_RST_CTRL 0x11FC
1a9fc855	151
f70a6566 LF	152	/* Video Decoder B Registers */
	153	#define VDEC_B_MODE_CTRL 0x1200
	154	#define VDEC_B_OUT_CTRL1 0x1204
	155	#define VDEC_B_OUT_CTRL_NS 0x1208
	156	#define VDEC_B_GEN_STAT 0x120C
1a9fc855	157	#define VDEC_B_INT_STAT_MASK 0x1210
f70a6566 LF	158	#define VDEC_B_LUMA_CTRL 0x1214
	159	#define VDEC_B_CHROMA_CTRL 0x1218
	160	#define VDEC_B_CRUSH_CTRL 0x121C
1a9fc855 MCC	161	#define VDEC_B_HORIZ_TIM_CTRL 0x1220
	162	#define VDEC_B_VERT_TIM_CTRL 0x1224
	163	#define VDEC_B_MISC_TIM_CTRL 0x1228
f70a6566 LF	164	#define VDEC_B_FIELD_COUNT 0x122C
	165	#define VDEC_B_HSCALE_CTRL 0x1230
	166	#define VDEC_B_VSCALE_CTRL 0x1234
	167	#define VDEC_B_MAN_VGA_CTRL 0x1238
	168	#define VDEC_B_MAN_AGC_CTRL 0x123C
	169	#define VDEC_B_DFE_CTRL1 0x1240
	170	#define VDEC_B_DFE_CTRL2 0x1244
	171	#define VDEC_B_DFE_CTRL3 0x1248
	172	#define VDEC_B_PLL_CTRL 0x124C
1a9fc855	173	#define VDEC_B_PLL_CTRL_FAST 0x1250
f70a6566 LF	174	#define VDEC_B_HTL_CTRL 0x1254
	175	#define VDEC_B_SRC_CFG 0x1258
	176	#define VDEC_B_SC_STEP_SIZE 0x125C
1a9fc855	177	#define VDEC_B_SC_CONVERGE_CTRL 0x1260
f70a6566	178	#define VDEC_B_SC_LOOP_CTRL 0x1264
1a9fc855 MCC	179	#define VDEC_B_COMB_2D_HFS_CFG 0x1268
	180	#define VDEC_B_COMB_2D_HFD_CFG 0x126C
	181	#define VDEC_B_COMB_2D_LF_CFG 0x1270
	182	#define VDEC_B_COMB_2D_BLEND 0x1274
	183	#define VDEC_B_COMB_MISC_CTRL 0x1278
f70a6566 LF	184	#define VDEC_B_COMB_FLAT_THRESH_CTRL 0x127C
	185	#define VDEC_B_COMB_TEST 0x1280
	186	#define VDEC_B_BP_MISC_CTRL 0x1284
	187	#define VDEC_B_VCR_DET_CTRL 0x1288
1a9fc855 MCC	188	#define VDEC_B_NOISE_DET_CTRL 0x128C
1a9fc855 MCC	189	#define VDEC_B_COMB_FLAT_NOISE_CTRL 0x1290
f70a6566	190	#define VDEC_B_VERSION 0x13F8
1a9fc855 MCC	191	#define VDEC_B_SOFT_RST_CTRL 0x13FC
1a9fc855 MCC	192
6d8c2ba1	193	/* Video Decoder C Registers */
f70a6566 LF	194	#define VDEC_C_MODE_CTRL 0x1400
	195	#define VDEC_C_OUT_CTRL1 0x1404
	196	#define VDEC_C_OUT_CTRL_NS 0x1408
	197	#define VDEC_C_GEN_STAT 0x140C
1a9fc855	198	#define VDEC_C_INT_STAT_MASK 0x1410
f70a6566 LF	199	#define VDEC_C_LUMA_CTRL 0x1414
	200	#define VDEC_C_CHROMA_CTRL 0x1418
	201	#define VDEC_C_CRUSH_CTRL 0x141C
1a9fc855 MCC	202	#define VDEC_C_HORIZ_TIM_CTRL 0x1420
	203	#define VDEC_C_VERT_TIM_CTRL 0x1424
	204	#define VDEC_C_MISC_TIM_CTRL 0x1428
f70a6566 LF	205	#define VDEC_C_FIELD_COUNT 0x142C
	206	#define VDEC_C_HSCALE_CTRL 0x1430
	207	#define VDEC_C_VSCALE_CTRL 0x1434
	208	#define VDEC_C_MAN_VGA_CTRL 0x1438
	209	#define VDEC_C_MAN_AGC_CTRL 0x143C
	210	#define VDEC_C_DFE_CTRL1 0x1440
	211	#define VDEC_C_DFE_CTRL2 0x1444
	212	#define VDEC_C_DFE_CTRL3 0x1448
	213	#define VDEC_C_PLL_CTRL 0x144C
1a9fc855	214	#define VDEC_C_PLL_CTRL_FAST 0x1450
f70a6566 LF	215	#define VDEC_C_HTL_CTRL 0x1454
	216	#define VDEC_C_SRC_CFG 0x1458
	217	#define VDEC_C_SC_STEP_SIZE 0x145C
1a9fc855	218	#define VDEC_C_SC_CONVERGE_CTRL 0x1460
f70a6566	219	#define VDEC_C_SC_LOOP_CTRL 0x1464
1a9fc855 MCC	220	#define VDEC_C_COMB_2D_HFS_CFG 0x1468
	221	#define VDEC_C_COMB_2D_HFD_CFG 0x146C
	222	#define VDEC_C_COMB_2D_LF_CFG 0x1470
	223	#define VDEC_C_COMB_2D_BLEND 0x1474
	224	#define VDEC_C_COMB_MISC_CTRL 0x1478
f70a6566 LF	225	#define VDEC_C_COMB_FLAT_THRESH_CTRL 0x147C
	226	#define VDEC_C_COMB_TEST 0x1480
	227	#define VDEC_C_BP_MISC_CTRL 0x1484
	228	#define VDEC_C_VCR_DET_CTRL 0x1488
1a9fc855 MCC	229	#define VDEC_C_NOISE_DET_CTRL 0x148C
1a9fc855 MCC	230	#define VDEC_C_COMB_FLAT_NOISE_CTRL 0x1490
f70a6566	231	#define VDEC_C_VERSION 0x15F8
1a9fc855 MCC	232	#define VDEC_C_SOFT_RST_CTRL 0x15FC
1a9fc855 MCC	233
6d8c2ba1	234	/* Video Decoder D Registers */
f70a6566 LF	235	#define VDEC_D_MODE_CTRL 0x1600
	236	#define VDEC_D_OUT_CTRL1 0x1604
	237	#define VDEC_D_OUT_CTRL_NS 0x1608
	238	#define VDEC_D_GEN_STAT 0x160C
1a9fc855	239	#define VDEC_D_INT_STAT_MASK 0x1610
f70a6566 LF	240	#define VDEC_D_LUMA_CTRL 0x1614
	241	#define VDEC_D_CHROMA_CTRL 0x1618
	242	#define VDEC_D_CRUSH_CTRL 0x161C
1a9fc855 MCC	243	#define VDEC_D_HORIZ_TIM_CTRL 0x1620
	244	#define VDEC_D_VERT_TIM_CTRL 0x1624
	245	#define VDEC_D_MISC_TIM_CTRL 0x1628
f70a6566 LF	246	#define VDEC_D_FIELD_COUNT 0x162C
	247	#define VDEC_D_HSCALE_CTRL 0x1630
	248	#define VDEC_D_VSCALE_CTRL 0x1634
	249	#define VDEC_D_MAN_VGA_CTRL 0x1638
	250	#define VDEC_D_MAN_AGC_CTRL 0x163C
	251	#define VDEC_D_DFE_CTRL1 0x1640
	252	#define VDEC_D_DFE_CTRL2 0x1644
	253	#define VDEC_D_DFE_CTRL3 0x1648
	254	#define VDEC_D_PLL_CTRL 0x164C
1a9fc855	255	#define VDEC_D_PLL_CTRL_FAST 0x1650
f70a6566 LF	256	#define VDEC_D_HTL_CTRL 0x1654
	257	#define VDEC_D_SRC_CFG 0x1658
	258	#define VDEC_D_SC_STEP_SIZE 0x165C
1a9fc855	259	#define VDEC_D_SC_CONVERGE_CTRL 0x1660
f70a6566	260	#define VDEC_D_SC_LOOP_CTRL 0x1664
1a9fc855 MCC	261	#define VDEC_D_COMB_2D_HFS_CFG 0x1668
	262	#define VDEC_D_COMB_2D_HFD_CFG 0x166C
	263	#define VDEC_D_COMB_2D_LF_CFG 0x1670
	264	#define VDEC_D_COMB_2D_BLEND 0x1674
	265	#define VDEC_D_COMB_MISC_CTRL 0x1678
f70a6566 LF	266	#define VDEC_D_COMB_FLAT_THRESH_CTRL 0x167C
	267	#define VDEC_D_COMB_TEST 0x1680
	268	#define VDEC_D_BP_MISC_CTRL 0x1684
	269	#define VDEC_D_VCR_DET_CTRL 0x1688
1a9fc855 MCC	270	#define VDEC_D_NOISE_DET_CTRL 0x168C
1a9fc855 MCC	271	#define VDEC_D_COMB_FLAT_NOISE_CTRL 0x1690
f70a6566	272	#define VDEC_D_VERSION 0x17F8
1a9fc855 MCC	273	#define VDEC_D_SOFT_RST_CTRL 0x17FC
1a9fc855 MCC	274
6d8c2ba1	275	/* Video Decoder E Registers */
f70a6566 LF	276	#define VDEC_E_MODE_CTRL 0x1800
	277	#define VDEC_E_OUT_CTRL1 0x1804
	278	#define VDEC_E_OUT_CTRL_NS 0x1808
	279	#define VDEC_E_GEN_STAT 0x180C
1a9fc855	280	#define VDEC_E_INT_STAT_MASK 0x1810
f70a6566 LF	281	#define VDEC_E_LUMA_CTRL 0x1814
	282	#define VDEC_E_CHROMA_CTRL 0x1818
	283	#define VDEC_E_CRUSH_CTRL 0x181C
1a9fc855 MCC	284	#define VDEC_E_HORIZ_TIM_CTRL 0x1820
	285	#define VDEC_E_VERT_TIM_CTRL 0x1824
	286	#define VDEC_E_MISC_TIM_CTRL 0x1828
f70a6566 LF	287	#define VDEC_E_FIELD_COUNT 0x182C
	288	#define VDEC_E_HSCALE_CTRL 0x1830
	289	#define VDEC_E_VSCALE_CTRL 0x1834
	290	#define VDEC_E_MAN_VGA_CTRL 0x1838
	291	#define VDEC_E_MAN_AGC_CTRL 0x183C
	292	#define VDEC_E_DFE_CTRL1 0x1840
	293	#define VDEC_E_DFE_CTRL2 0x1844
	294	#define VDEC_E_DFE_CTRL3 0x1848
	295	#define VDEC_E_PLL_CTRL 0x184C
1a9fc855	296	#define VDEC_E_PLL_CTRL_FAST 0x1850
f70a6566 LF	297	#define VDEC_E_HTL_CTRL 0x1854
	298	#define VDEC_E_SRC_CFG 0x1858
	299	#define VDEC_E_SC_STEP_SIZE 0x185C
1a9fc855	300	#define VDEC_E_SC_CONVERGE_CTRL 0x1860
f70a6566	301	#define VDEC_E_SC_LOOP_CTRL 0x1864
1a9fc855 MCC	302	#define VDEC_E_COMB_2D_HFS_CFG 0x1868
	303	#define VDEC_E_COMB_2D_HFD_CFG 0x186C
	304	#define VDEC_E_COMB_2D_LF_CFG 0x1870
	305	#define VDEC_E_COMB_2D_BLEND 0x1874
	306	#define VDEC_E_COMB_MISC_CTRL 0x1878
f70a6566 LF	307	#define VDEC_E_COMB_FLAT_THRESH_CTRL 0x187C
	308	#define VDEC_E_COMB_TEST 0x1880
	309	#define VDEC_E_BP_MISC_CTRL 0x1884
	310	#define VDEC_E_VCR_DET_CTRL 0x1888
1a9fc855 MCC	311	#define VDEC_E_NOISE_DET_CTRL 0x188C
1a9fc855 MCC	312	#define VDEC_E_COMB_FLAT_NOISE_CTRL 0x1890
f70a6566	313	#define VDEC_E_VERSION 0x19F8
1a9fc855 MCC	314	#define VDEC_E_SOFT_RST_CTRL 0x19FC
1a9fc855 MCC	315
6d8c2ba1	316	/* Video Decoder F Registers */
f70a6566 LF	317	#define VDEC_F_MODE_CTRL 0x1A00
	318	#define VDEC_F_OUT_CTRL1 0x1A04
	319	#define VDEC_F_OUT_CTRL_NS 0x1A08
	320	#define VDEC_F_GEN_STAT 0x1A0C
1a9fc855	321	#define VDEC_F_INT_STAT_MASK 0x1A10
f70a6566 LF	322	#define VDEC_F_LUMA_CTRL 0x1A14
	323	#define VDEC_F_CHROMA_CTRL 0x1A18
	324	#define VDEC_F_CRUSH_CTRL 0x1A1C
1a9fc855 MCC	325	#define VDEC_F_HORIZ_TIM_CTRL 0x1A20
	326	#define VDEC_F_VERT_TIM_CTRL 0x1A24
	327	#define VDEC_F_MISC_TIM_CTRL 0x1A28
f70a6566 LF	328	#define VDEC_F_FIELD_COUNT 0x1A2C
	329	#define VDEC_F_HSCALE_CTRL 0x1A30
	330	#define VDEC_F_VSCALE_CTRL 0x1A34
	331	#define VDEC_F_MAN_VGA_CTRL 0x1A38
	332	#define VDEC_F_MAN_AGC_CTRL 0x1A3C
	333	#define VDEC_F_DFE_CTRL1 0x1A40
	334	#define VDEC_F_DFE_CTRL2 0x1A44
	335	#define VDEC_F_DFE_CTRL3 0x1A48
	336	#define VDEC_F_PLL_CTRL 0x1A4C
1a9fc855	337	#define VDEC_F_PLL_CTRL_FAST 0x1A50
f70a6566 LF	338	#define VDEC_F_HTL_CTRL 0x1A54
	339	#define VDEC_F_SRC_CFG 0x1A58
	340	#define VDEC_F_SC_STEP_SIZE 0x1A5C
1a9fc855	341	#define VDEC_F_SC_CONVERGE_CTRL 0x1A60
f70a6566	342	#define VDEC_F_SC_LOOP_CTRL 0x1A64
1a9fc855 MCC	343	#define VDEC_F_COMB_2D_HFS_CFG 0x1A68
	344	#define VDEC_F_COMB_2D_HFD_CFG 0x1A6C
	345	#define VDEC_F_COMB_2D_LF_CFG 0x1A70
	346	#define VDEC_F_COMB_2D_BLEND 0x1A74
	347	#define VDEC_F_COMB_MISC_CTRL 0x1A78
f70a6566 LF	348	#define VDEC_F_COMB_FLAT_THRESH_CTRL 0x1A7C
	349	#define VDEC_F_COMB_TEST 0x1A80
	350	#define VDEC_F_BP_MISC_CTRL 0x1A84
	351	#define VDEC_F_VCR_DET_CTRL 0x1A88
1a9fc855 MCC	352	#define VDEC_F_NOISE_DET_CTRL 0x1A8C
1a9fc855 MCC	353	#define VDEC_F_COMB_FLAT_NOISE_CTRL 0x1A90
f70a6566	354	#define VDEC_F_VERSION 0x1BF8
1a9fc855 MCC	355	#define VDEC_F_SOFT_RST_CTRL 0x1BFC
1a9fc855 MCC	356
6d8c2ba1	357	/* Video Decoder G Registers */
f70a6566 LF	358	#define VDEC_G_MODE_CTRL 0x1C00
	359	#define VDEC_G_OUT_CTRL1 0x1C04
	360	#define VDEC_G_OUT_CTRL_NS 0x1C08
	361	#define VDEC_G_GEN_STAT 0x1C0C
1a9fc855	362	#define VDEC_G_INT_STAT_MASK 0x1C10
f70a6566 LF	363	#define VDEC_G_LUMA_CTRL 0x1C14
	364	#define VDEC_G_CHROMA_CTRL 0x1C18
	365	#define VDEC_G_CRUSH_CTRL 0x1C1C
1a9fc855 MCC	366	#define VDEC_G_HORIZ_TIM_CTRL 0x1C20
	367	#define VDEC_G_VERT_TIM_CTRL 0x1C24
	368	#define VDEC_G_MISC_TIM_CTRL 0x1C28
f70a6566 LF	369	#define VDEC_G_FIELD_COUNT 0x1C2C
	370	#define VDEC_G_HSCALE_CTRL 0x1C30
	371	#define VDEC_G_VSCALE_CTRL 0x1C34
	372	#define VDEC_G_MAN_VGA_CTRL 0x1C38
	373	#define VDEC_G_MAN_AGC_CTRL 0x1C3C
	374	#define VDEC_G_DFE_CTRL1 0x1C40
	375	#define VDEC_G_DFE_CTRL2 0x1C44
	376	#define VDEC_G_DFE_CTRL3 0x1C48
	377	#define VDEC_G_PLL_CTRL 0x1C4C
1a9fc855	378	#define VDEC_G_PLL_CTRL_FAST 0x1C50
f70a6566 LF	379	#define VDEC_G_HTL_CTRL 0x1C54
	380	#define VDEC_G_SRC_CFG 0x1C58
	381	#define VDEC_G_SC_STEP_SIZE 0x1C5C
1a9fc855	382	#define VDEC_G_SC_CONVERGE_CTRL 0x1C60
f70a6566	383	#define VDEC_G_SC_LOOP_CTRL 0x1C64
1a9fc855 MCC	384	#define VDEC_G_COMB_2D_HFS_CFG 0x1C68
	385	#define VDEC_G_COMB_2D_HFD_CFG 0x1C6C
	386	#define VDEC_G_COMB_2D_LF_CFG 0x1C70
	387	#define VDEC_G_COMB_2D_BLEND 0x1C74
	388	#define VDEC_G_COMB_MISC_CTRL 0x1C78
f70a6566 LF	389	#define VDEC_G_COMB_FLAT_THRESH_CTRL 0x1C7C
	390	#define VDEC_G_COMB_TEST 0x1C80
	391	#define VDEC_G_BP_MISC_CTRL 0x1C84
	392	#define VDEC_G_VCR_DET_CTRL 0x1C88
1a9fc855 MCC	393	#define VDEC_G_NOISE_DET_CTRL 0x1C8C
1a9fc855 MCC	394	#define VDEC_G_COMB_FLAT_NOISE_CTRL 0x1C90
f70a6566	395	#define VDEC_G_VERSION 0x1DF8
1a9fc855 MCC	396	#define VDEC_G_SOFT_RST_CTRL 0x1DFC
1a9fc855 MCC	397
f70a6566 LF	398	/* Video Decoder H Registers */
	399	#define VDEC_H_MODE_CTRL 0x1E00
	400	#define VDEC_H_OUT_CTRL1 0x1E04
	401	#define VDEC_H_OUT_CTRL_NS 0x1E08
	402	#define VDEC_H_GEN_STAT 0x1E0C
1a9fc855	403	#define VDEC_H_INT_STAT_MASK 0x1E1E
f70a6566 LF	404	#define VDEC_H_LUMA_CTRL 0x1E14
	405	#define VDEC_H_CHROMA_CTRL 0x1E18
	406	#define VDEC_H_CRUSH_CTRL 0x1E1C
1a9fc855 MCC	407	#define VDEC_H_HORIZ_TIM_CTRL 0x1E20
	408	#define VDEC_H_VERT_TIM_CTRL 0x1E24
	409	#define VDEC_H_MISC_TIM_CTRL 0x1E28
f70a6566 LF	410	#define VDEC_H_FIELD_COUNT 0x1E2C
	411	#define VDEC_H_HSCALE_CTRL 0x1E30
	412	#define VDEC_H_VSCALE_CTRL 0x1E34
	413	#define VDEC_H_MAN_VGA_CTRL 0x1E38
	414	#define VDEC_H_MAN_AGC_CTRL 0x1E3C
	415	#define VDEC_H_DFE_CTRL1 0x1E40
	416	#define VDEC_H_DFE_CTRL2 0x1E44
	417	#define VDEC_H_DFE_CTRL3 0x1E48
	418	#define VDEC_H_PLL_CTRL 0x1E4C
1a9fc855	419	#define VDEC_H_PLL_CTRL_FAST 0x1E50
f70a6566 LF	420	#define VDEC_H_HTL_CTRL 0x1E54
	421	#define VDEC_H_SRC_CFG 0x1E58
	422	#define VDEC_H_SC_STEP_SIZE 0x1E5C
1a9fc855	423	#define VDEC_H_SC_CONVERGE_CTRL 0x1E60
f70a6566	424	#define VDEC_H_SC_LOOP_CTRL 0x1E64
1a9fc855 MCC	425	#define VDEC_H_COMB_2D_HFS_CFG 0x1E68
	426	#define VDEC_H_COMB_2D_HFD_CFG 0x1E6C
	427	#define VDEC_H_COMB_2D_LF_CFG 0x1E70
	428	#define VDEC_H_COMB_2D_BLEND 0x1E74
	429	#define VDEC_H_COMB_MISC_CTRL 0x1E78
f70a6566 LF	430	#define VDEC_H_COMB_FLAT_THRESH_CTRL 0x1E7C
	431	#define VDEC_H_COMB_TEST 0x1E80
	432	#define VDEC_H_BP_MISC_CTRL 0x1E84
	433	#define VDEC_H_VCR_DET_CTRL 0x1E88
1a9fc855 MCC	434	#define VDEC_H_NOISE_DET_CTRL 0x1E8C
1a9fc855 MCC	435	#define VDEC_H_COMB_FLAT_NOISE_CTRL 0x1E90
f70a6566	436	#define VDEC_H_VERSION 0x1FF8
1a9fc855 MCC	437	#define VDEC_H_SOFT_RST_CTRL 0x1FFC
1a9fc855 MCC	438
6d8c2ba1 PB	439	/*****************************************************************************/
6d8c2ba1 PB	440	/* LUMA_CTRL register fields */
f70a6566	441	#define VDEC_A_BRITE_CTRL 0x1014
e4115bb2 RP	442	#define VDEC_A_CNTRST_CTRL 0x1015
e4115bb2 RP	443	#define VDEC_A_PEAK_SEL 0x1016
1a9fc855	444
6d8c2ba1 PB	445	/*****************************************************************************/
6d8c2ba1 PB	446	/* CHROMA_CTRL register fields */
e4115bb2 RP	447	#define VDEC_A_USAT_CTRL 0x1018
	448	#define VDEC_A_VSAT_CTRL 0x1019
	449	#define VDEC_A_HUE_CTRL 0x101A
1a9fc855	450
02b20b0b	451	#endif