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Commit | Line | Data |
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02b20b0b MCC |
1 | /* |
2 | * Driver for the Conexant CX25821 PCIe bridge | |
3 | * | |
bb4c9a74 | 4 | * Copyright (C) 2009 Conexant Systems Inc. |
02b20b0b | 5 | * Authors <shu.lin@conexant.com>, <hiep.huynh@conexant.com> |
b671ae6b | 6 | * Based on Steven Toth <stoth@linuxtv.org> cx25821 driver |
6d8c2ba1 PB |
7 | * Parts adapted/taken from Eduardo Moscoso Rubino |
8 | * Copyright (C) 2009 Eduardo Moscoso Rubino <moscoso@TopoLogica.com> | |
9 | * | |
02b20b0b MCC |
10 | * |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2 of the License, or | |
14 | * (at your option) any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | * | |
20 | * GNU General Public License for more details. | |
02b20b0b MCC |
21 | */ |
22 | ||
36d89f7d JP |
23 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
24 | ||
02b20b0b MCC |
25 | #include "cx25821-video.h" |
26 | ||
27 | MODULE_DESCRIPTION("v4l2 driver module for cx25821 based TV cards"); | |
6d8c2ba1 | 28 | MODULE_AUTHOR("Hiep Huynh <hiep.huynh@conexant.com>"); |
02b20b0b MCC |
29 | MODULE_LICENSE("GPL"); |
30 | ||
53e712d0 | 31 | static unsigned int video_nr[] = {[0 ... (CX25821_MAXBOARDS - 1)] = UNSET }; |
02b20b0b MCC |
32 | |
33 | module_param_array(video_nr, int, NULL, 0444); | |
02b20b0b MCC |
34 | |
35 | MODULE_PARM_DESC(video_nr, "video device numbers"); | |
02b20b0b | 36 | |
1a9fc855 | 37 | static unsigned int video_debug = VIDEO_DEBUG; |
02b20b0b MCC |
38 | module_param(video_debug, int, 0644); |
39 | MODULE_PARM_DESC(video_debug, "enable debug messages [video]"); | |
40 | ||
41 | static unsigned int irq_debug; | |
42 | module_param(irq_debug, int, 0644); | |
43 | MODULE_PARM_DESC(irq_debug, "enable debug messages [IRQ handler]"); | |
44 | ||
02b20b0b MCC |
45 | #define FORMAT_FLAGS_PACKED 0x01 |
46 | ||
95c232a2 | 47 | static const struct cx25821_fmt formats[] = { |
1a9fc855 | 48 | { |
d7d93387 MCC |
49 | .name = "4:1:1, packed, Y41P", |
50 | .fourcc = V4L2_PIX_FMT_Y41P, | |
51 | .depth = 12, | |
52 | .flags = FORMAT_FLAGS_PACKED, | |
53 | }, { | |
54 | .name = "4:2:2, packed, YUYV", | |
55 | .fourcc = V4L2_PIX_FMT_YUYV, | |
56 | .depth = 16, | |
57 | .flags = FORMAT_FLAGS_PACKED, | |
d7d93387 | 58 | }, |
02b20b0b MCC |
59 | }; |
60 | ||
95c232a2 | 61 | static const struct cx25821_fmt *cx25821_format_by_fourcc(unsigned int fourcc) |
02b20b0b | 62 | { |
1a9fc855 | 63 | unsigned int i; |
02b20b0b | 64 | |
1a9fc855 MCC |
65 | for (i = 0; i < ARRAY_SIZE(formats); i++) |
66 | if (formats[i].fourcc == fourcc) | |
67 | return formats + i; | |
1a9fc855 | 68 | return NULL; |
02b20b0b MCC |
69 | } |
70 | ||
02b20b0b | 71 | int cx25821_start_video_dma(struct cx25821_dev *dev, |
1a9fc855 MCC |
72 | struct cx25821_dmaqueue *q, |
73 | struct cx25821_buffer *buf, | |
bfef0d35 | 74 | const struct sram_channel *channel) |
02b20b0b | 75 | { |
1a9fc855 | 76 | int tmp = 0; |
02b20b0b | 77 | |
1a9fc855 MCC |
78 | /* setup fifo + format */ |
79 | cx25821_sram_channel_setup(dev, channel, buf->bpl, buf->risc.dma); | |
02b20b0b | 80 | |
1a9fc855 MCC |
81 | /* reset counter */ |
82 | cx_write(channel->gpcnt_ctl, 3); | |
02b20b0b | 83 | |
1a9fc855 MCC |
84 | /* enable irq */ |
85 | cx_set(PCI_INT_MSK, cx_read(PCI_INT_MSK) | (1 << channel->i)); | |
86 | cx_set(channel->int_msk, 0x11); | |
02b20b0b | 87 | |
1a9fc855 MCC |
88 | /* start dma */ |
89 | cx_write(channel->dma_ctl, 0x11); /* FIFO and RISC enable */ | |
02b20b0b | 90 | |
1a9fc855 MCC |
91 | /* make sure upstream setting if any is reversed */ |
92 | tmp = cx_read(VID_CH_MODE_SEL); | |
93 | cx_write(VID_CH_MODE_SEL, tmp & 0xFFFFFE00); | |
02b20b0b | 94 | |
1a9fc855 | 95 | return 0; |
02b20b0b MCC |
96 | } |
97 | ||
02b20b0b MCC |
98 | int cx25821_video_irq(struct cx25821_dev *dev, int chan_num, u32 status) |
99 | { | |
1a9fc855 MCC |
100 | int handled = 0; |
101 | u32 mask; | |
bfef0d35 | 102 | const struct sram_channel *channel = dev->channels[chan_num].sram_channels; |
1a9fc855 MCC |
103 | |
104 | mask = cx_read(channel->int_msk); | |
105 | if (0 == (status & mask)) | |
106 | return handled; | |
107 | ||
108 | cx_write(channel->int_stat, status); | |
109 | ||
110 | /* risc op code error */ | |
111 | if (status & (1 << 16)) { | |
36d89f7d JP |
112 | pr_warn("%s, %s: video risc op code error\n", |
113 | dev->name, channel->name); | |
1a9fc855 MCC |
114 | cx_clear(channel->dma_ctl, 0x11); |
115 | cx25821_sram_channel_dump(dev, channel); | |
116 | } | |
02b20b0b | 117 | |
1a9fc855 MCC |
118 | /* risc1 y */ |
119 | if (status & FLD_VID_DST_RISC1) { | |
b671ae6b HV |
120 | struct cx25821_dmaqueue *dmaq = |
121 | &dev->channels[channel->i].dma_vidq; | |
122 | struct cx25821_buffer *buf; | |
02b20b0b | 123 | |
1a9fc855 | 124 | spin_lock(&dev->slock); |
b671ae6b HV |
125 | if (!list_empty(&dmaq->active)) { |
126 | buf = list_entry(dmaq->active.next, | |
127 | struct cx25821_buffer, queue); | |
128 | ||
d6dd645e | 129 | buf->vb.vb2_buf.timestamp = ktime_get_ns(); |
2d700715 | 130 | buf->vb.sequence = dmaq->count++; |
b671ae6b | 131 | list_del(&buf->queue); |
2d700715 | 132 | vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_DONE); |
b671ae6b | 133 | } |
1a9fc855 MCC |
134 | spin_unlock(&dev->slock); |
135 | handled++; | |
136 | } | |
137 | return handled; | |
02b20b0b MCC |
138 | } |
139 | ||
df9ecb0c | 140 | static int cx25821_queue_setup(struct vb2_queue *q, |
b671ae6b | 141 | unsigned int *num_buffers, unsigned int *num_planes, |
36c0f8b3 | 142 | unsigned int sizes[], struct device *alloc_devs[]) |
02b20b0b | 143 | { |
b671ae6b | 144 | struct cx25821_channel *chan = q->drv_priv; |
11c8a2df HV |
145 | unsigned size = (chan->fmt->depth * chan->width * chan->height) >> 3; |
146 | ||
df9ecb0c HV |
147 | if (*num_planes) |
148 | return sizes[0] < size ? -EINVAL : 0; | |
02b20b0b | 149 | |
b671ae6b | 150 | *num_planes = 1; |
df9ecb0c | 151 | sizes[0] = size; |
1a9fc855 | 152 | return 0; |
02b20b0b MCC |
153 | } |
154 | ||
b671ae6b | 155 | static int cx25821_buffer_prepare(struct vb2_buffer *vb) |
02b20b0b | 156 | { |
2d700715 | 157 | struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); |
b671ae6b | 158 | struct cx25821_channel *chan = vb->vb2_queue->drv_priv; |
2efe2cc4 | 159 | struct cx25821_dev *dev = chan->dev; |
1a9fc855 | 160 | struct cx25821_buffer *buf = |
2d700715 | 161 | container_of(vbuf, struct cx25821_buffer, vb); |
b671ae6b | 162 | struct sg_table *sgt = vb2_dma_sg_plane_desc(vb, 0); |
30fdf035 | 163 | u32 line0_offset; |
1a9fc855 | 164 | int bpl_local = LINE_SIZE_D1; |
b671ae6b | 165 | int ret; |
1a9fc855 | 166 | |
b671ae6b HV |
167 | if (chan->pixel_formats == PIXEL_FRMT_411) |
168 | buf->bpl = (chan->fmt->depth * chan->width) >> 3; | |
169 | else | |
170 | buf->bpl = (chan->fmt->depth >> 3) * chan->width; | |
bb4c9a74 | 171 | |
b671ae6b | 172 | if (vb2_plane_size(vb, 0) < chan->height * buf->bpl) |
1a9fc855 | 173 | return -EINVAL; |
b671ae6b | 174 | vb2_set_plane_payload(vb, 0, chan->height * buf->bpl); |
2d700715 | 175 | buf->vb.field = chan->field; |
bb4c9a74 | 176 | |
b671ae6b HV |
177 | if (chan->pixel_formats == PIXEL_FRMT_411) { |
178 | bpl_local = buf->bpl; | |
179 | } else { | |
180 | bpl_local = buf->bpl; /* Default */ | |
1a9fc855 | 181 | |
b671ae6b HV |
182 | if (chan->use_cif_resolution) { |
183 | if (dev->tvnorm & V4L2_STD_625_50) | |
184 | bpl_local = 352 << 1; | |
185 | else | |
186 | bpl_local = chan->cif_width << 1; | |
bb4c9a74 | 187 | } |
bb4c9a74 MCC |
188 | } |
189 | ||
b671ae6b HV |
190 | switch (chan->field) { |
191 | case V4L2_FIELD_TOP: | |
192 | ret = cx25821_risc_buffer(dev->pci, &buf->risc, | |
193 | sgt->sgl, 0, UNSET, | |
194 | buf->bpl, 0, chan->height); | |
195 | break; | |
196 | case V4L2_FIELD_BOTTOM: | |
197 | ret = cx25821_risc_buffer(dev->pci, &buf->risc, | |
198 | sgt->sgl, UNSET, 0, | |
199 | buf->bpl, 0, chan->height); | |
200 | break; | |
201 | case V4L2_FIELD_INTERLACED: | |
202 | /* All other formats are top field first */ | |
203 | line0_offset = 0; | |
204 | dprintk(1, "top field first\n"); | |
205 | ||
206 | ret = cx25821_risc_buffer(dev->pci, &buf->risc, | |
207 | sgt->sgl, line0_offset, | |
208 | bpl_local, bpl_local, bpl_local, | |
209 | chan->height >> 1); | |
210 | break; | |
211 | case V4L2_FIELD_SEQ_TB: | |
212 | ret = cx25821_risc_buffer(dev->pci, &buf->risc, | |
213 | sgt->sgl, | |
214 | 0, buf->bpl * (chan->height >> 1), | |
215 | buf->bpl, 0, chan->height >> 1); | |
216 | break; | |
217 | case V4L2_FIELD_SEQ_BT: | |
218 | ret = cx25821_risc_buffer(dev->pci, &buf->risc, | |
219 | sgt->sgl, | |
220 | buf->bpl * (chan->height >> 1), 0, | |
221 | buf->bpl, 0, chan->height >> 1); | |
222 | break; | |
223 | default: | |
224 | WARN_ON(1); | |
225 | ret = -EINVAL; | |
226 | break; | |
bb4c9a74 | 227 | } |
02b20b0b | 228 | |
1a9fc855 | 229 | dprintk(2, "[%p/%d] buffer_prep - %dx%d %dbpp \"%s\" - dma=0x%08lx\n", |
2d700715 | 230 | buf, buf->vb.vb2_buf.index, chan->width, chan->height, |
b671ae6b HV |
231 | chan->fmt->depth, chan->fmt->name, |
232 | (unsigned long)buf->risc.dma); | |
02b20b0b | 233 | |
b671ae6b | 234 | return ret; |
02b20b0b MCC |
235 | } |
236 | ||
b671ae6b | 237 | static void cx25821_buffer_finish(struct vb2_buffer *vb) |
02b20b0b | 238 | { |
2d700715 | 239 | struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); |
1a9fc855 | 240 | struct cx25821_buffer *buf = |
2d700715 | 241 | container_of(vbuf, struct cx25821_buffer, vb); |
b671ae6b HV |
242 | struct cx25821_channel *chan = vb->vb2_queue->drv_priv; |
243 | struct cx25821_dev *dev = chan->dev; | |
02b20b0b | 244 | |
b671ae6b | 245 | cx25821_free_buffer(dev, buf); |
02b20b0b MCC |
246 | } |
247 | ||
b671ae6b | 248 | static void cx25821_buffer_queue(struct vb2_buffer *vb) |
6d8c2ba1 | 249 | { |
2d700715 | 250 | struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); |
8e4ac074 | 251 | struct cx25821_buffer *buf = |
2d700715 | 252 | container_of(vbuf, struct cx25821_buffer, vb); |
b671ae6b | 253 | struct cx25821_channel *chan = vb->vb2_queue->drv_priv; |
2efe2cc4 | 254 | struct cx25821_dev *dev = chan->dev; |
b671ae6b | 255 | struct cx25821_buffer *prev; |
2efe2cc4 | 256 | struct cx25821_dmaqueue *q = &dev->channels[chan->id].dma_vidq; |
e6cf66c1 | 257 | |
b671ae6b HV |
258 | buf->risc.cpu[1] = cpu_to_le32(buf->risc.dma + 12); |
259 | buf->risc.jmp[0] = cpu_to_le32(RISC_JUMP | RISC_CNT_INC); | |
260 | buf->risc.jmp[1] = cpu_to_le32(buf->risc.dma + 12); | |
261 | buf->risc.jmp[2] = cpu_to_le32(0); /* bits 63-32 */ | |
262 | ||
263 | if (list_empty(&q->active)) { | |
264 | list_add_tail(&buf->queue, &q->active); | |
e6cf66c1 | 265 | } else { |
b671ae6b | 266 | buf->risc.cpu[0] |= cpu_to_le32(RISC_IRQ1); |
e6cf66c1 | 267 | prev = list_entry(q->active.prev, struct cx25821_buffer, |
b671ae6b HV |
268 | queue); |
269 | list_add_tail(&buf->queue, &q->active); | |
270 | prev->risc.jmp[1] = cpu_to_le32(buf->risc.dma); | |
8ebbda49 | 271 | } |
6d8c2ba1 PB |
272 | } |
273 | ||
b671ae6b | 274 | static int cx25821_start_streaming(struct vb2_queue *q, unsigned int count) |
6d8c2ba1 | 275 | { |
b671ae6b | 276 | struct cx25821_channel *chan = q->drv_priv; |
8d125c50 | 277 | struct cx25821_dev *dev = chan->dev; |
b671ae6b HV |
278 | struct cx25821_dmaqueue *dmaq = &dev->channels[chan->id].dma_vidq; |
279 | struct cx25821_buffer *buf = list_entry(dmaq->active.next, | |
280 | struct cx25821_buffer, queue); | |
84293f08 | 281 | |
b671ae6b HV |
282 | dmaq->count = 0; |
283 | cx25821_start_video_dma(dev, dmaq, buf, chan->sram_channels); | |
284 | return 0; | |
6d8c2ba1 PB |
285 | } |
286 | ||
b671ae6b | 287 | static void cx25821_stop_streaming(struct vb2_queue *q) |
6d8c2ba1 | 288 | { |
b671ae6b | 289 | struct cx25821_channel *chan = q->drv_priv; |
2efe2cc4 | 290 | struct cx25821_dev *dev = chan->dev; |
b671ae6b HV |
291 | struct cx25821_dmaqueue *dmaq = &dev->channels[chan->id].dma_vidq; |
292 | unsigned long flags; | |
6d8c2ba1 | 293 | |
b671ae6b HV |
294 | cx_write(chan->sram_channels->dma_ctl, 0); /* FIFO and RISC disable */ |
295 | spin_lock_irqsave(&dev->slock, flags); | |
296 | while (!list_empty(&dmaq->active)) { | |
297 | struct cx25821_buffer *buf = list_entry(dmaq->active.next, | |
298 | struct cx25821_buffer, queue); | |
6d8c2ba1 | 299 | |
b671ae6b | 300 | list_del(&buf->queue); |
2d700715 | 301 | vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR); |
21377cdd | 302 | } |
b671ae6b | 303 | spin_unlock_irqrestore(&dev->slock, flags); |
6d8c2ba1 PB |
304 | } |
305 | ||
10accd2e | 306 | static const struct vb2_ops cx25821_video_qops = { |
b671ae6b HV |
307 | .queue_setup = cx25821_queue_setup, |
308 | .buf_prepare = cx25821_buffer_prepare, | |
309 | .buf_finish = cx25821_buffer_finish, | |
310 | .buf_queue = cx25821_buffer_queue, | |
311 | .wait_prepare = vb2_ops_wait_prepare, | |
312 | .wait_finish = vb2_ops_wait_finish, | |
313 | .start_streaming = cx25821_start_streaming, | |
314 | .stop_streaming = cx25821_stop_streaming, | |
315 | }; | |
316 | ||
95c232a2 | 317 | /* VIDEO IOCTLS */ |
4c1d0f73 HV |
318 | |
319 | static int cx25821_vidioc_enum_fmt_vid_cap(struct file *file, void *priv, | |
320 | struct v4l2_fmtdesc *f) | |
321 | { | |
322 | if (unlikely(f->index >= ARRAY_SIZE(formats))) | |
323 | return -EINVAL; | |
324 | ||
325 | strlcpy(f->description, formats[f->index].name, sizeof(f->description)); | |
326 | f->pixelformat = formats[f->index].fourcc; | |
327 | ||
328 | return 0; | |
329 | } | |
330 | ||
95c232a2 HV |
331 | static int cx25821_vidioc_g_fmt_vid_cap(struct file *file, void *priv, |
332 | struct v4l2_format *f) | |
333 | { | |
2efe2cc4 | 334 | struct cx25821_channel *chan = video_drvdata(file); |
95c232a2 | 335 | |
2efe2cc4 HV |
336 | f->fmt.pix.width = chan->width; |
337 | f->fmt.pix.height = chan->height; | |
b671ae6b | 338 | f->fmt.pix.field = chan->field; |
2efe2cc4 | 339 | f->fmt.pix.pixelformat = chan->fmt->fourcc; |
988f7b80 HV |
340 | f->fmt.pix.bytesperline = (chan->width * chan->fmt->depth) >> 3; |
341 | f->fmt.pix.sizeimage = chan->height * f->fmt.pix.bytesperline; | |
342 | f->fmt.pix.colorspace = V4L2_COLORSPACE_SMPTE170M; | |
95c232a2 HV |
343 | |
344 | return 0; | |
345 | } | |
346 | ||
347 | static int cx25821_vidioc_try_fmt_vid_cap(struct file *file, void *priv, | |
348 | struct v4l2_format *f) | |
349 | { | |
988f7b80 HV |
350 | struct cx25821_channel *chan = video_drvdata(file); |
351 | struct cx25821_dev *dev = chan->dev; | |
95c232a2 | 352 | const struct cx25821_fmt *fmt; |
988f7b80 | 353 | enum v4l2_field field = f->fmt.pix.field; |
66f93178 | 354 | unsigned int maxh; |
988f7b80 | 355 | unsigned w; |
95c232a2 HV |
356 | |
357 | fmt = cx25821_format_by_fourcc(f->fmt.pix.pixelformat); | |
358 | if (NULL == fmt) | |
359 | return -EINVAL; | |
988f7b80 HV |
360 | maxh = (dev->tvnorm & V4L2_STD_625_50) ? 576 : 480; |
361 | ||
362 | w = f->fmt.pix.width; | |
363 | if (field != V4L2_FIELD_BOTTOM) | |
364 | field = V4L2_FIELD_TOP; | |
365 | if (w < 352) { | |
366 | w = 176; | |
367 | f->fmt.pix.height = maxh / 4; | |
368 | } else if (w < 720) { | |
369 | w = 352; | |
370 | f->fmt.pix.height = maxh / 2; | |
371 | } else { | |
372 | w = 720; | |
373 | f->fmt.pix.height = maxh; | |
374 | field = V4L2_FIELD_INTERLACED; | |
95c232a2 | 375 | } |
95c232a2 | 376 | f->fmt.pix.field = field; |
988f7b80 | 377 | f->fmt.pix.width = w; |
95c232a2 HV |
378 | f->fmt.pix.bytesperline = (f->fmt.pix.width * fmt->depth) >> 3; |
379 | f->fmt.pix.sizeimage = f->fmt.pix.height * f->fmt.pix.bytesperline; | |
988f7b80 | 380 | f->fmt.pix.colorspace = V4L2_COLORSPACE_SMPTE170M; |
95c232a2 HV |
381 | |
382 | return 0; | |
383 | } | |
6d8c2ba1 PB |
384 | |
385 | static int vidioc_s_fmt_vid_cap(struct file *file, void *priv, | |
c1e6e241 | 386 | struct v4l2_format *f) |
6d8c2ba1 | 387 | { |
2efe2cc4 | 388 | struct cx25821_channel *chan = video_drvdata(file); |
8d125c50 | 389 | struct cx25821_dev *dev = chan->dev; |
a39bea3a | 390 | int pix_format = PIXEL_FRMT_422; |
a6aa0dc4 | 391 | int err; |
a39bea3a | 392 | |
255c040a | 393 | err = cx25821_vidioc_try_fmt_vid_cap(file, priv, f); |
6d8c2ba1 | 394 | |
255c040a LF |
395 | if (0 != err) |
396 | return err; | |
6d8c2ba1 | 397 | |
2efe2cc4 | 398 | chan->fmt = cx25821_format_by_fourcc(f->fmt.pix.pixelformat); |
b671ae6b | 399 | chan->field = f->fmt.pix.field; |
988f7b80 HV |
400 | chan->width = f->fmt.pix.width; |
401 | chan->height = f->fmt.pix.height; | |
6d8c2ba1 | 402 | |
6678762a LF |
403 | if (f->fmt.pix.pixelformat == V4L2_PIX_FMT_Y41P) |
404 | pix_format = PIXEL_FRMT_411; | |
6678762a | 405 | else |
988f7b80 | 406 | pix_format = PIXEL_FRMT_422; |
6d8c2ba1 | 407 | |
6678762a | 408 | cx25821_set_pixel_format(dev, SRAM_CH00, pix_format); |
6d8c2ba1 | 409 | |
6678762a | 410 | /* check if cif resolution */ |
2efe2cc4 HV |
411 | if (chan->width == 320 || chan->width == 352) |
412 | chan->use_cif_resolution = 1; | |
6678762a | 413 | else |
2efe2cc4 | 414 | chan->use_cif_resolution = 0; |
6d8c2ba1 | 415 | |
2efe2cc4 HV |
416 | chan->cif_width = chan->width; |
417 | medusa_set_resolution(dev, chan->width, SRAM_CH00); | |
6678762a | 418 | return 0; |
6d8c2ba1 PB |
419 | } |
420 | ||
6d8c2ba1 PB |
421 | static int vidioc_log_status(struct file *file, void *priv) |
422 | { | |
8d125c50 HV |
423 | struct cx25821_channel *chan = video_drvdata(file); |
424 | struct cx25821_dev *dev = chan->dev; | |
425 | const struct sram_channel *sram_ch = chan->sram_channels; | |
02859b61 | 426 | u32 tmp = 0; |
6d8c2ba1 | 427 | |
02859b61 | 428 | tmp = cx_read(sram_ch->dma_ctl); |
36d89f7d JP |
429 | pr_info("Video input 0 is %s\n", |
430 | (tmp & 0x11) ? "streaming" : "stopped"); | |
02859b61 | 431 | return 0; |
6d8c2ba1 PB |
432 | } |
433 | ||
02b20b0b | 434 | |
95c232a2 | 435 | static int cx25821_vidioc_querycap(struct file *file, void *priv, |
c1e6e241 | 436 | struct v4l2_capability *cap) |
02b20b0b | 437 | { |
8d125c50 HV |
438 | struct cx25821_channel *chan = video_drvdata(file); |
439 | struct cx25821_dev *dev = chan->dev; | |
3dd473ca HV |
440 | const u32 cap_input = V4L2_CAP_VIDEO_CAPTURE | |
441 | V4L2_CAP_READWRITE | V4L2_CAP_STREAMING; | |
0df13d99 | 442 | const u32 cap_output = V4L2_CAP_VIDEO_OUTPUT | V4L2_CAP_READWRITE; |
1a9fc855 MCC |
443 | |
444 | strcpy(cap->driver, "cx25821"); | |
445 | strlcpy(cap->card, cx25821_boards[dev->board].name, sizeof(cap->card)); | |
446 | sprintf(cap->bus_info, "PCIe:%s", pci_name(dev->pci)); | |
8d125c50 | 447 | if (chan->id >= VID_CHANNEL_NUM) |
3dd473ca HV |
448 | cap->device_caps = cap_output; |
449 | else | |
450 | cap->device_caps = cap_input; | |
0df13d99 | 451 | cap->capabilities = cap_input | cap_output | V4L2_CAP_DEVICE_CAPS; |
1a9fc855 | 452 | return 0; |
02b20b0b MCC |
453 | } |
454 | ||
95c232a2 | 455 | static int cx25821_vidioc_g_std(struct file *file, void *priv, v4l2_std_id *tvnorms) |
18c73af6 | 456 | { |
8d125c50 | 457 | struct cx25821_channel *chan = video_drvdata(file); |
18c73af6 | 458 | |
8d125c50 | 459 | *tvnorms = chan->dev->tvnorm; |
18c73af6 HV |
460 | return 0; |
461 | } | |
462 | ||
a3f17af2 MCC |
463 | static int cx25821_vidioc_s_std(struct file *file, void *priv, |
464 | v4l2_std_id tvnorms) | |
02b20b0b | 465 | { |
8d125c50 HV |
466 | struct cx25821_channel *chan = video_drvdata(file); |
467 | struct cx25821_dev *dev = chan->dev; | |
02b20b0b | 468 | |
314527ac | 469 | if (dev->tvnorm == tvnorms) |
1a9fc855 | 470 | return 0; |
02b20b0b | 471 | |
a6aa0dc4 | 472 | dev->tvnorm = tvnorms; |
988f7b80 HV |
473 | chan->width = 720; |
474 | chan->height = (dev->tvnorm & V4L2_STD_625_50) ? 576 : 480; | |
02b20b0b | 475 | |
1a9fc855 | 476 | medusa_set_videostandard(dev); |
02b20b0b | 477 | |
1a9fc855 | 478 | return 0; |
02b20b0b | 479 | } |
02b20b0b | 480 | |
95c232a2 HV |
481 | static int cx25821_vidioc_enum_input(struct file *file, void *priv, |
482 | struct v4l2_input *i) | |
02b20b0b | 483 | { |
a6aa0dc4 | 484 | if (i->index) |
1a9fc855 | 485 | return -EINVAL; |
02b20b0b | 486 | |
1a9fc855 | 487 | i->type = V4L2_INPUT_TYPE_CAMERA; |
1a9fc855 | 488 | i->std = CX25821_NORMS; |
a6aa0dc4 | 489 | strcpy(i->name, "Composite"); |
1a9fc855 | 490 | return 0; |
02b20b0b MCC |
491 | } |
492 | ||
95c232a2 | 493 | static int cx25821_vidioc_g_input(struct file *file, void *priv, unsigned int *i) |
bb4c9a74 | 494 | { |
a6aa0dc4 | 495 | *i = 0; |
1a9fc855 | 496 | return 0; |
02b20b0b MCC |
497 | } |
498 | ||
95c232a2 | 499 | static int cx25821_vidioc_s_input(struct file *file, void *priv, unsigned int i) |
02b20b0b | 500 | { |
a6aa0dc4 | 501 | return i ? -EINVAL : 0; |
02b20b0b MCC |
502 | } |
503 | ||
f8d7ee70 | 504 | static int cx25821_s_ctrl(struct v4l2_ctrl *ctrl) |
02b20b0b | 505 | { |
f8d7ee70 HV |
506 | struct cx25821_channel *chan = |
507 | container_of(ctrl->handler, struct cx25821_channel, hdl); | |
508 | struct cx25821_dev *dev = chan->dev; | |
02b20b0b | 509 | |
f8d7ee70 | 510 | switch (ctrl->id) { |
1a9fc855 | 511 | case V4L2_CID_BRIGHTNESS: |
f8d7ee70 | 512 | medusa_set_brightness(dev, ctrl->val, chan->id); |
02b20b0b | 513 | break; |
1a9fc855 | 514 | case V4L2_CID_HUE: |
f8d7ee70 | 515 | medusa_set_hue(dev, ctrl->val, chan->id); |
02b20b0b | 516 | break; |
1a9fc855 | 517 | case V4L2_CID_CONTRAST: |
f8d7ee70 | 518 | medusa_set_contrast(dev, ctrl->val, chan->id); |
02b20b0b | 519 | break; |
1a9fc855 | 520 | case V4L2_CID_SATURATION: |
f8d7ee70 | 521 | medusa_set_saturation(dev, ctrl->val, chan->id); |
02b20b0b | 522 | break; |
1a9fc855 | 523 | default: |
f8d7ee70 | 524 | return -EINVAL; |
02b20b0b | 525 | } |
f8d7ee70 | 526 | return 0; |
02b20b0b MCC |
527 | } |
528 | ||
1f198870 HV |
529 | static int cx25821_vidioc_enum_output(struct file *file, void *priv, |
530 | struct v4l2_output *o) | |
6d8c2ba1 | 531 | { |
1f198870 HV |
532 | if (o->index) |
533 | return -EINVAL; | |
6d8c2ba1 | 534 | |
1f198870 HV |
535 | o->type = V4L2_INPUT_TYPE_CAMERA; |
536 | o->std = CX25821_NORMS; | |
537 | strcpy(o->name, "Composite"); | |
6f87cc6c | 538 | return 0; |
6d8c2ba1 PB |
539 | } |
540 | ||
1f198870 | 541 | static int cx25821_vidioc_g_output(struct file *file, void *priv, unsigned int *o) |
6d8c2ba1 | 542 | { |
1f198870 | 543 | *o = 0; |
f9ef6be3 | 544 | return 0; |
6d8c2ba1 PB |
545 | } |
546 | ||
1f198870 | 547 | static int cx25821_vidioc_s_output(struct file *file, void *priv, unsigned int o) |
6d8c2ba1 | 548 | { |
1f198870 | 549 | return o ? -EINVAL : 0; |
6d8c2ba1 PB |
550 | } |
551 | ||
e90878ab HV |
552 | static int cx25821_vidioc_try_fmt_vid_out(struct file *file, void *priv, |
553 | struct v4l2_format *f) | |
554 | { | |
555 | struct cx25821_channel *chan = video_drvdata(file); | |
556 | struct cx25821_dev *dev = chan->dev; | |
557 | const struct cx25821_fmt *fmt; | |
558 | ||
559 | fmt = cx25821_format_by_fourcc(f->fmt.pix.pixelformat); | |
560 | if (NULL == fmt) | |
561 | return -EINVAL; | |
562 | f->fmt.pix.width = 720; | |
563 | f->fmt.pix.height = (dev->tvnorm & V4L2_STD_625_50) ? 576 : 480; | |
564 | f->fmt.pix.field = V4L2_FIELD_INTERLACED; | |
565 | f->fmt.pix.bytesperline = (f->fmt.pix.width * fmt->depth) >> 3; | |
566 | f->fmt.pix.sizeimage = f->fmt.pix.height * f->fmt.pix.bytesperline; | |
567 | f->fmt.pix.colorspace = V4L2_COLORSPACE_SMPTE170M; | |
e90878ab HV |
568 | return 0; |
569 | } | |
570 | ||
571 | static int vidioc_s_fmt_vid_out(struct file *file, void *priv, | |
572 | struct v4l2_format *f) | |
573 | { | |
574 | struct cx25821_channel *chan = video_drvdata(file); | |
575 | int err; | |
576 | ||
577 | err = cx25821_vidioc_try_fmt_vid_out(file, priv, f); | |
578 | ||
579 | if (0 != err) | |
580 | return err; | |
581 | ||
582 | chan->fmt = cx25821_format_by_fourcc(f->fmt.pix.pixelformat); | |
b671ae6b | 583 | chan->field = f->fmt.pix.field; |
e90878ab HV |
584 | chan->width = f->fmt.pix.width; |
585 | chan->height = f->fmt.pix.height; | |
586 | if (f->fmt.pix.pixelformat == V4L2_PIX_FMT_Y41P) | |
587 | chan->pixel_formats = PIXEL_FRMT_411; | |
588 | else | |
589 | chan->pixel_formats = PIXEL_FRMT_422; | |
590 | return 0; | |
591 | } | |
592 | ||
f8d7ee70 HV |
593 | static const struct v4l2_ctrl_ops cx25821_ctrl_ops = { |
594 | .s_ctrl = cx25821_s_ctrl, | |
595 | }; | |
596 | ||
6d8c2ba1 | 597 | static const struct v4l2_file_operations video_fops = { |
fa7ce1f4 | 598 | .owner = THIS_MODULE, |
8d125c50 | 599 | .open = v4l2_fh_open, |
b671ae6b HV |
600 | .release = vb2_fop_release, |
601 | .read = vb2_fop_read, | |
602 | .poll = vb2_fop_poll, | |
1f198870 | 603 | .unlocked_ioctl = video_ioctl2, |
b671ae6b | 604 | .mmap = vb2_fop_mmap, |
6d8c2ba1 PB |
605 | }; |
606 | ||
607 | static const struct v4l2_ioctl_ops video_ioctl_ops = { | |
fa7ce1f4 LF |
608 | .vidioc_querycap = cx25821_vidioc_querycap, |
609 | .vidioc_enum_fmt_vid_cap = cx25821_vidioc_enum_fmt_vid_cap, | |
610 | .vidioc_g_fmt_vid_cap = cx25821_vidioc_g_fmt_vid_cap, | |
611 | .vidioc_try_fmt_vid_cap = cx25821_vidioc_try_fmt_vid_cap, | |
612 | .vidioc_s_fmt_vid_cap = vidioc_s_fmt_vid_cap, | |
b671ae6b HV |
613 | .vidioc_reqbufs = vb2_ioctl_reqbufs, |
614 | .vidioc_prepare_buf = vb2_ioctl_prepare_buf, | |
11c8a2df | 615 | .vidioc_create_bufs = vb2_ioctl_create_bufs, |
b671ae6b HV |
616 | .vidioc_querybuf = vb2_ioctl_querybuf, |
617 | .vidioc_qbuf = vb2_ioctl_qbuf, | |
618 | .vidioc_dqbuf = vb2_ioctl_dqbuf, | |
619 | .vidioc_streamon = vb2_ioctl_streamon, | |
620 | .vidioc_streamoff = vb2_ioctl_streamoff, | |
18c73af6 | 621 | .vidioc_g_std = cx25821_vidioc_g_std, |
fa7ce1f4 | 622 | .vidioc_s_std = cx25821_vidioc_s_std, |
fa7ce1f4 LF |
623 | .vidioc_enum_input = cx25821_vidioc_enum_input, |
624 | .vidioc_g_input = cx25821_vidioc_g_input, | |
625 | .vidioc_s_input = cx25821_vidioc_s_input, | |
fa7ce1f4 | 626 | .vidioc_log_status = vidioc_log_status, |
8d125c50 HV |
627 | .vidioc_subscribe_event = v4l2_ctrl_subscribe_event, |
628 | .vidioc_unsubscribe_event = v4l2_event_unsubscribe, | |
6d8c2ba1 PB |
629 | }; |
630 | ||
ffd3c233 HV |
631 | static const struct video_device cx25821_video_device = { |
632 | .name = "cx25821-video", | |
527db49d | 633 | .fops = &video_fops, |
467870ca | 634 | .release = video_device_release_empty, |
ffd3c233 | 635 | .minor = -1, |
527db49d LF |
636 | .ioctl_ops = &video_ioctl_ops, |
637 | .tvnorms = CX25821_NORMS, | |
6d8c2ba1 | 638 | }; |
ffd3c233 | 639 | |
1f198870 HV |
640 | static const struct v4l2_file_operations video_out_fops = { |
641 | .owner = THIS_MODULE, | |
642 | .open = v4l2_fh_open, | |
b671ae6b HV |
643 | .release = vb2_fop_release, |
644 | .write = vb2_fop_write, | |
645 | .poll = vb2_fop_poll, | |
1f198870 | 646 | .unlocked_ioctl = video_ioctl2, |
b671ae6b | 647 | .mmap = vb2_fop_mmap, |
1f198870 HV |
648 | }; |
649 | ||
650 | static const struct v4l2_ioctl_ops video_out_ioctl_ops = { | |
651 | .vidioc_querycap = cx25821_vidioc_querycap, | |
e90878ab HV |
652 | .vidioc_enum_fmt_vid_out = cx25821_vidioc_enum_fmt_vid_cap, |
653 | .vidioc_g_fmt_vid_out = cx25821_vidioc_g_fmt_vid_cap, | |
654 | .vidioc_try_fmt_vid_out = cx25821_vidioc_try_fmt_vid_out, | |
655 | .vidioc_s_fmt_vid_out = vidioc_s_fmt_vid_out, | |
1f198870 HV |
656 | .vidioc_g_std = cx25821_vidioc_g_std, |
657 | .vidioc_s_std = cx25821_vidioc_s_std, | |
658 | .vidioc_enum_output = cx25821_vidioc_enum_output, | |
659 | .vidioc_g_output = cx25821_vidioc_g_output, | |
660 | .vidioc_s_output = cx25821_vidioc_s_output, | |
661 | .vidioc_log_status = vidioc_log_status, | |
662 | }; | |
663 | ||
664 | static const struct video_device cx25821_video_out_device = { | |
665 | .name = "cx25821-video", | |
666 | .fops = &video_out_fops, | |
667 | .release = video_device_release_empty, | |
668 | .minor = -1, | |
669 | .ioctl_ops = &video_out_ioctl_ops, | |
670 | .tvnorms = CX25821_NORMS, | |
671 | }; | |
672 | ||
ffd3c233 HV |
673 | void cx25821_video_unregister(struct cx25821_dev *dev, int chan_num) |
674 | { | |
675 | cx_clear(PCI_INT_MSK, 1); | |
676 | ||
467870ca HV |
677 | if (video_is_registered(&dev->channels[chan_num].vdev)) { |
678 | video_unregister_device(&dev->channels[chan_num].vdev); | |
f8d7ee70 | 679 | v4l2_ctrl_handler_free(&dev->channels[chan_num].hdl); |
ffd3c233 | 680 | } |
ffd3c233 HV |
681 | } |
682 | ||
683 | int cx25821_video_register(struct cx25821_dev *dev) | |
684 | { | |
685 | int err; | |
686 | int i; | |
687 | ||
be178cb4 | 688 | /* initial device configuration */ |
a6aa0dc4 | 689 | dev->tvnorm = V4L2_STD_NTSC_M; |
be178cb4 | 690 | |
ffd3c233 HV |
691 | spin_lock_init(&dev->slock); |
692 | ||
b6f21dc3 | 693 | for (i = 0; i < MAX_VID_CAP_CHANNEL_NUM - 1; ++i) { |
2efe2cc4 HV |
694 | struct cx25821_channel *chan = &dev->channels[i]; |
695 | struct video_device *vdev = &chan->vdev; | |
696 | struct v4l2_ctrl_handler *hdl = &chan->hdl; | |
b671ae6b | 697 | struct vb2_queue *q; |
1f198870 | 698 | bool is_output = i > SRAM_CH08; |
467870ca | 699 | |
ffd3c233 HV |
700 | if (i == SRAM_CH08) /* audio channel */ |
701 | continue; | |
702 | ||
1f198870 HV |
703 | if (!is_output) { |
704 | v4l2_ctrl_handler_init(hdl, 4); | |
705 | v4l2_ctrl_new_std(hdl, &cx25821_ctrl_ops, | |
706 | V4L2_CID_BRIGHTNESS, 0, 10000, 1, 6200); | |
707 | v4l2_ctrl_new_std(hdl, &cx25821_ctrl_ops, | |
708 | V4L2_CID_CONTRAST, 0, 10000, 1, 5000); | |
709 | v4l2_ctrl_new_std(hdl, &cx25821_ctrl_ops, | |
710 | V4L2_CID_SATURATION, 0, 10000, 1, 5000); | |
711 | v4l2_ctrl_new_std(hdl, &cx25821_ctrl_ops, | |
712 | V4L2_CID_HUE, 0, 10000, 1, 5000); | |
713 | if (hdl->error) { | |
714 | err = hdl->error; | |
715 | goto fail_unreg; | |
716 | } | |
717 | err = v4l2_ctrl_handler_setup(hdl); | |
718 | if (err) | |
719 | goto fail_unreg; | |
7087d31b HV |
720 | } else { |
721 | chan->out = &dev->vid_out_data[i - SRAM_CH09]; | |
722 | chan->out->chan = chan; | |
f8d7ee70 | 723 | } |
ffd3c233 | 724 | |
2efe2cc4 | 725 | chan->sram_channels = &cx25821_sram_channels[i]; |
2efe2cc4 | 726 | chan->width = 720; |
b671ae6b | 727 | chan->field = V4L2_FIELD_INTERLACED; |
2efe2cc4 HV |
728 | if (dev->tvnorm & V4L2_STD_625_50) |
729 | chan->height = 576; | |
730 | else | |
731 | chan->height = 480; | |
ffd3c233 | 732 | |
2efe2cc4 HV |
733 | if (chan->pixel_formats == PIXEL_FRMT_411) |
734 | chan->fmt = cx25821_format_by_fourcc(V4L2_PIX_FMT_Y41P); | |
735 | else | |
736 | chan->fmt = cx25821_format_by_fourcc(V4L2_PIX_FMT_YUYV); | |
ffd3c233 | 737 | |
2efe2cc4 | 738 | cx_write(chan->sram_channels->int_stat, 0xffffffff); |
ffd3c233 | 739 | |
2efe2cc4 | 740 | INIT_LIST_HEAD(&chan->dma_vidq.active); |
2efe2cc4 | 741 | |
b671ae6b HV |
742 | q = &chan->vidq; |
743 | ||
744 | q->type = is_output ? V4L2_BUF_TYPE_VIDEO_OUTPUT : | |
745 | V4L2_BUF_TYPE_VIDEO_CAPTURE; | |
746 | q->io_modes = VB2_MMAP | VB2_USERPTR | VB2_DMABUF; | |
747 | q->io_modes |= is_output ? VB2_WRITE : VB2_READ; | |
748 | q->gfp_flags = GFP_DMA32; | |
749 | q->min_buffers_needed = 2; | |
750 | q->drv_priv = chan; | |
751 | q->buf_struct_size = sizeof(struct cx25821_buffer); | |
752 | q->ops = &cx25821_video_qops; | |
753 | q->mem_ops = &vb2_dma_sg_memops; | |
754 | q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; | |
755 | q->lock = &dev->lock; | |
2bc46b3a | 756 | q->dev = &dev->pci->dev; |
2efe2cc4 | 757 | |
b671ae6b HV |
758 | if (!is_output) { |
759 | err = vb2_queue_init(q); | |
760 | if (err < 0) | |
761 | goto fail_unreg; | |
762 | } | |
ffd3c233 HV |
763 | |
764 | /* register v4l devices */ | |
1f198870 | 765 | *vdev = is_output ? cx25821_video_out_device : cx25821_video_device; |
467870ca | 766 | vdev->v4l2_dev = &dev->v4l2_dev; |
1f198870 HV |
767 | if (!is_output) |
768 | vdev->ctrl_handler = hdl; | |
769 | else | |
770 | vdev->vfl_dir = VFL_DIR_TX; | |
be178cb4 | 771 | vdev->lock = &dev->lock; |
b671ae6b | 772 | vdev->queue = q; |
467870ca | 773 | snprintf(vdev->name, sizeof(vdev->name), "%s #%d", dev->name, i); |
2efe2cc4 | 774 | video_set_drvdata(vdev, chan); |
ffd3c233 | 775 | |
467870ca HV |
776 | err = video_register_device(vdev, VFL_TYPE_GRABBER, |
777 | video_nr[dev->nr]); | |
ffd3c233 HV |
778 | |
779 | if (err < 0) | |
780 | goto fail_unreg; | |
ffd3c233 HV |
781 | } |
782 | ||
783 | /* set PCI interrupt */ | |
784 | cx_set(PCI_INT_MSK, 0xff); | |
785 | ||
ffd3c233 HV |
786 | return 0; |
787 | ||
788 | fail_unreg: | |
467870ca HV |
789 | while (i >= 0) |
790 | cx25821_video_unregister(dev, i--); | |
ffd3c233 HV |
791 | return err; |
792 | } |