[mirror_ubuntu-jammy-kernel.git] / drivers / media / pci / cx25821 / cx25821.h

/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
 *  Driver for the Conexant CX25821 PCIe bridge
 *
 *  Copyright (C) 2009 Conexant Systems Inc.
 *  Authors  <shu.lin@conexant.com>, <hiep.huynh@conexant.com>
 *  Based on Steven Toth <stoth@linuxtv.org> cx23885 driver
 */

#ifndef CX25821_H_
#define CX25821_H_

#include <linux/pci.h>
#include <linux/i2c.h>
#include <linux/interrupt.h>
#include <linux/delay.h>
#include <linux/sched.h>
#include <linux/kdev_t.h>

#include <media/v4l2-common.h>
#include <media/v4l2-device.h>
#include <media/v4l2-ctrls.h>
#include <media/videobuf2-v4l2.h>
#include <media/videobuf2-dma-sg.h>

#include "cx25821-reg.h"
#include "cx25821-medusa-reg.h"
#include "cx25821-sram.h"
#include "cx25821-audio.h"

#include <linux/version.h>
#include <linux/mutex.h>

#define UNSET (-1U)
#define NO_SYNC_LINE (-1U)

#define CX25821_MAXBOARDS 2

#define LINE_SIZE_D1    1440

/* Number of decoders and encoders */
#define MAX_DECODERS            8
#define MAX_ENCODERS            2
#define QUAD_DECODERS           4
#define MAX_CAMERAS             16

/* Max number of inputs by card */
#define MAX_CX25821_INPUT     8
#define RESOURCE_VIDEO0       1
#define RESOURCE_VIDEO1       2
#define RESOURCE_VIDEO2       4
#define RESOURCE_VIDEO3       8
#define RESOURCE_VIDEO4       16
#define RESOURCE_VIDEO5       32
#define RESOURCE_VIDEO6       64
#define RESOURCE_VIDEO7       128
#define RESOURCE_VIDEO8       256
#define RESOURCE_VIDEO9       512
#define RESOURCE_VIDEO10      1024
#define RESOURCE_VIDEO11      2048

#define BUFFER_TIMEOUT     (HZ)	/* 0.5 seconds */

#define UNKNOWN_BOARD        0
#define CX25821_BOARD        1

/* Currently supported by the driver */
#define CX25821_NORMS (\
	V4L2_STD_NTSC_M |  V4L2_STD_NTSC_M_JP | V4L2_STD_NTSC_M_KR | \
	V4L2_STD_PAL_BG |  V4L2_STD_PAL_DK    |  V4L2_STD_PAL_I    | \
	V4L2_STD_PAL_M  |  V4L2_STD_PAL_N     |  V4L2_STD_PAL_H    | \
	V4L2_STD_PAL_Nc)

#define CX25821_BOARD_CONEXANT_ATHENA10 1
#define MAX_VID_CHANNEL_NUM     12

/*
 * Maximum capture-only channels. This can go away once video/audio output
 * is fully supported in this driver.
 */
#define MAX_VID_CAP_CHANNEL_NUM     10

#define VID_CHANNEL_NUM 8

struct cx25821_fmt {
	char *name;
	u32 fourcc;		/* v4l2 format id */
	int depth;
	int flags;
	u32 cxformat;
};

struct cx25821_tvnorm {
	char *name;
	v4l2_std_id id;
	u32 cxiformat;
	u32 cxoformat;
};

enum cx25821_src_sel_type {
	CX25821_SRC_SEL_EXT_656_VIDEO = 0,
	CX25821_SRC_SEL_PARALLEL_MPEG_VIDEO
};

struct cx25821_riscmem {
	unsigned int   size;
	__le32         *cpu;
	__le32         *jmp;
	dma_addr_t     dma;
};

/* buffer for one video frame */
struct cx25821_buffer {
	/* common v4l buffer stuff -- must be first */
	struct vb2_v4l2_buffer vb;
	struct list_head queue;

	/* cx25821 specific */
	unsigned int bpl;
	struct cx25821_riscmem risc;
	const struct cx25821_fmt *fmt;
};

enum port {
	CX25821_UNDEFINED = 0,
	CX25821_RAW,
	CX25821_264
};

struct cx25821_board {
	const char *name;
	enum port porta;
	enum port portb;
	enum port portc;

	u32 clk_freq;
};

struct cx25821_i2c {
	struct cx25821_dev *dev;

	int nr;

	/* i2c i/o */
	struct i2c_adapter i2c_adap;
	struct i2c_client i2c_client;
	u32 i2c_rc;

	/* cx25821 registers used for raw address */
	u32 i2c_period;
	u32 reg_ctrl;
	u32 reg_stat;
	u32 reg_addr;
	u32 reg_rdata;
	u32 reg_wdata;
};

struct cx25821_dmaqueue {
	struct list_head active;
	u32 count;
};

struct cx25821_dev;

struct cx25821_channel;

struct cx25821_video_out_data {
	struct cx25821_channel *chan;
	int _line_size;
	int _prog_cnt;
	int _pixel_format;
	int _is_first_frame;
	int _is_running;
	int _file_status;
	int _lines_count;
	int _frame_count;
	unsigned int _risc_size;

	__le32 *_dma_virt_start_addr;
	__le32 *_dma_virt_addr;
	dma_addr_t _dma_phys_addr;
	dma_addr_t _dma_phys_start_addr;

	unsigned int _data_buf_size;
	__le32 *_data_buf_virt_addr;
	dma_addr_t _data_buf_phys_addr;

	u32 upstream_riscbuf_size;
	u32 upstream_databuf_size;
	int is_60hz;
	int _frame_index;
	int cur_frame_index;
	int curpos;
	wait_queue_head_t waitq;
};

struct cx25821_channel {
	unsigned id;
	struct cx25821_dev *dev;

	struct v4l2_ctrl_handler hdl;

	struct video_device vdev;
	struct cx25821_dmaqueue dma_vidq;
	struct vb2_queue vidq;

	const struct sram_channel *sram_channels;

	const struct cx25821_fmt *fmt;
	unsigned field;
	unsigned int width, height;
	int pixel_formats;
	int use_cif_resolution;
	int cif_width;

	/* video output data for the video output channel */
	struct cx25821_video_out_data *out;
};

struct snd_card;

struct cx25821_dev {
	struct v4l2_device v4l2_dev;

	/* pci stuff */
	struct pci_dev *pci;
	unsigned char pci_rev, pci_lat;
	int pci_bus, pci_slot;
	u32 base_io_addr;
	u32 __iomem *lmmio;
	u8 __iomem *bmmio;
	int pci_irqmask;
	int hwrevision;
	/* used by cx25821-alsa */
	struct snd_card *card;

	u32 clk_freq;

	/* I2C adapters: Master 1 & 2 (External) & Master 3 (Internal only) */
	struct cx25821_i2c i2c_bus[3];

	int nr;
	struct mutex lock;

	struct cx25821_channel channels[MAX_VID_CHANNEL_NUM];

	/* board details */
	unsigned int board;
	char name[32];

	/* Analog video */
	unsigned int input;
	v4l2_std_id tvnorm;
	unsigned short _max_num_decoders;

	/* Analog Audio Upstream */
	int _audio_is_running;
	int _audiopixel_format;
	int _is_first_audio_frame;
	int _audiofile_status;
	int _audio_lines_count;
	int _audioframe_count;
	int _audio_upstream_channel;
	int _last_index_irq;    /* The last interrupt index processed. */

	__le32 *_risc_audio_jmp_addr;
	__le32 *_risc_virt_start_addr;
	__le32 *_risc_virt_addr;
	dma_addr_t _risc_phys_addr;
	dma_addr_t _risc_phys_start_addr;

	unsigned int _audiorisc_size;
	unsigned int _audiodata_buf_size;
	__le32 *_audiodata_buf_virt_addr;
	dma_addr_t _audiodata_buf_phys_addr;
	char *_audiofilename;
	u32 audio_upstream_riscbuf_size;
	u32 audio_upstream_databuf_size;
	int _audioframe_index;
	struct work_struct _audio_work_entry;
	char *input_audiofilename;

	/* V4l */
	spinlock_t slock;

	/* Video Upstream */
	struct cx25821_video_out_data vid_out_data[2];
};

static inline struct cx25821_dev *get_cx25821(struct v4l2_device *v4l2_dev)
{
	return container_of(v4l2_dev, struct cx25821_dev, v4l2_dev);
}

extern struct cx25821_board cx25821_boards[];

#define SRAM_CH00  0		/* Video A */
#define SRAM_CH01  1		/* Video B */
#define SRAM_CH02  2		/* Video C */
#define SRAM_CH03  3		/* Video D */
#define SRAM_CH04  4		/* Video E */
#define SRAM_CH05  5		/* Video F */
#define SRAM_CH06  6		/* Video G */
#define SRAM_CH07  7		/* Video H */

#define SRAM_CH08  8		/* Audio A */
#define SRAM_CH09  9		/* Video Upstream I */
#define SRAM_CH10  10		/* Video Upstream J */
#define SRAM_CH11  11		/* Audio Upstream AUD_CHANNEL_B */

#define VID_UPSTREAM_SRAM_CHANNEL_I     SRAM_CH09
#define VID_UPSTREAM_SRAM_CHANNEL_J     SRAM_CH10
#define AUDIO_UPSTREAM_SRAM_CHANNEL_B   SRAM_CH11

struct sram_channel {
	char *name;
	u32 i;
	u32 cmds_start;
	u32 ctrl_start;
	u32 cdt;
	u32 fifo_start;
	u32 fifo_size;
	u32 ptr1_reg;
	u32 ptr2_reg;
	u32 cnt1_reg;
	u32 cnt2_reg;
	u32 int_msk;
	u32 int_stat;
	u32 int_mstat;
	u32 dma_ctl;
	u32 gpcnt_ctl;
	u32 gpcnt;
	u32 aud_length;
	u32 aud_cfg;
	u32 fld_aud_fifo_en;
	u32 fld_aud_risc_en;

	/* For Upstream Video */
	u32 vid_fmt_ctl;
	u32 vid_active_ctl1;
	u32 vid_active_ctl2;
	u32 vid_cdt_size;

	u32 vip_ctl;
	u32 pix_frmt;
	u32 jumponly;
	u32 irq_bit;
};

extern const struct sram_channel cx25821_sram_channels[];

#define cx_read(reg)             readl(dev->lmmio + ((reg)>>2))
#define cx_write(reg, value)     writel((value), dev->lmmio + ((reg)>>2))

#define cx_andor(reg, mask, value) \
	writel((readl(dev->lmmio+((reg)>>2)) & ~(mask)) |\
	((value) & (mask)), dev->lmmio+((reg)>>2))

#define cx_set(reg, bit)          cx_andor((reg), (bit), (bit))
#define cx_clear(reg, bit)        cx_andor((reg), (bit), 0)

#define Set_GPIO_Bit(Bit)                       (1 << Bit)
#define Clear_GPIO_Bit(Bit)                     (~(1 << Bit))

#define CX25821_ERR(fmt, args...)			\
	pr_err("(%d): " fmt, dev->board, ##args)
#define CX25821_WARN(fmt, args...)			\
	pr_warn("(%d): " fmt, dev->board, ##args)
#define CX25821_INFO(fmt, args...)			\
	pr_info("(%d): " fmt, dev->board, ##args)

extern int cx25821_i2c_register(struct cx25821_i2c *bus);
extern int cx25821_i2c_read(struct cx25821_i2c *bus, u16 reg_addr, int *value);
extern int cx25821_i2c_write(struct cx25821_i2c *bus, u16 reg_addr, int value);
extern int cx25821_i2c_unregister(struct cx25821_i2c *bus);
extern void cx25821_gpio_init(struct cx25821_dev *dev);
extern void cx25821_set_gpiopin_direction(struct cx25821_dev *dev,
					  int pin_number, int pin_logic_value);

extern int medusa_video_init(struct cx25821_dev *dev);
extern int medusa_set_videostandard(struct cx25821_dev *dev);
extern void medusa_set_resolution(struct cx25821_dev *dev, int width,
				  int decoder_select);
extern int medusa_set_brightness(struct cx25821_dev *dev, int brightness,
				 int decoder);
extern int medusa_set_contrast(struct cx25821_dev *dev, int contrast,
			       int decoder);
extern int medusa_set_hue(struct cx25821_dev *dev, int hue, int decoder);
extern int medusa_set_saturation(struct cx25821_dev *dev, int saturation,
				 int decoder);

extern int cx25821_sram_channel_setup(struct cx25821_dev *dev,
				      const struct sram_channel *ch, unsigned int bpl,
				      u32 risc);

extern int cx25821_riscmem_alloc(struct pci_dev *pci,
				 struct cx25821_riscmem *risc,
				 unsigned int size);
extern int cx25821_risc_buffer(struct pci_dev *pci, struct cx25821_riscmem *risc,
			       struct scatterlist *sglist,
			       unsigned int top_offset,
			       unsigned int bottom_offset,
			       unsigned int bpl,
			       unsigned int padding, unsigned int lines);
extern int cx25821_risc_databuffer_audio(struct pci_dev *pci,
					 struct cx25821_riscmem *risc,
					 struct scatterlist *sglist,
					 unsigned int bpl,
					 unsigned int lines, unsigned int lpi);
extern void cx25821_free_buffer(struct cx25821_dev *dev,
				struct cx25821_buffer *buf);
extern void cx25821_sram_channel_dump(struct cx25821_dev *dev,
				      const struct sram_channel *ch);
extern void cx25821_sram_channel_dump_audio(struct cx25821_dev *dev,
					    const struct sram_channel *ch);

extern struct cx25821_dev *cx25821_dev_get(struct pci_dev *pci);
extern void cx25821_print_irqbits(char *name, char *tag, char **strings,
				  int len, u32 bits, u32 mask);
extern void cx25821_dev_unregister(struct cx25821_dev *dev);
extern int cx25821_sram_channel_setup_audio(struct cx25821_dev *dev,
					    const struct sram_channel *ch,
					    unsigned int bpl, u32 risc);

extern void cx25821_set_pixel_format(struct cx25821_dev *dev, int channel,
				     u32 format);

#endif
Commit	Line	Data
c942fddf	1	/* SPDX-License-Identifier: GPL-2.0-or-later */
02b20b0b MCC	2	/*
	3	* Driver for the Conexant CX25821 PCIe bridge
	4	*
bb4c9a74	5	* Copyright (C) 2009 Conexant Systems Inc.
02b20b0b MCC	6	* Authors <shu.lin@conexant.com>, <hiep.huynh@conexant.com>
02b20b0b MCC	7	* Based on Steven Toth <stoth@linuxtv.org> cx23885 driver
02b20b0b MCC	8	*/
02b20b0b MCC	9
02b20b0b MCC	10	#ifndef CX25821_H_
	11	#define CX25821_H_
	12
	13	#include <linux/pci.h>
	14	#include <linux/i2c.h>
02b20b0b MCC	15	#include <linux/interrupt.h>
	16	#include <linux/delay.h>
	17	#include <linux/sched.h>
	18	#include <linux/kdev_t.h>
	19
	20	#include <media/v4l2-common.h>
bb4c9a74	21	#include <media/v4l2-device.h>
f8d7ee70	22	#include <media/v4l2-ctrls.h>
2d700715	23	#include <media/videobuf2-v4l2.h>
b671ae6b	24	#include <media/videobuf2-dma-sg.h>
02b20b0b	25
02b20b0b MCC	26	#include "cx25821-reg.h"
	27	#include "cx25821-medusa-reg.h"
	28	#include "cx25821-sram.h"
	29	#include "cx25821-audio.h"
02b20b0b MCC	30
	31	#include <linux/version.h>
	32	#include <linux/mutex.h>
	33
02b20b0b MCC	34	#define UNSET (-1U)
	35	#define NO_SYNC_LINE (-1U)
	36
	37	#define CX25821_MAXBOARDS 2
	38
02b20b0b MCC	39	#define LINE_SIZE_D1 1440
02b20b0b MCC	40
6d8c2ba1	41	/* Number of decoders and encoders */
02b20b0b MCC	42	#define MAX_DECODERS 8
	43	#define MAX_ENCODERS 2
	44	#define QUAD_DECODERS 4
	45	#define MAX_CAMERAS 16
	46
	47	/* Max number of inputs by card */
c7855ee5	48	#define MAX_CX25821_INPUT 8
02b20b0b MCC	49	#define RESOURCE_VIDEO0 1
	50	#define RESOURCE_VIDEO1 2
	51	#define RESOURCE_VIDEO2 4
	52	#define RESOURCE_VIDEO3 8
	53	#define RESOURCE_VIDEO4 16
	54	#define RESOURCE_VIDEO5 32
	55	#define RESOURCE_VIDEO6 64
	56	#define RESOURCE_VIDEO7 128
	57	#define RESOURCE_VIDEO8 256
	58	#define RESOURCE_VIDEO9 512
	59	#define RESOURCE_VIDEO10 1024
	60	#define RESOURCE_VIDEO11 2048
02b20b0b	61
1a9fc855	62	#define BUFFER_TIMEOUT (HZ) /* 0.5 seconds */
02b20b0b	63
c7855ee5	64	#define UNKNOWN_BOARD 0
02b20b0b MCC	65	#define CX25821_BOARD 1
02b20b0b MCC	66
bb4c9a74	67	/* Currently supported by the driver */
02b20b0b	68	#define CX25821_NORMS (\
e4115bb2 RP	69	V4L2_STD_NTSC_M \| V4L2_STD_NTSC_M_JP \| V4L2_STD_NTSC_M_KR \| \
	70	V4L2_STD_PAL_BG \| V4L2_STD_PAL_DK \| V4L2_STD_PAL_I \| \
	71	V4L2_STD_PAL_M \| V4L2_STD_PAL_N \| V4L2_STD_PAL_H \| \
	72	V4L2_STD_PAL_Nc)
02b20b0b MCC	73
	74	#define CX25821_BOARD_CONEXANT_ATHENA10 1
	75	#define MAX_VID_CHANNEL_NUM 12
b6f21dc3 HV	76
	77	/*
	78	* Maximum capture-only channels. This can go away once video/audio output
	79	* is fully supported in this driver.
	80	*/
	81	#define MAX_VID_CAP_CHANNEL_NUM 10
	82
02b20b0b MCC	83	#define VID_CHANNEL_NUM 8
	84
	85	struct cx25821_fmt {
1a9fc855 MCC	86	char *name;
	87	u32 fourcc; /* v4l2 format id */
	88	int depth;
	89	int flags;
	90	u32 cxformat;
02b20b0b MCC	91	};
02b20b0b MCC	92
02b20b0b	93	struct cx25821_tvnorm {
1a9fc855 MCC	94	char *name;
	95	v4l2_std_id id;
	96	u32 cxiformat;
	97	u32 cxoformat;
02b20b0b MCC	98	};
02b20b0b MCC	99
02b20b0b	100	enum cx25821_src_sel_type {
1a9fc855 MCC	101	CX25821_SRC_SEL_EXT_656_VIDEO = 0,
1a9fc855 MCC	102	CX25821_SRC_SEL_PARALLEL_MPEG_VIDEO
02b20b0b MCC	103	};
02b20b0b MCC	104
5ede94c7 HV	105	struct cx25821_riscmem {
	106	unsigned int size;
	107	__le32 *cpu;
	108	__le32 *jmp;
	109	dma_addr_t dma;
	110	};
	111
02b20b0b MCC	112	/* buffer for one video frame */
02b20b0b MCC	113	struct cx25821_buffer {
1a9fc855	114	/* common v4l buffer stuff -- must be first */
2d700715	115	struct vb2_v4l2_buffer vb;
b671ae6b	116	struct list_head queue;
1a9fc855 MCC	117
	118	/* cx25821 specific */
	119	unsigned int bpl;
5ede94c7	120	struct cx25821_riscmem risc;
95c232a2	121	const struct cx25821_fmt *fmt;
02b20b0b MCC	122	};
02b20b0b MCC	123
7ae70c8b	124	enum port {
1a9fc855 MCC	125	CX25821_UNDEFINED = 0,
	126	CX25821_RAW,
	127	CX25821_264
7ae70c8b	128	};
02b20b0b MCC	129
02b20b0b MCC	130	struct cx25821_board {
c854d888	131	const char *name;
7ae70c8b LF	132	enum port porta;
	133	enum port portb;
	134	enum port portc;
1a9fc855 MCC	135
1a9fc855 MCC	136	u32 clk_freq;
02b20b0b MCC	137	};
02b20b0b MCC	138
02b20b0b	139	struct cx25821_i2c {
1a9fc855 MCC	140	struct cx25821_dev *dev;
	141
	142	int nr;
	143
	144	/* i2c i/o */
	145	struct i2c_adapter i2c_adap;
1a9fc855 MCC	146	struct i2c_client i2c_client;
	147	u32 i2c_rc;
	148
16790554	149	/* cx25821 registers used for raw address */
1a9fc855 MCC	150	u32 i2c_period;
	151	u32 reg_ctrl;
	152	u32 reg_stat;
	153	u32 reg_addr;
	154	u32 reg_rdata;
	155	u32 reg_wdata;
02b20b0b MCC	156	};
	157
	158	struct cx25821_dmaqueue {
1a9fc855	159	struct list_head active;
1a9fc855	160	u32 count;
02b20b0b MCC	161	};
02b20b0b MCC	162
f8d7ee70 HV	163	struct cx25821_dev;
f8d7ee70 HV	164
7087d31b HV	165	struct cx25821_channel;
	166
	167	struct cx25821_video_out_data {
	168	struct cx25821_channel *chan;
	169	int _line_size;
	170	int _prog_cnt;
	171	int _pixel_format;
	172	int _is_first_frame;
	173	int _is_running;
	174	int _file_status;
	175	int _lines_count;
	176	int _frame_count;
	177	unsigned int _risc_size;
	178
	179	__le32 *_dma_virt_start_addr;
	180	__le32 *_dma_virt_addr;
	181	dma_addr_t _dma_phys_addr;
	182	dma_addr_t _dma_phys_start_addr;
	183
	184	unsigned int _data_buf_size;
	185	__le32 *_data_buf_virt_addr;
	186	dma_addr_t _data_buf_phys_addr;
	187
	188	u32 upstream_riscbuf_size;
	189	u32 upstream_databuf_size;
7087d31b HV	190	int is_60hz;
7087d31b HV	191	int _frame_index;
ea3f7ac6 HV	192	int cur_frame_index;
	193	int curpos;
	194	wait_queue_head_t waitq;
7087d31b HV	195	};
7087d31b HV	196
6d8c2ba1	197	struct cx25821_channel {
f8d7ee70 HV	198	unsigned id;
f8d7ee70 HV	199	struct cx25821_dev *dev;
6d8c2ba1	200
f8d7ee70	201	struct v4l2_ctrl_handler hdl;
6d8c2ba1	202
467870ca	203	struct video_device vdev;
2efe2cc4	204	struct cx25821_dmaqueue dma_vidq;
b671ae6b	205	struct vb2_queue vidq;
6d8c2ba1	206
bfef0d35	207	const struct sram_channel *sram_channels;
6d8c2ba1	208
2efe2cc4	209	const struct cx25821_fmt *fmt;
b671ae6b	210	unsigned field;
2efe2cc4	211	unsigned int width, height;
e4115bb2 RP	212	int pixel_formats;
	213	int use_cif_resolution;
	214	int cif_width;
7087d31b HV	215
	216	/* video output data for the video output channel */
	217	struct cx25821_video_out_data *out;
6d8c2ba1 PB	218	};
6d8c2ba1 PB	219
a8f35ce3 HV	220	struct snd_card;
a8f35ce3 HV	221
02b20b0b	222	struct cx25821_dev {
1a9fc855 MCC	223	struct v4l2_device v4l2_dev;
1a9fc855 MCC	224
1a9fc855 MCC	225	/* pci stuff */
	226	struct pci_dev *pci;
	227	unsigned char pci_rev, pci_lat;
	228	int pci_bus, pci_slot;
	229	u32 base_io_addr;
	230	u32 __iomem *lmmio;
	231	u8 __iomem *bmmio;
	232	int pci_irqmask;
	233	int hwrevision;
a8f35ce3 HV	234	/* used by cx25821-alsa */
a8f35ce3 HV	235	struct snd_card *card;
1a9fc855 MCC	236
	237	u32 clk_freq;
	238
	239	/* I2C adapters: Master 1 & 2 (External) & Master 3 (Internal only) */
	240	struct cx25821_i2c i2c_bus[3];
	241
	242	int nr;
	243	struct mutex lock;
	244
e4115bb2	245	struct cx25821_channel channels[MAX_VID_CHANNEL_NUM];
6d8c2ba1	246
1a9fc855 MCC	247	/* board details */
	248	unsigned int board;
	249	char name[32];
	250
1a9fc855	251	/* Analog video */
1a9fc855	252	unsigned int input;
1a9fc855	253	v4l2_std_id tvnorm;
1a9fc855 MCC	254	unsigned short _max_num_decoders;
1a9fc855 MCC	255
1a9fc855 MCC	256	/* Analog Audio Upstream */
	257	int _audio_is_running;
	258	int _audiopixel_format;
	259	int _is_first_audio_frame;
	260	int _audiofile_status;
	261	int _audio_lines_count;
	262	int _audioframe_count;
6100c579	263	int _audio_upstream_channel;
e4115bb2	264	int _last_index_irq; /* The last interrupt index processed. */
1a9fc855 MCC	265
	266	__le32 *_risc_audio_jmp_addr;
	267	__le32 *_risc_virt_start_addr;
	268	__le32 *_risc_virt_addr;
	269	dma_addr_t _risc_phys_addr;
	270	dma_addr_t _risc_phys_start_addr;
	271
	272	unsigned int _audiorisc_size;
	273	unsigned int _audiodata_buf_size;
	274	__le32 *_audiodata_buf_virt_addr;
	275	dma_addr_t _audiodata_buf_phys_addr;
	276	char *_audiofilename;
1a9fc855 MCC	277	u32 audio_upstream_riscbuf_size;
1a9fc855 MCC	278	u32 audio_upstream_databuf_size;
1a9fc855	279	int _audioframe_index;
1a9fc855	280	struct work_struct _audio_work_entry;
1a9fc855	281	char *input_audiofilename;
7087d31b HV	282
	283	/* V4l */
	284	spinlock_t slock;
	285
	286	/* Video Upstream */
	287	struct cx25821_video_out_data vid_out_data[2];
02b20b0b MCC	288	};
02b20b0b MCC	289
02b20b0b MCC	290	static inline struct cx25821_dev get_cx25821(struct v4l2_device v4l2_dev)
02b20b0b MCC	291	{
1a9fc855	292	return container_of(v4l2_dev, struct cx25821_dev, v4l2_dev);
02b20b0b MCC	293	}
02b20b0b MCC	294
02b20b0b	295	extern struct cx25821_board cx25821_boards[];
02b20b0b	296
1a9fc855 MCC	297	#define SRAM_CH00 0 /* Video A */
	298	#define SRAM_CH01 1 /* Video B */
	299	#define SRAM_CH02 2 /* Video C */
	300	#define SRAM_CH03 3 /* Video D */
	301	#define SRAM_CH04 4 /* Video E */
	302	#define SRAM_CH05 5 /* Video F */
	303	#define SRAM_CH06 6 /* Video G */
	304	#define SRAM_CH07 7 /* Video H */
02b20b0b	305
1a9fc855 MCC	306	#define SRAM_CH08 8 /* Audio A */
	307	#define SRAM_CH09 9 /* Video Upstream I */
	308	#define SRAM_CH10 10 /* Video Upstream J */
	309	#define SRAM_CH11 11 /* Audio Upstream AUD_CHANNEL_B */
02b20b0b MCC	310
	311	#define VID_UPSTREAM_SRAM_CHANNEL_I SRAM_CH09
	312	#define VID_UPSTREAM_SRAM_CHANNEL_J SRAM_CH10
	313	#define AUDIO_UPSTREAM_SRAM_CHANNEL_B SRAM_CH11
02b20b0b MCC	314
02b20b0b MCC	315	struct sram_channel {
1a9fc855 MCC	316	char *name;
	317	u32 i;
	318	u32 cmds_start;
	319	u32 ctrl_start;
	320	u32 cdt;
	321	u32 fifo_start;
	322	u32 fifo_size;
	323	u32 ptr1_reg;
	324	u32 ptr2_reg;
	325	u32 cnt1_reg;
	326	u32 cnt2_reg;
	327	u32 int_msk;
	328	u32 int_stat;
	329	u32 int_mstat;
	330	u32 dma_ctl;
	331	u32 gpcnt_ctl;
	332	u32 gpcnt;
	333	u32 aud_length;
	334	u32 aud_cfg;
	335	u32 fld_aud_fifo_en;
	336	u32 fld_aud_risc_en;
	337
e4115bb2	338	/* For Upstream Video */
1a9fc855 MCC	339	u32 vid_fmt_ctl;
	340	u32 vid_active_ctl1;
	341	u32 vid_active_ctl2;
	342	u32 vid_cdt_size;
	343
	344	u32 vip_ctl;
	345	u32 pix_frmt;
	346	u32 jumponly;
	347	u32 irq_bit;
02b20b0b	348	};
bfef0d35 HV	349
bfef0d35 HV	350	extern const struct sram_channel cx25821_sram_channels[];
02b20b0b	351
02b20b0b MCC	352	#define cx_read(reg) readl(dev->lmmio + ((reg)>>2))
	353	#define cx_write(reg, value) writel((value), dev->lmmio + ((reg)>>2))
	354
	355	#define cx_andor(reg, mask, value) \
e4115bb2 RP	356	writel((readl(dev->lmmio+((reg)>>2)) & ~(mask)) \|\
e4115bb2 RP	357	((value) & (mask)), dev->lmmio+((reg)>>2))
02b20b0b MCC	358
	359	#define cx_set(reg, bit) cx_andor((reg), (bit), (bit))
	360	#define cx_clear(reg, bit) cx_andor((reg), (bit), 0)
	361
	362	#define Set_GPIO_Bit(Bit) (1 << Bit)
	363	#define Clear_GPIO_Bit(Bit) (~(1 << Bit))
	364
36d89f7d JP	365	#define CX25821_ERR(fmt, args...) \
	366	pr_err("(%d): " fmt, dev->board, ##args)
	367	#define CX25821_WARN(fmt, args...) \
	368	pr_warn("(%d): " fmt, dev->board, ##args)
	369	#define CX25821_INFO(fmt, args...) \
	370	pr_info("(%d): " fmt, dev->board, ##args)
02b20b0b	371
1a9fc855	372	extern int cx25821_i2c_register(struct cx25821_i2c *bus);
1a9fc855 MCC	373	extern int cx25821_i2c_read(struct cx25821_i2c bus, u16 reg_addr, int value);
	374	extern int cx25821_i2c_write(struct cx25821_i2c *bus, u16 reg_addr, int value);
	375	extern int cx25821_i2c_unregister(struct cx25821_i2c *bus);
02b20b0b	376	extern void cx25821_gpio_init(struct cx25821_dev *dev);
1a9fc855 MCC	377	extern void cx25821_set_gpiopin_direction(struct cx25821_dev *dev,
	378	int pin_number, int pin_logic_value);
	379
	380	extern int medusa_video_init(struct cx25821_dev *dev);
	381	extern int medusa_set_videostandard(struct cx25821_dev *dev);
	382	extern void medusa_set_resolution(struct cx25821_dev *dev, int width,
	383	int decoder_select);
	384	extern int medusa_set_brightness(struct cx25821_dev *dev, int brightness,
	385	int decoder);
	386	extern int medusa_set_contrast(struct cx25821_dev *dev, int contrast,
	387	int decoder);
	388	extern int medusa_set_hue(struct cx25821_dev *dev, int hue, int decoder);
	389	extern int medusa_set_saturation(struct cx25821_dev *dev, int saturation,
	390	int decoder);
	391
	392	extern int cx25821_sram_channel_setup(struct cx25821_dev *dev,
bfef0d35	393	const struct sram_channel *ch, unsigned int bpl,
1a9fc855	394	u32 risc);
02b20b0b	395
5ede94c7 HV	396	extern int cx25821_riscmem_alloc(struct pci_dev *pci,
	397	struct cx25821_riscmem *risc,
	398	unsigned int size);
	399	extern int cx25821_risc_buffer(struct pci_dev pci, struct cx25821_riscmem risc,
1a9fc855 MCC	400	struct scatterlist *sglist,
	401	unsigned int top_offset,
	402	unsigned int bottom_offset,
	403	unsigned int bpl,
	404	unsigned int padding, unsigned int lines);
02b20b0b	405	extern int cx25821_risc_databuffer_audio(struct pci_dev *pci,
5ede94c7	406	struct cx25821_riscmem *risc,
1a9fc855 MCC	407	struct scatterlist *sglist,
	408	unsigned int bpl,
	409	unsigned int lines, unsigned int lpi);
b671ae6b	410	extern void cx25821_free_buffer(struct cx25821_dev *dev,
1a9fc855	411	struct cx25821_buffer *buf);
1a9fc855	412	extern void cx25821_sram_channel_dump(struct cx25821_dev *dev,
bfef0d35	413	const struct sram_channel *ch);
1a9fc855	414	extern void cx25821_sram_channel_dump_audio(struct cx25821_dev *dev,
bfef0d35	415	const struct sram_channel *ch);
1a9fc855 MCC	416
	417	extern struct cx25821_dev cx25821_dev_get(struct pci_dev pci);
	418	extern void cx25821_print_irqbits(char name, char tag, char **strings,
	419	int len, u32 bits, u32 mask);
02b20b0b MCC	420	extern void cx25821_dev_unregister(struct cx25821_dev *dev);
02b20b0b MCC	421	extern int cx25821_sram_channel_setup_audio(struct cx25821_dev *dev,
bfef0d35	422	const struct sram_channel *ch,
1a9fc855 MCC	423	unsigned int bpl, u32 risc);
1a9fc855 MCC	424
1a9fc855 MCC	425	extern void cx25821_set_pixel_format(struct cx25821_dev *dev, int channel,
1a9fc855 MCC	426	u32 format);
95c232a2	427
02b20b0b	428	#endif