[mirror_ubuntu-jammy-kernel.git] / drivers / media / pci / cx25821 / cx25821.h

/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
 *  Driver for the Conexant CX25821 PCIe bridge
 *
 *  Copyright (C) 2009 Conexant Systems Inc.
 *  Authors  <shu.lin@conexant.com>, <hiep.huynh@conexant.com>
 *  Based on Steven Toth <stoth@linuxtv.org> cx23885 driver
 */

#ifndef CX25821_H_
#define CX25821_H_

#include <linux/pci.h>
#include <linux/i2c.h>
#include <linux/interrupt.h>
#include <linux/delay.h>
#include <linux/sched.h>
#include <linux/kdev_t.h>

#include <media/v4l2-common.h>
#include <media/v4l2-device.h>
#include <media/v4l2-ctrls.h>
#include <media/videobuf2-v4l2.h>
#include <media/videobuf2-dma-sg.h>

#include "cx25821-reg.h"
#include "cx25821-medusa-reg.h"
#include "cx25821-sram.h"
#include "cx25821-audio.h"

#include <linux/mutex.h>

#define UNSET (-1U)
#define NO_SYNC_LINE (-1U)

#define CX25821_MAXBOARDS 2

#define LINE_SIZE_D1    1440

/* Number of decoders and encoders */
#define MAX_DECODERS            8
#define MAX_ENCODERS            2
#define QUAD_DECODERS           4
#define MAX_CAMERAS             16

/* Max number of inputs by card */
#define MAX_CX25821_INPUT     8
#define RESOURCE_VIDEO0       1
#define RESOURCE_VIDEO1       2
#define RESOURCE_VIDEO2       4
#define RESOURCE_VIDEO3       8
#define RESOURCE_VIDEO4       16
#define RESOURCE_VIDEO5       32
#define RESOURCE_VIDEO6       64
#define RESOURCE_VIDEO7       128
#define RESOURCE_VIDEO8       256
#define RESOURCE_VIDEO9       512
#define RESOURCE_VIDEO10      1024
#define RESOURCE_VIDEO11      2048

#define BUFFER_TIMEOUT     (HZ)	/* 0.5 seconds */

#define UNKNOWN_BOARD        0
#define CX25821_BOARD        1

/* Currently supported by the driver */
#define CX25821_NORMS (\
	V4L2_STD_NTSC_M |  V4L2_STD_NTSC_M_JP | V4L2_STD_NTSC_M_KR | \
	V4L2_STD_PAL_BG |  V4L2_STD_PAL_DK    |  V4L2_STD_PAL_I    | \
	V4L2_STD_PAL_M  |  V4L2_STD_PAL_N     |  V4L2_STD_PAL_H    | \
	V4L2_STD_PAL_Nc)

#define CX25821_BOARD_CONEXANT_ATHENA10 1
#define MAX_VID_CHANNEL_NUM     12

/*
 * Maximum capture-only channels. This can go away once video/audio output
 * is fully supported in this driver.
 */
#define MAX_VID_CAP_CHANNEL_NUM     10

#define VID_CHANNEL_NUM 8

struct cx25821_fmt {
	u32 fourcc;		/* v4l2 format id */
	int depth;
	int flags;
	u32 cxformat;
};

struct cx25821_tvnorm {
	char *name;
	v4l2_std_id id;
	u32 cxiformat;
	u32 cxoformat;
};

enum cx25821_src_sel_type {
	CX25821_SRC_SEL_EXT_656_VIDEO = 0,
	CX25821_SRC_SEL_PARALLEL_MPEG_VIDEO
};

struct cx25821_riscmem {
	unsigned int   size;
	__le32         *cpu;
	__le32         *jmp;
	dma_addr_t     dma;
};

/* buffer for one video frame */
struct cx25821_buffer {
	/* common v4l buffer stuff -- must be first */
	struct vb2_v4l2_buffer vb;
	struct list_head queue;

	/* cx25821 specific */
	unsigned int bpl;
	struct cx25821_riscmem risc;
	const struct cx25821_fmt *fmt;
};

enum port {
	CX25821_UNDEFINED = 0,
	CX25821_RAW,
	CX25821_264
};

struct cx25821_board {
	const char *name;
	enum port porta;
	enum port portb;
	enum port portc;

	u32 clk_freq;
};

struct cx25821_i2c {
	struct cx25821_dev *dev;

	int nr;

	/* i2c i/o */
	struct i2c_adapter i2c_adap;
	struct i2c_client i2c_client;
	u32 i2c_rc;

	/* cx25821 registers used for raw address */
	u32 i2c_period;
	u32 reg_ctrl;
	u32 reg_stat;
	u32 reg_addr;
	u32 reg_rdata;
	u32 reg_wdata;
};

struct cx25821_dmaqueue {
	struct list_head active;
	u32 count;
};

struct cx25821_dev;

struct cx25821_channel;

struct cx25821_video_out_data {
	struct cx25821_channel *chan;
	int _line_size;
	int _prog_cnt;
	int _pixel_format;
	int _is_first_frame;
	int _is_running;
	int _file_status;
	int _lines_count;
	int _frame_count;
	unsigned int _risc_size;

	__le32 *_dma_virt_start_addr;
	__le32 *_dma_virt_addr;
	dma_addr_t _dma_phys_addr;
	dma_addr_t _dma_phys_start_addr;

	unsigned int _data_buf_size;
	__le32 *_data_buf_virt_addr;
	dma_addr_t _data_buf_phys_addr;

	u32 upstream_riscbuf_size;
	u32 upstream_databuf_size;
	int is_60hz;
	int _frame_index;
	int cur_frame_index;
	int curpos;
	wait_queue_head_t waitq;
};

struct cx25821_channel {
	unsigned id;
	struct cx25821_dev *dev;

	struct v4l2_ctrl_handler hdl;

	struct video_device vdev;
	struct cx25821_dmaqueue dma_vidq;
	struct vb2_queue vidq;

	const struct sram_channel *sram_channels;

	const struct cx25821_fmt *fmt;
	unsigned field;
	unsigned int width, height;
	int pixel_formats;
	int use_cif_resolution;
	int cif_width;

	/* video output data for the video output channel */
	struct cx25821_video_out_data *out;
};

struct snd_card;

struct cx25821_dev {
	struct v4l2_device v4l2_dev;

	/* pci stuff */
	struct pci_dev *pci;
	unsigned char pci_rev, pci_lat;
	int pci_bus, pci_slot;
	u32 base_io_addr;
	u32 __iomem *lmmio;
	u8 __iomem *bmmio;
	int pci_irqmask;
	int hwrevision;
	/* used by cx25821-alsa */
	struct snd_card *card;

	u32 clk_freq;

	/* I2C adapters: Master 1 & 2 (External) & Master 3 (Internal only) */
	struct cx25821_i2c i2c_bus[3];

	int nr;
	struct mutex lock;

	struct cx25821_channel channels[MAX_VID_CHANNEL_NUM];

	/* board details */
	unsigned int board;
	char name[32];

	/* Analog video */
	unsigned int input;
	v4l2_std_id tvnorm;
	unsigned short _max_num_decoders;

	/* Analog Audio Upstream */
	int _audio_is_running;
	int _audiopixel_format;
	int _is_first_audio_frame;
	int _audiofile_status;
	int _audio_lines_count;
	int _audioframe_count;
	int _audio_upstream_channel;
	int _last_index_irq;    /* The last interrupt index processed. */

	__le32 *_risc_audio_jmp_addr;
	__le32 *_risc_virt_start_addr;
	__le32 *_risc_virt_addr;
	dma_addr_t _risc_phys_addr;
	dma_addr_t _risc_phys_start_addr;

	unsigned int _audiorisc_size;
	unsigned int _audiodata_buf_size;
	__le32 *_audiodata_buf_virt_addr;
	dma_addr_t _audiodata_buf_phys_addr;
	char *_audiofilename;
	u32 audio_upstream_riscbuf_size;
	u32 audio_upstream_databuf_size;
	int _audioframe_index;
	struct work_struct _audio_work_entry;
	char *input_audiofilename;

	/* V4l */
	spinlock_t slock;

	/* Video Upstream */
	struct cx25821_video_out_data vid_out_data[2];
};

static inline struct cx25821_dev *get_cx25821(struct v4l2_device *v4l2_dev)
{
	return container_of(v4l2_dev, struct cx25821_dev, v4l2_dev);
}

extern struct cx25821_board cx25821_boards[];

#define SRAM_CH00  0		/* Video A */
#define SRAM_CH01  1		/* Video B */
#define SRAM_CH02  2		/* Video C */
#define SRAM_CH03  3		/* Video D */
#define SRAM_CH04  4		/* Video E */
#define SRAM_CH05  5		/* Video F */
#define SRAM_CH06  6		/* Video G */
#define SRAM_CH07  7		/* Video H */

#define SRAM_CH08  8		/* Audio A */
#define SRAM_CH09  9		/* Video Upstream I */
#define SRAM_CH10  10		/* Video Upstream J */
#define SRAM_CH11  11		/* Audio Upstream AUD_CHANNEL_B */

#define VID_UPSTREAM_SRAM_CHANNEL_I     SRAM_CH09
#define VID_UPSTREAM_SRAM_CHANNEL_J     SRAM_CH10
#define AUDIO_UPSTREAM_SRAM_CHANNEL_B   SRAM_CH11

struct sram_channel {
	char *name;
	u32 i;
	u32 cmds_start;
	u32 ctrl_start;
	u32 cdt;
	u32 fifo_start;
	u32 fifo_size;
	u32 ptr1_reg;
	u32 ptr2_reg;
	u32 cnt1_reg;
	u32 cnt2_reg;
	u32 int_msk;
	u32 int_stat;
	u32 int_mstat;
	u32 dma_ctl;
	u32 gpcnt_ctl;
	u32 gpcnt;
	u32 aud_length;
	u32 aud_cfg;
	u32 fld_aud_fifo_en;
	u32 fld_aud_risc_en;

	/* For Upstream Video */
	u32 vid_fmt_ctl;
	u32 vid_active_ctl1;
	u32 vid_active_ctl2;
	u32 vid_cdt_size;

	u32 vip_ctl;
	u32 pix_frmt;
	u32 jumponly;
	u32 irq_bit;
};

extern const struct sram_channel cx25821_sram_channels[];

#define cx_read(reg)             readl(dev->lmmio + ((reg)>>2))
#define cx_write(reg, value)     writel((value), dev->lmmio + ((reg)>>2))

#define cx_andor(reg, mask, value) \
	writel((readl(dev->lmmio+((reg)>>2)) & ~(mask)) |\
	((value) & (mask)), dev->lmmio+((reg)>>2))

#define cx_set(reg, bit)          cx_andor((reg), (bit), (bit))
#define cx_clear(reg, bit)        cx_andor((reg), (bit), 0)

#define Set_GPIO_Bit(Bit)                       (1 << Bit)
#define Clear_GPIO_Bit(Bit)                     (~(1 << Bit))

#define CX25821_ERR(fmt, args...)			\
	pr_err("(%d): " fmt, dev->board, ##args)
#define CX25821_WARN(fmt, args...)			\
	pr_warn("(%d): " fmt, dev->board, ##args)
#define CX25821_INFO(fmt, args...)			\
	pr_info("(%d): " fmt, dev->board, ##args)

extern int cx25821_i2c_register(struct cx25821_i2c *bus);
extern int cx25821_i2c_read(struct cx25821_i2c *bus, u16 reg_addr, int *value);
extern int cx25821_i2c_write(struct cx25821_i2c *bus, u16 reg_addr, int value);
extern int cx25821_i2c_unregister(struct cx25821_i2c *bus);
extern void cx25821_gpio_init(struct cx25821_dev *dev);
extern void cx25821_set_gpiopin_direction(struct cx25821_dev *dev,
					  int pin_number, int pin_logic_value);

extern int medusa_video_init(struct cx25821_dev *dev);
extern int medusa_set_videostandard(struct cx25821_dev *dev);
extern void medusa_set_resolution(struct cx25821_dev *dev, int width,
				  int decoder_select);
extern int medusa_set_brightness(struct cx25821_dev *dev, int brightness,
				 int decoder);
extern int medusa_set_contrast(struct cx25821_dev *dev, int contrast,
			       int decoder);
extern int medusa_set_hue(struct cx25821_dev *dev, int hue, int decoder);
extern int medusa_set_saturation(struct cx25821_dev *dev, int saturation,
				 int decoder);

extern int cx25821_sram_channel_setup(struct cx25821_dev *dev,
				      const struct sram_channel *ch, unsigned int bpl,
				      u32 risc);

extern int cx25821_riscmem_alloc(struct pci_dev *pci,
				 struct cx25821_riscmem *risc,
				 unsigned int size);
extern int cx25821_risc_buffer(struct pci_dev *pci, struct cx25821_riscmem *risc,
			       struct scatterlist *sglist,
			       unsigned int top_offset,
			       unsigned int bottom_offset,
			       unsigned int bpl,
			       unsigned int padding, unsigned int lines);
extern int cx25821_risc_databuffer_audio(struct pci_dev *pci,
					 struct cx25821_riscmem *risc,
					 struct scatterlist *sglist,
					 unsigned int bpl,
					 unsigned int lines, unsigned int lpi);
extern void cx25821_free_buffer(struct cx25821_dev *dev,
				struct cx25821_buffer *buf);
extern void cx25821_sram_channel_dump(struct cx25821_dev *dev,
				      const struct sram_channel *ch);
extern void cx25821_sram_channel_dump_audio(struct cx25821_dev *dev,
					    const struct sram_channel *ch);

extern struct cx25821_dev *cx25821_dev_get(struct pci_dev *pci);
extern void cx25821_print_irqbits(char *name, char *tag, char **strings,
				  int len, u32 bits, u32 mask);
extern void cx25821_dev_unregister(struct cx25821_dev *dev);
extern int cx25821_sram_channel_setup_audio(struct cx25821_dev *dev,
					    const struct sram_channel *ch,
					    unsigned int bpl, u32 risc);

extern void cx25821_set_pixel_format(struct cx25821_dev *dev, int channel,
				     u32 format);

#endif
Commit	Line	Data
c942fddf	1	/* SPDX-License-Identifier: GPL-2.0-or-later */
02b20b0b MCC	2	/*
	3	* Driver for the Conexant CX25821 PCIe bridge
	4	*
bb4c9a74	5	* Copyright (C) 2009 Conexant Systems Inc.
02b20b0b MCC	6	* Authors <shu.lin@conexant.com>, <hiep.huynh@conexant.com>
02b20b0b MCC	7	* Based on Steven Toth <stoth@linuxtv.org> cx23885 driver
02b20b0b MCC	8	*/
02b20b0b MCC	9
02b20b0b MCC	10	#ifndef CX25821_H_
	11	#define CX25821_H_
	12
	13	#include <linux/pci.h>
	14	#include <linux/i2c.h>
02b20b0b MCC	15	#include <linux/interrupt.h>
	16	#include <linux/delay.h>
	17	#include <linux/sched.h>
	18	#include <linux/kdev_t.h>
	19
	20	#include <media/v4l2-common.h>
bb4c9a74	21	#include <media/v4l2-device.h>
f8d7ee70	22	#include <media/v4l2-ctrls.h>
2d700715	23	#include <media/videobuf2-v4l2.h>
b671ae6b	24	#include <media/videobuf2-dma-sg.h>
02b20b0b	25
02b20b0b MCC	26	#include "cx25821-reg.h"
	27	#include "cx25821-medusa-reg.h"
	28	#include "cx25821-sram.h"
	29	#include "cx25821-audio.h"
02b20b0b	30
02b20b0b MCC	31	#include <linux/mutex.h>
02b20b0b MCC	32
02b20b0b MCC	33	#define UNSET (-1U)
	34	#define NO_SYNC_LINE (-1U)
	35
	36	#define CX25821_MAXBOARDS 2
	37
02b20b0b MCC	38	#define LINE_SIZE_D1 1440
02b20b0b MCC	39
6d8c2ba1	40	/* Number of decoders and encoders */
02b20b0b MCC	41	#define MAX_DECODERS 8
	42	#define MAX_ENCODERS 2
	43	#define QUAD_DECODERS 4
	44	#define MAX_CAMERAS 16
	45
	46	/* Max number of inputs by card */
c7855ee5	47	#define MAX_CX25821_INPUT 8
02b20b0b MCC	48	#define RESOURCE_VIDEO0 1
	49	#define RESOURCE_VIDEO1 2
	50	#define RESOURCE_VIDEO2 4
	51	#define RESOURCE_VIDEO3 8
	52	#define RESOURCE_VIDEO4 16
	53	#define RESOURCE_VIDEO5 32
	54	#define RESOURCE_VIDEO6 64
	55	#define RESOURCE_VIDEO7 128
	56	#define RESOURCE_VIDEO8 256
	57	#define RESOURCE_VIDEO9 512
	58	#define RESOURCE_VIDEO10 1024
	59	#define RESOURCE_VIDEO11 2048
02b20b0b	60
1a9fc855	61	#define BUFFER_TIMEOUT (HZ) /* 0.5 seconds */
02b20b0b	62
c7855ee5	63	#define UNKNOWN_BOARD 0
02b20b0b MCC	64	#define CX25821_BOARD 1
02b20b0b MCC	65
bb4c9a74	66	/* Currently supported by the driver */
02b20b0b	67	#define CX25821_NORMS (\
e4115bb2 RP	68	V4L2_STD_NTSC_M \| V4L2_STD_NTSC_M_JP \| V4L2_STD_NTSC_M_KR \| \
	69	V4L2_STD_PAL_BG \| V4L2_STD_PAL_DK \| V4L2_STD_PAL_I \| \
	70	V4L2_STD_PAL_M \| V4L2_STD_PAL_N \| V4L2_STD_PAL_H \| \
	71	V4L2_STD_PAL_Nc)
02b20b0b MCC	72
	73	#define CX25821_BOARD_CONEXANT_ATHENA10 1
	74	#define MAX_VID_CHANNEL_NUM 12
b6f21dc3 HV	75
	76	/*
	77	* Maximum capture-only channels. This can go away once video/audio output
	78	* is fully supported in this driver.
	79	*/
	80	#define MAX_VID_CAP_CHANNEL_NUM 10
	81
02b20b0b MCC	82	#define VID_CHANNEL_NUM 8
	83
	84	struct cx25821_fmt {
1a9fc855 MCC	85	u32 fourcc; /* v4l2 format id */
	86	int depth;
	87	int flags;
	88	u32 cxformat;
02b20b0b MCC	89	};
02b20b0b MCC	90
02b20b0b	91	struct cx25821_tvnorm {
1a9fc855 MCC	92	char *name;
	93	v4l2_std_id id;
	94	u32 cxiformat;
	95	u32 cxoformat;
02b20b0b MCC	96	};
02b20b0b MCC	97
02b20b0b	98	enum cx25821_src_sel_type {
1a9fc855 MCC	99	CX25821_SRC_SEL_EXT_656_VIDEO = 0,
1a9fc855 MCC	100	CX25821_SRC_SEL_PARALLEL_MPEG_VIDEO
02b20b0b MCC	101	};
02b20b0b MCC	102
5ede94c7 HV	103	struct cx25821_riscmem {
	104	unsigned int size;
	105	__le32 *cpu;
	106	__le32 *jmp;
	107	dma_addr_t dma;
	108	};
	109
02b20b0b MCC	110	/* buffer for one video frame */
02b20b0b MCC	111	struct cx25821_buffer {
1a9fc855	112	/* common v4l buffer stuff -- must be first */
2d700715	113	struct vb2_v4l2_buffer vb;
b671ae6b	114	struct list_head queue;
1a9fc855 MCC	115
	116	/* cx25821 specific */
	117	unsigned int bpl;
5ede94c7	118	struct cx25821_riscmem risc;
95c232a2	119	const struct cx25821_fmt *fmt;
02b20b0b MCC	120	};
02b20b0b MCC	121
7ae70c8b	122	enum port {
1a9fc855 MCC	123	CX25821_UNDEFINED = 0,
	124	CX25821_RAW,
	125	CX25821_264
7ae70c8b	126	};
02b20b0b MCC	127
02b20b0b MCC	128	struct cx25821_board {
c854d888	129	const char *name;
7ae70c8b LF	130	enum port porta;
	131	enum port portb;
	132	enum port portc;
1a9fc855 MCC	133
1a9fc855 MCC	134	u32 clk_freq;
02b20b0b MCC	135	};
02b20b0b MCC	136
02b20b0b	137	struct cx25821_i2c {
1a9fc855 MCC	138	struct cx25821_dev *dev;
	139
	140	int nr;
	141
	142	/* i2c i/o */
	143	struct i2c_adapter i2c_adap;
1a9fc855 MCC	144	struct i2c_client i2c_client;
	145	u32 i2c_rc;
	146
16790554	147	/* cx25821 registers used for raw address */
1a9fc855 MCC	148	u32 i2c_period;
	149	u32 reg_ctrl;
	150	u32 reg_stat;
	151	u32 reg_addr;
	152	u32 reg_rdata;
	153	u32 reg_wdata;
02b20b0b MCC	154	};
	155
	156	struct cx25821_dmaqueue {
1a9fc855	157	struct list_head active;
1a9fc855	158	u32 count;
02b20b0b MCC	159	};
02b20b0b MCC	160
f8d7ee70 HV	161	struct cx25821_dev;
f8d7ee70 HV	162
7087d31b HV	163	struct cx25821_channel;
	164
	165	struct cx25821_video_out_data {
	166	struct cx25821_channel *chan;
	167	int _line_size;
	168	int _prog_cnt;
	169	int _pixel_format;
	170	int _is_first_frame;
	171	int _is_running;
	172	int _file_status;
	173	int _lines_count;
	174	int _frame_count;
	175	unsigned int _risc_size;
	176
	177	__le32 *_dma_virt_start_addr;
	178	__le32 *_dma_virt_addr;
	179	dma_addr_t _dma_phys_addr;
	180	dma_addr_t _dma_phys_start_addr;
	181
	182	unsigned int _data_buf_size;
	183	__le32 *_data_buf_virt_addr;
	184	dma_addr_t _data_buf_phys_addr;
	185
	186	u32 upstream_riscbuf_size;
	187	u32 upstream_databuf_size;
7087d31b HV	188	int is_60hz;
7087d31b HV	189	int _frame_index;
ea3f7ac6 HV	190	int cur_frame_index;
	191	int curpos;
	192	wait_queue_head_t waitq;
7087d31b HV	193	};
7087d31b HV	194
6d8c2ba1	195	struct cx25821_channel {
f8d7ee70 HV	196	unsigned id;
f8d7ee70 HV	197	struct cx25821_dev *dev;
6d8c2ba1	198
f8d7ee70	199	struct v4l2_ctrl_handler hdl;
6d8c2ba1	200
467870ca	201	struct video_device vdev;
2efe2cc4	202	struct cx25821_dmaqueue dma_vidq;
b671ae6b	203	struct vb2_queue vidq;
6d8c2ba1	204
bfef0d35	205	const struct sram_channel *sram_channels;
6d8c2ba1	206
2efe2cc4	207	const struct cx25821_fmt *fmt;
b671ae6b	208	unsigned field;
2efe2cc4	209	unsigned int width, height;
e4115bb2 RP	210	int pixel_formats;
	211	int use_cif_resolution;
	212	int cif_width;
7087d31b HV	213
	214	/* video output data for the video output channel */
	215	struct cx25821_video_out_data *out;
6d8c2ba1 PB	216	};
6d8c2ba1 PB	217
a8f35ce3 HV	218	struct snd_card;
a8f35ce3 HV	219
02b20b0b	220	struct cx25821_dev {
1a9fc855 MCC	221	struct v4l2_device v4l2_dev;
1a9fc855 MCC	222
1a9fc855 MCC	223	/* pci stuff */
	224	struct pci_dev *pci;
	225	unsigned char pci_rev, pci_lat;
	226	int pci_bus, pci_slot;
	227	u32 base_io_addr;
	228	u32 __iomem *lmmio;
	229	u8 __iomem *bmmio;
	230	int pci_irqmask;
	231	int hwrevision;
a8f35ce3 HV	232	/* used by cx25821-alsa */
a8f35ce3 HV	233	struct snd_card *card;
1a9fc855 MCC	234
	235	u32 clk_freq;
	236
	237	/* I2C adapters: Master 1 & 2 (External) & Master 3 (Internal only) */
	238	struct cx25821_i2c i2c_bus[3];
	239
	240	int nr;
	241	struct mutex lock;
	242
e4115bb2	243	struct cx25821_channel channels[MAX_VID_CHANNEL_NUM];
6d8c2ba1	244
1a9fc855 MCC	245	/* board details */
	246	unsigned int board;
	247	char name[32];
	248
1a9fc855	249	/* Analog video */
1a9fc855	250	unsigned int input;
1a9fc855	251	v4l2_std_id tvnorm;
1a9fc855 MCC	252	unsigned short _max_num_decoders;
1a9fc855 MCC	253
1a9fc855 MCC	254	/* Analog Audio Upstream */
	255	int _audio_is_running;
	256	int _audiopixel_format;
	257	int _is_first_audio_frame;
	258	int _audiofile_status;
	259	int _audio_lines_count;
	260	int _audioframe_count;
6100c579	261	int _audio_upstream_channel;
e4115bb2	262	int _last_index_irq; /* The last interrupt index processed. */
1a9fc855 MCC	263
	264	__le32 *_risc_audio_jmp_addr;
	265	__le32 *_risc_virt_start_addr;
	266	__le32 *_risc_virt_addr;
	267	dma_addr_t _risc_phys_addr;
	268	dma_addr_t _risc_phys_start_addr;
	269
	270	unsigned int _audiorisc_size;
	271	unsigned int _audiodata_buf_size;
	272	__le32 *_audiodata_buf_virt_addr;
	273	dma_addr_t _audiodata_buf_phys_addr;
	274	char *_audiofilename;
1a9fc855 MCC	275	u32 audio_upstream_riscbuf_size;
1a9fc855 MCC	276	u32 audio_upstream_databuf_size;
1a9fc855	277	int _audioframe_index;
1a9fc855	278	struct work_struct _audio_work_entry;
1a9fc855	279	char *input_audiofilename;
7087d31b HV	280
	281	/* V4l */
	282	spinlock_t slock;
	283
	284	/* Video Upstream */
	285	struct cx25821_video_out_data vid_out_data[2];
02b20b0b MCC	286	};
02b20b0b MCC	287
02b20b0b MCC	288	static inline struct cx25821_dev get_cx25821(struct v4l2_device v4l2_dev)
02b20b0b MCC	289	{
1a9fc855	290	return container_of(v4l2_dev, struct cx25821_dev, v4l2_dev);
02b20b0b MCC	291	}
02b20b0b MCC	292
02b20b0b	293	extern struct cx25821_board cx25821_boards[];
02b20b0b	294
1a9fc855 MCC	295	#define SRAM_CH00 0 /* Video A */
	296	#define SRAM_CH01 1 /* Video B */
	297	#define SRAM_CH02 2 /* Video C */
	298	#define SRAM_CH03 3 /* Video D */
	299	#define SRAM_CH04 4 /* Video E */
	300	#define SRAM_CH05 5 /* Video F */
	301	#define SRAM_CH06 6 /* Video G */
	302	#define SRAM_CH07 7 /* Video H */
02b20b0b	303
1a9fc855 MCC	304	#define SRAM_CH08 8 /* Audio A */
	305	#define SRAM_CH09 9 /* Video Upstream I */
	306	#define SRAM_CH10 10 /* Video Upstream J */
	307	#define SRAM_CH11 11 /* Audio Upstream AUD_CHANNEL_B */
02b20b0b MCC	308
	309	#define VID_UPSTREAM_SRAM_CHANNEL_I SRAM_CH09
	310	#define VID_UPSTREAM_SRAM_CHANNEL_J SRAM_CH10
	311	#define AUDIO_UPSTREAM_SRAM_CHANNEL_B SRAM_CH11
02b20b0b MCC	312
02b20b0b MCC	313	struct sram_channel {
1a9fc855 MCC	314	char *name;
	315	u32 i;
	316	u32 cmds_start;
	317	u32 ctrl_start;
	318	u32 cdt;
	319	u32 fifo_start;
	320	u32 fifo_size;
	321	u32 ptr1_reg;
	322	u32 ptr2_reg;
	323	u32 cnt1_reg;
	324	u32 cnt2_reg;
	325	u32 int_msk;
	326	u32 int_stat;
	327	u32 int_mstat;
	328	u32 dma_ctl;
	329	u32 gpcnt_ctl;
	330	u32 gpcnt;
	331	u32 aud_length;
	332	u32 aud_cfg;
	333	u32 fld_aud_fifo_en;
	334	u32 fld_aud_risc_en;
	335
e4115bb2	336	/* For Upstream Video */
1a9fc855 MCC	337	u32 vid_fmt_ctl;
	338	u32 vid_active_ctl1;
	339	u32 vid_active_ctl2;
	340	u32 vid_cdt_size;
	341
	342	u32 vip_ctl;
	343	u32 pix_frmt;
	344	u32 jumponly;
	345	u32 irq_bit;
02b20b0b	346	};
bfef0d35 HV	347
bfef0d35 HV	348	extern const struct sram_channel cx25821_sram_channels[];
02b20b0b	349
02b20b0b MCC	350	#define cx_read(reg) readl(dev->lmmio + ((reg)>>2))
	351	#define cx_write(reg, value) writel((value), dev->lmmio + ((reg)>>2))
	352
	353	#define cx_andor(reg, mask, value) \
e4115bb2 RP	354	writel((readl(dev->lmmio+((reg)>>2)) & ~(mask)) \|\
e4115bb2 RP	355	((value) & (mask)), dev->lmmio+((reg)>>2))
02b20b0b MCC	356
	357	#define cx_set(reg, bit) cx_andor((reg), (bit), (bit))
	358	#define cx_clear(reg, bit) cx_andor((reg), (bit), 0)
	359
	360	#define Set_GPIO_Bit(Bit) (1 << Bit)
	361	#define Clear_GPIO_Bit(Bit) (~(1 << Bit))
	362
36d89f7d JP	363	#define CX25821_ERR(fmt, args...) \
	364	pr_err("(%d): " fmt, dev->board, ##args)
	365	#define CX25821_WARN(fmt, args...) \
	366	pr_warn("(%d): " fmt, dev->board, ##args)
	367	#define CX25821_INFO(fmt, args...) \
	368	pr_info("(%d): " fmt, dev->board, ##args)
02b20b0b	369
1a9fc855	370	extern int cx25821_i2c_register(struct cx25821_i2c *bus);
1a9fc855 MCC	371	extern int cx25821_i2c_read(struct cx25821_i2c bus, u16 reg_addr, int value);
	372	extern int cx25821_i2c_write(struct cx25821_i2c *bus, u16 reg_addr, int value);
	373	extern int cx25821_i2c_unregister(struct cx25821_i2c *bus);
02b20b0b	374	extern void cx25821_gpio_init(struct cx25821_dev *dev);
1a9fc855 MCC	375	extern void cx25821_set_gpiopin_direction(struct cx25821_dev *dev,
	376	int pin_number, int pin_logic_value);
	377
	378	extern int medusa_video_init(struct cx25821_dev *dev);
	379	extern int medusa_set_videostandard(struct cx25821_dev *dev);
	380	extern void medusa_set_resolution(struct cx25821_dev *dev, int width,
	381	int decoder_select);
	382	extern int medusa_set_brightness(struct cx25821_dev *dev, int brightness,
	383	int decoder);
	384	extern int medusa_set_contrast(struct cx25821_dev *dev, int contrast,
	385	int decoder);
	386	extern int medusa_set_hue(struct cx25821_dev *dev, int hue, int decoder);
	387	extern int medusa_set_saturation(struct cx25821_dev *dev, int saturation,
	388	int decoder);
	389
	390	extern int cx25821_sram_channel_setup(struct cx25821_dev *dev,
bfef0d35	391	const struct sram_channel *ch, unsigned int bpl,
1a9fc855	392	u32 risc);
02b20b0b	393
5ede94c7 HV	394	extern int cx25821_riscmem_alloc(struct pci_dev *pci,
	395	struct cx25821_riscmem *risc,
	396	unsigned int size);
	397	extern int cx25821_risc_buffer(struct pci_dev pci, struct cx25821_riscmem risc,
1a9fc855 MCC	398	struct scatterlist *sglist,
	399	unsigned int top_offset,
	400	unsigned int bottom_offset,
	401	unsigned int bpl,
	402	unsigned int padding, unsigned int lines);
02b20b0b	403	extern int cx25821_risc_databuffer_audio(struct pci_dev *pci,
5ede94c7	404	struct cx25821_riscmem *risc,
1a9fc855 MCC	405	struct scatterlist *sglist,
	406	unsigned int bpl,
	407	unsigned int lines, unsigned int lpi);
b671ae6b	408	extern void cx25821_free_buffer(struct cx25821_dev *dev,
1a9fc855	409	struct cx25821_buffer *buf);
1a9fc855	410	extern void cx25821_sram_channel_dump(struct cx25821_dev *dev,
bfef0d35	411	const struct sram_channel *ch);
1a9fc855	412	extern void cx25821_sram_channel_dump_audio(struct cx25821_dev *dev,
bfef0d35	413	const struct sram_channel *ch);
1a9fc855 MCC	414
	415	extern struct cx25821_dev cx25821_dev_get(struct pci_dev pci);
	416	extern void cx25821_print_irqbits(char name, char tag, char **strings,
	417	int len, u32 bits, u32 mask);
02b20b0b MCC	418	extern void cx25821_dev_unregister(struct cx25821_dev *dev);
02b20b0b MCC	419	extern int cx25821_sram_channel_setup_audio(struct cx25821_dev *dev,
bfef0d35	420	const struct sram_channel *ch,
1a9fc855 MCC	421	unsigned int bpl, u32 risc);
1a9fc855 MCC	422
1a9fc855 MCC	423	extern void cx25821_set_pixel_format(struct cx25821_dev *dev, int channel,
1a9fc855 MCC	424	u32 format);
95c232a2	425
02b20b0b	426	#endif