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1da177e4 1/*
1da177e4
LT
2 *
3 * device driver for Conexant 2388x based TV cards
4 * video4linux video interface
5 *
6 * (c) 2003-04 Gerd Knorr <kraxel@bytesex.org> [SuSE Labs]
7 *
32590819 8 * (c) 2005-2006 Mauro Carvalho Chehab <mchehab@kernel.org>
8d87cb9f
MCC
9 * - Multituner support
10 * - video_ioctl2 conversion
11 * - PAL/M fixes
12 *
1da177e4
LT
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
1da177e4
LT
22 */
23
65bc2fe8
MCC
24#include "cx88.h"
25
1da177e4
LT
26#include <linux/init.h>
27#include <linux/list.h>
28#include <linux/module.h>
1da177e4
LT
29#include <linux/kmod.h>
30#include <linux/kernel.h>
31#include <linux/slab.h>
32#include <linux/interrupt.h>
c24228da 33#include <linux/dma-mapping.h>
1da177e4
LT
34#include <linux/delay.h>
35#include <linux/kthread.h>
36#include <asm/div64.h>
37
5e453dc7 38#include <media/v4l2-common.h>
35ea11ff 39#include <media/v4l2-ioctl.h>
1a3c60a0 40#include <media/v4l2-event.h>
b5dcee22 41#include <media/i2c/wm8775.h>
1da177e4
LT
42
43MODULE_DESCRIPTION("v4l2 driver module for cx2388x based TV cards");
44MODULE_AUTHOR("Gerd Knorr <kraxel@bytesex.org> [SuSE Labs]");
45MODULE_LICENSE("GPL");
1990d50b 46MODULE_VERSION(CX88_VERSION);
1da177e4
LT
47
48/* ------------------------------------------------------------------ */
49
50static unsigned int video_nr[] = {[0 ... (CX88_MAXBOARDS - 1)] = UNSET };
51static unsigned int vbi_nr[] = {[0 ... (CX88_MAXBOARDS - 1)] = UNSET };
52static unsigned int radio_nr[] = {[0 ... (CX88_MAXBOARDS - 1)] = UNSET };
53
54module_param_array(video_nr, int, NULL, 0444);
55module_param_array(vbi_nr, int, NULL, 0444);
56module_param_array(radio_nr, int, NULL, 0444);
57
7b61ba8f
MCC
58MODULE_PARM_DESC(video_nr, "video device numbers");
59MODULE_PARM_DESC(vbi_nr, "vbi device numbers");
60MODULE_PARM_DESC(radio_nr, "radio device numbers");
1da177e4 61
ff699e6b 62static unsigned int video_debug;
7b61ba8f
MCC
63module_param(video_debug, int, 0644);
64MODULE_PARM_DESC(video_debug, "enable debug messages [video]");
1da177e4 65
ff699e6b 66static unsigned int irq_debug;
7b61ba8f
MCC
67module_param(irq_debug, int, 0644);
68MODULE_PARM_DESC(irq_debug, "enable debug messages [IRQ handler]");
1da177e4 69
65bc2fe8
MCC
70#define dprintk(level, fmt, arg...) do { \
71 if (video_debug >= level) \
72 printk(KERN_DEBUG pr_fmt("%s: video:" fmt), \
73 __func__, ##arg); \
74} while (0)
75
1da177e4
LT
76/* ------------------------------------------------------------------- */
77/* static data */
78
2e4e98e7 79static const struct cx8800_fmt formats[] = {
1da177e4
LT
80 {
81 .name = "8 bpp, gray",
82 .fourcc = V4L2_PIX_FMT_GREY,
83 .cxformat = ColorFormatY8,
84 .depth = 8,
85 .flags = FORMAT_FLAGS_PACKED,
7b61ba8f 86 }, {
1da177e4
LT
87 .name = "15 bpp RGB, le",
88 .fourcc = V4L2_PIX_FMT_RGB555,
89 .cxformat = ColorFormatRGB15,
90 .depth = 16,
91 .flags = FORMAT_FLAGS_PACKED,
7b61ba8f 92 }, {
1da177e4
LT
93 .name = "15 bpp RGB, be",
94 .fourcc = V4L2_PIX_FMT_RGB555X,
95 .cxformat = ColorFormatRGB15 | ColorFormatBSWAP,
96 .depth = 16,
97 .flags = FORMAT_FLAGS_PACKED,
7b61ba8f 98 }, {
1da177e4
LT
99 .name = "16 bpp RGB, le",
100 .fourcc = V4L2_PIX_FMT_RGB565,
101 .cxformat = ColorFormatRGB16,
102 .depth = 16,
103 .flags = FORMAT_FLAGS_PACKED,
7b61ba8f 104 }, {
1da177e4
LT
105 .name = "16 bpp RGB, be",
106 .fourcc = V4L2_PIX_FMT_RGB565X,
107 .cxformat = ColorFormatRGB16 | ColorFormatBSWAP,
108 .depth = 16,
109 .flags = FORMAT_FLAGS_PACKED,
7b61ba8f 110 }, {
1da177e4
LT
111 .name = "24 bpp RGB, le",
112 .fourcc = V4L2_PIX_FMT_BGR24,
113 .cxformat = ColorFormatRGB24,
114 .depth = 24,
115 .flags = FORMAT_FLAGS_PACKED,
7b61ba8f 116 }, {
1da177e4
LT
117 .name = "32 bpp RGB, le",
118 .fourcc = V4L2_PIX_FMT_BGR32,
119 .cxformat = ColorFormatRGB32,
120 .depth = 32,
121 .flags = FORMAT_FLAGS_PACKED,
7b61ba8f 122 }, {
1da177e4
LT
123 .name = "32 bpp RGB, be",
124 .fourcc = V4L2_PIX_FMT_RGB32,
399426ca
MCC
125 .cxformat = ColorFormatRGB32 | ColorFormatBSWAP |
126 ColorFormatWSWAP,
1da177e4
LT
127 .depth = 32,
128 .flags = FORMAT_FLAGS_PACKED,
7b61ba8f 129 }, {
1da177e4
LT
130 .name = "4:2:2, packed, YUYV",
131 .fourcc = V4L2_PIX_FMT_YUYV,
132 .cxformat = ColorFormatYUY2,
133 .depth = 16,
134 .flags = FORMAT_FLAGS_PACKED,
7b61ba8f 135 }, {
1da177e4
LT
136 .name = "4:2:2, packed, UYVY",
137 .fourcc = V4L2_PIX_FMT_UYVY,
138 .cxformat = ColorFormatYUY2 | ColorFormatBSWAP,
139 .depth = 16,
140 .flags = FORMAT_FLAGS_PACKED,
141 },
142};
143
7b61ba8f 144static const struct cx8800_fmt *format_by_fourcc(unsigned int fourcc)
1da177e4
LT
145{
146 unsigned int i;
147
148 for (i = 0; i < ARRAY_SIZE(formats); i++)
149 if (formats[i].fourcc == fourcc)
399426ca 150 return formats + i;
1da177e4
LT
151 return NULL;
152}
153
154/* ------------------------------------------------------------------- */
155
bac63981
HV
156struct cx88_ctrl {
157 /* control information */
158 u32 id;
159 s32 minimum;
160 s32 maximum;
161 u32 step;
162 s32 default_value;
163
164 /* control register information */
165 u32 off;
166 u32 reg;
167 u32 sreg;
168 u32 mask;
169 u32 shift;
170};
171
8c7cb12a 172static const struct cx88_ctrl cx8800_vid_ctls[] = {
1da177e4
LT
173 /* --- video --- */
174 {
bac63981
HV
175 .id = V4L2_CID_BRIGHTNESS,
176 .minimum = 0x00,
177 .maximum = 0xff,
178 .step = 1,
179 .default_value = 0x7f,
180 .off = 128,
181 .reg = MO_CONTR_BRIGHT,
182 .mask = 0x00ff,
183 .shift = 0,
7b61ba8f 184 }, {
bac63981
HV
185 .id = V4L2_CID_CONTRAST,
186 .minimum = 0,
187 .maximum = 0xff,
188 .step = 1,
189 .default_value = 0x3f,
190 .off = 0,
191 .reg = MO_CONTR_BRIGHT,
192 .mask = 0xff00,
193 .shift = 8,
7b61ba8f 194 }, {
bac63981
HV
195 .id = V4L2_CID_HUE,
196 .minimum = 0,
197 .maximum = 0xff,
198 .step = 1,
199 .default_value = 0x7f,
200 .off = 128,
201 .reg = MO_HUE,
202 .mask = 0x00ff,
203 .shift = 0,
7b61ba8f 204 }, {
1da177e4
LT
205 /* strictly, this only describes only U saturation.
206 * V saturation is handled specially through code.
207 */
bac63981
HV
208 .id = V4L2_CID_SATURATION,
209 .minimum = 0,
210 .maximum = 0xff,
211 .step = 1,
212 .default_value = 0x7f,
213 .off = 0,
214 .reg = MO_UV_SATURATION,
215 .mask = 0x00ff,
216 .shift = 0,
eea16e36 217 }, {
bac63981
HV
218 .id = V4L2_CID_SHARPNESS,
219 .minimum = 0,
220 .maximum = 4,
221 .step = 1,
222 .default_value = 0x0,
223 .off = 0,
399426ca
MCC
224 /*
225 * NOTE: the value is converted and written to both even
226 * and odd registers in the code
227 */
bac63981
HV
228 .reg = MO_FILTER_ODD,
229 .mask = 7 << 7,
230 .shift = 7,
eea16e36 231 }, {
bac63981
HV
232 .id = V4L2_CID_CHROMA_AGC,
233 .minimum = 0,
234 .maximum = 1,
235 .default_value = 0x1,
236 .reg = MO_INPUT_FORMAT,
237 .mask = 1 << 10,
238 .shift = 10,
1b879c43 239 }, {
bac63981
HV
240 .id = V4L2_CID_COLOR_KILLER,
241 .minimum = 0,
242 .maximum = 1,
243 .default_value = 0x1,
244 .reg = MO_INPUT_FORMAT,
245 .mask = 1 << 9,
246 .shift = 9,
bded70d2 247 }, {
bac63981
HV
248 .id = V4L2_CID_BAND_STOP_FILTER,
249 .minimum = 0,
250 .maximum = 1,
251 .step = 1,
252 .default_value = 0x0,
253 .off = 0,
254 .reg = MO_HTOTAL,
255 .mask = 3 << 11,
256 .shift = 11,
8c7cb12a
HV
257 }
258};
259
260static const struct cx88_ctrl cx8800_aud_ctls[] = {
261 {
bac63981
HV
262 /* --- audio --- */
263 .id = V4L2_CID_AUDIO_MUTE,
264 .minimum = 0,
265 .maximum = 1,
266 .default_value = 1,
267 .reg = AUD_VOL_CTL,
268 .sreg = SHADOW_AUD_VOL_CTL,
269 .mask = (1 << 6),
270 .shift = 6,
7b61ba8f 271 }, {
bac63981
HV
272 .id = V4L2_CID_AUDIO_VOLUME,
273 .minimum = 0,
274 .maximum = 0x3f,
275 .step = 1,
276 .default_value = 0x3f,
277 .reg = AUD_VOL_CTL,
278 .sreg = SHADOW_AUD_VOL_CTL,
279 .mask = 0x3f,
280 .shift = 0,
7b61ba8f 281 }, {
bac63981
HV
282 .id = V4L2_CID_AUDIO_BALANCE,
283 .minimum = 0,
284 .maximum = 0x7f,
285 .step = 1,
286 .default_value = 0x40,
287 .reg = AUD_BAL_CTL,
288 .sreg = SHADOW_AUD_BAL_CTL,
289 .mask = 0x7f,
290 .shift = 0,
1da177e4
LT
291 }
292};
1da177e4 293
8c7cb12a
HV
294enum {
295 CX8800_VID_CTLS = ARRAY_SIZE(cx8800_vid_ctls),
296 CX8800_AUD_CTLS = ARRAY_SIZE(cx8800_aud_ctls),
297};
38a2713a 298
1da177e4
LT
299/* ------------------------------------------------------------------ */
300
e90311a1 301int cx88_video_mux(struct cx88_core *core, unsigned int input)
1da177e4 302{
e52e98a7 303 /* struct cx88_core *core = dev->core; */
1da177e4 304
7b61ba8f 305 dprintk(1, "video_mux: %d [vmux=%d,gpio=0x%x,0x%x,0x%x,0x%x]\n",
6a59d64c 306 input, INPUT(input).vmux,
7b61ba8f
MCC
307 INPUT(input).gpio0, INPUT(input).gpio1,
308 INPUT(input).gpio2, INPUT(input).gpio3);
e52e98a7 309 core->input = input;
6a59d64c
TP
310 cx_andor(MO_INPUT_FORMAT, 0x03 << 14, INPUT(input).vmux << 14);
311 cx_write(MO_GP3_IO, INPUT(input).gpio3);
312 cx_write(MO_GP0_IO, INPUT(input).gpio0);
313 cx_write(MO_GP1_IO, INPUT(input).gpio1);
314 cx_write(MO_GP2_IO, INPUT(input).gpio2);
1da177e4 315
6a59d64c 316 switch (INPUT(input).type) {
1da177e4
LT
317 case CX88_VMUX_SVIDEO:
318 cx_set(MO_AFECFG_IO, 0x00000001);
319 cx_set(MO_INPUT_FORMAT, 0x00010010);
320 cx_set(MO_FILTER_EVEN, 0x00002020);
321 cx_set(MO_FILTER_ODD, 0x00002020);
322 break;
323 default:
324 cx_clear(MO_AFECFG_IO, 0x00000001);
325 cx_clear(MO_INPUT_FORMAT, 0x00010010);
326 cx_clear(MO_FILTER_EVEN, 0x00002020);
327 cx_clear(MO_FILTER_ODD, 0x00002020);
328 break;
329 }
f24546a9 330
399426ca
MCC
331 /*
332 * if there are audioroutes defined, we have an external
333 * ADC to deal with audio
334 */
66e6fbdf 335 if (INPUT(input).audioroute) {
399426ca
MCC
336 /*
337 * The wm8775 module has the "2" route hardwired into
338 * the initialization. Some boards may use different
339 * routes for different inputs. HVR-1300 surely does
340 */
609c4c12 341 if (core->sd_wm8775) {
5325b427 342 call_all(core, audio, s_routing,
6e1f4df7 343 INPUT(input).audioroute, 0, 0);
66e6fbdf 344 }
399426ca
MCC
345 /*
346 * cx2388's C-ADC is connected to the tuner only.
347 * When used with S-Video, that ADC is busy dealing with
348 * chroma, so an external must be used for baseband audio
349 */
6e1f4df7 350 if (INPUT(input).type != CX88_VMUX_TELEVISION &&
351 INPUT(input).type != CX88_VMUX_CABLE) {
430189da
DB
352 /* "I2S ADC mode" */
353 core->tvaudio = WW_I2SADC;
354 cx88_set_tvaudio(core);
355 } else {
356 /* Normal mode */
357 cx_write(AUD_I2SCNTL, 0x0);
358 cx_clear(AUD_CTL, EN_I2SIN_ENABLE);
359 }
f24546a9 360 }
66e6fbdf 361
1da177e4
LT
362 return 0;
363}
e90311a1 364EXPORT_SYMBOL(cx88_video_mux);
1da177e4
LT
365
366/* ------------------------------------------------------------------ */
367
368static int start_video_dma(struct cx8800_dev *dev,
369 struct cx88_dmaqueue *q,
370 struct cx88_buffer *buf)
371{
372 struct cx88_core *core = dev->core;
373
374 /* setup fifo + format */
e52e98a7 375 cx88_sram_channel_setup(core, &cx88_sram_channels[SRAM_CH21],
1da177e4 376 buf->bpl, buf->risc.dma);
ccd6f1d4 377 cx88_set_scale(core, core->width, core->height, core->field);
637bc207 378 cx_write(MO_COLOR_CTRL, dev->fmt->cxformat | ColorFormatGamma);
1da177e4
LT
379
380 /* reset counter */
7b61ba8f 381 cx_write(MO_VIDY_GPCNTRL, GP_COUNT_CONTROL_RESET);
9450684b 382 q->count = 0;
1da177e4
LT
383
384 /* enable irqs */
8ddac9ee 385 cx_set(MO_PCI_INTMSK, core->pci_irqmask | PCI_INT_VIDINT);
e52e98a7 386
399426ca
MCC
387 /*
388 * Enables corresponding bits at PCI_INT_STAT:
389 * bits 0 to 4: video, audio, transport stream, VIP, Host
390 * bit 7: timer
391 * bits 8 and 9: DMA complete for: SRC, DST
392 * bits 10 and 11: BERR signal asserted for RISC: RD, WR
393 * bits 12 to 15: BERR signal asserted for: BRDG, SRC, DST, IPB
e52e98a7 394 */
1da177e4
LT
395 cx_set(MO_VID_INTMSK, 0x0f0011);
396
397 /* enable capture */
7b61ba8f 398 cx_set(VID_CAPTURE_CONTROL, 0x06);
1da177e4
LT
399
400 /* start dma */
399426ca 401 cx_set(MO_DEV_CNTRL2, (1 << 5));
e52e98a7 402 cx_set(MO_VID_DMACNTRL, 0x11); /* Planar Y and packed FIFO and RISC enable */
1da177e4
LT
403
404 return 0;
405}
406
17bc98a4 407#ifdef CONFIG_PM
1da177e4
LT
408static int stop_video_dma(struct cx8800_dev *dev)
409{
410 struct cx88_core *core = dev->core;
411
412 /* stop dma */
413 cx_clear(MO_VID_DMACNTRL, 0x11);
414
415 /* disable capture */
7b61ba8f 416 cx_clear(VID_CAPTURE_CONTROL, 0x06);
1da177e4
LT
417
418 /* disable irqs */
8ddac9ee 419 cx_clear(MO_PCI_INTMSK, PCI_INT_VIDINT);
1da177e4
LT
420 cx_clear(MO_VID_INTMSK, 0x0f0011);
421 return 0;
422}
423
424static int restart_video_queue(struct cx8800_dev *dev,
425 struct cx88_dmaqueue *q)
426{
6f11adc6 427 struct cx88_buffer *buf;
1da177e4
LT
428
429 if (!list_empty(&q->active)) {
0b6b6302 430 buf = list_entry(q->active.next, struct cx88_buffer, list);
7b61ba8f 431 dprintk(2, "restart_queue [%p/%d]: restart dma\n",
2d700715 432 buf, buf->vb.vb2_buf.index);
1da177e4 433 start_video_dma(dev, q, buf);
1da177e4 434 }
6f11adc6 435 return 0;
1da177e4 436}
bc5e66bd 437#endif
1da177e4
LT
438
439/* ------------------------------------------------------------------ */
440
df9ecb0c 441static int queue_setup(struct vb2_queue *q,
399426ca
MCC
442 unsigned int *num_buffers, unsigned int *num_planes,
443 unsigned int sizes[], struct device *alloc_devs[])
1da177e4 444{
0b6b6302 445 struct cx8800_dev *dev = q->drv_priv;
ccd6f1d4 446 struct cx88_core *core = dev->core;
0b6b6302
HV
447
448 *num_planes = 1;
ccd6f1d4 449 sizes[0] = (dev->fmt->depth * core->width * core->height) >> 3;
1da177e4
LT
450 return 0;
451}
452
0b6b6302 453static int buffer_prepare(struct vb2_buffer *vb)
1da177e4 454{
2d700715 455 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
0b6b6302 456 struct cx8800_dev *dev = vb->vb2_queue->drv_priv;
e52e98a7 457 struct cx88_core *core = dev->core;
2d700715 458 struct cx88_buffer *buf = container_of(vbuf, struct cx88_buffer, vb);
0b6b6302 459 struct sg_table *sgt = vb2_dma_sg_plane_desc(vb, 0);
1da177e4 460
ccd6f1d4 461 buf->bpl = core->width * dev->fmt->depth >> 3;
0b6b6302 462
ccd6f1d4 463 if (vb2_plane_size(vb, 0) < core->height * buf->bpl)
1da177e4 464 return -EINVAL;
ccd6f1d4 465 vb2_set_plane_payload(vb, 0, core->height * buf->bpl);
1da177e4 466
ccd6f1d4 467 switch (core->field) {
637bc207
HV
468 case V4L2_FIELD_TOP:
469 cx88_risc_buffer(dev->pci, &buf->risc,
0b6b6302 470 sgt->sgl, 0, UNSET,
ccd6f1d4 471 buf->bpl, 0, core->height);
637bc207
HV
472 break;
473 case V4L2_FIELD_BOTTOM:
474 cx88_risc_buffer(dev->pci, &buf->risc,
0b6b6302 475 sgt->sgl, UNSET, 0,
ccd6f1d4 476 buf->bpl, 0, core->height);
637bc207
HV
477 break;
478 case V4L2_FIELD_SEQ_TB:
479 cx88_risc_buffer(dev->pci, &buf->risc,
0b6b6302 480 sgt->sgl,
ccd6f1d4 481 0, buf->bpl * (core->height >> 1),
637bc207 482 buf->bpl, 0,
ccd6f1d4 483 core->height >> 1);
637bc207
HV
484 break;
485 case V4L2_FIELD_SEQ_BT:
486 cx88_risc_buffer(dev->pci, &buf->risc,
0b6b6302 487 sgt->sgl,
ccd6f1d4 488 buf->bpl * (core->height >> 1), 0,
637bc207 489 buf->bpl, 0,
ccd6f1d4 490 core->height >> 1);
637bc207
HV
491 break;
492 case V4L2_FIELD_INTERLACED:
493 default:
494 cx88_risc_buffer(dev->pci, &buf->risc,
0b6b6302 495 sgt->sgl, 0, buf->bpl,
637bc207 496 buf->bpl, buf->bpl,
ccd6f1d4 497 core->height >> 1);
637bc207 498 break;
1da177e4 499 }
399426ca
MCC
500 dprintk(2,
501 "[%p/%d] buffer_prepare - %dx%d %dbpp \"%s\" - dma=0x%08lx\n",
2d700715 502 buf, buf->vb.vb2_buf.index,
ccd6f1d4 503 core->width, core->height, dev->fmt->depth, dev->fmt->name,
1da177e4 504 (unsigned long)buf->risc.dma);
1da177e4 505 return 0;
0b6b6302
HV
506}
507
508static void buffer_finish(struct vb2_buffer *vb)
509{
2d700715 510 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
0b6b6302 511 struct cx8800_dev *dev = vb->vb2_queue->drv_priv;
2d700715 512 struct cx88_buffer *buf = container_of(vbuf, struct cx88_buffer, vb);
5e7045e3 513 struct cx88_riscmem *risc = &buf->risc;
1da177e4 514
5e7045e3
HV
515 if (risc->cpu)
516 pci_free_consistent(dev->pci, risc->size, risc->cpu, risc->dma);
517 memset(risc, 0, sizeof(*risc));
1da177e4
LT
518}
519
0b6b6302 520static void buffer_queue(struct vb2_buffer *vb)
1da177e4 521{
2d700715 522 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
0b6b6302 523 struct cx8800_dev *dev = vb->vb2_queue->drv_priv;
2d700715 524 struct cx88_buffer *buf = container_of(vbuf, struct cx88_buffer, vb);
1da177e4 525 struct cx88_buffer *prev;
1da177e4
LT
526 struct cx88_dmaqueue *q = &dev->vidq;
527
0b6b6302
HV
528 /* add jump to start */
529 buf->risc.cpu[1] = cpu_to_le32(buf->risc.dma + 8);
530 buf->risc.jmp[0] = cpu_to_le32(RISC_JUMP | RISC_CNT_INC);
531 buf->risc.jmp[1] = cpu_to_le32(buf->risc.dma + 8);
1da177e4 532
6f11adc6 533 if (list_empty(&q->active)) {
0b6b6302 534 list_add_tail(&buf->list, &q->active);
7b61ba8f 535 dprintk(2, "[%p/%d] buffer_queue - first active\n",
2d700715 536 buf, buf->vb.vb2_buf.index);
1da177e4
LT
537
538 } else {
0b6b6302
HV
539 buf->risc.cpu[0] |= cpu_to_le32(RISC_IRQ1);
540 prev = list_entry(q->active.prev, struct cx88_buffer, list);
541 list_add_tail(&buf->list, &q->active);
637bc207
HV
542 prev->risc.jmp[1] = cpu_to_le32(buf->risc.dma);
543 dprintk(2, "[%p/%d] buffer_queue - append to active\n",
2d700715 544 buf, buf->vb.vb2_buf.index);
1da177e4
LT
545 }
546}
547
0b6b6302 548static int start_streaming(struct vb2_queue *q, unsigned int count)
1da177e4 549{
0b6b6302
HV
550 struct cx8800_dev *dev = q->drv_priv;
551 struct cx88_dmaqueue *dmaq = &dev->vidq;
552 struct cx88_buffer *buf = list_entry(dmaq->active.next,
553 struct cx88_buffer, list);
1da177e4 554
0b6b6302
HV
555 start_video_dma(dev, dmaq, buf);
556 return 0;
1da177e4
LT
557}
558
0b6b6302
HV
559static void stop_streaming(struct vb2_queue *q)
560{
561 struct cx8800_dev *dev = q->drv_priv;
562 struct cx88_core *core = dev->core;
563 struct cx88_dmaqueue *dmaq = &dev->vidq;
564 unsigned long flags;
1da177e4 565
0b6b6302
HV
566 cx_clear(MO_VID_DMACNTRL, 0x11);
567 cx_clear(VID_CAPTURE_CONTROL, 0x06);
568 spin_lock_irqsave(&dev->slock, flags);
569 while (!list_empty(&dmaq->active)) {
570 struct cx88_buffer *buf = list_entry(dmaq->active.next,
571 struct cx88_buffer, list);
edbd138e 572
0b6b6302 573 list_del(&buf->list);
2d700715 574 vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR);
1da177e4 575 }
0b6b6302 576 spin_unlock_irqrestore(&dev->slock, flags);
1da177e4
LT
577}
578
10accd2e 579static const struct vb2_ops cx8800_video_qops = {
0b6b6302
HV
580 .queue_setup = queue_setup,
581 .buf_prepare = buffer_prepare,
582 .buf_finish = buffer_finish,
583 .buf_queue = buffer_queue,
584 .wait_prepare = vb2_ops_wait_prepare,
585 .wait_finish = vb2_ops_wait_finish,
586 .start_streaming = start_streaming,
587 .stop_streaming = stop_streaming,
588};
edbd138e 589
0b6b6302 590/* ------------------------------------------------------------------ */
1da177e4 591
0b6b6302 592static int radio_open(struct file *file)
1da177e4 593{
63b0d5ad 594 struct cx8800_dev *dev = video_drvdata(file);
5401c2db 595 struct cx88_core *core = dev->core;
0b6b6302 596 int ret = v4l2_fh_open(file);
1da177e4 597
0b6b6302
HV
598 if (ret)
599 return ret;
1da177e4 600
0b6b6302
HV
601 cx_write(MO_GP3_IO, core->board.radio.gpio3);
602 cx_write(MO_GP0_IO, core->board.radio.gpio0);
603 cx_write(MO_GP1_IO, core->board.radio.gpio1);
604 cx_write(MO_GP2_IO, core->board.radio.gpio2);
605 if (core->board.radio.audioroute) {
606 if (core->sd_wm8775) {
607 call_all(core, audio, s_routing,
399426ca 608 core->board.radio.audioroute, 0, 0);
430189da 609 }
0b6b6302
HV
610 /* "I2S ADC mode" */
611 core->tvaudio = WW_I2SADC;
612 cx88_set_tvaudio(core);
1da177e4 613 } else {
0b6b6302
HV
614 /* FM Mode */
615 core->tvaudio = WW_FM;
616 cx88_set_tvaudio(core);
617 cx88_set_stereo(core, V4L2_TUNER_MODE_STEREO, 1);
1da177e4 618 }
0b6b6302 619 call_all(core, tuner, s_radio);
1da177e4
LT
620 return 0;
621}
622
1da177e4 623/* ------------------------------------------------------------------ */
8d87cb9f 624/* VIDEO CTRL IOCTLS */
1da177e4 625
8c7cb12a
HV
626static int cx8800_s_vid_ctrl(struct v4l2_ctrl *ctrl)
627{
628 struct cx88_core *core =
629 container_of(ctrl->handler, struct cx88_core, video_hdl);
630 const struct cx88_ctrl *cc = ctrl->priv;
631 u32 value, mask;
632
633 mask = cc->mask;
634 switch (ctrl->id) {
635 case V4L2_CID_SATURATION:
636 /* special v_sat handling */
637
638 value = ((ctrl->val - cc->off) << cc->shift) & cc->mask;
639
640 if (core->tvnorm & V4L2_STD_SECAM) {
641 /* For SECAM, both U and V sat should be equal */
642 value = value << 8 | value;
643 } else {
644 /* Keeps U Saturation proportional to V Sat */
645 value = (value * 0x5a) / 0x7f << 8 | value;
646 }
647 mask = 0xffff;
648 break;
649 case V4L2_CID_SHARPNESS:
650 /* 0b000, 0b100, 0b101, 0b110, or 0b111 */
651 value = (ctrl->val < 1 ? 0 : ((ctrl->val + 3) << 7));
652 /* needs to be set for both fields */
653 cx_andor(MO_FILTER_EVEN, mask, value);
654 break;
655 case V4L2_CID_CHROMA_AGC:
656 value = ((ctrl->val - cc->off) << cc->shift) & cc->mask;
657 break;
658 default:
659 value = ((ctrl->val - cc->off) << cc->shift) & cc->mask;
660 break;
661 }
399426ca
MCC
662 dprintk(1,
663 "set_control id=0x%X(%s) ctrl=0x%02x, reg=0x%02x val=0x%02x (mask 0x%02x)%s\n",
664 ctrl->id, ctrl->name, ctrl->val, cc->reg, value,
665 mask, cc->sreg ? " [shadowed]" : "");
8c7cb12a
HV
666 if (cc->sreg)
667 cx_sandor(cc->sreg, cc->reg, mask, value);
668 else
669 cx_andor(cc->reg, mask, value);
670 return 0;
671}
672
673static int cx8800_s_aud_ctrl(struct v4l2_ctrl *ctrl)
1da177e4 674{
bac63981 675 struct cx88_core *core =
8c7cb12a 676 container_of(ctrl->handler, struct cx88_core, audio_hdl);
bac63981 677 const struct cx88_ctrl *cc = ctrl->priv;
7b61ba8f 678 u32 value, mask;
6951803c
LR
679
680 /* Pass changes onto any WM8775 */
609c4c12 681 if (core->sd_wm8775) {
bac63981 682 switch (ctrl->id) {
6951803c 683 case V4L2_CID_AUDIO_MUTE:
bac63981 684 wm8775_s_ctrl(core, ctrl->id, ctrl->val);
6951803c
LR
685 break;
686 case V4L2_CID_AUDIO_VOLUME:
bac63981
HV
687 wm8775_s_ctrl(core, ctrl->id, (ctrl->val) ?
688 (0x90 + ctrl->val) << 8 : 0);
6951803c
LR
689 break;
690 case V4L2_CID_AUDIO_BALANCE:
bac63981 691 wm8775_s_ctrl(core, ctrl->id, ctrl->val << 9);
6951803c
LR
692 break;
693 default:
6951803c
LR
694 break;
695 }
6951803c
LR
696 }
697
bac63981
HV
698 mask = cc->mask;
699 switch (ctrl->id) {
1da177e4 700 case V4L2_CID_AUDIO_BALANCE:
399426ca
MCC
701 value = (ctrl->val < 0x40) ?
702 (0x7f - ctrl->val) : (ctrl->val - 0x40);
1da177e4
LT
703 break;
704 case V4L2_CID_AUDIO_VOLUME:
bac63981 705 value = 0x3f - (ctrl->val & 0x3f);
1da177e4 706 break;
1da177e4 707 default:
bac63981 708 value = ((ctrl->val - cc->off) << cc->shift) & cc->mask;
1da177e4
LT
709 break;
710 }
399426ca
MCC
711 dprintk(1,
712 "set_control id=0x%X(%s) ctrl=0x%02x, reg=0x%02x val=0x%02x (mask 0x%02x)%s\n",
713 ctrl->id, ctrl->name, ctrl->val, cc->reg, value,
714 mask, cc->sreg ? " [shadowed]" : "");
bac63981
HV
715 if (cc->sreg)
716 cx_sandor(cc->sreg, cc->reg, mask, value);
717 else
718 cx_andor(cc->reg, mask, value);
1da177e4
LT
719 return 0;
720}
1da177e4
LT
721
722/* ------------------------------------------------------------------ */
8d87cb9f 723/* VIDEO IOCTLS */
1da177e4 724
78b526a4 725static int vidioc_g_fmt_vid_cap(struct file *file, void *priv,
399426ca 726 struct v4l2_format *f)
1da177e4 727{
0b6b6302 728 struct cx8800_dev *dev = video_drvdata(file);
ccd6f1d4 729 struct cx88_core *core = dev->core;
8d87cb9f 730
ccd6f1d4
HV
731 f->fmt.pix.width = core->width;
732 f->fmt.pix.height = core->height;
733 f->fmt.pix.field = core->field;
c5a86144 734 f->fmt.pix.pixelformat = dev->fmt->fourcc;
8d87cb9f 735 f->fmt.pix.bytesperline =
c5a86144 736 (f->fmt.pix.width * dev->fmt->depth) >> 3;
8d87cb9f
MCC
737 f->fmt.pix.sizeimage =
738 f->fmt.pix.height * f->fmt.pix.bytesperline;
c5a86144 739 f->fmt.pix.colorspace = V4L2_COLORSPACE_SMPTE170M;
8d87cb9f 740 return 0;
1da177e4
LT
741}
742
78b526a4 743static int vidioc_try_fmt_vid_cap(struct file *file, void *priv,
399426ca 744 struct v4l2_format *f)
1da177e4 745{
0b6b6302
HV
746 struct cx8800_dev *dev = video_drvdata(file);
747 struct cx88_core *core = dev->core;
2e4e98e7 748 const struct cx8800_fmt *fmt;
8d87cb9f
MCC
749 enum v4l2_field field;
750 unsigned int maxw, maxh;
e52e98a7 751
8d87cb9f 752 fmt = format_by_fourcc(f->fmt.pix.pixelformat);
399426ca 753 if (!fmt)
8d87cb9f 754 return -EINVAL;
1da177e4 755
ccd6f1d4
HV
756 maxw = norm_maxw(core->tvnorm);
757 maxh = norm_maxh(core->tvnorm);
1da177e4 758
ccd6f1d4 759 field = f->fmt.pix.field;
8d87cb9f
MCC
760
761 switch (field) {
762 case V4L2_FIELD_TOP:
763 case V4L2_FIELD_BOTTOM:
8d87cb9f 764 case V4L2_FIELD_INTERLACED:
ccd6f1d4
HV
765 case V4L2_FIELD_SEQ_BT:
766 case V4L2_FIELD_SEQ_TB:
8d87cb9f 767 break;
1da177e4 768 default:
ccd6f1d4
HV
769 field = (f->fmt.pix.height > maxh / 2)
770 ? V4L2_FIELD_INTERLACED
771 : V4L2_FIELD_BOTTOM;
772 break;
1da177e4 773 }
ccd6f1d4
HV
774 if (V4L2_FIELD_HAS_T_OR_B(field))
775 maxh /= 2;
8d87cb9f 776
4b89945e
TP
777 v4l_bound_align_image(&f->fmt.pix.width, 48, maxw, 2,
778 &f->fmt.pix.height, 32, maxh, 0, 0);
ccd6f1d4 779 f->fmt.pix.field = field;
8d87cb9f
MCC
780 f->fmt.pix.bytesperline =
781 (f->fmt.pix.width * fmt->depth) >> 3;
782 f->fmt.pix.sizeimage =
783 f->fmt.pix.height * f->fmt.pix.bytesperline;
9450684b 784 f->fmt.pix.colorspace = V4L2_COLORSPACE_SMPTE170M;
8d87cb9f
MCC
785
786 return 0;
1da177e4
LT
787}
788
78b526a4 789static int vidioc_s_fmt_vid_cap(struct file *file, void *priv,
399426ca 790 struct v4l2_format *f)
1da177e4 791{
0b6b6302 792 struct cx8800_dev *dev = video_drvdata(file);
ccd6f1d4 793 struct cx88_core *core = dev->core;
7b61ba8f 794 int err = vidioc_try_fmt_vid_cap(file, priv, f);
8d87cb9f 795
7b61ba8f 796 if (err != 0)
8d87cb9f 797 return err;
078859a3
HV
798 if (vb2_is_busy(&dev->vb2_vidq) || vb2_is_busy(&dev->vb2_vbiq))
799 return -EBUSY;
800 if (core->dvbdev && vb2_is_busy(&core->dvbdev->vb2_mpegq))
801 return -EBUSY;
ccd6f1d4
HV
802 dev->fmt = format_by_fourcc(f->fmt.pix.pixelformat);
803 core->width = f->fmt.pix.width;
804 core->height = f->fmt.pix.height;
805 core->field = f->fmt.pix.field;
8d87cb9f 806 return 0;
1da177e4
LT
807}
808
4839c58f
MCC
809int cx88_querycap(struct file *file, struct cx88_core *core,
810 struct v4l2_capability *cap)
902e197d
HV
811{
812 struct video_device *vdev = video_devdata(file);
813
814 strlcpy(cap->card, core->board.name, sizeof(cap->card));
815 cap->device_caps = V4L2_CAP_READWRITE | V4L2_CAP_STREAMING;
7b61ba8f 816 if (core->board.tuner_type != UNSET)
902e197d
HV
817 cap->device_caps |= V4L2_CAP_TUNER;
818 switch (vdev->vfl_type) {
819 case VFL_TYPE_RADIO:
820 cap->device_caps = V4L2_CAP_RADIO | V4L2_CAP_TUNER;
821 break;
822 case VFL_TYPE_GRABBER:
823 cap->device_caps |= V4L2_CAP_VIDEO_CAPTURE;
824 break;
825 case VFL_TYPE_VBI:
826 cap->device_caps |= V4L2_CAP_VBI_CAPTURE;
827 break;
4839c58f
MCC
828 default:
829 return -EINVAL;
902e197d
HV
830 }
831 cap->capabilities = cap->device_caps | V4L2_CAP_VIDEO_CAPTURE |
832 V4L2_CAP_VBI_CAPTURE | V4L2_CAP_DEVICE_CAPS;
833 if (core->board.radio.type == CX88_RADIO)
834 cap->capabilities |= V4L2_CAP_RADIO;
4839c58f 835 return 0;
902e197d
HV
836}
837EXPORT_SYMBOL(cx88_querycap);
838
839static int vidioc_querycap(struct file *file, void *priv,
399426ca 840 struct v4l2_capability *cap)
1da177e4 841{
0b6b6302
HV
842 struct cx8800_dev *dev = video_drvdata(file);
843 struct cx88_core *core = dev->core;
1da177e4 844
8d87cb9f 845 strcpy(cap->driver, "cx8800");
902e197d 846 sprintf(cap->bus_info, "PCI:%s", pci_name(dev->pci));
4839c58f 847 return cx88_querycap(file, core, cap);
8d87cb9f 848}
e52e98a7 849
7b61ba8f 850static int vidioc_enum_fmt_vid_cap(struct file *file, void *priv,
399426ca 851 struct v4l2_fmtdesc *f)
8d87cb9f
MCC
852{
853 if (unlikely(f->index >= ARRAY_SIZE(formats)))
854 return -EINVAL;
855
7b61ba8f 856 strlcpy(f->description, formats[f->index].name, sizeof(f->description));
8d87cb9f
MCC
857 f->pixelformat = formats[f->index].fourcc;
858
859 return 0;
860}
1da177e4 861
48d68801
HV
862static int vidioc_g_std(struct file *file, void *priv, v4l2_std_id *tvnorm)
863{
0b6b6302
HV
864 struct cx8800_dev *dev = video_drvdata(file);
865 struct cx88_core *core = dev->core;
48d68801
HV
866
867 *tvnorm = core->tvnorm;
868 return 0;
869}
870
314527ac 871static int vidioc_s_std(struct file *file, void *priv, v4l2_std_id tvnorms)
e52e98a7 872{
0b6b6302
HV
873 struct cx8800_dev *dev = video_drvdata(file);
874 struct cx88_core *core = dev->core;
e52e98a7 875
078859a3 876 return cx88_set_tvnorm(core, tvnorms);
8d87cb9f 877}
1da177e4 878
8d87cb9f 879/* only one input in this sample driver */
7b61ba8f 880int cx88_enum_input(struct cx88_core *core, struct v4l2_input *i)
8d87cb9f 881{
2e4e98e7 882 static const char * const iname[] = {
7b61ba8f
MCC
883 [CX88_VMUX_COMPOSITE1] = "Composite1",
884 [CX88_VMUX_COMPOSITE2] = "Composite2",
885 [CX88_VMUX_COMPOSITE3] = "Composite3",
886 [CX88_VMUX_COMPOSITE4] = "Composite4",
887 [CX88_VMUX_SVIDEO] = "S-Video",
888 [CX88_VMUX_TELEVISION] = "Television",
889 [CX88_VMUX_CABLE] = "Cable TV",
890 [CX88_VMUX_DVB] = "DVB",
891 [CX88_VMUX_DEBUG] = "for debug only",
8d87cb9f 892 };
f3334bcb 893 unsigned int n = i->index;
1da177e4 894
8d87cb9f
MCC
895 if (n >= 4)
896 return -EINVAL;
399426ca 897 if (!INPUT(n).type)
8d87cb9f 898 return -EINVAL;
8d87cb9f 899 i->type = V4L2_INPUT_TYPE_CAMERA;
7b61ba8f 900 strcpy(i->name, iname[INPUT(n).type]);
399426ca
MCC
901 if ((INPUT(n).type == CX88_VMUX_TELEVISION) ||
902 (INPUT(n).type == CX88_VMUX_CABLE))
8d87cb9f 903 i->type = V4L2_INPUT_TYPE_TUNER;
399426ca 904
f33e9868 905 i->std = CX88_NORMS;
8d87cb9f
MCC
906 return 0;
907}
54da49f5
MCC
908EXPORT_SYMBOL(cx88_enum_input);
909
7b61ba8f 910static int vidioc_enum_input(struct file *file, void *priv,
399426ca 911 struct v4l2_input *i)
54da49f5 912{
0b6b6302
HV
913 struct cx8800_dev *dev = video_drvdata(file);
914 struct cx88_core *core = dev->core;
7b61ba8f
MCC
915
916 return cx88_enum_input(core, i);
54da49f5 917}
1da177e4 918
7b61ba8f 919static int vidioc_g_input(struct file *file, void *priv, unsigned int *i)
8d87cb9f 920{
0b6b6302
HV
921 struct cx8800_dev *dev = video_drvdata(file);
922 struct cx88_core *core = dev->core;
1da177e4 923
8d87cb9f
MCC
924 *i = core->input;
925 return 0;
926}
1da177e4 927
7b61ba8f 928static int vidioc_s_input(struct file *file, void *priv, unsigned int i)
8d87cb9f 929{
0b6b6302
HV
930 struct cx8800_dev *dev = video_drvdata(file);
931 struct cx88_core *core = dev->core;
1da177e4 932
8d87cb9f
MCC
933 if (i >= 4)
934 return -EINVAL;
399426ca 935 if (!INPUT(i).type)
f33e9868 936 return -EINVAL;
1da177e4 937
8d87cb9f 938 cx88_newstation(core);
7b61ba8f 939 cx88_video_mux(core, i);
8d87cb9f
MCC
940 return 0;
941}
1da177e4 942
7b61ba8f 943static int vidioc_g_tuner(struct file *file, void *priv,
399426ca 944 struct v4l2_tuner *t)
8d87cb9f 945{
0b6b6302
HV
946 struct cx8800_dev *dev = video_drvdata(file);
947 struct cx88_core *core = dev->core;
8d87cb9f 948 u32 reg;
1da177e4 949
7b61ba8f 950 if (unlikely(core->board.tuner_type == UNSET))
8d87cb9f 951 return -EINVAL;
7b61ba8f 952 if (t->index != 0)
243d8c0f 953 return -EINVAL;
a82decf6 954
8d87cb9f 955 strcpy(t->name, "Television");
8d87cb9f
MCC
956 t->capability = V4L2_TUNER_CAP_NORM;
957 t->rangehigh = 0xffffffffUL;
f33e9868 958 call_all(core, tuner, g_tuner, t);
a82decf6 959
7b61ba8f 960 cx88_get_stereo(core, t);
8d87cb9f 961 reg = cx_read(MO_DEVICE_STATUS);
399426ca 962 t->signal = (reg & (1 << 5)) ? 0xffff : 0x0000;
8d87cb9f
MCC
963 return 0;
964}
41ef7c1e 965
7b61ba8f 966static int vidioc_s_tuner(struct file *file, void *priv,
399426ca 967 const struct v4l2_tuner *t)
8d87cb9f 968{
0b6b6302
HV
969 struct cx8800_dev *dev = video_drvdata(file);
970 struct cx88_core *core = dev->core;
41ef7c1e 971
7b61ba8f 972 if (core->board.tuner_type == UNSET)
8d87cb9f 973 return -EINVAL;
7b61ba8f 974 if (t->index != 0)
8d87cb9f 975 return -EINVAL;
c5287ba1 976
8d87cb9f
MCC
977 cx88_set_stereo(core, t->audmode, 1);
978 return 0;
979}
902fc997 980
7b61ba8f 981static int vidioc_g_frequency(struct file *file, void *priv,
399426ca 982 struct v4l2_frequency *f)
8d87cb9f 983{
0b6b6302
HV
984 struct cx8800_dev *dev = video_drvdata(file);
985 struct cx88_core *core = dev->core;
902fc997 986
7b61ba8f 987 if (unlikely(core->board.tuner_type == UNSET))
8d87cb9f 988 return -EINVAL;
f33e9868
HV
989 if (f->tuner)
990 return -EINVAL;
8d87cb9f 991
8d87cb9f
MCC
992 f->frequency = core->freq;
993
b8341e1d 994 call_all(core, tuner, g_frequency, f);
1da177e4 995
1da177e4
LT
996 return 0;
997}
998
7b61ba8f 999int cx88_set_freq(struct cx88_core *core,
399426ca 1000 const struct v4l2_frequency *f)
1da177e4 1001{
b530a447
HV
1002 struct v4l2_frequency new_freq = *f;
1003
7b61ba8f 1004 if (unlikely(core->board.tuner_type == UNSET))
8d87cb9f
MCC
1005 return -EINVAL;
1006 if (unlikely(f->tuner != 0))
1007 return -EINVAL;
54da49f5 1008
8d87cb9f 1009 cx88_newstation(core);
b8341e1d 1010 call_all(core, tuner, s_frequency, f);
b530a447
HV
1011 call_all(core, tuner, g_frequency, &new_freq);
1012 core->freq = new_freq.frequency;
c7b0ac05 1013
8d87cb9f 1014 /* When changing channels it is required to reset TVAUDIO */
7b61ba8f 1015 usleep_range(10000, 20000);
8d87cb9f 1016 cx88_set_tvaudio(core);
c7b0ac05 1017
8d87cb9f 1018 return 0;
1da177e4 1019}
54da49f5
MCC
1020EXPORT_SYMBOL(cx88_set_freq);
1021
7b61ba8f 1022static int vidioc_s_frequency(struct file *file, void *priv,
399426ca 1023 const struct v4l2_frequency *f)
54da49f5 1024{
0b6b6302
HV
1025 struct cx8800_dev *dev = video_drvdata(file);
1026 struct cx88_core *core = dev->core;
54da49f5 1027
edbd138e 1028 return cx88_set_freq(core, f);
54da49f5 1029}
1da177e4 1030
dbbff48f 1031#ifdef CONFIG_VIDEO_ADV_DEBUG
7b61ba8f 1032static int vidioc_g_register(struct file *file, void *fh,
399426ca 1033 struct v4l2_dbg_register *reg)
dbbff48f 1034{
0b6b6302
HV
1035 struct cx8800_dev *dev = video_drvdata(file);
1036 struct cx88_core *core = dev->core;
dbbff48f 1037
dbbff48f 1038 /* cx2388x has a 24-bit register space */
7feeb148 1039 reg->val = cx_read(reg->reg & 0xfffffc);
aecde8b5 1040 reg->size = 4;
dbbff48f
TP
1041 return 0;
1042}
1043
7b61ba8f 1044static int vidioc_s_register(struct file *file, void *fh,
399426ca 1045 const struct v4l2_dbg_register *reg)
dbbff48f 1046{
0b6b6302
HV
1047 struct cx8800_dev *dev = video_drvdata(file);
1048 struct cx88_core *core = dev->core;
dbbff48f 1049
7feeb148 1050 cx_write(reg->reg & 0xfffffc, reg->val);
dbbff48f
TP
1051 return 0;
1052}
1053#endif
8d87cb9f
MCC
1054
1055/* ----------------------------------------------------------- */
1056/* RADIO ESPECIFIC IOCTLS */
1da177e4
LT
1057/* ----------------------------------------------------------- */
1058
7b61ba8f 1059static int radio_g_tuner(struct file *file, void *priv,
399426ca 1060 struct v4l2_tuner *t)
8d87cb9f 1061{
0b6b6302
HV
1062 struct cx8800_dev *dev = video_drvdata(file);
1063 struct cx88_core *core = dev->core;
1da177e4 1064
8d87cb9f
MCC
1065 if (unlikely(t->index > 0))
1066 return -EINVAL;
1da177e4 1067
8d87cb9f 1068 strcpy(t->name, "Radio");
1da177e4 1069
b8341e1d 1070 call_all(core, tuner, g_tuner, t);
8d87cb9f
MCC
1071 return 0;
1072}
1da177e4 1073
7b61ba8f 1074static int radio_s_tuner(struct file *file, void *priv,
399426ca 1075 const struct v4l2_tuner *t)
8d87cb9f 1076{
0b6b6302
HV
1077 struct cx8800_dev *dev = video_drvdata(file);
1078 struct cx88_core *core = dev->core;
a82decf6 1079
7b61ba8f 1080 if (t->index != 0)
8d87cb9f 1081 return -EINVAL;
1da177e4 1082
b8341e1d 1083 call_all(core, tuner, s_tuner, t);
8d87cb9f
MCC
1084 return 0;
1085}
1da177e4 1086
1da177e4
LT
1087/* ----------------------------------------------------------- */
1088
2e4e98e7 1089static const char *cx88_vid_irqs[32] = {
41ef7c1e
MCC
1090 "y_risci1", "u_risci1", "v_risci1", "vbi_risc1",
1091 "y_risci2", "u_risci2", "v_risci2", "vbi_risc2",
1092 "y_oflow", "u_oflow", "v_oflow", "vbi_oflow",
1093 "y_sync", "u_sync", "v_sync", "vbi_sync",
1094 "opc_err", "par_err", "rip_err", "pci_abort",
1095};
1096
1da177e4
LT
1097static void cx8800_vid_irq(struct cx8800_dev *dev)
1098{
1099 struct cx88_core *core = dev->core;
1100 u32 status, mask, count;
1101
1102 status = cx_read(MO_VID_INTSTAT);
1103 mask = cx_read(MO_VID_INTMSK);
1104 if (0 == (status & mask))
1105 return;
1106 cx_write(MO_VID_INTSTAT, status);
1107 if (irq_debug || (status & mask & ~0xff))
65bc2fe8 1108 cx88_print_irqbits("irq vid",
66623a04
MCC
1109 cx88_vid_irqs, ARRAY_SIZE(cx88_vid_irqs),
1110 status, mask);
1da177e4
LT
1111
1112 /* risc op code error */
1113 if (status & (1 << 16)) {
65bc2fe8 1114 pr_warn("video risc op code error\n");
1da177e4
LT
1115 cx_clear(MO_VID_DMACNTRL, 0x11);
1116 cx_clear(VID_CAPTURE_CONTROL, 0x06);
e52e98a7 1117 cx88_sram_channel_dump(core, &cx88_sram_channels[SRAM_CH21]);
1da177e4
LT
1118 }
1119
1120 /* risc1 y */
1121 if (status & 0x01) {
1122 spin_lock(&dev->slock);
1123 count = cx_read(MO_VIDY_GPCNT);
e52e98a7 1124 cx88_wakeup(core, &dev->vidq, count);
1da177e4
LT
1125 spin_unlock(&dev->slock);
1126 }
1127
1128 /* risc1 vbi */
1129 if (status & 0x08) {
1130 spin_lock(&dev->slock);
1131 count = cx_read(MO_VBI_GPCNT);
e52e98a7 1132 cx88_wakeup(core, &dev->vbiq, count);
1da177e4
LT
1133 spin_unlock(&dev->slock);
1134 }
1da177e4
LT
1135}
1136
7d12e780 1137static irqreturn_t cx8800_irq(int irq, void *dev_id)
1da177e4
LT
1138{
1139 struct cx8800_dev *dev = dev_id;
1140 struct cx88_core *core = dev->core;
1141 u32 status;
1142 int loop, handled = 0;
1143
1144 for (loop = 0; loop < 10; loop++) {
8ddac9ee
TP
1145 status = cx_read(MO_PCI_INTSTAT) &
1146 (core->pci_irqmask | PCI_INT_VIDINT);
7b61ba8f 1147 if (status == 0)
1da177e4
LT
1148 goto out;
1149 cx_write(MO_PCI_INTSTAT, status);
1150 handled = 1;
1151
1152 if (status & core->pci_irqmask)
7b61ba8f 1153 cx88_core_irq(core, status);
8ddac9ee 1154 if (status & PCI_INT_VIDINT)
1da177e4 1155 cx8800_vid_irq(dev);
c2c1b415 1156 }
7b61ba8f 1157 if (loop == 10) {
65bc2fe8 1158 pr_warn("irq loop -- clearing mask\n");
7b61ba8f 1159 cx_write(MO_PCI_INTMSK, 0);
1da177e4
LT
1160 }
1161
1162 out:
1163 return IRQ_RETVAL(handled);
1164}
1165
1166/* ----------------------------------------------------------- */
1167/* exported stuff */
1168
7b61ba8f 1169static const struct v4l2_file_operations video_fops = {
1da177e4 1170 .owner = THIS_MODULE,
0b6b6302
HV
1171 .open = v4l2_fh_open,
1172 .release = vb2_fop_release,
1173 .read = vb2_fop_read,
1174 .poll = vb2_fop_poll,
1175 .mmap = vb2_fop_mmap,
b6187264 1176 .unlocked_ioctl = video_ioctl2,
1da177e4
LT
1177};
1178
a399810c 1179static const struct v4l2_ioctl_ops video_ioctl_ops = {
8d87cb9f 1180 .vidioc_querycap = vidioc_querycap,
78b526a4
HV
1181 .vidioc_enum_fmt_vid_cap = vidioc_enum_fmt_vid_cap,
1182 .vidioc_g_fmt_vid_cap = vidioc_g_fmt_vid_cap,
1183 .vidioc_try_fmt_vid_cap = vidioc_try_fmt_vid_cap,
1184 .vidioc_s_fmt_vid_cap = vidioc_s_fmt_vid_cap,
0b6b6302
HV
1185 .vidioc_reqbufs = vb2_ioctl_reqbufs,
1186 .vidioc_querybuf = vb2_ioctl_querybuf,
1187 .vidioc_qbuf = vb2_ioctl_qbuf,
1188 .vidioc_dqbuf = vb2_ioctl_dqbuf,
48d68801 1189 .vidioc_g_std = vidioc_g_std,
8d87cb9f
MCC
1190 .vidioc_s_std = vidioc_s_std,
1191 .vidioc_enum_input = vidioc_enum_input,
1192 .vidioc_g_input = vidioc_g_input,
1193 .vidioc_s_input = vidioc_s_input,
0b6b6302
HV
1194 .vidioc_streamon = vb2_ioctl_streamon,
1195 .vidioc_streamoff = vb2_ioctl_streamoff,
8d87cb9f
MCC
1196 .vidioc_g_tuner = vidioc_g_tuner,
1197 .vidioc_s_tuner = vidioc_s_tuner,
1198 .vidioc_g_frequency = vidioc_g_frequency,
1199 .vidioc_s_frequency = vidioc_s_frequency,
1a3c60a0
HV
1200 .vidioc_subscribe_event = v4l2_ctrl_subscribe_event,
1201 .vidioc_unsubscribe_event = v4l2_event_unsubscribe,
dbbff48f
TP
1202#ifdef CONFIG_VIDEO_ADV_DEBUG
1203 .vidioc_g_register = vidioc_g_register,
1204 .vidioc_s_register = vidioc_s_register,
1205#endif
a399810c
HV
1206};
1207
2e4e98e7 1208static const struct video_device cx8800_video_template = {
a399810c 1209 .name = "cx8800-video",
a399810c 1210 .fops = &video_fops,
7b61ba8f 1211 .ioctl_ops = &video_ioctl_ops,
63ab1bdc 1212 .tvnorms = CX88_NORMS,
1da177e4
LT
1213};
1214
f33e9868
HV
1215static const struct v4l2_ioctl_ops vbi_ioctl_ops = {
1216 .vidioc_querycap = vidioc_querycap,
1217 .vidioc_g_fmt_vbi_cap = cx8800_vbi_fmt,
1218 .vidioc_try_fmt_vbi_cap = cx8800_vbi_fmt,
1219 .vidioc_s_fmt_vbi_cap = cx8800_vbi_fmt,
0b6b6302
HV
1220 .vidioc_reqbufs = vb2_ioctl_reqbufs,
1221 .vidioc_querybuf = vb2_ioctl_querybuf,
1222 .vidioc_qbuf = vb2_ioctl_qbuf,
1223 .vidioc_dqbuf = vb2_ioctl_dqbuf,
48d68801 1224 .vidioc_g_std = vidioc_g_std,
f33e9868
HV
1225 .vidioc_s_std = vidioc_s_std,
1226 .vidioc_enum_input = vidioc_enum_input,
1227 .vidioc_g_input = vidioc_g_input,
1228 .vidioc_s_input = vidioc_s_input,
0b6b6302
HV
1229 .vidioc_streamon = vb2_ioctl_streamon,
1230 .vidioc_streamoff = vb2_ioctl_streamoff,
f33e9868
HV
1231 .vidioc_g_tuner = vidioc_g_tuner,
1232 .vidioc_s_tuner = vidioc_s_tuner,
1233 .vidioc_g_frequency = vidioc_g_frequency,
1234 .vidioc_s_frequency = vidioc_s_frequency,
f33e9868
HV
1235#ifdef CONFIG_VIDEO_ADV_DEBUG
1236 .vidioc_g_register = vidioc_g_register,
1237 .vidioc_s_register = vidioc_s_register,
1238#endif
1239};
1240
1241static const struct video_device cx8800_vbi_template = {
1242 .name = "cx8800-vbi",
1243 .fops = &video_fops,
1244 .ioctl_ops = &vbi_ioctl_ops,
1245 .tvnorms = CX88_NORMS,
f33e9868
HV
1246};
1247
7b61ba8f 1248static const struct v4l2_file_operations radio_fops = {
1da177e4 1249 .owner = THIS_MODULE,
0b6b6302 1250 .open = radio_open,
1a3c60a0 1251 .poll = v4l2_ctrl_poll,
0b6b6302 1252 .release = v4l2_fh_release,
b6187264 1253 .unlocked_ioctl = video_ioctl2,
1da177e4
LT
1254};
1255
a399810c 1256static const struct v4l2_ioctl_ops radio_ioctl_ops = {
902e197d 1257 .vidioc_querycap = vidioc_querycap,
8d87cb9f 1258 .vidioc_g_tuner = radio_g_tuner,
8d87cb9f 1259 .vidioc_s_tuner = radio_s_tuner,
8d87cb9f
MCC
1260 .vidioc_g_frequency = vidioc_g_frequency,
1261 .vidioc_s_frequency = vidioc_s_frequency,
1a3c60a0
HV
1262 .vidioc_subscribe_event = v4l2_ctrl_subscribe_event,
1263 .vidioc_unsubscribe_event = v4l2_event_unsubscribe,
a75d2048
TP
1264#ifdef CONFIG_VIDEO_ADV_DEBUG
1265 .vidioc_g_register = vidioc_g_register,
1266 .vidioc_s_register = vidioc_s_register,
1267#endif
1da177e4
LT
1268};
1269
2e4e98e7 1270static const struct video_device cx8800_radio_template = {
a399810c 1271 .name = "cx8800-radio",
a399810c 1272 .fops = &radio_fops,
7b61ba8f 1273 .ioctl_ops = &radio_ioctl_ops,
a399810c
HV
1274};
1275
8c7cb12a
HV
1276static const struct v4l2_ctrl_ops cx8800_ctrl_vid_ops = {
1277 .s_ctrl = cx8800_s_vid_ctrl,
1278};
1279
1280static const struct v4l2_ctrl_ops cx8800_ctrl_aud_ops = {
1281 .s_ctrl = cx8800_s_aud_ctrl,
bac63981
HV
1282};
1283
1da177e4
LT
1284/* ----------------------------------------------------------- */
1285
1286static void cx8800_unregister_video(struct cx8800_dev *dev)
1287{
34080bc2
HV
1288 video_unregister_device(&dev->radio_dev);
1289 video_unregister_device(&dev->vbi_dev);
1290 video_unregister_device(&dev->video_dev);
1da177e4
LT
1291}
1292
4c62e976
GKH
1293static int cx8800_initdev(struct pci_dev *pci_dev,
1294 const struct pci_device_id *pci_id)
1da177e4
LT
1295{
1296 struct cx8800_dev *dev;
1297 struct cx88_core *core;
0b6b6302 1298 struct vb2_queue *q;
1da177e4 1299 int err;
bac63981 1300 int i;
1da177e4 1301
7b61ba8f 1302 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
399426ca 1303 if (!dev)
1da177e4 1304 return -ENOMEM;
1da177e4
LT
1305
1306 /* pci init */
1307 dev->pci = pci_dev;
1308 if (pci_enable_device(pci_dev)) {
1309 err = -EIO;
1310 goto fail_free;
1311 }
1312 core = cx88_core_get(dev->pci);
399426ca 1313 if (!core) {
1da177e4
LT
1314 err = -EINVAL;
1315 goto fail_free;
1316 }
1317 dev->core = core;
1318
1319 /* print pci info */
abd34d8d 1320 dev->pci_rev = pci_dev->revision;
4ac97914 1321 pci_read_config_byte(pci_dev, PCI_LATENCY_TIMER, &dev->pci_lat);
65bc2fe8
MCC
1322 pr_info("found at %s, rev: %d, irq: %d, latency: %d, mmio: 0x%llx\n",
1323 pci_name(pci_dev), dev->pci_rev, pci_dev->irq,
1324 dev->pci_lat,
1325 (unsigned long long)pci_resource_start(pci_dev, 0));
1da177e4
LT
1326
1327 pci_set_master(pci_dev);
7b61ba8f 1328 err = pci_set_dma_mask(pci_dev, DMA_BIT_MASK(32));
1a47de6e 1329 if (err) {
65bc2fe8 1330 pr_err("Oops: no 32bit PCI DMA ???\n");
1da177e4
LT
1331 goto fail_core;
1332 }
1333
1334 /* initialize driver struct */
1da177e4 1335 spin_lock_init(&dev->slock);
1da177e4
LT
1336
1337 /* init video dma queues */
1338 INIT_LIST_HEAD(&dev->vidq.active);
1da177e4
LT
1339
1340 /* init vbi dma queues */
1341 INIT_LIST_HEAD(&dev->vbiq.active);
1da177e4
LT
1342
1343 /* get irq */
1344 err = request_irq(pci_dev->irq, cx8800_irq,
3e018fe4 1345 IRQF_SHARED, core->name, dev);
1da177e4 1346 if (err < 0) {
65bc2fe8 1347 pr_err("can't get IRQ %d\n", pci_dev->irq);
1da177e4
LT
1348 goto fail_core;
1349 }
1350 cx_set(MO_PCI_INTMSK, core->pci_irqmask);
1351
8c7cb12a
HV
1352 for (i = 0; i < CX8800_AUD_CTLS; i++) {
1353 const struct cx88_ctrl *cc = &cx8800_aud_ctls[i];
1354 struct v4l2_ctrl *vc;
1355
1356 vc = v4l2_ctrl_new_std(&core->audio_hdl, &cx8800_ctrl_aud_ops,
399426ca
MCC
1357 cc->id, cc->minimum, cc->maximum,
1358 cc->step, cc->default_value);
1359 if (!vc) {
8c7cb12a
HV
1360 err = core->audio_hdl.error;
1361 goto fail_core;
1362 }
1363 vc->priv = (void *)cc;
1364 }
1365
1366 for (i = 0; i < CX8800_VID_CTLS; i++) {
1367 const struct cx88_ctrl *cc = &cx8800_vid_ctls[i];
bac63981
HV
1368 struct v4l2_ctrl *vc;
1369
8c7cb12a 1370 vc = v4l2_ctrl_new_std(&core->video_hdl, &cx8800_ctrl_vid_ops,
399426ca
MCC
1371 cc->id, cc->minimum, cc->maximum,
1372 cc->step, cc->default_value);
1373 if (!vc) {
8c7cb12a 1374 err = core->video_hdl.error;
bac63981
HV
1375 goto fail_core;
1376 }
1377 vc->priv = (void *)cc;
8c7cb12a
HV
1378 if (vc->id == V4L2_CID_CHROMA_AGC)
1379 core->chroma_agc = vc;
bac63981 1380 }
34a6b7d0 1381 v4l2_ctrl_add_handler(&core->video_hdl, &core->audio_hdl, NULL);
bac63981 1382
1da177e4 1383 /* load and configure helper modules */
e52e98a7 1384
facd2366 1385 if (core->board.audio_chip == CX88_AUDIO_WM8775) {
6951803c
LR
1386 struct i2c_board_info wm8775_info = {
1387 .type = "wm8775",
1388 .addr = 0x36 >> 1,
1389 .platform_data = &core->wm8775_data,
1390 };
1391 struct v4l2_subdev *sd;
1392
1393 if (core->boardnr == CX88_BOARD_HAUPPAUGE_NOVASPLUS_S1)
1394 core->wm8775_data.is_nova_s = true;
1395 else
1396 core->wm8775_data.is_nova_s = false;
1397
1398 sd = v4l2_i2c_new_subdev_board(&core->v4l2_dev, &core->i2c_adap,
399426ca
MCC
1399 &wm8775_info, NULL);
1400 if (sd) {
bac63981 1401 core->sd_wm8775 = sd;
6951803c 1402 sd->grp_id = WM8775_GID;
bac63981 1403 }
6951803c 1404 }
b8341e1d 1405
facd2366 1406 if (core->board.audio_chip == CX88_AUDIO_TVAUDIO) {
399426ca
MCC
1407 /*
1408 * This probes for a tda9874 as is used on some
1409 * Pixelview Ultra boards.
1410 */
9a1f8b34 1411 v4l2_i2c_new_subdev(&core->v4l2_dev, &core->i2c_adap,
399426ca 1412 "tvaudio", 0, I2C_ADDRS(0xb0 >> 1));
b8341e1d 1413 }
3057906d 1414
6fcecce7
MK
1415 switch (core->boardnr) {
1416 case CX88_BOARD_DVICO_FUSIONHDTV_5_GOLD:
b8341e1d 1417 case CX88_BOARD_DVICO_FUSIONHDTV_7_GOLD: {
2e4e98e7 1418 static const struct i2c_board_info rtc_info = {
b8341e1d
HV
1419 I2C_BOARD_INFO("isl1208", 0x6f)
1420 };
1421
6fcecce7 1422 request_module("rtc-isl1208");
b8341e1d
HV
1423 core->i2c_rtc = i2c_new_device(&core->i2c_adap, &rtc_info);
1424 }
06eeefe8 1425 /* fall-through */
8efd2e28
MK
1426 case CX88_BOARD_DVICO_FUSIONHDTV_5_PCI_NANO:
1427 request_module("ir-kbd-i2c");
6fcecce7
MK
1428 }
1429
121ec132
MCC
1430 /* Sets device info at pci_dev */
1431 pci_set_drvdata(pci_dev, dev);
1432
ccd6f1d4 1433 dev->fmt = format_by_fourcc(V4L2_PIX_FMT_BGR24);
c5a86144 1434
078859a3
HV
1435 /* Maintain a reference so cx88-blackbird can query the 8800 device. */
1436 core->v4ldev = dev;
1437
121ec132
MCC
1438 /* initial device configuration */
1439 mutex_lock(&core->lock);
4e0973a9 1440 cx88_set_tvnorm(core, V4L2_STD_NTSC_M);
8c7cb12a
HV
1441 v4l2_ctrl_handler_setup(&core->video_hdl);
1442 v4l2_ctrl_handler_setup(&core->audio_hdl);
121ec132
MCC
1443 cx88_video_mux(core, 0);
1444
0b6b6302
HV
1445 q = &dev->vb2_vidq;
1446 q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
1447 q->io_modes = VB2_MMAP | VB2_USERPTR | VB2_DMABUF | VB2_READ;
1448 q->gfp_flags = GFP_DMA32;
1449 q->min_buffers_needed = 2;
1450 q->drv_priv = dev;
1451 q->buf_struct_size = sizeof(struct cx88_buffer);
1452 q->ops = &cx8800_video_qops;
1453 q->mem_ops = &vb2_dma_sg_memops;
1454 q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
1455 q->lock = &core->lock;
2bc46b3a 1456 q->dev = &dev->pci->dev;
0b6b6302
HV
1457
1458 err = vb2_queue_init(q);
1459 if (err < 0)
1460 goto fail_unreg;
1461
1462 q = &dev->vb2_vbiq;
1463 q->type = V4L2_BUF_TYPE_VBI_CAPTURE;
1464 q->io_modes = VB2_MMAP | VB2_USERPTR | VB2_DMABUF | VB2_READ;
1465 q->gfp_flags = GFP_DMA32;
1466 q->min_buffers_needed = 2;
1467 q->drv_priv = dev;
1468 q->buf_struct_size = sizeof(struct cx88_buffer);
1469 q->ops = &cx8800_vbi_qops;
1470 q->mem_ops = &vb2_dma_sg_memops;
1471 q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
1472 q->lock = &core->lock;
2bc46b3a 1473 q->dev = &dev->pci->dev;
0b6b6302
HV
1474
1475 err = vb2_queue_init(q);
1476 if (err < 0)
1477 goto fail_unreg;
1478
1da177e4 1479 /* register v4l devices */
34080bc2
HV
1480 cx88_vdev_init(core, dev->pci, &dev->video_dev,
1481 &cx8800_video_template, "video");
1482 video_set_drvdata(&dev->video_dev, dev);
1483 dev->video_dev.ctrl_handler = &core->video_hdl;
1484 dev->video_dev.queue = &dev->vb2_vidq;
1485 err = video_register_device(&dev->video_dev, VFL_TYPE_GRABBER,
1da177e4
LT
1486 video_nr[core->nr]);
1487 if (err < 0) {
65bc2fe8 1488 pr_err("can't register video device\n");
1da177e4
LT
1489 goto fail_unreg;
1490 }
65bc2fe8
MCC
1491 pr_info("registered device %s [v4l2]\n",
1492 video_device_node_name(&dev->video_dev));
1da177e4 1493
34080bc2
HV
1494 cx88_vdev_init(core, dev->pci, &dev->vbi_dev,
1495 &cx8800_vbi_template, "vbi");
1496 video_set_drvdata(&dev->vbi_dev, dev);
1497 dev->vbi_dev.queue = &dev->vb2_vbiq;
1498 err = video_register_device(&dev->vbi_dev, VFL_TYPE_VBI,
1da177e4
LT
1499 vbi_nr[core->nr]);
1500 if (err < 0) {
65bc2fe8 1501 pr_err("can't register vbi device\n");
1da177e4
LT
1502 goto fail_unreg;
1503 }
65bc2fe8
MCC
1504 pr_info("registered device %s\n",
1505 video_device_node_name(&dev->vbi_dev));
1da177e4 1506
6a59d64c 1507 if (core->board.radio.type == CX88_RADIO) {
34080bc2
HV
1508 cx88_vdev_init(core, dev->pci, &dev->radio_dev,
1509 &cx8800_radio_template, "radio");
1510 video_set_drvdata(&dev->radio_dev, dev);
1511 dev->radio_dev.ctrl_handler = &core->audio_hdl;
1512 err = video_register_device(&dev->radio_dev, VFL_TYPE_RADIO,
1da177e4
LT
1513 radio_nr[core->nr]);
1514 if (err < 0) {
65bc2fe8 1515 pr_err("can't register radio device\n");
1da177e4
LT
1516 goto fail_unreg;
1517 }
65bc2fe8
MCC
1518 pr_info("registered device %s\n",
1519 video_device_node_name(&dev->radio_dev));
1da177e4
LT
1520 }
1521
1da177e4 1522 /* start tvaudio thread */
c39ba330 1523 if (core->board.tuner_type != UNSET) {
399426ca
MCC
1524 core->kthread = kthread_run(cx88_audio_thread,
1525 core, "cx88 tvaudio");
32b78de7
CG
1526 if (IS_ERR(core->kthread)) {
1527 err = PTR_ERR(core->kthread);
65bc2fe8
MCC
1528 pr_err("failed to create cx88 audio thread, err=%d\n",
1529 err);
32b78de7
CG
1530 }
1531 }
121ec132
MCC
1532 mutex_unlock(&core->lock);
1533
1da177e4
LT
1534 return 0;
1535
1536fail_unreg:
1537 cx8800_unregister_video(dev);
1538 free_irq(pci_dev->irq, dev);
121ec132 1539 mutex_unlock(&core->lock);
1da177e4 1540fail_core:
078859a3 1541 core->v4ldev = NULL;
7b61ba8f 1542 cx88_core_put(core, dev->pci);
1da177e4
LT
1543fail_free:
1544 kfree(dev);
1545 return err;
1546}
1547
4c62e976 1548static void cx8800_finidev(struct pci_dev *pci_dev)
1da177e4 1549{
4ac97914 1550 struct cx8800_dev *dev = pci_get_drvdata(pci_dev);
e52e98a7 1551 struct cx88_core *core = dev->core;
1da177e4
LT
1552
1553 /* stop thread */
e52e98a7
MCC
1554 if (core->kthread) {
1555 kthread_stop(core->kthread);
1556 core->kthread = NULL;
1da177e4
LT
1557 }
1558
b12203d2 1559 if (core->ir)
92f4fc10 1560 cx88_ir_stop(core);
b12203d2 1561
e52e98a7 1562 cx88_shutdown(core); /* FIXME */
1da177e4
LT
1563
1564 /* unregister stuff */
1565
1566 free_irq(pci_dev->irq, dev);
1567 cx8800_unregister_video(dev);
98822de9 1568 pci_disable_device(pci_dev);
1da177e4 1569
078859a3
HV
1570 core->v4ldev = NULL;
1571
1da177e4 1572 /* free memory */
7b61ba8f 1573 cx88_core_put(core, dev->pci);
1da177e4
LT
1574 kfree(dev);
1575}
1576
17bc98a4 1577#ifdef CONFIG_PM
1da177e4
LT
1578static int cx8800_suspend(struct pci_dev *pci_dev, pm_message_t state)
1579{
b45009b0 1580 struct cx8800_dev *dev = pci_get_drvdata(pci_dev);
1da177e4 1581 struct cx88_core *core = dev->core;
5ddfbbb9 1582 unsigned long flags;
1da177e4
LT
1583
1584 /* stop video+vbi capture */
5ddfbbb9 1585 spin_lock_irqsave(&dev->slock, flags);
1da177e4 1586 if (!list_empty(&dev->vidq.active)) {
65bc2fe8 1587 pr_info("suspend video\n");
1da177e4 1588 stop_video_dma(dev);
1da177e4
LT
1589 }
1590 if (!list_empty(&dev->vbiq.active)) {
65bc2fe8 1591 pr_info("suspend vbi\n");
1da177e4 1592 cx8800_stop_vbi_dma(dev);
1da177e4 1593 }
5ddfbbb9 1594 spin_unlock_irqrestore(&dev->slock, flags);
1da177e4 1595
13595a51 1596 if (core->ir)
92f4fc10 1597 cx88_ir_stop(core);
1da177e4 1598 /* FIXME -- shutdown device */
e52e98a7 1599 cx88_shutdown(core);
1da177e4
LT
1600
1601 pci_save_state(pci_dev);
399426ca
MCC
1602 if (pci_set_power_state(pci_dev,
1603 pci_choose_state(pci_dev, state)) != 0) {
1da177e4
LT
1604 pci_disable_device(pci_dev);
1605 dev->state.disabled = 1;
1606 }
1607 return 0;
1608}
1609
1610static int cx8800_resume(struct pci_dev *pci_dev)
1611{
b45009b0 1612 struct cx8800_dev *dev = pci_get_drvdata(pci_dev);
1da177e4 1613 struct cx88_core *core = dev->core;
5ddfbbb9 1614 unsigned long flags;
08adb9e2 1615 int err;
1da177e4
LT
1616
1617 if (dev->state.disabled) {
7b61ba8f 1618 err = pci_enable_device(pci_dev);
08adb9e2 1619 if (err) {
65bc2fe8 1620 pr_err("can't enable device\n");
08adb9e2
MCC
1621 return err;
1622 }
1623
1da177e4
LT
1624 dev->state.disabled = 0;
1625 }
7b61ba8f 1626 err = pci_set_power_state(pci_dev, PCI_D0);
08adb9e2 1627 if (err) {
65bc2fe8 1628 pr_err("can't set power state\n");
08adb9e2
MCC
1629 pci_disable_device(pci_dev);
1630 dev->state.disabled = 1;
1631
1632 return err;
1633 }
1da177e4
LT
1634 pci_restore_state(pci_dev);
1635
1da177e4 1636 /* FIXME: re-initialize hardware */
e52e98a7 1637 cx88_reset(core);
13595a51 1638 if (core->ir)
92f4fc10 1639 cx88_ir_start(core);
13595a51
MCC
1640
1641 cx_set(MO_PCI_INTMSK, core->pci_irqmask);
1da177e4
LT
1642
1643 /* restart video+vbi capture */
5ddfbbb9 1644 spin_lock_irqsave(&dev->slock, flags);
1da177e4 1645 if (!list_empty(&dev->vidq.active)) {
65bc2fe8 1646 pr_info("resume video\n");
7b61ba8f 1647 restart_video_queue(dev, &dev->vidq);
1da177e4
LT
1648 }
1649 if (!list_empty(&dev->vbiq.active)) {
65bc2fe8 1650 pr_info("resume vbi\n");
7b61ba8f 1651 cx8800_restart_vbi_queue(dev, &dev->vbiq);
1da177e4 1652 }
5ddfbbb9 1653 spin_unlock_irqrestore(&dev->slock, flags);
1da177e4
LT
1654
1655 return 0;
1656}
17bc98a4 1657#endif
1da177e4
LT
1658
1659/* ----------------------------------------------------------- */
1660
2e4e98e7 1661static const struct pci_device_id cx8800_pci_tbl[] = {
1da177e4
LT
1662 {
1663 .vendor = 0x14f1,
1664 .device = 0x8800,
b45009b0
MCC
1665 .subvendor = PCI_ANY_ID,
1666 .subdevice = PCI_ANY_ID,
7b61ba8f 1667 }, {
1da177e4
LT
1668 /* --- end of list --- */
1669 }
1670};
1671MODULE_DEVICE_TABLE(pci, cx8800_pci_tbl);
1672
1673static struct pci_driver cx8800_pci_driver = {
b45009b0
MCC
1674 .name = "cx8800",
1675 .id_table = cx8800_pci_tbl,
1676 .probe = cx8800_initdev,
4c62e976 1677 .remove = cx8800_finidev,
17bc98a4 1678#ifdef CONFIG_PM
1da177e4
LT
1679 .suspend = cx8800_suspend,
1680 .resume = cx8800_resume,
17bc98a4 1681#endif
1da177e4
LT
1682};
1683
06333e0a 1684module_pci_driver(cx8800_pci_driver);