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[media] cx18: remove deprecated IRQF_DISABLED
[mirror_ubuntu-hirsute-kernel.git] / drivers / media / pci / cx88 / cx88-video.c
CommitLineData
1da177e4 1/*
1da177e4
LT		 2 *
3 * device driver for Conexant 2388x based TV cards
4 * video4linux video interface
5 *
6 * (c) 2003-04 Gerd Knorr <kraxel@bytesex.org> [SuSE Labs]
7 *
8d87cb9f
MCC		 8 * (c) 2005-2006 Mauro Carvalho Chehab <mchehab@infradead.org>
9 * - Multituner support
10 * - video_ioctl2 conversion
11 * - PAL/M fixes
12 *
1da177e4
LT		 13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
26 */
27
28#include <linux/init.h>
29#include <linux/list.h>
30#include <linux/module.h>
1da177e4
LT		 31#include <linux/kmod.h>
32#include <linux/kernel.h>
33#include <linux/slab.h>
34#include <linux/interrupt.h>
c24228da 35#include <linux/dma-mapping.h>
1da177e4
LT		 36#include <linux/delay.h>
37#include <linux/kthread.h>
38#include <asm/div64.h>
39
40#include "cx88.h"
5e453dc7 41#include <media/v4l2-common.h>
35ea11ff 42#include <media/v4l2-ioctl.h>
1a3c60a0 43#include <media/v4l2-event.h>
6951803c 44#include <media/wm8775.h>
1da177e4
LT		 45
46MODULE_DESCRIPTION("v4l2 driver module for cx2388x based TV cards");
47MODULE_AUTHOR("Gerd Knorr <kraxel@bytesex.org> [SuSE Labs]");
48MODULE_LICENSE("GPL");
1990d50b 49MODULE_VERSION(CX88_VERSION);
1da177e4
LT		 50
51/* ------------------------------------------------------------------ */
52
53static unsigned int video_nr[] = {[0 ... (CX88_MAXBOARDS - 1)] = UNSET };
54static unsigned int vbi_nr[] = {[0 ... (CX88_MAXBOARDS - 1)] = UNSET };
55static unsigned int radio_nr[] = {[0 ... (CX88_MAXBOARDS - 1)] = UNSET };
56
57module_param_array(video_nr, int, NULL, 0444);
58module_param_array(vbi_nr, int, NULL, 0444);
59module_param_array(radio_nr, int, NULL, 0444);
60
61MODULE_PARM_DESC(video_nr,"video device numbers");
62MODULE_PARM_DESC(vbi_nr,"vbi device numbers");
63MODULE_PARM_DESC(radio_nr,"radio device numbers");
64
ff699e6b 65static unsigned int video_debug;
1da177e4
LT		 66module_param(video_debug,int,0644);
67MODULE_PARM_DESC(video_debug,"enable debug messages [video]");
68
ff699e6b 69static unsigned int irq_debug;
1da177e4
LT		 70module_param(irq_debug,int,0644);
71MODULE_PARM_DESC(irq_debug,"enable debug messages [IRQ handler]");
72
73static unsigned int vid_limit = 16;
74module_param(vid_limit,int,0644);
75MODULE_PARM_DESC(vid_limit,"capture memory limit in megabytes");
76
77#define dprintk(level,fmt, arg...) if (video_debug >= level) \
e52e98a7 78 printk(KERN_DEBUG "%s/0: " fmt, core->name , ## arg)
1da177e4 79
1da177e4
LT		 80/* ------------------------------------------------------------------- */
81/* static data */
82
2e4e98e7 83static const struct cx8800_fmt formats[] = {
1da177e4
LT		 84 {
85 .name = "8 bpp, gray",
86 .fourcc = V4L2_PIX_FMT_GREY,
87 .cxformat = ColorFormatY8,
88 .depth = 8,
89 .flags = FORMAT_FLAGS_PACKED,
90 },{
91 .name = "15 bpp RGB, le",
92 .fourcc = V4L2_PIX_FMT_RGB555,
93 .cxformat = ColorFormatRGB15,
94 .depth = 16,
95 .flags = FORMAT_FLAGS_PACKED,
96 },{
97 .name = "15 bpp RGB, be",
98 .fourcc = V4L2_PIX_FMT_RGB555X,
99 .cxformat = ColorFormatRGB15 | ColorFormatBSWAP,
100 .depth = 16,
101 .flags = FORMAT_FLAGS_PACKED,
102 },{
103 .name = "16 bpp RGB, le",
104 .fourcc = V4L2_PIX_FMT_RGB565,
105 .cxformat = ColorFormatRGB16,
106 .depth = 16,
107 .flags = FORMAT_FLAGS_PACKED,
108 },{
109 .name = "16 bpp RGB, be",
110 .fourcc = V4L2_PIX_FMT_RGB565X,
111 .cxformat = ColorFormatRGB16 | ColorFormatBSWAP,
112 .depth = 16,
113 .flags = FORMAT_FLAGS_PACKED,
114 },{
115 .name = "24 bpp RGB, le",
116 .fourcc = V4L2_PIX_FMT_BGR24,
117 .cxformat = ColorFormatRGB24,
118 .depth = 24,
119 .flags = FORMAT_FLAGS_PACKED,
120 },{
121 .name = "32 bpp RGB, le",
122 .fourcc = V4L2_PIX_FMT_BGR32,
123 .cxformat = ColorFormatRGB32,
124 .depth = 32,
125 .flags = FORMAT_FLAGS_PACKED,
126 },{
127 .name = "32 bpp RGB, be",
128 .fourcc = V4L2_PIX_FMT_RGB32,
129 .cxformat = ColorFormatRGB32 | ColorFormatBSWAP | ColorFormatWSWAP,
130 .depth = 32,
131 .flags = FORMAT_FLAGS_PACKED,
132 },{
133 .name = "4:2:2, packed, YUYV",
134 .fourcc = V4L2_PIX_FMT_YUYV,
135 .cxformat = ColorFormatYUY2,
136 .depth = 16,
137 .flags = FORMAT_FLAGS_PACKED,
138 },{
139 .name = "4:2:2, packed, UYVY",
140 .fourcc = V4L2_PIX_FMT_UYVY,
141 .cxformat = ColorFormatYUY2 | ColorFormatBSWAP,
142 .depth = 16,
143 .flags = FORMAT_FLAGS_PACKED,
144 },
145};
146
2e4e98e7 147static const struct cx8800_fmt* format_by_fourcc(unsigned int fourcc)
1da177e4
LT		 148{
149 unsigned int i;
150
151 for (i = 0; i < ARRAY_SIZE(formats); i++)
152 if (formats[i].fourcc == fourcc)
153 return formats+i;
154 return NULL;
155}
156
157/* ------------------------------------------------------------------- */
158
bac63981
HV		 159struct cx88_ctrl {
160 /* control information */
161 u32 id;
162 s32 minimum;
163 s32 maximum;
164 u32 step;
165 s32 default_value;
166
167 /* control register information */
168 u32 off;
169 u32 reg;
170 u32 sreg;
171 u32 mask;
172 u32 shift;
173};
174
8c7cb12a 175static const struct cx88_ctrl cx8800_vid_ctls[] = {
1da177e4
LT		 176 /* --- video --- */
177 {
bac63981
HV		 178 .id = V4L2_CID_BRIGHTNESS,
179 .minimum = 0x00,
180 .maximum = 0xff,
181 .step = 1,
182 .default_value = 0x7f,
183 .off = 128,
184 .reg = MO_CONTR_BRIGHT,
185 .mask = 0x00ff,
186 .shift = 0,
1da177e4 187 },{
bac63981
HV		 188 .id = V4L2_CID_CONTRAST,
189 .minimum = 0,
190 .maximum = 0xff,
191 .step = 1,
192 .default_value = 0x3f,
193 .off = 0,
194 .reg = MO_CONTR_BRIGHT,
195 .mask = 0xff00,
196 .shift = 8,
1da177e4 197 },{
bac63981
HV		 198 .id = V4L2_CID_HUE,
199 .minimum = 0,
200 .maximum = 0xff,
201 .step = 1,
202 .default_value = 0x7f,
203 .off = 128,
204 .reg = MO_HUE,
205 .mask = 0x00ff,
206 .shift = 0,
1da177e4
LT		 207 },{
208 /* strictly, this only describes only U saturation.
209 * V saturation is handled specially through code.
210 */
bac63981
HV		 211 .id = V4L2_CID_SATURATION,
212 .minimum = 0,
213 .maximum = 0xff,
214 .step = 1,
215 .default_value = 0x7f,
216 .off = 0,
217 .reg = MO_UV_SATURATION,
218 .mask = 0x00ff,
219 .shift = 0,
eea16e36 220 }, {
bac63981
HV		 221 .id = V4L2_CID_SHARPNESS,
222 .minimum = 0,
223 .maximum = 4,
224 .step = 1,
225 .default_value = 0x0,
226 .off = 0,
eea16e36 227 /* NOTE: the value is converted and written to both even
228 and odd registers in the code */
bac63981
HV		 229 .reg = MO_FILTER_ODD,
230 .mask = 7 << 7,
231 .shift = 7,
eea16e36 232 }, {
bac63981
HV		 233 .id = V4L2_CID_CHROMA_AGC,
234 .minimum = 0,
235 .maximum = 1,
236 .default_value = 0x1,
237 .reg = MO_INPUT_FORMAT,
238 .mask = 1 << 10,
239 .shift = 10,
1b879c43 240 }, {
bac63981
HV		 241 .id = V4L2_CID_COLOR_KILLER,
242 .minimum = 0,
243 .maximum = 1,
244 .default_value = 0x1,
245 .reg = MO_INPUT_FORMAT,
246 .mask = 1 << 9,
247 .shift = 9,
bded70d2 248 }, {
bac63981
HV		 249 .id = V4L2_CID_BAND_STOP_FILTER,
250 .minimum = 0,
251 .maximum = 1,
252 .step = 1,
253 .default_value = 0x0,
254 .off = 0,
255 .reg = MO_HTOTAL,
256 .mask = 3 << 11,
257 .shift = 11,
8c7cb12a
HV		 258 }
259};
260
261static const struct cx88_ctrl cx8800_aud_ctls[] = {
262 {
bac63981
HV		 263 /* --- audio --- */
264 .id = V4L2_CID_AUDIO_MUTE,
265 .minimum = 0,
266 .maximum = 1,
267 .default_value = 1,
268 .reg = AUD_VOL_CTL,
269 .sreg = SHADOW_AUD_VOL_CTL,
270 .mask = (1 << 6),
271 .shift = 6,
1da177e4 272 },{
bac63981
HV		 273 .id = V4L2_CID_AUDIO_VOLUME,
274 .minimum = 0,
275 .maximum = 0x3f,
276 .step = 1,
277 .default_value = 0x3f,
278 .reg = AUD_VOL_CTL,
279 .sreg = SHADOW_AUD_VOL_CTL,
280 .mask = 0x3f,
281 .shift = 0,
1da177e4 282 },{
bac63981
HV		 283 .id = V4L2_CID_AUDIO_BALANCE,
284 .minimum = 0,
285 .maximum = 0x7f,
286 .step = 1,
287 .default_value = 0x40,
288 .reg = AUD_BAL_CTL,
289 .sreg = SHADOW_AUD_BAL_CTL,
290 .mask = 0x7f,
291 .shift = 0,
1da177e4
LT		 292 }
293};
1da177e4 294
8c7cb12a
HV		 295enum {
296 CX8800_VID_CTLS = ARRAY_SIZE(cx8800_vid_ctls),
297 CX8800_AUD_CTLS = ARRAY_SIZE(cx8800_aud_ctls),
298};
38a2713a 299
1da177e4
LT		 300/* ------------------------------------------------------------------- */
301/* resource management */
302
303static int res_get(struct cx8800_dev *dev, struct cx8800_fh *fh, unsigned int bit)
304{
e52e98a7 305 struct cx88_core *core = dev->core;
1da177e4
LT		 306 if (fh->resources & bit)
307 /* have it already allocated */
308 return 1;
309
310 /* is it free? */
3593cab5 311 mutex_lock(&core->lock);
1da177e4
LT		 312 if (dev->resources & bit) {
313 /* no, someone else uses it */
3593cab5 314 mutex_unlock(&core->lock);
1da177e4
LT		 315 return 0;
316 }
317 /* it's free, grab it */
318 fh->resources |= bit;
319 dev->resources |= bit;
320 dprintk(1,"res: get %d\n",bit);
3593cab5 321 mutex_unlock(&core->lock);
1da177e4
LT		 322 return 1;
323}
324
325static
326int res_check(struct cx8800_fh *fh, unsigned int bit)
327{
328 return (fh->resources & bit);
329}
330
331static
332int res_locked(struct cx8800_dev *dev, unsigned int bit)
333{
334 return (dev->resources & bit);
335}
336
337static
338void res_free(struct cx8800_dev *dev, struct cx8800_fh *fh, unsigned int bits)
339{
e52e98a7 340 struct cx88_core *core = dev->core;
ae24601b 341 BUG_ON((fh->resources & bits) != bits);
1da177e4 342
3593cab5 343 mutex_lock(&core->lock);
1da177e4
LT		 344 fh->resources &= ~bits;
345 dev->resources &= ~bits;
346 dprintk(1,"res: put %d\n",bits);
3593cab5 347 mutex_unlock(&core->lock);
1da177e4
LT		 348}
349
350/* ------------------------------------------------------------------ */
351
e90311a1 352int cx88_video_mux(struct cx88_core *core, unsigned int input)
1da177e4 353{
e52e98a7 354 /* struct cx88_core *core = dev->core; */
1da177e4
LT		 355
356 dprintk(1,"video_mux: %d [vmux=%d,gpio=0x%x,0x%x,0x%x,0x%x]\n",
6a59d64c
TP		 357 input, INPUT(input).vmux,
358 INPUT(input).gpio0,INPUT(input).gpio1,
359 INPUT(input).gpio2,INPUT(input).gpio3);
e52e98a7 360 core->input = input;
6a59d64c
TP		 361 cx_andor(MO_INPUT_FORMAT, 0x03 << 14, INPUT(input).vmux << 14);
362 cx_write(MO_GP3_IO, INPUT(input).gpio3);
363 cx_write(MO_GP0_IO, INPUT(input).gpio0);
364 cx_write(MO_GP1_IO, INPUT(input).gpio1);
365 cx_write(MO_GP2_IO, INPUT(input).gpio2);
1da177e4 366
6a59d64c 367 switch (INPUT(input).type) {
1da177e4
LT		 368 case CX88_VMUX_SVIDEO:
369 cx_set(MO_AFECFG_IO, 0x00000001);
370 cx_set(MO_INPUT_FORMAT, 0x00010010);
371 cx_set(MO_FILTER_EVEN, 0x00002020);
372 cx_set(MO_FILTER_ODD, 0x00002020);
373 break;
374 default:
375 cx_clear(MO_AFECFG_IO, 0x00000001);
376 cx_clear(MO_INPUT_FORMAT, 0x00010010);
377 cx_clear(MO_FILTER_EVEN, 0x00002020);
378 cx_clear(MO_FILTER_ODD, 0x00002020);
379 break;
380 }
f24546a9 381
66e6fbdf
RC		 382 /* if there are audioroutes defined, we have an external
383 ADC to deal with audio */
66e6fbdf 384 if (INPUT(input).audioroute) {
66e6fbdf
RC		 385 /* The wm8775 module has the "2" route hardwired into
386 the initialization. Some boards may use different
387 routes for different inputs. HVR-1300 surely does */
609c4c12 388 if (core->sd_wm8775) {
5325b427 389 call_all(core, audio, s_routing,
6e1f4df7 390 INPUT(input).audioroute, 0, 0);
66e6fbdf 391 }
430189da
DB		 392 /* cx2388's C-ADC is connected to the tuner only.
393 When used with S-Video, that ADC is busy dealing with
394 chroma, so an external must be used for baseband audio */
6e1f4df7 395 if (INPUT(input).type != CX88_VMUX_TELEVISION &&
396 INPUT(input).type != CX88_VMUX_CABLE) {
430189da
DB		 397 /* "I2S ADC mode" */
398 core->tvaudio = WW_I2SADC;
399 cx88_set_tvaudio(core);
400 } else {
401 /* Normal mode */
402 cx_write(AUD_I2SCNTL, 0x0);
403 cx_clear(AUD_CTL, EN_I2SIN_ENABLE);
404 }
f24546a9 405 }
66e6fbdf 406
1da177e4
LT		 407 return 0;
408}
e90311a1 409EXPORT_SYMBOL(cx88_video_mux);
1da177e4
LT		 410
411/* ------------------------------------------------------------------ */
412
413static int start_video_dma(struct cx8800_dev *dev,
414 struct cx88_dmaqueue *q,
415 struct cx88_buffer *buf)
416{
417 struct cx88_core *core = dev->core;
418
419 /* setup fifo + format */
e52e98a7 420 cx88_sram_channel_setup(core, &cx88_sram_channels[SRAM_CH21],
1da177e4 421 buf->bpl, buf->risc.dma);
e52e98a7 422 cx88_set_scale(core, buf->vb.width, buf->vb.height, buf->vb.field);
1da177e4
LT		 423 cx_write(MO_COLOR_CTRL, buf->fmt->cxformat | ColorFormatGamma);
424
425 /* reset counter */
426 cx_write(MO_VIDY_GPCNTRL,GP_COUNT_CONTROL_RESET);
427 q->count = 1;
428
429 /* enable irqs */
8ddac9ee 430 cx_set(MO_PCI_INTMSK, core->pci_irqmask | PCI_INT_VIDINT);
e52e98a7
MCC		 431
432 /* Enables corresponding bits at PCI_INT_STAT:
433 bits 0 to 4: video, audio, transport stream, VIP, Host
434 bit 7: timer
435 bits 8 and 9: DMA complete for: SRC, DST
436 bits 10 and 11: BERR signal asserted for RISC: RD, WR
437 bits 12 to 15: BERR signal asserted for: BRDG, SRC, DST, IPB
438 */
1da177e4
LT		 439 cx_set(MO_VID_INTMSK, 0x0f0011);
440
441 /* enable capture */
442 cx_set(VID_CAPTURE_CONTROL,0x06);
443
444 /* start dma */
445 cx_set(MO_DEV_CNTRL2, (1<<5));
e52e98a7 446 cx_set(MO_VID_DMACNTRL, 0x11); /* Planar Y and packed FIFO and RISC enable */
1da177e4
LT		 447
448 return 0;
449}
450
17bc98a4 451#ifdef CONFIG_PM
1da177e4
LT		 452static int stop_video_dma(struct cx8800_dev *dev)
453{
454 struct cx88_core *core = dev->core;
455
456 /* stop dma */
457 cx_clear(MO_VID_DMACNTRL, 0x11);
458
459 /* disable capture */
460 cx_clear(VID_CAPTURE_CONTROL,0x06);
461
462 /* disable irqs */
8ddac9ee 463 cx_clear(MO_PCI_INTMSK, PCI_INT_VIDINT);
1da177e4
LT		 464 cx_clear(MO_VID_INTMSK, 0x0f0011);
465 return 0;
466}
17bc98a4 467#endif
1da177e4
LT		 468
469static int restart_video_queue(struct cx8800_dev *dev,
470 struct cx88_dmaqueue *q)
471{
e52e98a7 472 struct cx88_core *core = dev->core;
1da177e4 473 struct cx88_buffer *buf, *prev;
1da177e4
LT		 474
475 if (!list_empty(&q->active)) {
4ac97914 476 buf = list_entry(q->active.next, struct cx88_buffer, vb.queue);
1da177e4
LT		 477 dprintk(2,"restart_queue [%p/%d]: restart dma\n",
478 buf, buf->vb.i);
479 start_video_dma(dev, q, buf);
8bb629e2
TP		 480 list_for_each_entry(buf, &q->active, vb.queue)
481 buf->count = q->count++;
1da177e4
LT		 482 mod_timer(&q->timeout, jiffies+BUFFER_TIMEOUT);
483 return 0;
484 }
485
486 prev = NULL;
487 for (;;) {
488 if (list_empty(&q->queued))
489 return 0;
4ac97914 490 buf = list_entry(q->queued.next, struct cx88_buffer, vb.queue);
1da177e4 491 if (NULL == prev) {
179e0917 492 list_move_tail(&buf->vb.queue, &q->active);
1da177e4 493 start_video_dma(dev, q, buf);
0fc0686e 494 buf->vb.state = VIDEOBUF_ACTIVE;
1da177e4
LT		 495 buf->count = q->count++;
496 mod_timer(&q->timeout, jiffies+BUFFER_TIMEOUT);
497 dprintk(2,"[%p/%d] restart_queue - first active\n",
498 buf,buf->vb.i);
499
500 } else if (prev->vb.width == buf->vb.width &&
501 prev->vb.height == buf->vb.height &&
502 prev->fmt == buf->fmt) {
179e0917 503 list_move_tail(&buf->vb.queue, &q->active);
0fc0686e 504 buf->vb.state = VIDEOBUF_ACTIVE;
1da177e4
LT		 505 buf->count = q->count++;
506 prev->risc.jmp[1] = cpu_to_le32(buf->risc.dma);
507 dprintk(2,"[%p/%d] restart_queue - move to active\n",
508 buf,buf->vb.i);
509 } else {
510 return 0;
511 }
512 prev = buf;
513 }
514}
515
516/* ------------------------------------------------------------------ */
517
518static int
519buffer_setup(struct videobuf_queue *q, unsigned int *count, unsigned int *size)
520{
521 struct cx8800_fh *fh = q->priv_data;
c5a86144 522 struct cx8800_dev *dev = fh->dev;
1da177e4 523
c5a86144 524 *size = dev->fmt->depth * dev->width * dev->height >> 3;
1da177e4
LT		 525 if (0 == *count)
526 *count = 32;
dab7e310
AB		 527 if (*size * *count > vid_limit * 1024 * 1024)
528 *count = (vid_limit * 1024 * 1024) / *size;
1da177e4
LT		 529 return 0;
530}
531
532static int
533buffer_prepare(struct videobuf_queue *q, struct videobuf_buffer *vb,
534 enum v4l2_field field)
535{
536 struct cx8800_fh *fh = q->priv_data;
537 struct cx8800_dev *dev = fh->dev;
e52e98a7 538 struct cx88_core *core = dev->core;
1da177e4 539 struct cx88_buffer *buf = container_of(vb,struct cx88_buffer,vb);
c1accaa2 540 struct videobuf_dmabuf *dma=videobuf_to_dma(&buf->vb);
1da177e4
LT		 541 int rc, init_buffer = 0;
542
c5a86144
HV		 543 BUG_ON(NULL == dev->fmt);
544 if (dev->width < 48 || dev->width > norm_maxw(core->tvnorm) ||
545 dev->height < 32 || dev->height > norm_maxh(core->tvnorm))
1da177e4 546 return -EINVAL;
c5a86144 547 buf->vb.size = (dev->width * dev->height * dev->fmt->depth) >> 3;
1da177e4
LT		 548 if (0 != buf->vb.baddr && buf->vb.bsize < buf->vb.size)
549 return -EINVAL;
550
c5a86144
HV		 551 if (buf->fmt != dev->fmt ||
552 buf->vb.width != dev->width ||
553 buf->vb.height != dev->height ||
1da177e4 554 buf->vb.field != field) {
c5a86144
HV		 555 buf->fmt = dev->fmt;
556 buf->vb.width = dev->width;
557 buf->vb.height = dev->height;
1da177e4
LT		 558 buf->vb.field = field;
559 init_buffer = 1;
560 }
561
0fc0686e 562 if (VIDEOBUF_NEEDS_INIT == buf->vb.state) {
1da177e4 563 init_buffer = 1;
c7b0ac05 564 if (0 != (rc = videobuf_iolock(q,&buf->vb,NULL)))
1da177e4
LT		 565 goto fail;
566 }
567
568 if (init_buffer) {
569 buf->bpl = buf->vb.width * buf->fmt->depth >> 3;
570 switch (buf->vb.field) {
571 case V4L2_FIELD_TOP:
572 cx88_risc_buffer(dev->pci, &buf->risc,
c1accaa2 573 dma->sglist, 0, UNSET,
1da177e4
LT		 574 buf->bpl, 0, buf->vb.height);
575 break;
576 case V4L2_FIELD_BOTTOM:
577 cx88_risc_buffer(dev->pci, &buf->risc,
c1accaa2 578 dma->sglist, UNSET, 0,
1da177e4
LT		 579 buf->bpl, 0, buf->vb.height);
580 break;
581 case V4L2_FIELD_INTERLACED:
582 cx88_risc_buffer(dev->pci, &buf->risc,
c1accaa2 583 dma->sglist, 0, buf->bpl,
1da177e4
LT		 584 buf->bpl, buf->bpl,
585 buf->vb.height >> 1);
586 break;
587 case V4L2_FIELD_SEQ_TB:
588 cx88_risc_buffer(dev->pci, &buf->risc,
c1accaa2 589 dma->sglist,
1da177e4
LT		 590 0, buf->bpl * (buf->vb.height >> 1),
591 buf->bpl, 0,
592 buf->vb.height >> 1);
593 break;
594 case V4L2_FIELD_SEQ_BT:
595 cx88_risc_buffer(dev->pci, &buf->risc,
c1accaa2 596 dma->sglist,
1da177e4
LT		 597 buf->bpl * (buf->vb.height >> 1), 0,
598 buf->bpl, 0,
599 buf->vb.height >> 1);
600 break;
601 default:
602 BUG();
603 }
604 }
605 dprintk(2,"[%p/%d] buffer_prepare - %dx%d %dbpp \"%s\" - dma=0x%08lx\n",
606 buf, buf->vb.i,
c5a86144 607 dev->width, dev->height, dev->fmt->depth, dev->fmt->name,
1da177e4
LT		 608 (unsigned long)buf->risc.dma);
609
0fc0686e 610 buf->vb.state = VIDEOBUF_PREPARED;
1da177e4
LT		 611 return 0;
612
613 fail:
c7b0ac05 614 cx88_free_buffer(q,buf);
1da177e4
LT		 615 return rc;
616}
617
618static void
619buffer_queue(struct videobuf_queue *vq, struct videobuf_buffer *vb)
620{
621 struct cx88_buffer *buf = container_of(vb,struct cx88_buffer,vb);
622 struct cx88_buffer *prev;
623 struct cx8800_fh *fh = vq->priv_data;
624 struct cx8800_dev *dev = fh->dev;
e52e98a7 625 struct cx88_core *core = dev->core;
1da177e4
LT		 626 struct cx88_dmaqueue *q = &dev->vidq;
627
628 /* add jump to stopper */
629 buf->risc.jmp[0] = cpu_to_le32(RISC_JUMP | RISC_IRQ1 | RISC_CNT_INC);
630 buf->risc.jmp[1] = cpu_to_le32(q->stopper.dma);
631
632 if (!list_empty(&q->queued)) {
633 list_add_tail(&buf->vb.queue,&q->queued);
0fc0686e 634 buf->vb.state = VIDEOBUF_QUEUED;
1da177e4
LT		 635 dprintk(2,"[%p/%d] buffer_queue - append to queued\n",
636 buf, buf->vb.i);
637
638 } else if (list_empty(&q->active)) {
639 list_add_tail(&buf->vb.queue,&q->active);
640 start_video_dma(dev, q, buf);
0fc0686e 641 buf->vb.state = VIDEOBUF_ACTIVE;
1da177e4
LT		 642 buf->count = q->count++;
643 mod_timer(&q->timeout, jiffies+BUFFER_TIMEOUT);
644 dprintk(2,"[%p/%d] buffer_queue - first active\n",
645 buf, buf->vb.i);
646
647 } else {
648 prev = list_entry(q->active.prev, struct cx88_buffer, vb.queue);
649 if (prev->vb.width == buf->vb.width &&
650 prev->vb.height == buf->vb.height &&
651 prev->fmt == buf->fmt) {
652 list_add_tail(&buf->vb.queue,&q->active);
0fc0686e 653 buf->vb.state = VIDEOBUF_ACTIVE;
1da177e4
LT		 654 buf->count = q->count++;
655 prev->risc.jmp[1] = cpu_to_le32(buf->risc.dma);
656 dprintk(2,"[%p/%d] buffer_queue - append to active\n",
657 buf, buf->vb.i);
658
659 } else {
660 list_add_tail(&buf->vb.queue,&q->queued);
0fc0686e 661 buf->vb.state = VIDEOBUF_QUEUED;
1da177e4
LT		 662 dprintk(2,"[%p/%d] buffer_queue - first queued\n",
663 buf, buf->vb.i);
664 }
665 }
666}
667
668static void buffer_release(struct videobuf_queue *q, struct videobuf_buffer *vb)
669{
670 struct cx88_buffer *buf = container_of(vb,struct cx88_buffer,vb);
1da177e4 671
c7b0ac05 672 cx88_free_buffer(q,buf);
1da177e4
LT		 673}
674
2e4e98e7 675static const struct videobuf_queue_ops cx8800_video_qops = {
1da177e4
LT		 676 .buf_setup = buffer_setup,
677 .buf_prepare = buffer_prepare,
678 .buf_queue = buffer_queue,
679 .buf_release = buffer_release,
680};
681
682/* ------------------------------------------------------------------ */
683
1da177e4
LT		 684
685/* ------------------------------------------------------------------ */
686
edbd138e 687static struct videobuf_queue *get_queue(struct file *file)
1da177e4 688{
edbd138e
HV		 689 struct video_device *vdev = video_devdata(file);
690 struct cx8800_fh *fh = file->private_data;
691
692 switch (vdev->vfl_type) {
693 case VFL_TYPE_GRABBER:
1da177e4 694 return &fh->vidq;
edbd138e 695 case VFL_TYPE_VBI:
1da177e4
LT		 696 return &fh->vbiq;
697 default:
698 BUG();
699 return NULL;
700 }
701}
702
edbd138e 703static int get_resource(struct file *file)
1da177e4 704{
edbd138e
HV		 705 struct video_device *vdev = video_devdata(file);
706
707 switch (vdev->vfl_type) {
708 case VFL_TYPE_GRABBER:
1da177e4 709 return RESOURCE_VIDEO;
edbd138e 710 case VFL_TYPE_VBI:
1da177e4
LT		 711 return RESOURCE_VBI;
712 default:
713 BUG();
714 return 0;
715 }
716}
717
bec43661 718static int video_open(struct file *file)
1da177e4 719{
63b0d5ad
LP		 720 struct video_device *vdev = video_devdata(file);
721 struct cx8800_dev *dev = video_drvdata(file);
5401c2db 722 struct cx88_core *core = dev->core;
1da177e4 723 struct cx8800_fh *fh;
1da177e4
LT		 724 enum v4l2_buf_type type = 0;
725 int radio = 0;
726
63b0d5ad
LP		 727 switch (vdev->vfl_type) {
728 case VFL_TYPE_GRABBER:
729 type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
730 break;
731 case VFL_TYPE_VBI:
732 type = V4L2_BUF_TYPE_VBI_CAPTURE;
733 break;
734 case VFL_TYPE_RADIO:
735 radio = 1;
736 break;
d56dc612 737 }
1da177e4 738
50462eb0
LP		 739 dprintk(1, "open dev=%s radio=%d type=%s\n",
740 video_device_node_name(vdev), radio, v4l2_type_names[type]);
1da177e4
LT		 741
742 /* allocate + initialize per filehandle data */
7408187d 743 fh = kzalloc(sizeof(*fh),GFP_KERNEL);
da497e30 744 if (unlikely(!fh))
1da177e4 745 return -ENOMEM;
da497e30 746
88bb42fb 747 v4l2_fh_init(&fh->fh, vdev);
1da177e4
LT		 748 file->private_data = fh;
749 fh->dev = dev;
1da177e4 750
da497e30 751 mutex_lock(&core->lock);
da497e30 752
0705135e
GL		 753 videobuf_queue_sg_init(&fh->vidq, &cx8800_video_qops,
754 &dev->pci->dev, &dev->slock,
1da177e4
LT		 755 V4L2_BUF_TYPE_VIDEO_CAPTURE,
756 V4L2_FIELD_INTERLACED,
757 sizeof(struct cx88_buffer),
08bff03e 758 fh, NULL);
0705135e
GL		 759 videobuf_queue_sg_init(&fh->vbiq, &cx8800_vbi_qops,
760 &dev->pci->dev, &dev->slock,
1da177e4
LT		 761 V4L2_BUF_TYPE_VBI_CAPTURE,
762 V4L2_FIELD_SEQ_TB,
763 sizeof(struct cx88_buffer),
08bff03e 764 fh, NULL);
1da177e4 765
edbd138e 766 if (vdev->vfl_type == VFL_TYPE_RADIO) {
1da177e4 767 dprintk(1,"video_open: setting radio device\n");
6a59d64c
TP		 768 cx_write(MO_GP3_IO, core->board.radio.gpio3);
769 cx_write(MO_GP0_IO, core->board.radio.gpio0);
770 cx_write(MO_GP1_IO, core->board.radio.gpio1);
771 cx_write(MO_GP2_IO, core->board.radio.gpio2);
430189da 772 if (core->board.radio.audioroute) {
609c4c12 773 if (core->sd_wm8775) {
5325b427
HV		 774 call_all(core, audio, s_routing,
775 core->board.radio.audioroute, 0, 0);
430189da
DB		 776 }
777 /* "I2S ADC mode" */
778 core->tvaudio = WW_I2SADC;
779 cx88_set_tvaudio(core);
780 } else {
781 /* FM Mode */
782 core->tvaudio = WW_FM;
783 cx88_set_tvaudio(core);
784 cx88_set_stereo(core,V4L2_TUNER_MODE_STEREO,1);
785 }
b8341e1d 786 call_all(core, tuner, s_radio);
1da177e4
LT		 787 }
788
8d115931 789 core->users++;
da497e30 790 mutex_unlock(&core->lock);
88bb42fb 791 v4l2_fh_add(&fh->fh);
3e010845 792
4ac97914 793 return 0;
1da177e4
LT		 794}
795
796static ssize_t
f9e7a020 797video_read(struct file *file, char __user *data, size_t count, loff_t *ppos)
1da177e4 798{
edbd138e 799 struct video_device *vdev = video_devdata(file);
1da177e4
LT		 800 struct cx8800_fh *fh = file->private_data;
801
edbd138e
HV		 802 switch (vdev->vfl_type) {
803 case VFL_TYPE_GRABBER:
1da177e4
LT		 804 if (res_locked(fh->dev,RESOURCE_VIDEO))
805 return -EBUSY;
806 return videobuf_read_one(&fh->vidq, data, count, ppos,
807 file->f_flags & O_NONBLOCK);
edbd138e 808 case VFL_TYPE_VBI:
1da177e4
LT		 809 if (!res_get(fh->dev,fh,RESOURCE_VBI))
810 return -EBUSY;
811 return videobuf_read_stream(&fh->vbiq, data, count, ppos, 1,
812 file->f_flags & O_NONBLOCK);
813 default:
814 BUG();
815 return 0;
816 }
817}
818
819static unsigned int
820video_poll(struct file *file, struct poll_table_struct *wait)
821{
edbd138e 822 struct video_device *vdev = video_devdata(file);
1da177e4
LT		 823 struct cx8800_fh *fh = file->private_data;
824 struct cx88_buffer *buf;
1a3c60a0 825 unsigned int rc = v4l2_ctrl_poll(file, wait);
1da177e4 826
edbd138e 827 if (vdev->vfl_type == VFL_TYPE_VBI) {
1da177e4 828 if (!res_get(fh->dev,fh,RESOURCE_VBI))
1a3c60a0
HV		 829 return rc | POLLERR;
830 return rc | videobuf_poll_stream(file, &fh->vbiq, wait);
1da177e4 831 }
9fd6418a 832 mutex_lock(&fh->vidq.vb_lock);
1da177e4
LT		 833 if (res_check(fh,RESOURCE_VIDEO)) {
834 /* streaming capture */
835 if (list_empty(&fh->vidq.stream))
9fd6418a 836 goto done;
1da177e4
LT		 837 buf = list_entry(fh->vidq.stream.next,struct cx88_buffer,vb.stream);
838 } else {
839 /* read() capture */
840 buf = (struct cx88_buffer*)fh->vidq.read_buf;
841 if (NULL == buf)
9fd6418a 842 goto done;
1da177e4
LT		 843 }
844 poll_wait(file, &buf->vb.done, wait);
0fc0686e
BP		 845 if (buf->vb.state == VIDEOBUF_DONE ||
846 buf->vb.state == VIDEOBUF_ERROR)
1a3c60a0 847 rc |= POLLIN|POLLRDNORM;
9fd6418a
F		 848done:
849 mutex_unlock(&fh->vidq.vb_lock);
850 return rc;
1da177e4
LT		 851}
852
bec43661 853static int video_release(struct file *file)
1da177e4
LT		 854{
855 struct cx8800_fh *fh = file->private_data;
856 struct cx8800_dev *dev = fh->dev;
857
858 /* turn off overlay */
859 if (res_check(fh, RESOURCE_OVERLAY)) {
860 /* FIXME */
861 res_free(dev,fh,RESOURCE_OVERLAY);
862 }
863
864 /* stop video capture */
865 if (res_check(fh, RESOURCE_VIDEO)) {
866 videobuf_queue_cancel(&fh->vidq);
867 res_free(dev,fh,RESOURCE_VIDEO);
868 }
869 if (fh->vidq.read_buf) {
870 buffer_release(&fh->vidq,fh->vidq.read_buf);
871 kfree(fh->vidq.read_buf);
872 }
873
874 /* stop vbi capture */
875 if (res_check(fh, RESOURCE_VBI)) {
053fcb60 876 videobuf_stop(&fh->vbiq);
1da177e4
LT		 877 res_free(dev,fh,RESOURCE_VBI);
878 }
879
880 videobuf_mmap_free(&fh->vidq);
881 videobuf_mmap_free(&fh->vbiq);
da497e30
MCC		 882
883 mutex_lock(&dev->core->lock);
88bb42fb
HV		 884 v4l2_fh_del(&fh->fh);
885 v4l2_fh_exit(&fh->fh);
1da177e4
LT		 886 file->private_data = NULL;
887 kfree(fh);
e52e98a7 888
8d115931
JN		 889 dev->core->users--;
890 if (!dev->core->users)
622b828a 891 call_all(dev->core, core, s_power, 0);
06f837ca 892 mutex_unlock(&dev->core->lock);
e52e98a7 893
1da177e4
LT		 894 return 0;
895}
896
897static int
898video_mmap(struct file *file, struct vm_area_struct * vma)
899{
edbd138e 900 return videobuf_mmap_mapper(get_queue(file), vma);
1da177e4
LT		 901}
902
903/* ------------------------------------------------------------------ */
8d87cb9f 904/* VIDEO CTRL IOCTLS */
1da177e4 905
8c7cb12a
HV		 906static int cx8800_s_vid_ctrl(struct v4l2_ctrl *ctrl)
907{
908 struct cx88_core *core =
909 container_of(ctrl->handler, struct cx88_core, video_hdl);
910 const struct cx88_ctrl *cc = ctrl->priv;
911 u32 value, mask;
912
913 mask = cc->mask;
914 switch (ctrl->id) {
915 case V4L2_CID_SATURATION:
916 /* special v_sat handling */
917
918 value = ((ctrl->val - cc->off) << cc->shift) & cc->mask;
919
920 if (core->tvnorm & V4L2_STD_SECAM) {
921 /* For SECAM, both U and V sat should be equal */
922 value = value << 8 | value;
923 } else {
924 /* Keeps U Saturation proportional to V Sat */
925 value = (value * 0x5a) / 0x7f << 8 | value;
926 }
927 mask = 0xffff;
928 break;
929 case V4L2_CID_SHARPNESS:
930 /* 0b000, 0b100, 0b101, 0b110, or 0b111 */
931 value = (ctrl->val < 1 ? 0 : ((ctrl->val + 3) << 7));
932 /* needs to be set for both fields */
933 cx_andor(MO_FILTER_EVEN, mask, value);
934 break;
935 case V4L2_CID_CHROMA_AGC:
936 value = ((ctrl->val - cc->off) << cc->shift) & cc->mask;
937 break;
938 default:
939 value = ((ctrl->val - cc->off) << cc->shift) & cc->mask;
940 break;
941 }
942 dprintk(1, "set_control id=0x%X(%s) ctrl=0x%02x, reg=0x%02x val=0x%02x (mask 0x%02x)%s\n",
943 ctrl->id, ctrl->name, ctrl->val, cc->reg, value,
944 mask, cc->sreg ? " [shadowed]" : "");
945 if (cc->sreg)
946 cx_sandor(cc->sreg, cc->reg, mask, value);
947 else
948 cx_andor(cc->reg, mask, value);
949 return 0;
950}
951
952static int cx8800_s_aud_ctrl(struct v4l2_ctrl *ctrl)
1da177e4 953{
bac63981 954 struct cx88_core *core =
8c7cb12a 955 container_of(ctrl->handler, struct cx88_core, audio_hdl);
bac63981 956 const struct cx88_ctrl *cc = ctrl->priv;
70f00044 957 u32 value,mask;
6951803c
LR		 958
959 /* Pass changes onto any WM8775 */
609c4c12 960 if (core->sd_wm8775) {
bac63981 961 switch (ctrl->id) {
6951803c 962 case V4L2_CID_AUDIO_MUTE:
bac63981 963 wm8775_s_ctrl(core, ctrl->id, ctrl->val);
6951803c
LR		 964 break;
965 case V4L2_CID_AUDIO_VOLUME:
bac63981
HV		 966 wm8775_s_ctrl(core, ctrl->id, (ctrl->val) ?
967 (0x90 + ctrl->val) << 8 : 0);
6951803c
LR		 968 break;
969 case V4L2_CID_AUDIO_BALANCE:
bac63981 970 wm8775_s_ctrl(core, ctrl->id, ctrl->val << 9);
6951803c
LR		 971 break;
972 default:
6951803c
LR		 973 break;
974 }
6951803c
LR		 975 }
976
bac63981
HV		 977 mask = cc->mask;
978 switch (ctrl->id) {
1da177e4 979 case V4L2_CID_AUDIO_BALANCE:
bac63981 980 value = (ctrl->val < 0x40) ? (0x7f - ctrl->val) : (ctrl->val - 0x40);
1da177e4
LT		 981 break;
982 case V4L2_CID_AUDIO_VOLUME:
bac63981 983 value = 0x3f - (ctrl->val & 0x3f);
1da177e4 984 break;
1da177e4 985 default:
bac63981 986 value = ((ctrl->val - cc->off) << cc->shift) & cc->mask;
1da177e4
LT		 987 break;
988 }
6457af5f 989 dprintk(1,"set_control id=0x%X(%s) ctrl=0x%02x, reg=0x%02x val=0x%02x (mask 0x%02x)%s\n",
bac63981
HV		 990 ctrl->id, ctrl->name, ctrl->val, cc->reg, value,
991 mask, cc->sreg ? " [shadowed]" : "");
992 if (cc->sreg)
993 cx_sandor(cc->sreg, cc->reg, mask, value);
994 else
995 cx_andor(cc->reg, mask, value);
1da177e4
LT		 996 return 0;
997}
1da177e4
LT		 998
999/* ------------------------------------------------------------------ */
8d87cb9f 1000/* VIDEO IOCTLS */
1da177e4 1001
78b526a4 1002static int vidioc_g_fmt_vid_cap(struct file *file, void *priv,
8d87cb9f 1003 struct v4l2_format *f)
1da177e4 1004{
8d87cb9f 1005 struct cx8800_fh *fh = priv;
c5a86144 1006 struct cx8800_dev *dev = fh->dev;
8d87cb9f 1007
c5a86144
HV		 1008 f->fmt.pix.width = dev->width;
1009 f->fmt.pix.height = dev->height;
8d87cb9f 1010 f->fmt.pix.field = fh->vidq.field;
c5a86144 1011 f->fmt.pix.pixelformat = dev->fmt->fourcc;
8d87cb9f 1012 f->fmt.pix.bytesperline =
c5a86144 1013 (f->fmt.pix.width * dev->fmt->depth) >> 3;
8d87cb9f
MCC		 1014 f->fmt.pix.sizeimage =
1015 f->fmt.pix.height * f->fmt.pix.bytesperline;
c5a86144 1016 f->fmt.pix.colorspace = V4L2_COLORSPACE_SMPTE170M;
8d87cb9f 1017 return 0;
1da177e4
LT		 1018}
1019
78b526a4 1020static int vidioc_try_fmt_vid_cap(struct file *file, void *priv,
8d87cb9f 1021 struct v4l2_format *f)
1da177e4 1022{
8d87cb9f 1023 struct cx88_core *core = ((struct cx8800_fh *)priv)->dev->core;
2e4e98e7 1024 const struct cx8800_fmt *fmt;
8d87cb9f
MCC		 1025 enum v4l2_field field;
1026 unsigned int maxw, maxh;
e52e98a7 1027
8d87cb9f
MCC		 1028 fmt = format_by_fourcc(f->fmt.pix.pixelformat);
1029 if (NULL == fmt)
1030 return -EINVAL;
1da177e4 1031
8d87cb9f
MCC		 1032 field = f->fmt.pix.field;
1033 maxw = norm_maxw(core->tvnorm);
1034 maxh = norm_maxh(core->tvnorm);
1da177e4 1035
8d87cb9f
MCC		 1036 if (V4L2_FIELD_ANY == field) {
1037 field = (f->fmt.pix.height > maxh/2)
1038 ? V4L2_FIELD_INTERLACED
1039 : V4L2_FIELD_BOTTOM;
1da177e4 1040 }
8d87cb9f
MCC		 1041
1042 switch (field) {
1043 case V4L2_FIELD_TOP:
1044 case V4L2_FIELD_BOTTOM:
1045 maxh = maxh / 2;
1046 break;
1047 case V4L2_FIELD_INTERLACED:
1048 break;
1da177e4
LT		 1049 default:
1050 return -EINVAL;
1051 }
8d87cb9f
MCC		 1052
1053 f->fmt.pix.field = field;
4b89945e
TP		 1054 v4l_bound_align_image(&f->fmt.pix.width, 48, maxw, 2,
1055 &f->fmt.pix.height, 32, maxh, 0, 0);
8d87cb9f
MCC		 1056 f->fmt.pix.bytesperline =
1057 (f->fmt.pix.width * fmt->depth) >> 3;
1058 f->fmt.pix.sizeimage =
1059 f->fmt.pix.height * f->fmt.pix.bytesperline;
1060
1061 return 0;
1da177e4
LT		 1062}
1063
78b526a4 1064static int vidioc_s_fmt_vid_cap(struct file *file, void *priv,
8d87cb9f 1065 struct v4l2_format *f)
1da177e4 1066{
8d87cb9f 1067 struct cx8800_fh *fh = priv;
c5a86144 1068 struct cx8800_dev *dev = fh->dev;
78b526a4 1069 int err = vidioc_try_fmt_vid_cap (file,priv,f);
8d87cb9f
MCC		 1070
1071 if (0 != err)
1072 return err;
c5a86144
HV		 1073 dev->fmt = format_by_fourcc(f->fmt.pix.pixelformat);
1074 dev->width = f->fmt.pix.width;
1075 dev->height = f->fmt.pix.height;
8d87cb9f
MCC		 1076 fh->vidq.field = f->fmt.pix.field;
1077 return 0;
1da177e4
LT		 1078}
1079
902e197d
HV		 1080void cx88_querycap(struct file *file, struct cx88_core *core,
1081 struct v4l2_capability *cap)
1082{
1083 struct video_device *vdev = video_devdata(file);
1084
1085 strlcpy(cap->card, core->board.name, sizeof(cap->card));
1086 cap->device_caps = V4L2_CAP_READWRITE | V4L2_CAP_STREAMING;
1087 if (UNSET != core->board.tuner_type)
1088 cap->device_caps |= V4L2_CAP_TUNER;
1089 switch (vdev->vfl_type) {
1090 case VFL_TYPE_RADIO:
1091 cap->device_caps = V4L2_CAP_RADIO | V4L2_CAP_TUNER;
1092 break;
1093 case VFL_TYPE_GRABBER:
1094 cap->device_caps |= V4L2_CAP_VIDEO_CAPTURE;
1095 break;
1096 case VFL_TYPE_VBI:
1097 cap->device_caps |= V4L2_CAP_VBI_CAPTURE;
1098 break;
1099 }
1100 cap->capabilities = cap->device_caps | V4L2_CAP_VIDEO_CAPTURE |
1101 V4L2_CAP_VBI_CAPTURE | V4L2_CAP_DEVICE_CAPS;
1102 if (core->board.radio.type == CX88_RADIO)
1103 cap->capabilities |= V4L2_CAP_RADIO;
1104}
1105EXPORT_SYMBOL(cx88_querycap);
1106
1107static int vidioc_querycap(struct file *file, void *priv,
8d87cb9f 1108 struct v4l2_capability *cap)
1da177e4 1109{
8d87cb9f 1110 struct cx8800_dev *dev = ((struct cx8800_fh *)priv)->dev;
1da177e4 1111 struct cx88_core *core = dev->core;
1da177e4 1112
8d87cb9f 1113 strcpy(cap->driver, "cx8800");
902e197d
HV		 1114 sprintf(cap->bus_info, "PCI:%s", pci_name(dev->pci));
1115 cx88_querycap(file, core, cap);
8d87cb9f
MCC		 1116 return 0;
1117}
e52e98a7 1118
78b526a4 1119static int vidioc_enum_fmt_vid_cap (struct file *file, void *priv,
8d87cb9f
MCC		 1120 struct v4l2_fmtdesc *f)
1121{
1122 if (unlikely(f->index >= ARRAY_SIZE(formats)))
1123 return -EINVAL;
1124
1125 strlcpy(f->description,formats[f->index].name,sizeof(f->description));
1126 f->pixelformat = formats[f->index].fourcc;
1127
1128 return 0;
1129}
1da177e4 1130
8d87cb9f
MCC		 1131static int vidioc_reqbufs (struct file *file, void *priv, struct v4l2_requestbuffers *p)
1132{
edbd138e 1133 return videobuf_reqbufs(get_queue(file), p);
8d87cb9f 1134}
e52e98a7 1135
8d87cb9f
MCC		 1136static int vidioc_querybuf (struct file *file, void *priv, struct v4l2_buffer *p)
1137{
edbd138e 1138 return videobuf_querybuf(get_queue(file), p);
8d87cb9f 1139}
e52e98a7 1140
8d87cb9f
MCC		 1141static int vidioc_qbuf (struct file *file, void *priv, struct v4l2_buffer *p)
1142{
edbd138e 1143 return videobuf_qbuf(get_queue(file), p);
8d87cb9f 1144}
e52e98a7 1145
8d87cb9f
MCC		 1146static int vidioc_dqbuf (struct file *file, void *priv, struct v4l2_buffer *p)
1147{
edbd138e
HV		 1148 return videobuf_dqbuf(get_queue(file), p,
1149 file->f_flags & O_NONBLOCK);
8d87cb9f 1150}
e52e98a7 1151
8d87cb9f
MCC		 1152static int vidioc_streamon(struct file *file, void *priv, enum v4l2_buf_type i)
1153{
edbd138e 1154 struct video_device *vdev = video_devdata(file);
8d87cb9f
MCC		 1155 struct cx8800_fh *fh = priv;
1156 struct cx8800_dev *dev = fh->dev;
1157
edbd138e
HV		 1158 if ((vdev->vfl_type == VFL_TYPE_GRABBER && i != V4L2_BUF_TYPE_VIDEO_CAPTURE) ||
1159 (vdev->vfl_type == VFL_TYPE_VBI && i != V4L2_BUF_TYPE_VBI_CAPTURE))
8d87cb9f 1160 return -EINVAL;
b058e3f3 1161
edbd138e 1162 if (unlikely(!res_get(dev, fh, get_resource(file))))
8d87cb9f 1163 return -EBUSY;
edbd138e 1164 return videobuf_streamon(get_queue(file));
8d87cb9f
MCC		 1165}
1166
1167static int vidioc_streamoff(struct file *file, void *priv, enum v4l2_buf_type i)
1168{
edbd138e 1169 struct video_device *vdev = video_devdata(file);
8d87cb9f
MCC		 1170 struct cx8800_fh *fh = priv;
1171 struct cx8800_dev *dev = fh->dev;
1172 int err, res;
1173
edbd138e
HV		 1174 if ((vdev->vfl_type == VFL_TYPE_GRABBER && i != V4L2_BUF_TYPE_VIDEO_CAPTURE) ||
1175 (vdev->vfl_type == VFL_TYPE_VBI && i != V4L2_BUF_TYPE_VBI_CAPTURE))
8d87cb9f
MCC		 1176 return -EINVAL;
1177
edbd138e
HV		 1178 res = get_resource(file);
1179 err = videobuf_streamoff(get_queue(file));
8d87cb9f
MCC		 1180 if (err < 0)
1181 return err;
1182 res_free(dev,fh,res);
e52e98a7
MCC		 1183 return 0;
1184}
1185
48d68801
HV		 1186static int vidioc_g_std(struct file *file, void *priv, v4l2_std_id *tvnorm)
1187{
1188 struct cx88_core *core = ((struct cx8800_fh *)priv)->dev->core;
1189
1190 *tvnorm = core->tvnorm;
1191 return 0;
1192}
1193
314527ac 1194static int vidioc_s_std(struct file *file, void *priv, v4l2_std_id tvnorms)
e52e98a7 1195{
8d87cb9f 1196 struct cx88_core *core = ((struct cx8800_fh *)priv)->dev->core;
e52e98a7 1197
8d87cb9f 1198 mutex_lock(&core->lock);
314527ac 1199 cx88_set_tvnorm(core, tvnorms);
8d87cb9f 1200 mutex_unlock(&core->lock);
63ab1bdc 1201
8d87cb9f
MCC		 1202 return 0;
1203}
1da177e4 1204
8d87cb9f 1205/* only one input in this sample driver */
54da49f5 1206int cx88_enum_input (struct cx88_core *core,struct v4l2_input *i)
8d87cb9f 1207{
2e4e98e7 1208 static const char * const iname[] = {
8d87cb9f
MCC		 1209 [ CX88_VMUX_COMPOSITE1 ] = "Composite1",
1210 [ CX88_VMUX_COMPOSITE2 ] = "Composite2",
1211 [ CX88_VMUX_COMPOSITE3 ] = "Composite3",
1212 [ CX88_VMUX_COMPOSITE4 ] = "Composite4",
1213 [ CX88_VMUX_SVIDEO ] = "S-Video",
1214 [ CX88_VMUX_TELEVISION ] = "Television",
1215 [ CX88_VMUX_CABLE ] = "Cable TV",
1216 [ CX88_VMUX_DVB ] = "DVB",
1217 [ CX88_VMUX_DEBUG ] = "for debug only",
1218 };
f3334bcb 1219 unsigned int n = i->index;
1da177e4 1220
8d87cb9f
MCC		 1221 if (n >= 4)
1222 return -EINVAL;
6a59d64c 1223 if (0 == INPUT(n).type)
8d87cb9f 1224 return -EINVAL;
8d87cb9f 1225 i->type = V4L2_INPUT_TYPE_CAMERA;
6a59d64c
TP		 1226 strcpy(i->name,iname[INPUT(n).type]);
1227 if ((CX88_VMUX_TELEVISION == INPUT(n).type) ||
473d8024 1228 (CX88_VMUX_CABLE == INPUT(n).type)) {
8d87cb9f 1229 i->type = V4L2_INPUT_TYPE_TUNER;
473d8024 1230 }
f33e9868 1231 i->std = CX88_NORMS;
8d87cb9f
MCC		 1232 return 0;
1233}
54da49f5
MCC		 1234EXPORT_SYMBOL(cx88_enum_input);
1235
1236static int vidioc_enum_input (struct file *file, void *priv,
1237 struct v4l2_input *i)
1238{
1239 struct cx88_core *core = ((struct cx8800_fh *)priv)->dev->core;
1240 return cx88_enum_input (core,i);
1241}
1da177e4 1242
8d87cb9f
MCC		 1243static int vidioc_g_input (struct file *file, void *priv, unsigned int *i)
1244{
1245 struct cx88_core *core = ((struct cx8800_fh *)priv)->dev->core;
1da177e4 1246
8d87cb9f
MCC		 1247 *i = core->input;
1248 return 0;
1249}
1da177e4 1250
8d87cb9f
MCC		 1251static int vidioc_s_input (struct file *file, void *priv, unsigned int i)
1252{
1253 struct cx88_core *core = ((struct cx8800_fh *)priv)->dev->core;
1da177e4 1254
8d87cb9f
MCC		 1255 if (i >= 4)
1256 return -EINVAL;
f33e9868
HV		 1257 if (0 == INPUT(i).type)
1258 return -EINVAL;
1da177e4 1259
8d87cb9f
MCC		 1260 mutex_lock(&core->lock);
1261 cx88_newstation(core);
e90311a1 1262 cx88_video_mux(core,i);
8d87cb9f
MCC		 1263 mutex_unlock(&core->lock);
1264 return 0;
1265}
1da177e4 1266
8d87cb9f
MCC		 1267static int vidioc_g_tuner (struct file *file, void *priv,
1268 struct v4l2_tuner *t)
1269{
1270 struct cx88_core *core = ((struct cx8800_fh *)priv)->dev->core;
1271 u32 reg;
1da177e4 1272
6a59d64c 1273 if (unlikely(UNSET == core->board.tuner_type))
8d87cb9f 1274 return -EINVAL;
243d8c0f
MCC		 1275 if (0 != t->index)
1276 return -EINVAL;
a82decf6 1277
8d87cb9f 1278 strcpy(t->name, "Television");
8d87cb9f
MCC		 1279 t->capability = V4L2_TUNER_CAP_NORM;
1280 t->rangehigh = 0xffffffffUL;
f33e9868 1281 call_all(core, tuner, g_tuner, t);
a82decf6 1282
8d87cb9f
MCC		 1283 cx88_get_stereo(core ,t);
1284 reg = cx_read(MO_DEVICE_STATUS);
1285 t->signal = (reg & (1<<5)) ? 0xffff : 0x0000;
1286 return 0;
1287}
41ef7c1e 1288
8d87cb9f 1289static int vidioc_s_tuner (struct file *file, void *priv,
2f73c7c5 1290 const struct v4l2_tuner *t)
8d87cb9f
MCC		 1291{
1292 struct cx88_core *core = ((struct cx8800_fh *)priv)->dev->core;
41ef7c1e 1293
6a59d64c 1294 if (UNSET == core->board.tuner_type)
8d87cb9f
MCC		 1295 return -EINVAL;
1296 if (0 != t->index)
1297 return -EINVAL;
c5287ba1 1298
8d87cb9f
MCC		 1299 cx88_set_stereo(core, t->audmode, 1);
1300 return 0;
1301}
902fc997 1302
8d87cb9f
MCC		 1303static int vidioc_g_frequency (struct file *file, void *priv,
1304 struct v4l2_frequency *f)
1305{
1306 struct cx8800_fh *fh = priv;
1307 struct cx88_core *core = fh->dev->core;
902fc997 1308
6a59d64c 1309 if (unlikely(UNSET == core->board.tuner_type))
8d87cb9f 1310 return -EINVAL;
f33e9868
HV		 1311 if (f->tuner)
1312 return -EINVAL;
8d87cb9f 1313
8d87cb9f
MCC		 1314 f->frequency = core->freq;
1315
b8341e1d 1316 call_all(core, tuner, g_frequency, f);
1da177e4 1317
1da177e4
LT		 1318 return 0;
1319}
1320
54da49f5 1321int cx88_set_freq (struct cx88_core *core,
b530a447 1322 const struct v4l2_frequency *f)
1da177e4 1323{
b530a447
HV		 1324 struct v4l2_frequency new_freq = *f;
1325
6a59d64c 1326 if (unlikely(UNSET == core->board.tuner_type))
8d87cb9f
MCC		 1327 return -EINVAL;
1328 if (unlikely(f->tuner != 0))
1329 return -EINVAL;
54da49f5 1330
8d87cb9f 1331 mutex_lock(&core->lock);
8d87cb9f 1332 cx88_newstation(core);
b8341e1d 1333 call_all(core, tuner, s_frequency, f);
b530a447
HV		 1334 call_all(core, tuner, g_frequency, &new_freq);
1335 core->freq = new_freq.frequency;
c7b0ac05 1336
8d87cb9f
MCC		 1337 /* When changing channels it is required to reset TVAUDIO */
1338 msleep (10);
1339 cx88_set_tvaudio(core);
c7b0ac05 1340
8d87cb9f 1341 mutex_unlock(&core->lock);
54da49f5 1342
8d87cb9f 1343 return 0;
1da177e4 1344}
54da49f5
MCC		 1345EXPORT_SYMBOL(cx88_set_freq);
1346
1347static int vidioc_s_frequency (struct file *file, void *priv,
b530a447 1348 const struct v4l2_frequency *f)
54da49f5
MCC		 1349{
1350 struct cx8800_fh *fh = priv;
1351 struct cx88_core *core = fh->dev->core;
1352
edbd138e 1353 return cx88_set_freq(core, f);
54da49f5 1354}
1da177e4 1355
dbbff48f
TP		 1356#ifdef CONFIG_VIDEO_ADV_DEBUG
1357static int vidioc_g_register (struct file *file, void *fh,
aecde8b5 1358 struct v4l2_dbg_register *reg)
dbbff48f
TP		 1359{
1360 struct cx88_core *core = ((struct cx8800_fh*)fh)->dev->core;
1361
dbbff48f 1362 /* cx2388x has a 24-bit register space */
7feeb148 1363 reg->val = cx_read(reg->reg & 0xfffffc);
aecde8b5 1364 reg->size = 4;
dbbff48f
TP		 1365 return 0;
1366}
1367
1368static int vidioc_s_register (struct file *file, void *fh,
977ba3b1 1369 const struct v4l2_dbg_register *reg)
dbbff48f
TP		 1370{
1371 struct cx88_core *core = ((struct cx8800_fh*)fh)->dev->core;
1372
7feeb148 1373 cx_write(reg->reg & 0xfffffc, reg->val);
dbbff48f
TP		 1374 return 0;
1375}
1376#endif
8d87cb9f
MCC		 1377
1378/* ----------------------------------------------------------- */
1379/* RADIO ESPECIFIC IOCTLS */
1da177e4
LT		 1380/* ----------------------------------------------------------- */
1381
8d87cb9f
MCC		 1382static int radio_g_tuner (struct file *file, void *priv,
1383 struct v4l2_tuner *t)
1384{
1385 struct cx88_core *core = ((struct cx8800_fh *)priv)->dev->core;
1da177e4 1386
8d87cb9f
MCC		 1387 if (unlikely(t->index > 0))
1388 return -EINVAL;
1da177e4 1389
8d87cb9f 1390 strcpy(t->name, "Radio");
1da177e4 1391
b8341e1d 1392 call_all(core, tuner, g_tuner, t);
8d87cb9f
MCC		 1393 return 0;
1394}
1da177e4 1395
8d87cb9f 1396static int radio_s_tuner (struct file *file, void *priv,
2f73c7c5 1397 const struct v4l2_tuner *t)
8d87cb9f
MCC		 1398{
1399 struct cx88_core *core = ((struct cx8800_fh *)priv)->dev->core;
a82decf6 1400
8d87cb9f
MCC		 1401 if (0 != t->index)
1402 return -EINVAL;
1da177e4 1403
b8341e1d 1404 call_all(core, tuner, s_tuner, t);
8d87cb9f
MCC		 1405 return 0;
1406}
1da177e4 1407
1da177e4
LT		 1408/* ----------------------------------------------------------- */
1409
1410static void cx8800_vid_timeout(unsigned long data)
1411{
1412 struct cx8800_dev *dev = (struct cx8800_dev*)data;
1413 struct cx88_core *core = dev->core;
1414 struct cx88_dmaqueue *q = &dev->vidq;
1415 struct cx88_buffer *buf;
1416 unsigned long flags;
1417
e52e98a7 1418 cx88_sram_channel_dump(core, &cx88_sram_channels[SRAM_CH21]);
1da177e4
LT		 1419
1420 cx_clear(MO_VID_DMACNTRL, 0x11);
1421 cx_clear(VID_CAPTURE_CONTROL, 0x06);
1422
1423 spin_lock_irqsave(&dev->slock,flags);
1424 while (!list_empty(&q->active)) {
1425 buf = list_entry(q->active.next, struct cx88_buffer, vb.queue);
1426 list_del(&buf->vb.queue);
0fc0686e 1427 buf->vb.state = VIDEOBUF_ERROR;
1da177e4
LT		 1428 wake_up(&buf->vb.done);
1429 printk("%s/0: [%p/%d] timeout - dma=0x%08lx\n", core->name,
1430 buf, buf->vb.i, (unsigned long)buf->risc.dma);
1431 }
1432 restart_video_queue(dev,q);
1433 spin_unlock_irqrestore(&dev->slock,flags);
1434}
1435
2e4e98e7 1436static const char *cx88_vid_irqs[32] = {
41ef7c1e
MCC		 1437 "y_risci1", "u_risci1", "v_risci1", "vbi_risc1",
1438 "y_risci2", "u_risci2", "v_risci2", "vbi_risc2",
1439 "y_oflow", "u_oflow", "v_oflow", "vbi_oflow",
1440 "y_sync", "u_sync", "v_sync", "vbi_sync",
1441 "opc_err", "par_err", "rip_err", "pci_abort",
1442};
1443
1da177e4
LT		 1444static void cx8800_vid_irq(struct cx8800_dev *dev)
1445{
1446 struct cx88_core *core = dev->core;
1447 u32 status, mask, count;
1448
1449 status = cx_read(MO_VID_INTSTAT);
1450 mask = cx_read(MO_VID_INTMSK);
1451 if (0 == (status & mask))
1452 return;
1453 cx_write(MO_VID_INTSTAT, status);
1454 if (irq_debug || (status & mask & ~0xff))
1455 cx88_print_irqbits(core->name, "irq vid",
66623a04
MCC		 1456 cx88_vid_irqs, ARRAY_SIZE(cx88_vid_irqs),
1457 status, mask);
1da177e4
LT		 1458
1459 /* risc op code error */
1460 if (status & (1 << 16)) {
1461 printk(KERN_WARNING "%s/0: video risc op code error\n",core->name);
1462 cx_clear(MO_VID_DMACNTRL, 0x11);
1463 cx_clear(VID_CAPTURE_CONTROL, 0x06);
e52e98a7 1464 cx88_sram_channel_dump(core, &cx88_sram_channels[SRAM_CH21]);
1da177e4
LT		 1465 }
1466
1467 /* risc1 y */
1468 if (status & 0x01) {
1469 spin_lock(&dev->slock);
1470 count = cx_read(MO_VIDY_GPCNT);
e52e98a7 1471 cx88_wakeup(core, &dev->vidq, count);
1da177e4
LT		 1472 spin_unlock(&dev->slock);
1473 }
1474
1475 /* risc1 vbi */
1476 if (status & 0x08) {
1477 spin_lock(&dev->slock);
1478 count = cx_read(MO_VBI_GPCNT);
e52e98a7 1479 cx88_wakeup(core, &dev->vbiq, count);
1da177e4
LT		 1480 spin_unlock(&dev->slock);
1481 }
1482
1483 /* risc2 y */
1484 if (status & 0x10) {
1485 dprintk(2,"stopper video\n");
1486 spin_lock(&dev->slock);
1487 restart_video_queue(dev,&dev->vidq);
1488 spin_unlock(&dev->slock);
1489 }
1490
1491 /* risc2 vbi */
1492 if (status & 0x80) {
1493 dprintk(2,"stopper vbi\n");
1494 spin_lock(&dev->slock);
1495 cx8800_restart_vbi_queue(dev,&dev->vbiq);
1496 spin_unlock(&dev->slock);
1497 }
1498}
1499
7d12e780 1500static irqreturn_t cx8800_irq(int irq, void *dev_id)
1da177e4
LT		 1501{
1502 struct cx8800_dev *dev = dev_id;
1503 struct cx88_core *core = dev->core;
1504 u32 status;
1505 int loop, handled = 0;
1506
1507 for (loop = 0; loop < 10; loop++) {
8ddac9ee
TP		 1508 status = cx_read(MO_PCI_INTSTAT) &
1509 (core->pci_irqmask | PCI_INT_VIDINT);
1da177e4
LT		 1510 if (0 == status)
1511 goto out;
1512 cx_write(MO_PCI_INTSTAT, status);
1513 handled = 1;
1514
1515 if (status & core->pci_irqmask)
1516 cx88_core_irq(core,status);
8ddac9ee 1517 if (status & PCI_INT_VIDINT)
1da177e4 1518 cx8800_vid_irq(dev);
c2c1b415 1519 }
1da177e4
LT		 1520 if (10 == loop) {
1521 printk(KERN_WARNING "%s/0: irq loop -- clearing mask\n",
1522 core->name);
1523 cx_write(MO_PCI_INTMSK,0);
1524 }
1525
1526 out:
1527 return IRQ_RETVAL(handled);
1528}
1529
1530/* ----------------------------------------------------------- */
1531/* exported stuff */
1532
bec43661 1533static const struct v4l2_file_operations video_fops =
1da177e4
LT		 1534{
1535 .owner = THIS_MODULE,
1536 .open = video_open,
1537 .release = video_release,
1538 .read = video_read,
1539 .poll = video_poll,
1540 .mmap = video_mmap,
b6187264 1541 .unlocked_ioctl = video_ioctl2,
1da177e4
LT		 1542};
1543
a399810c 1544static const struct v4l2_ioctl_ops video_ioctl_ops = {
8d87cb9f 1545 .vidioc_querycap = vidioc_querycap,
78b526a4
HV		 1546 .vidioc_enum_fmt_vid_cap = vidioc_enum_fmt_vid_cap,
1547 .vidioc_g_fmt_vid_cap = vidioc_g_fmt_vid_cap,
1548 .vidioc_try_fmt_vid_cap = vidioc_try_fmt_vid_cap,
1549 .vidioc_s_fmt_vid_cap = vidioc_s_fmt_vid_cap,
8d87cb9f
MCC		 1550 .vidioc_reqbufs = vidioc_reqbufs,
1551 .vidioc_querybuf = vidioc_querybuf,
1552 .vidioc_qbuf = vidioc_qbuf,
1553 .vidioc_dqbuf = vidioc_dqbuf,
48d68801 1554 .vidioc_g_std = vidioc_g_std,
8d87cb9f
MCC		 1555 .vidioc_s_std = vidioc_s_std,
1556 .vidioc_enum_input = vidioc_enum_input,
1557 .vidioc_g_input = vidioc_g_input,
1558 .vidioc_s_input = vidioc_s_input,
8d87cb9f
MCC		 1559 .vidioc_streamon = vidioc_streamon,
1560 .vidioc_streamoff = vidioc_streamoff,
8d87cb9f
MCC		 1561 .vidioc_g_tuner = vidioc_g_tuner,
1562 .vidioc_s_tuner = vidioc_s_tuner,
1563 .vidioc_g_frequency = vidioc_g_frequency,
1564 .vidioc_s_frequency = vidioc_s_frequency,
1a3c60a0
HV		 1565 .vidioc_subscribe_event = v4l2_ctrl_subscribe_event,
1566 .vidioc_unsubscribe_event = v4l2_event_unsubscribe,
dbbff48f
TP		 1567#ifdef CONFIG_VIDEO_ADV_DEBUG
1568 .vidioc_g_register = vidioc_g_register,
1569 .vidioc_s_register = vidioc_s_register,
1570#endif
a399810c
HV		 1571};
1572
2e4e98e7 1573static const struct video_device cx8800_video_template = {
a399810c 1574 .name = "cx8800-video",
a399810c 1575 .fops = &video_fops,
a399810c 1576 .ioctl_ops = &video_ioctl_ops,
63ab1bdc 1577 .tvnorms = CX88_NORMS,
1da177e4
LT		 1578};
1579
f33e9868
HV		 1580static const struct v4l2_ioctl_ops vbi_ioctl_ops = {
1581 .vidioc_querycap = vidioc_querycap,
1582 .vidioc_g_fmt_vbi_cap = cx8800_vbi_fmt,
1583 .vidioc_try_fmt_vbi_cap = cx8800_vbi_fmt,
1584 .vidioc_s_fmt_vbi_cap = cx8800_vbi_fmt,
1585 .vidioc_reqbufs = vidioc_reqbufs,
1586 .vidioc_querybuf = vidioc_querybuf,
1587 .vidioc_qbuf = vidioc_qbuf,
1588 .vidioc_dqbuf = vidioc_dqbuf,
48d68801 1589 .vidioc_g_std = vidioc_g_std,
f33e9868
HV		 1590 .vidioc_s_std = vidioc_s_std,
1591 .vidioc_enum_input = vidioc_enum_input,
1592 .vidioc_g_input = vidioc_g_input,
1593 .vidioc_s_input = vidioc_s_input,
1594 .vidioc_streamon = vidioc_streamon,
1595 .vidioc_streamoff = vidioc_streamoff,
1596 .vidioc_g_tuner = vidioc_g_tuner,
1597 .vidioc_s_tuner = vidioc_s_tuner,
1598 .vidioc_g_frequency = vidioc_g_frequency,
1599 .vidioc_s_frequency = vidioc_s_frequency,
f33e9868
HV		 1600#ifdef CONFIG_VIDEO_ADV_DEBUG
1601 .vidioc_g_register = vidioc_g_register,
1602 .vidioc_s_register = vidioc_s_register,
1603#endif
1604};
1605
1606static const struct video_device cx8800_vbi_template = {
1607 .name = "cx8800-vbi",
1608 .fops = &video_fops,
1609 .ioctl_ops = &vbi_ioctl_ops,
1610 .tvnorms = CX88_NORMS,
f33e9868
HV		 1611};
1612
bec43661 1613static const struct v4l2_file_operations radio_fops =
1da177e4
LT		 1614{
1615 .owner = THIS_MODULE,
1616 .open = video_open,
1a3c60a0 1617 .poll = v4l2_ctrl_poll,
1da177e4 1618 .release = video_release,
b6187264 1619 .unlocked_ioctl = video_ioctl2,
1da177e4
LT		 1620};
1621
a399810c 1622static const struct v4l2_ioctl_ops radio_ioctl_ops = {
902e197d 1623 .vidioc_querycap = vidioc_querycap,
8d87cb9f 1624 .vidioc_g_tuner = radio_g_tuner,
8d87cb9f 1625 .vidioc_s_tuner = radio_s_tuner,
8d87cb9f
MCC		 1626 .vidioc_g_frequency = vidioc_g_frequency,
1627 .vidioc_s_frequency = vidioc_s_frequency,
1a3c60a0
HV		 1628 .vidioc_subscribe_event = v4l2_ctrl_subscribe_event,
1629 .vidioc_unsubscribe_event = v4l2_event_unsubscribe,
a75d2048
TP		 1630#ifdef CONFIG_VIDEO_ADV_DEBUG
1631 .vidioc_g_register = vidioc_g_register,
1632 .vidioc_s_register = vidioc_s_register,
1633#endif
1da177e4
LT		 1634};
1635
2e4e98e7 1636static const struct video_device cx8800_radio_template = {
a399810c 1637 .name = "cx8800-radio",
a399810c 1638 .fops = &radio_fops,
a399810c
HV		 1639 .ioctl_ops = &radio_ioctl_ops,
1640};
1641
8c7cb12a
HV		 1642static const struct v4l2_ctrl_ops cx8800_ctrl_vid_ops = {
1643 .s_ctrl = cx8800_s_vid_ctrl,
1644};
1645
1646static const struct v4l2_ctrl_ops cx8800_ctrl_aud_ops = {
1647 .s_ctrl = cx8800_s_aud_ctrl,
bac63981
HV		 1648};
1649
1da177e4
LT		 1650/* ----------------------------------------------------------- */
1651
1652static void cx8800_unregister_video(struct cx8800_dev *dev)
1653{
1654 if (dev->radio_dev) {
f0813b4c 1655 if (video_is_registered(dev->radio_dev))
1da177e4
LT		 1656 video_unregister_device(dev->radio_dev);
1657 else
1658 video_device_release(dev->radio_dev);
1659 dev->radio_dev = NULL;
1660 }
1661 if (dev->vbi_dev) {
f0813b4c 1662 if (video_is_registered(dev->vbi_dev))
1da177e4
LT		 1663 video_unregister_device(dev->vbi_dev);
1664 else
1665 video_device_release(dev->vbi_dev);
1666 dev->vbi_dev = NULL;
1667 }
1668 if (dev->video_dev) {
f0813b4c 1669 if (video_is_registered(dev->video_dev))
1da177e4
LT		 1670 video_unregister_device(dev->video_dev);
1671 else
1672 video_device_release(dev->video_dev);
1673 dev->video_dev = NULL;
1674 }
1675}
1676
4c62e976
GKH		 1677static int cx8800_initdev(struct pci_dev *pci_dev,
1678 const struct pci_device_id *pci_id)
1da177e4
LT		 1679{
1680 struct cx8800_dev *dev;
1681 struct cx88_core *core;
1682 int err;
bac63981 1683 int i;
1da177e4 1684
7408187d 1685 dev = kzalloc(sizeof(*dev),GFP_KERNEL);
1da177e4
LT		 1686 if (NULL == dev)
1687 return -ENOMEM;
1da177e4
LT		 1688
1689 /* pci init */
1690 dev->pci = pci_dev;
1691 if (pci_enable_device(pci_dev)) {
1692 err = -EIO;
1693 goto fail_free;
1694 }
1695 core = cx88_core_get(dev->pci);
1696 if (NULL == core) {
1697 err = -EINVAL;
1698 goto fail_free;
1699 }
1700 dev->core = core;
1701
1702 /* print pci info */
abd34d8d 1703 dev->pci_rev = pci_dev->revision;
4ac97914
MCC		 1704 pci_read_config_byte(pci_dev, PCI_LATENCY_TIMER, &dev->pci_lat);
1705 printk(KERN_INFO "%s/0: found at %s, rev: %d, irq: %d, "
228aef63 1706 "latency: %d, mmio: 0x%llx\n", core->name,
1da177e4 1707 pci_name(pci_dev), dev->pci_rev, pci_dev->irq,
228aef63 1708 dev->pci_lat,(unsigned long long)pci_resource_start(pci_dev,0));
1da177e4
LT		 1709
1710 pci_set_master(pci_dev);
284901a9 1711 if (!pci_dma_supported(pci_dev,DMA_BIT_MASK(32))) {
1da177e4
LT		 1712 printk("%s/0: Oops: no 32bit PCI DMA ???\n",core->name);
1713 err = -EIO;
1714 goto fail_core;
1715 }
1716
1717 /* initialize driver struct */
1da177e4 1718 spin_lock_init(&dev->slock);
48d68801 1719 core->tvnorm = V4L2_STD_NTSC_M;
1da177e4
LT		 1720
1721 /* init video dma queues */
1722 INIT_LIST_HEAD(&dev->vidq.active);
1723 INIT_LIST_HEAD(&dev->vidq.queued);
1724 dev->vidq.timeout.function = cx8800_vid_timeout;
1725 dev->vidq.timeout.data = (unsigned long)dev;
1726 init_timer(&dev->vidq.timeout);
1727 cx88_risc_stopper(dev->pci,&dev->vidq.stopper,
1728 MO_VID_DMACNTRL,0x11,0x00);
1729
1730 /* init vbi dma queues */
1731 INIT_LIST_HEAD(&dev->vbiq.active);
1732 INIT_LIST_HEAD(&dev->vbiq.queued);
1733 dev->vbiq.timeout.function = cx8800_vbi_timeout;
1734 dev->vbiq.timeout.data = (unsigned long)dev;
1735 init_timer(&dev->vbiq.timeout);
1736 cx88_risc_stopper(dev->pci,&dev->vbiq.stopper,
1737 MO_VID_DMACNTRL,0x88,0x00);
1738
1739 /* get irq */
1740 err = request_irq(pci_dev->irq, cx8800_irq,
8076fe32 1741 IRQF_SHARED | IRQF_DISABLED, core->name, dev);
1da177e4 1742 if (err < 0) {
5772f813 1743 printk(KERN_ERR "%s/0: can't get IRQ %d\n",
1da177e4
LT		 1744 core->name,pci_dev->irq);
1745 goto fail_core;
1746 }
1747 cx_set(MO_PCI_INTMSK, core->pci_irqmask);
1748
8c7cb12a
HV		 1749 for (i = 0; i < CX8800_AUD_CTLS; i++) {
1750 const struct cx88_ctrl *cc = &cx8800_aud_ctls[i];
1751 struct v4l2_ctrl *vc;
1752
1753 vc = v4l2_ctrl_new_std(&core->audio_hdl, &cx8800_ctrl_aud_ops,
1754 cc->id, cc->minimum, cc->maximum, cc->step, cc->default_value);
1755 if (vc == NULL) {
1756 err = core->audio_hdl.error;
1757 goto fail_core;
1758 }
1759 vc->priv = (void *)cc;
1760 }
1761
1762 for (i = 0; i < CX8800_VID_CTLS; i++) {
1763 const struct cx88_ctrl *cc = &cx8800_vid_ctls[i];
bac63981
HV		 1764 struct v4l2_ctrl *vc;
1765
8c7cb12a 1766 vc = v4l2_ctrl_new_std(&core->video_hdl, &cx8800_ctrl_vid_ops,
bac63981
HV		 1767 cc->id, cc->minimum, cc->maximum, cc->step, cc->default_value);
1768 if (vc == NULL) {
8c7cb12a 1769 err = core->video_hdl.error;
bac63981
HV		 1770 goto fail_core;
1771 }
1772 vc->priv = (void *)cc;
8c7cb12a
HV		 1773 if (vc->id == V4L2_CID_CHROMA_AGC)
1774 core->chroma_agc = vc;
bac63981 1775 }
34a6b7d0 1776 v4l2_ctrl_add_handler(&core->video_hdl, &core->audio_hdl, NULL);
bac63981 1777
1da177e4 1778 /* load and configure helper modules */
e52e98a7 1779
facd2366 1780 if (core->board.audio_chip == CX88_AUDIO_WM8775) {
6951803c
LR		 1781 struct i2c_board_info wm8775_info = {
1782 .type = "wm8775",
1783 .addr = 0x36 >> 1,
1784 .platform_data = &core->wm8775_data,
1785 };
1786 struct v4l2_subdev *sd;
1787
1788 if (core->boardnr == CX88_BOARD_HAUPPAUGE_NOVASPLUS_S1)
1789 core->wm8775_data.is_nova_s = true;
1790 else
1791 core->wm8775_data.is_nova_s = false;
1792
1793 sd = v4l2_i2c_new_subdev_board(&core->v4l2_dev, &core->i2c_adap,
1794 &wm8775_info, NULL);
bac63981
HV		 1795 if (sd != NULL) {
1796 core->sd_wm8775 = sd;
6951803c 1797 sd->grp_id = WM8775_GID;
bac63981 1798 }
6951803c 1799 }
b8341e1d 1800
facd2366 1801 if (core->board.audio_chip == CX88_AUDIO_TVAUDIO) {
b8341e1d
HV		 1802 /* This probes for a tda9874 as is used on some
1803 Pixelview Ultra boards. */
9a1f8b34
LP		 1804 v4l2_i2c_new_subdev(&core->v4l2_dev, &core->i2c_adap,
1805 "tvaudio", 0, I2C_ADDRS(0xb0 >> 1));
b8341e1d 1806 }
3057906d 1807
6fcecce7
MK		 1808 switch (core->boardnr) {
1809 case CX88_BOARD_DVICO_FUSIONHDTV_5_GOLD:
b8341e1d 1810 case CX88_BOARD_DVICO_FUSIONHDTV_7_GOLD: {
2e4e98e7 1811 static const struct i2c_board_info rtc_info = {
b8341e1d
HV		 1812 I2C_BOARD_INFO("isl1208", 0x6f)
1813 };
1814
6fcecce7 1815 request_module("rtc-isl1208");
b8341e1d
HV		 1816 core->i2c_rtc = i2c_new_device(&core->i2c_adap, &rtc_info);
1817 }
8efd2e28
MK		 1818 /* break intentionally omitted */
1819 case CX88_BOARD_DVICO_FUSIONHDTV_5_PCI_NANO:
1820 request_module("ir-kbd-i2c");
6fcecce7
MK		 1821 }
1822
121ec132
MCC		 1823 /* Sets device info at pci_dev */
1824 pci_set_drvdata(pci_dev, dev);
1825
c5a86144
HV		 1826 dev->width = 320;
1827 dev->height = 240;
1828 dev->fmt = format_by_fourcc(V4L2_PIX_FMT_BGR24);
1829
121ec132
MCC		 1830 /* initial device configuration */
1831 mutex_lock(&core->lock);
1832 cx88_set_tvnorm(core, core->tvnorm);
8c7cb12a
HV		 1833 v4l2_ctrl_handler_setup(&core->video_hdl);
1834 v4l2_ctrl_handler_setup(&core->audio_hdl);
121ec132
MCC		 1835 cx88_video_mux(core, 0);
1836
1da177e4
LT		 1837 /* register v4l devices */
1838 dev->video_dev = cx88_vdev_init(core,dev->pci,
1839 &cx8800_video_template,"video");
63b0d5ad 1840 video_set_drvdata(dev->video_dev, dev);
8c7cb12a 1841 dev->video_dev->ctrl_handler = &core->video_hdl;
1da177e4
LT		 1842 err = video_register_device(dev->video_dev,VFL_TYPE_GRABBER,
1843 video_nr[core->nr]);
1844 if (err < 0) {
5772f813 1845 printk(KERN_ERR "%s/0: can't register video device\n",
1da177e4
LT		 1846 core->name);
1847 goto fail_unreg;
1848 }
38c7c036
LP		 1849 printk(KERN_INFO "%s/0: registered device %s [v4l2]\n",
1850 core->name, video_device_node_name(dev->video_dev));
1da177e4
LT		 1851
1852 dev->vbi_dev = cx88_vdev_init(core,dev->pci,&cx8800_vbi_template,"vbi");
63b0d5ad 1853 video_set_drvdata(dev->vbi_dev, dev);
1da177e4
LT		 1854 err = video_register_device(dev->vbi_dev,VFL_TYPE_VBI,
1855 vbi_nr[core->nr]);
1856 if (err < 0) {
5772f813 1857 printk(KERN_ERR "%s/0: can't register vbi device\n",
1da177e4
LT		 1858 core->name);
1859 goto fail_unreg;
1860 }
38c7c036
LP		 1861 printk(KERN_INFO "%s/0: registered device %s\n",
1862 core->name, video_device_node_name(dev->vbi_dev));
1da177e4 1863
6a59d64c 1864 if (core->board.radio.type == CX88_RADIO) {
1da177e4
LT		 1865 dev->radio_dev = cx88_vdev_init(core,dev->pci,
1866 &cx8800_radio_template,"radio");
63b0d5ad 1867 video_set_drvdata(dev->radio_dev, dev);
8c7cb12a 1868 dev->radio_dev->ctrl_handler = &core->audio_hdl;
1da177e4
LT		 1869 err = video_register_device(dev->radio_dev,VFL_TYPE_RADIO,
1870 radio_nr[core->nr]);
1871 if (err < 0) {
5772f813 1872 printk(KERN_ERR "%s/0: can't register radio device\n",
1da177e4
LT		 1873 core->name);
1874 goto fail_unreg;
1875 }
38c7c036
LP		 1876 printk(KERN_INFO "%s/0: registered device %s\n",
1877 core->name, video_device_node_name(dev->radio_dev));
1da177e4
LT		 1878 }
1879
1da177e4 1880 /* start tvaudio thread */
6a59d64c 1881 if (core->board.tuner_type != TUNER_ABSENT) {
1da177e4 1882 core->kthread = kthread_run(cx88_audio_thread, core, "cx88 tvaudio");
32b78de7
CG		 1883 if (IS_ERR(core->kthread)) {
1884 err = PTR_ERR(core->kthread);
5772f813
TP		 1885 printk(KERN_ERR "%s/0: failed to create cx88 audio thread, err=%d\n",
1886 core->name, err);
32b78de7
CG		 1887 }
1888 }
121ec132
MCC		 1889 mutex_unlock(&core->lock);
1890
1da177e4
LT		 1891 return 0;
1892
1893fail_unreg:
1894 cx8800_unregister_video(dev);
1895 free_irq(pci_dev->irq, dev);
121ec132 1896 mutex_unlock(&core->lock);
1da177e4
LT		 1897fail_core:
1898 cx88_core_put(core,dev->pci);
1899fail_free:
1900 kfree(dev);
1901 return err;
1902}
1903
4c62e976 1904static void cx8800_finidev(struct pci_dev *pci_dev)
1da177e4 1905{
4ac97914 1906 struct cx8800_dev *dev = pci_get_drvdata(pci_dev);
e52e98a7 1907 struct cx88_core *core = dev->core;
1da177e4
LT		 1908
1909 /* stop thread */
e52e98a7
MCC		 1910 if (core->kthread) {
1911 kthread_stop(core->kthread);
1912 core->kthread = NULL;
1da177e4
LT		 1913 }
1914
b12203d2 1915 if (core->ir)
92f4fc10 1916 cx88_ir_stop(core);
b12203d2 1917
e52e98a7 1918 cx88_shutdown(core); /* FIXME */
1da177e4
LT		 1919 pci_disable_device(pci_dev);
1920
1921 /* unregister stuff */
1922
1923 free_irq(pci_dev->irq, dev);
1924 cx8800_unregister_video(dev);
1da177e4
LT		 1925
1926 /* free memory */
1927 btcx_riscmem_free(dev->pci,&dev->vidq.stopper);
e52e98a7 1928 cx88_core_put(core,dev->pci);
1da177e4
LT		 1929 kfree(dev);
1930}
1931
17bc98a4 1932#ifdef CONFIG_PM
1da177e4
LT		 1933static int cx8800_suspend(struct pci_dev *pci_dev, pm_message_t state)
1934{
b45009b0 1935 struct cx8800_dev *dev = pci_get_drvdata(pci_dev);
1da177e4 1936 struct cx88_core *core = dev->core;
5ddfbbb9 1937 unsigned long flags;
1da177e4
LT		 1938
1939 /* stop video+vbi capture */
5ddfbbb9 1940 spin_lock_irqsave(&dev->slock, flags);
1da177e4 1941 if (!list_empty(&dev->vidq.active)) {
5772f813 1942 printk("%s/0: suspend video\n", core->name);
1da177e4
LT		 1943 stop_video_dma(dev);
1944 del_timer(&dev->vidq.timeout);
1945 }
1946 if (!list_empty(&dev->vbiq.active)) {
5772f813 1947 printk("%s/0: suspend vbi\n", core->name);
1da177e4
LT		 1948 cx8800_stop_vbi_dma(dev);
1949 del_timer(&dev->vbiq.timeout);
1950 }
5ddfbbb9 1951 spin_unlock_irqrestore(&dev->slock, flags);
1da177e4 1952
13595a51 1953 if (core->ir)
92f4fc10 1954 cx88_ir_stop(core);
1da177e4 1955 /* FIXME -- shutdown device */
e52e98a7 1956 cx88_shutdown(core);
1da177e4
LT		 1957
1958 pci_save_state(pci_dev);
1959 if (0 != pci_set_power_state(pci_dev, pci_choose_state(pci_dev, state))) {
1960 pci_disable_device(pci_dev);
1961 dev->state.disabled = 1;
1962 }
1963 return 0;
1964}
1965
1966static int cx8800_resume(struct pci_dev *pci_dev)
1967{
b45009b0 1968 struct cx8800_dev *dev = pci_get_drvdata(pci_dev);
1da177e4 1969 struct cx88_core *core = dev->core;
5ddfbbb9 1970 unsigned long flags;
08adb9e2 1971 int err;
1da177e4
LT		 1972
1973 if (dev->state.disabled) {
08adb9e2
MCC		 1974 err=pci_enable_device(pci_dev);
1975 if (err) {
5772f813
TP		 1976 printk(KERN_ERR "%s/0: can't enable device\n",
1977 core->name);
08adb9e2
MCC		 1978 return err;
1979 }
1980
1da177e4
LT		 1981 dev->state.disabled = 0;
1982 }
08adb9e2
MCC		 1983 err= pci_set_power_state(pci_dev, PCI_D0);
1984 if (err) {
5772f813 1985 printk(KERN_ERR "%s/0: can't set power state\n", core->name);
08adb9e2
MCC		 1986 pci_disable_device(pci_dev);
1987 dev->state.disabled = 1;
1988
1989 return err;
1990 }
1da177e4
LT		 1991 pci_restore_state(pci_dev);
1992
1da177e4 1993 /* FIXME: re-initialize hardware */
e52e98a7 1994 cx88_reset(core);
13595a51 1995 if (core->ir)
92f4fc10 1996 cx88_ir_start(core);
13595a51
MCC		 1997
1998 cx_set(MO_PCI_INTMSK, core->pci_irqmask);
1da177e4
LT		 1999
2000 /* restart video+vbi capture */
5ddfbbb9 2001 spin_lock_irqsave(&dev->slock, flags);
1da177e4 2002 if (!list_empty(&dev->vidq.active)) {
5772f813 2003 printk("%s/0: resume video\n", core->name);
1da177e4
LT		 2004 restart_video_queue(dev,&dev->vidq);
2005 }
2006 if (!list_empty(&dev->vbiq.active)) {
5772f813 2007 printk("%s/0: resume vbi\n", core->name);
1da177e4
LT		 2008 cx8800_restart_vbi_queue(dev,&dev->vbiq);
2009 }
5ddfbbb9 2010 spin_unlock_irqrestore(&dev->slock, flags);
1da177e4
LT		 2011
2012 return 0;
2013}
17bc98a4 2014#endif
1da177e4
LT		 2015
2016/* ----------------------------------------------------------- */
2017
2e4e98e7 2018static const struct pci_device_id cx8800_pci_tbl[] = {
1da177e4
LT		 2019 {
2020 .vendor = 0x14f1,
2021 .device = 0x8800,
b45009b0
MCC		 2022 .subvendor = PCI_ANY_ID,
2023 .subdevice = PCI_ANY_ID,
1da177e4
LT		 2024 },{
2025 /* --- end of list --- */
2026 }
2027};
2028MODULE_DEVICE_TABLE(pci, cx8800_pci_tbl);
2029
2030static struct pci_driver cx8800_pci_driver = {
b45009b0
MCC		 2031 .name = "cx8800",
2032 .id_table = cx8800_pci_tbl,
2033 .probe = cx8800_initdev,
4c62e976 2034 .remove = cx8800_finidev,
17bc98a4 2035#ifdef CONFIG_PM
1da177e4
LT		 2036 .suspend = cx8800_suspend,
2037 .resume = cx8800_resume,
17bc98a4 2038#endif
1da177e4
LT		 2039};
2040
06333e0a 2041module_pci_driver(cx8800_pci_driver);
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