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Commit | Line | Data |
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1da177e4 | 1 | /* |
1da177e4 LT |
2 | * |
3 | * device driver for Conexant 2388x based TV cards | |
4 | * video4linux video interface | |
5 | * | |
6 | * (c) 2003-04 Gerd Knorr <kraxel@bytesex.org> [SuSE Labs] | |
7 | * | |
8d87cb9f MCC |
8 | * (c) 2005-2006 Mauro Carvalho Chehab <mchehab@infradead.org> |
9 | * - Multituner support | |
10 | * - video_ioctl2 conversion | |
11 | * - PAL/M fixes | |
12 | * | |
1da177e4 LT |
13 | * This program is free software; you can redistribute it and/or modify |
14 | * it under the terms of the GNU General Public License as published by | |
15 | * the Free Software Foundation; either version 2 of the License, or | |
16 | * (at your option) any later version. | |
17 | * | |
18 | * This program is distributed in the hope that it will be useful, | |
19 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
20 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
21 | * GNU General Public License for more details. | |
22 | * | |
23 | * You should have received a copy of the GNU General Public License | |
24 | * along with this program; if not, write to the Free Software | |
25 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
26 | */ | |
27 | ||
28 | #include <linux/init.h> | |
29 | #include <linux/list.h> | |
30 | #include <linux/module.h> | |
1da177e4 LT |
31 | #include <linux/kmod.h> |
32 | #include <linux/kernel.h> | |
33 | #include <linux/slab.h> | |
34 | #include <linux/interrupt.h> | |
c24228da | 35 | #include <linux/dma-mapping.h> |
1da177e4 LT |
36 | #include <linux/delay.h> |
37 | #include <linux/kthread.h> | |
38 | #include <asm/div64.h> | |
39 | ||
40 | #include "cx88.h" | |
5e453dc7 | 41 | #include <media/v4l2-common.h> |
35ea11ff | 42 | #include <media/v4l2-ioctl.h> |
1a3c60a0 | 43 | #include <media/v4l2-event.h> |
6951803c | 44 | #include <media/wm8775.h> |
1da177e4 LT |
45 | |
46 | MODULE_DESCRIPTION("v4l2 driver module for cx2388x based TV cards"); | |
47 | MODULE_AUTHOR("Gerd Knorr <kraxel@bytesex.org> [SuSE Labs]"); | |
48 | MODULE_LICENSE("GPL"); | |
1990d50b | 49 | MODULE_VERSION(CX88_VERSION); |
1da177e4 LT |
50 | |
51 | /* ------------------------------------------------------------------ */ | |
52 | ||
53 | static unsigned int video_nr[] = {[0 ... (CX88_MAXBOARDS - 1)] = UNSET }; | |
54 | static unsigned int vbi_nr[] = {[0 ... (CX88_MAXBOARDS - 1)] = UNSET }; | |
55 | static unsigned int radio_nr[] = {[0 ... (CX88_MAXBOARDS - 1)] = UNSET }; | |
56 | ||
57 | module_param_array(video_nr, int, NULL, 0444); | |
58 | module_param_array(vbi_nr, int, NULL, 0444); | |
59 | module_param_array(radio_nr, int, NULL, 0444); | |
60 | ||
61 | MODULE_PARM_DESC(video_nr,"video device numbers"); | |
62 | MODULE_PARM_DESC(vbi_nr,"vbi device numbers"); | |
63 | MODULE_PARM_DESC(radio_nr,"radio device numbers"); | |
64 | ||
ff699e6b | 65 | static unsigned int video_debug; |
1da177e4 LT |
66 | module_param(video_debug,int,0644); |
67 | MODULE_PARM_DESC(video_debug,"enable debug messages [video]"); | |
68 | ||
ff699e6b | 69 | static unsigned int irq_debug; |
1da177e4 LT |
70 | module_param(irq_debug,int,0644); |
71 | MODULE_PARM_DESC(irq_debug,"enable debug messages [IRQ handler]"); | |
72 | ||
73 | static unsigned int vid_limit = 16; | |
74 | module_param(vid_limit,int,0644); | |
75 | MODULE_PARM_DESC(vid_limit,"capture memory limit in megabytes"); | |
76 | ||
77 | #define dprintk(level,fmt, arg...) if (video_debug >= level) \ | |
e52e98a7 | 78 | printk(KERN_DEBUG "%s/0: " fmt, core->name , ## arg) |
1da177e4 | 79 | |
1da177e4 LT |
80 | /* ------------------------------------------------------------------- */ |
81 | /* static data */ | |
82 | ||
2e4e98e7 | 83 | static const struct cx8800_fmt formats[] = { |
1da177e4 LT |
84 | { |
85 | .name = "8 bpp, gray", | |
86 | .fourcc = V4L2_PIX_FMT_GREY, | |
87 | .cxformat = ColorFormatY8, | |
88 | .depth = 8, | |
89 | .flags = FORMAT_FLAGS_PACKED, | |
90 | },{ | |
91 | .name = "15 bpp RGB, le", | |
92 | .fourcc = V4L2_PIX_FMT_RGB555, | |
93 | .cxformat = ColorFormatRGB15, | |
94 | .depth = 16, | |
95 | .flags = FORMAT_FLAGS_PACKED, | |
96 | },{ | |
97 | .name = "15 bpp RGB, be", | |
98 | .fourcc = V4L2_PIX_FMT_RGB555X, | |
99 | .cxformat = ColorFormatRGB15 | ColorFormatBSWAP, | |
100 | .depth = 16, | |
101 | .flags = FORMAT_FLAGS_PACKED, | |
102 | },{ | |
103 | .name = "16 bpp RGB, le", | |
104 | .fourcc = V4L2_PIX_FMT_RGB565, | |
105 | .cxformat = ColorFormatRGB16, | |
106 | .depth = 16, | |
107 | .flags = FORMAT_FLAGS_PACKED, | |
108 | },{ | |
109 | .name = "16 bpp RGB, be", | |
110 | .fourcc = V4L2_PIX_FMT_RGB565X, | |
111 | .cxformat = ColorFormatRGB16 | ColorFormatBSWAP, | |
112 | .depth = 16, | |
113 | .flags = FORMAT_FLAGS_PACKED, | |
114 | },{ | |
115 | .name = "24 bpp RGB, le", | |
116 | .fourcc = V4L2_PIX_FMT_BGR24, | |
117 | .cxformat = ColorFormatRGB24, | |
118 | .depth = 24, | |
119 | .flags = FORMAT_FLAGS_PACKED, | |
120 | },{ | |
121 | .name = "32 bpp RGB, le", | |
122 | .fourcc = V4L2_PIX_FMT_BGR32, | |
123 | .cxformat = ColorFormatRGB32, | |
124 | .depth = 32, | |
125 | .flags = FORMAT_FLAGS_PACKED, | |
126 | },{ | |
127 | .name = "32 bpp RGB, be", | |
128 | .fourcc = V4L2_PIX_FMT_RGB32, | |
129 | .cxformat = ColorFormatRGB32 | ColorFormatBSWAP | ColorFormatWSWAP, | |
130 | .depth = 32, | |
131 | .flags = FORMAT_FLAGS_PACKED, | |
132 | },{ | |
133 | .name = "4:2:2, packed, YUYV", | |
134 | .fourcc = V4L2_PIX_FMT_YUYV, | |
135 | .cxformat = ColorFormatYUY2, | |
136 | .depth = 16, | |
137 | .flags = FORMAT_FLAGS_PACKED, | |
138 | },{ | |
139 | .name = "4:2:2, packed, UYVY", | |
140 | .fourcc = V4L2_PIX_FMT_UYVY, | |
141 | .cxformat = ColorFormatYUY2 | ColorFormatBSWAP, | |
142 | .depth = 16, | |
143 | .flags = FORMAT_FLAGS_PACKED, | |
144 | }, | |
145 | }; | |
146 | ||
2e4e98e7 | 147 | static const struct cx8800_fmt* format_by_fourcc(unsigned int fourcc) |
1da177e4 LT |
148 | { |
149 | unsigned int i; | |
150 | ||
151 | for (i = 0; i < ARRAY_SIZE(formats); i++) | |
152 | if (formats[i].fourcc == fourcc) | |
153 | return formats+i; | |
154 | return NULL; | |
155 | } | |
156 | ||
157 | /* ------------------------------------------------------------------- */ | |
158 | ||
bac63981 HV |
159 | struct cx88_ctrl { |
160 | /* control information */ | |
161 | u32 id; | |
162 | s32 minimum; | |
163 | s32 maximum; | |
164 | u32 step; | |
165 | s32 default_value; | |
166 | ||
167 | /* control register information */ | |
168 | u32 off; | |
169 | u32 reg; | |
170 | u32 sreg; | |
171 | u32 mask; | |
172 | u32 shift; | |
173 | }; | |
174 | ||
8c7cb12a | 175 | static const struct cx88_ctrl cx8800_vid_ctls[] = { |
1da177e4 LT |
176 | /* --- video --- */ |
177 | { | |
bac63981 HV |
178 | .id = V4L2_CID_BRIGHTNESS, |
179 | .minimum = 0x00, | |
180 | .maximum = 0xff, | |
181 | .step = 1, | |
182 | .default_value = 0x7f, | |
183 | .off = 128, | |
184 | .reg = MO_CONTR_BRIGHT, | |
185 | .mask = 0x00ff, | |
186 | .shift = 0, | |
1da177e4 | 187 | },{ |
bac63981 HV |
188 | .id = V4L2_CID_CONTRAST, |
189 | .minimum = 0, | |
190 | .maximum = 0xff, | |
191 | .step = 1, | |
192 | .default_value = 0x3f, | |
193 | .off = 0, | |
194 | .reg = MO_CONTR_BRIGHT, | |
195 | .mask = 0xff00, | |
196 | .shift = 8, | |
1da177e4 | 197 | },{ |
bac63981 HV |
198 | .id = V4L2_CID_HUE, |
199 | .minimum = 0, | |
200 | .maximum = 0xff, | |
201 | .step = 1, | |
202 | .default_value = 0x7f, | |
203 | .off = 128, | |
204 | .reg = MO_HUE, | |
205 | .mask = 0x00ff, | |
206 | .shift = 0, | |
1da177e4 LT |
207 | },{ |
208 | /* strictly, this only describes only U saturation. | |
209 | * V saturation is handled specially through code. | |
210 | */ | |
bac63981 HV |
211 | .id = V4L2_CID_SATURATION, |
212 | .minimum = 0, | |
213 | .maximum = 0xff, | |
214 | .step = 1, | |
215 | .default_value = 0x7f, | |
216 | .off = 0, | |
217 | .reg = MO_UV_SATURATION, | |
218 | .mask = 0x00ff, | |
219 | .shift = 0, | |
eea16e36 | 220 | }, { |
bac63981 HV |
221 | .id = V4L2_CID_SHARPNESS, |
222 | .minimum = 0, | |
223 | .maximum = 4, | |
224 | .step = 1, | |
225 | .default_value = 0x0, | |
226 | .off = 0, | |
eea16e36 | 227 | /* NOTE: the value is converted and written to both even |
228 | and odd registers in the code */ | |
bac63981 HV |
229 | .reg = MO_FILTER_ODD, |
230 | .mask = 7 << 7, | |
231 | .shift = 7, | |
eea16e36 | 232 | }, { |
bac63981 HV |
233 | .id = V4L2_CID_CHROMA_AGC, |
234 | .minimum = 0, | |
235 | .maximum = 1, | |
236 | .default_value = 0x1, | |
237 | .reg = MO_INPUT_FORMAT, | |
238 | .mask = 1 << 10, | |
239 | .shift = 10, | |
1b879c43 | 240 | }, { |
bac63981 HV |
241 | .id = V4L2_CID_COLOR_KILLER, |
242 | .minimum = 0, | |
243 | .maximum = 1, | |
244 | .default_value = 0x1, | |
245 | .reg = MO_INPUT_FORMAT, | |
246 | .mask = 1 << 9, | |
247 | .shift = 9, | |
bded70d2 | 248 | }, { |
bac63981 HV |
249 | .id = V4L2_CID_BAND_STOP_FILTER, |
250 | .minimum = 0, | |
251 | .maximum = 1, | |
252 | .step = 1, | |
253 | .default_value = 0x0, | |
254 | .off = 0, | |
255 | .reg = MO_HTOTAL, | |
256 | .mask = 3 << 11, | |
257 | .shift = 11, | |
8c7cb12a HV |
258 | } |
259 | }; | |
260 | ||
261 | static const struct cx88_ctrl cx8800_aud_ctls[] = { | |
262 | { | |
bac63981 HV |
263 | /* --- audio --- */ |
264 | .id = V4L2_CID_AUDIO_MUTE, | |
265 | .minimum = 0, | |
266 | .maximum = 1, | |
267 | .default_value = 1, | |
268 | .reg = AUD_VOL_CTL, | |
269 | .sreg = SHADOW_AUD_VOL_CTL, | |
270 | .mask = (1 << 6), | |
271 | .shift = 6, | |
1da177e4 | 272 | },{ |
bac63981 HV |
273 | .id = V4L2_CID_AUDIO_VOLUME, |
274 | .minimum = 0, | |
275 | .maximum = 0x3f, | |
276 | .step = 1, | |
277 | .default_value = 0x3f, | |
278 | .reg = AUD_VOL_CTL, | |
279 | .sreg = SHADOW_AUD_VOL_CTL, | |
280 | .mask = 0x3f, | |
281 | .shift = 0, | |
1da177e4 | 282 | },{ |
bac63981 HV |
283 | .id = V4L2_CID_AUDIO_BALANCE, |
284 | .minimum = 0, | |
285 | .maximum = 0x7f, | |
286 | .step = 1, | |
287 | .default_value = 0x40, | |
288 | .reg = AUD_BAL_CTL, | |
289 | .sreg = SHADOW_AUD_BAL_CTL, | |
290 | .mask = 0x7f, | |
291 | .shift = 0, | |
1da177e4 LT |
292 | } |
293 | }; | |
1da177e4 | 294 | |
8c7cb12a HV |
295 | enum { |
296 | CX8800_VID_CTLS = ARRAY_SIZE(cx8800_vid_ctls), | |
297 | CX8800_AUD_CTLS = ARRAY_SIZE(cx8800_aud_ctls), | |
298 | }; | |
38a2713a | 299 | |
1da177e4 LT |
300 | /* ------------------------------------------------------------------- */ |
301 | /* resource management */ | |
302 | ||
303 | static int res_get(struct cx8800_dev *dev, struct cx8800_fh *fh, unsigned int bit) | |
304 | { | |
e52e98a7 | 305 | struct cx88_core *core = dev->core; |
1da177e4 LT |
306 | if (fh->resources & bit) |
307 | /* have it already allocated */ | |
308 | return 1; | |
309 | ||
310 | /* is it free? */ | |
3593cab5 | 311 | mutex_lock(&core->lock); |
1da177e4 LT |
312 | if (dev->resources & bit) { |
313 | /* no, someone else uses it */ | |
3593cab5 | 314 | mutex_unlock(&core->lock); |
1da177e4 LT |
315 | return 0; |
316 | } | |
317 | /* it's free, grab it */ | |
318 | fh->resources |= bit; | |
319 | dev->resources |= bit; | |
320 | dprintk(1,"res: get %d\n",bit); | |
3593cab5 | 321 | mutex_unlock(&core->lock); |
1da177e4 LT |
322 | return 1; |
323 | } | |
324 | ||
325 | static | |
326 | int res_check(struct cx8800_fh *fh, unsigned int bit) | |
327 | { | |
328 | return (fh->resources & bit); | |
329 | } | |
330 | ||
331 | static | |
332 | int res_locked(struct cx8800_dev *dev, unsigned int bit) | |
333 | { | |
334 | return (dev->resources & bit); | |
335 | } | |
336 | ||
337 | static | |
338 | void res_free(struct cx8800_dev *dev, struct cx8800_fh *fh, unsigned int bits) | |
339 | { | |
e52e98a7 | 340 | struct cx88_core *core = dev->core; |
ae24601b | 341 | BUG_ON((fh->resources & bits) != bits); |
1da177e4 | 342 | |
3593cab5 | 343 | mutex_lock(&core->lock); |
1da177e4 LT |
344 | fh->resources &= ~bits; |
345 | dev->resources &= ~bits; | |
346 | dprintk(1,"res: put %d\n",bits); | |
3593cab5 | 347 | mutex_unlock(&core->lock); |
1da177e4 LT |
348 | } |
349 | ||
350 | /* ------------------------------------------------------------------ */ | |
351 | ||
e90311a1 | 352 | int cx88_video_mux(struct cx88_core *core, unsigned int input) |
1da177e4 | 353 | { |
e52e98a7 | 354 | /* struct cx88_core *core = dev->core; */ |
1da177e4 LT |
355 | |
356 | dprintk(1,"video_mux: %d [vmux=%d,gpio=0x%x,0x%x,0x%x,0x%x]\n", | |
6a59d64c TP |
357 | input, INPUT(input).vmux, |
358 | INPUT(input).gpio0,INPUT(input).gpio1, | |
359 | INPUT(input).gpio2,INPUT(input).gpio3); | |
e52e98a7 | 360 | core->input = input; |
6a59d64c TP |
361 | cx_andor(MO_INPUT_FORMAT, 0x03 << 14, INPUT(input).vmux << 14); |
362 | cx_write(MO_GP3_IO, INPUT(input).gpio3); | |
363 | cx_write(MO_GP0_IO, INPUT(input).gpio0); | |
364 | cx_write(MO_GP1_IO, INPUT(input).gpio1); | |
365 | cx_write(MO_GP2_IO, INPUT(input).gpio2); | |
1da177e4 | 366 | |
6a59d64c | 367 | switch (INPUT(input).type) { |
1da177e4 LT |
368 | case CX88_VMUX_SVIDEO: |
369 | cx_set(MO_AFECFG_IO, 0x00000001); | |
370 | cx_set(MO_INPUT_FORMAT, 0x00010010); | |
371 | cx_set(MO_FILTER_EVEN, 0x00002020); | |
372 | cx_set(MO_FILTER_ODD, 0x00002020); | |
373 | break; | |
374 | default: | |
375 | cx_clear(MO_AFECFG_IO, 0x00000001); | |
376 | cx_clear(MO_INPUT_FORMAT, 0x00010010); | |
377 | cx_clear(MO_FILTER_EVEN, 0x00002020); | |
378 | cx_clear(MO_FILTER_ODD, 0x00002020); | |
379 | break; | |
380 | } | |
f24546a9 | 381 | |
66e6fbdf RC |
382 | /* if there are audioroutes defined, we have an external |
383 | ADC to deal with audio */ | |
66e6fbdf | 384 | if (INPUT(input).audioroute) { |
66e6fbdf RC |
385 | /* The wm8775 module has the "2" route hardwired into |
386 | the initialization. Some boards may use different | |
387 | routes for different inputs. HVR-1300 surely does */ | |
388 | if (core->board.audio_chip && | |
38f9d308 | 389 | core->board.audio_chip == V4L2_IDENT_WM8775) { |
5325b427 | 390 | call_all(core, audio, s_routing, |
6e1f4df7 | 391 | INPUT(input).audioroute, 0, 0); |
66e6fbdf | 392 | } |
430189da DB |
393 | /* cx2388's C-ADC is connected to the tuner only. |
394 | When used with S-Video, that ADC is busy dealing with | |
395 | chroma, so an external must be used for baseband audio */ | |
6e1f4df7 | 396 | if (INPUT(input).type != CX88_VMUX_TELEVISION && |
397 | INPUT(input).type != CX88_VMUX_CABLE) { | |
430189da DB |
398 | /* "I2S ADC mode" */ |
399 | core->tvaudio = WW_I2SADC; | |
400 | cx88_set_tvaudio(core); | |
401 | } else { | |
402 | /* Normal mode */ | |
403 | cx_write(AUD_I2SCNTL, 0x0); | |
404 | cx_clear(AUD_CTL, EN_I2SIN_ENABLE); | |
405 | } | |
f24546a9 | 406 | } |
66e6fbdf | 407 | |
1da177e4 LT |
408 | return 0; |
409 | } | |
e90311a1 | 410 | EXPORT_SYMBOL(cx88_video_mux); |
1da177e4 LT |
411 | |
412 | /* ------------------------------------------------------------------ */ | |
413 | ||
414 | static int start_video_dma(struct cx8800_dev *dev, | |
415 | struct cx88_dmaqueue *q, | |
416 | struct cx88_buffer *buf) | |
417 | { | |
418 | struct cx88_core *core = dev->core; | |
419 | ||
420 | /* setup fifo + format */ | |
e52e98a7 | 421 | cx88_sram_channel_setup(core, &cx88_sram_channels[SRAM_CH21], |
1da177e4 | 422 | buf->bpl, buf->risc.dma); |
e52e98a7 | 423 | cx88_set_scale(core, buf->vb.width, buf->vb.height, buf->vb.field); |
1da177e4 LT |
424 | cx_write(MO_COLOR_CTRL, buf->fmt->cxformat | ColorFormatGamma); |
425 | ||
426 | /* reset counter */ | |
427 | cx_write(MO_VIDY_GPCNTRL,GP_COUNT_CONTROL_RESET); | |
428 | q->count = 1; | |
429 | ||
430 | /* enable irqs */ | |
8ddac9ee | 431 | cx_set(MO_PCI_INTMSK, core->pci_irqmask | PCI_INT_VIDINT); |
e52e98a7 MCC |
432 | |
433 | /* Enables corresponding bits at PCI_INT_STAT: | |
434 | bits 0 to 4: video, audio, transport stream, VIP, Host | |
435 | bit 7: timer | |
436 | bits 8 and 9: DMA complete for: SRC, DST | |
437 | bits 10 and 11: BERR signal asserted for RISC: RD, WR | |
438 | bits 12 to 15: BERR signal asserted for: BRDG, SRC, DST, IPB | |
439 | */ | |
1da177e4 LT |
440 | cx_set(MO_VID_INTMSK, 0x0f0011); |
441 | ||
442 | /* enable capture */ | |
443 | cx_set(VID_CAPTURE_CONTROL,0x06); | |
444 | ||
445 | /* start dma */ | |
446 | cx_set(MO_DEV_CNTRL2, (1<<5)); | |
e52e98a7 | 447 | cx_set(MO_VID_DMACNTRL, 0x11); /* Planar Y and packed FIFO and RISC enable */ |
1da177e4 LT |
448 | |
449 | return 0; | |
450 | } | |
451 | ||
17bc98a4 | 452 | #ifdef CONFIG_PM |
1da177e4 LT |
453 | static int stop_video_dma(struct cx8800_dev *dev) |
454 | { | |
455 | struct cx88_core *core = dev->core; | |
456 | ||
457 | /* stop dma */ | |
458 | cx_clear(MO_VID_DMACNTRL, 0x11); | |
459 | ||
460 | /* disable capture */ | |
461 | cx_clear(VID_CAPTURE_CONTROL,0x06); | |
462 | ||
463 | /* disable irqs */ | |
8ddac9ee | 464 | cx_clear(MO_PCI_INTMSK, PCI_INT_VIDINT); |
1da177e4 LT |
465 | cx_clear(MO_VID_INTMSK, 0x0f0011); |
466 | return 0; | |
467 | } | |
17bc98a4 | 468 | #endif |
1da177e4 LT |
469 | |
470 | static int restart_video_queue(struct cx8800_dev *dev, | |
471 | struct cx88_dmaqueue *q) | |
472 | { | |
e52e98a7 | 473 | struct cx88_core *core = dev->core; |
1da177e4 | 474 | struct cx88_buffer *buf, *prev; |
1da177e4 LT |
475 | |
476 | if (!list_empty(&q->active)) { | |
4ac97914 | 477 | buf = list_entry(q->active.next, struct cx88_buffer, vb.queue); |
1da177e4 LT |
478 | dprintk(2,"restart_queue [%p/%d]: restart dma\n", |
479 | buf, buf->vb.i); | |
480 | start_video_dma(dev, q, buf); | |
8bb629e2 TP |
481 | list_for_each_entry(buf, &q->active, vb.queue) |
482 | buf->count = q->count++; | |
1da177e4 LT |
483 | mod_timer(&q->timeout, jiffies+BUFFER_TIMEOUT); |
484 | return 0; | |
485 | } | |
486 | ||
487 | prev = NULL; | |
488 | for (;;) { | |
489 | if (list_empty(&q->queued)) | |
490 | return 0; | |
4ac97914 | 491 | buf = list_entry(q->queued.next, struct cx88_buffer, vb.queue); |
1da177e4 | 492 | if (NULL == prev) { |
179e0917 | 493 | list_move_tail(&buf->vb.queue, &q->active); |
1da177e4 | 494 | start_video_dma(dev, q, buf); |
0fc0686e | 495 | buf->vb.state = VIDEOBUF_ACTIVE; |
1da177e4 LT |
496 | buf->count = q->count++; |
497 | mod_timer(&q->timeout, jiffies+BUFFER_TIMEOUT); | |
498 | dprintk(2,"[%p/%d] restart_queue - first active\n", | |
499 | buf,buf->vb.i); | |
500 | ||
501 | } else if (prev->vb.width == buf->vb.width && | |
502 | prev->vb.height == buf->vb.height && | |
503 | prev->fmt == buf->fmt) { | |
179e0917 | 504 | list_move_tail(&buf->vb.queue, &q->active); |
0fc0686e | 505 | buf->vb.state = VIDEOBUF_ACTIVE; |
1da177e4 LT |
506 | buf->count = q->count++; |
507 | prev->risc.jmp[1] = cpu_to_le32(buf->risc.dma); | |
508 | dprintk(2,"[%p/%d] restart_queue - move to active\n", | |
509 | buf,buf->vb.i); | |
510 | } else { | |
511 | return 0; | |
512 | } | |
513 | prev = buf; | |
514 | } | |
515 | } | |
516 | ||
517 | /* ------------------------------------------------------------------ */ | |
518 | ||
519 | static int | |
520 | buffer_setup(struct videobuf_queue *q, unsigned int *count, unsigned int *size) | |
521 | { | |
522 | struct cx8800_fh *fh = q->priv_data; | |
c5a86144 | 523 | struct cx8800_dev *dev = fh->dev; |
1da177e4 | 524 | |
c5a86144 | 525 | *size = dev->fmt->depth * dev->width * dev->height >> 3; |
1da177e4 LT |
526 | if (0 == *count) |
527 | *count = 32; | |
dab7e310 AB |
528 | if (*size * *count > vid_limit * 1024 * 1024) |
529 | *count = (vid_limit * 1024 * 1024) / *size; | |
1da177e4 LT |
530 | return 0; |
531 | } | |
532 | ||
533 | static int | |
534 | buffer_prepare(struct videobuf_queue *q, struct videobuf_buffer *vb, | |
535 | enum v4l2_field field) | |
536 | { | |
537 | struct cx8800_fh *fh = q->priv_data; | |
538 | struct cx8800_dev *dev = fh->dev; | |
e52e98a7 | 539 | struct cx88_core *core = dev->core; |
1da177e4 | 540 | struct cx88_buffer *buf = container_of(vb,struct cx88_buffer,vb); |
c1accaa2 | 541 | struct videobuf_dmabuf *dma=videobuf_to_dma(&buf->vb); |
1da177e4 LT |
542 | int rc, init_buffer = 0; |
543 | ||
c5a86144 HV |
544 | BUG_ON(NULL == dev->fmt); |
545 | if (dev->width < 48 || dev->width > norm_maxw(core->tvnorm) || | |
546 | dev->height < 32 || dev->height > norm_maxh(core->tvnorm)) | |
1da177e4 | 547 | return -EINVAL; |
c5a86144 | 548 | buf->vb.size = (dev->width * dev->height * dev->fmt->depth) >> 3; |
1da177e4 LT |
549 | if (0 != buf->vb.baddr && buf->vb.bsize < buf->vb.size) |
550 | return -EINVAL; | |
551 | ||
c5a86144 HV |
552 | if (buf->fmt != dev->fmt || |
553 | buf->vb.width != dev->width || | |
554 | buf->vb.height != dev->height || | |
1da177e4 | 555 | buf->vb.field != field) { |
c5a86144 HV |
556 | buf->fmt = dev->fmt; |
557 | buf->vb.width = dev->width; | |
558 | buf->vb.height = dev->height; | |
1da177e4 LT |
559 | buf->vb.field = field; |
560 | init_buffer = 1; | |
561 | } | |
562 | ||
0fc0686e | 563 | if (VIDEOBUF_NEEDS_INIT == buf->vb.state) { |
1da177e4 | 564 | init_buffer = 1; |
c7b0ac05 | 565 | if (0 != (rc = videobuf_iolock(q,&buf->vb,NULL))) |
1da177e4 LT |
566 | goto fail; |
567 | } | |
568 | ||
569 | if (init_buffer) { | |
570 | buf->bpl = buf->vb.width * buf->fmt->depth >> 3; | |
571 | switch (buf->vb.field) { | |
572 | case V4L2_FIELD_TOP: | |
573 | cx88_risc_buffer(dev->pci, &buf->risc, | |
c1accaa2 | 574 | dma->sglist, 0, UNSET, |
1da177e4 LT |
575 | buf->bpl, 0, buf->vb.height); |
576 | break; | |
577 | case V4L2_FIELD_BOTTOM: | |
578 | cx88_risc_buffer(dev->pci, &buf->risc, | |
c1accaa2 | 579 | dma->sglist, UNSET, 0, |
1da177e4 LT |
580 | buf->bpl, 0, buf->vb.height); |
581 | break; | |
582 | case V4L2_FIELD_INTERLACED: | |
583 | cx88_risc_buffer(dev->pci, &buf->risc, | |
c1accaa2 | 584 | dma->sglist, 0, buf->bpl, |
1da177e4 LT |
585 | buf->bpl, buf->bpl, |
586 | buf->vb.height >> 1); | |
587 | break; | |
588 | case V4L2_FIELD_SEQ_TB: | |
589 | cx88_risc_buffer(dev->pci, &buf->risc, | |
c1accaa2 | 590 | dma->sglist, |
1da177e4 LT |
591 | 0, buf->bpl * (buf->vb.height >> 1), |
592 | buf->bpl, 0, | |
593 | buf->vb.height >> 1); | |
594 | break; | |
595 | case V4L2_FIELD_SEQ_BT: | |
596 | cx88_risc_buffer(dev->pci, &buf->risc, | |
c1accaa2 | 597 | dma->sglist, |
1da177e4 LT |
598 | buf->bpl * (buf->vb.height >> 1), 0, |
599 | buf->bpl, 0, | |
600 | buf->vb.height >> 1); | |
601 | break; | |
602 | default: | |
603 | BUG(); | |
604 | } | |
605 | } | |
606 | dprintk(2,"[%p/%d] buffer_prepare - %dx%d %dbpp \"%s\" - dma=0x%08lx\n", | |
607 | buf, buf->vb.i, | |
c5a86144 | 608 | dev->width, dev->height, dev->fmt->depth, dev->fmt->name, |
1da177e4 LT |
609 | (unsigned long)buf->risc.dma); |
610 | ||
0fc0686e | 611 | buf->vb.state = VIDEOBUF_PREPARED; |
1da177e4 LT |
612 | return 0; |
613 | ||
614 | fail: | |
c7b0ac05 | 615 | cx88_free_buffer(q,buf); |
1da177e4 LT |
616 | return rc; |
617 | } | |
618 | ||
619 | static void | |
620 | buffer_queue(struct videobuf_queue *vq, struct videobuf_buffer *vb) | |
621 | { | |
622 | struct cx88_buffer *buf = container_of(vb,struct cx88_buffer,vb); | |
623 | struct cx88_buffer *prev; | |
624 | struct cx8800_fh *fh = vq->priv_data; | |
625 | struct cx8800_dev *dev = fh->dev; | |
e52e98a7 | 626 | struct cx88_core *core = dev->core; |
1da177e4 LT |
627 | struct cx88_dmaqueue *q = &dev->vidq; |
628 | ||
629 | /* add jump to stopper */ | |
630 | buf->risc.jmp[0] = cpu_to_le32(RISC_JUMP | RISC_IRQ1 | RISC_CNT_INC); | |
631 | buf->risc.jmp[1] = cpu_to_le32(q->stopper.dma); | |
632 | ||
633 | if (!list_empty(&q->queued)) { | |
634 | list_add_tail(&buf->vb.queue,&q->queued); | |
0fc0686e | 635 | buf->vb.state = VIDEOBUF_QUEUED; |
1da177e4 LT |
636 | dprintk(2,"[%p/%d] buffer_queue - append to queued\n", |
637 | buf, buf->vb.i); | |
638 | ||
639 | } else if (list_empty(&q->active)) { | |
640 | list_add_tail(&buf->vb.queue,&q->active); | |
641 | start_video_dma(dev, q, buf); | |
0fc0686e | 642 | buf->vb.state = VIDEOBUF_ACTIVE; |
1da177e4 LT |
643 | buf->count = q->count++; |
644 | mod_timer(&q->timeout, jiffies+BUFFER_TIMEOUT); | |
645 | dprintk(2,"[%p/%d] buffer_queue - first active\n", | |
646 | buf, buf->vb.i); | |
647 | ||
648 | } else { | |
649 | prev = list_entry(q->active.prev, struct cx88_buffer, vb.queue); | |
650 | if (prev->vb.width == buf->vb.width && | |
651 | prev->vb.height == buf->vb.height && | |
652 | prev->fmt == buf->fmt) { | |
653 | list_add_tail(&buf->vb.queue,&q->active); | |
0fc0686e | 654 | buf->vb.state = VIDEOBUF_ACTIVE; |
1da177e4 LT |
655 | buf->count = q->count++; |
656 | prev->risc.jmp[1] = cpu_to_le32(buf->risc.dma); | |
657 | dprintk(2,"[%p/%d] buffer_queue - append to active\n", | |
658 | buf, buf->vb.i); | |
659 | ||
660 | } else { | |
661 | list_add_tail(&buf->vb.queue,&q->queued); | |
0fc0686e | 662 | buf->vb.state = VIDEOBUF_QUEUED; |
1da177e4 LT |
663 | dprintk(2,"[%p/%d] buffer_queue - first queued\n", |
664 | buf, buf->vb.i); | |
665 | } | |
666 | } | |
667 | } | |
668 | ||
669 | static void buffer_release(struct videobuf_queue *q, struct videobuf_buffer *vb) | |
670 | { | |
671 | struct cx88_buffer *buf = container_of(vb,struct cx88_buffer,vb); | |
1da177e4 | 672 | |
c7b0ac05 | 673 | cx88_free_buffer(q,buf); |
1da177e4 LT |
674 | } |
675 | ||
2e4e98e7 | 676 | static const struct videobuf_queue_ops cx8800_video_qops = { |
1da177e4 LT |
677 | .buf_setup = buffer_setup, |
678 | .buf_prepare = buffer_prepare, | |
679 | .buf_queue = buffer_queue, | |
680 | .buf_release = buffer_release, | |
681 | }; | |
682 | ||
683 | /* ------------------------------------------------------------------ */ | |
684 | ||
1da177e4 LT |
685 | |
686 | /* ------------------------------------------------------------------ */ | |
687 | ||
edbd138e | 688 | static struct videobuf_queue *get_queue(struct file *file) |
1da177e4 | 689 | { |
edbd138e HV |
690 | struct video_device *vdev = video_devdata(file); |
691 | struct cx8800_fh *fh = file->private_data; | |
692 | ||
693 | switch (vdev->vfl_type) { | |
694 | case VFL_TYPE_GRABBER: | |
1da177e4 | 695 | return &fh->vidq; |
edbd138e | 696 | case VFL_TYPE_VBI: |
1da177e4 LT |
697 | return &fh->vbiq; |
698 | default: | |
699 | BUG(); | |
700 | return NULL; | |
701 | } | |
702 | } | |
703 | ||
edbd138e | 704 | static int get_resource(struct file *file) |
1da177e4 | 705 | { |
edbd138e HV |
706 | struct video_device *vdev = video_devdata(file); |
707 | ||
708 | switch (vdev->vfl_type) { | |
709 | case VFL_TYPE_GRABBER: | |
1da177e4 | 710 | return RESOURCE_VIDEO; |
edbd138e | 711 | case VFL_TYPE_VBI: |
1da177e4 LT |
712 | return RESOURCE_VBI; |
713 | default: | |
714 | BUG(); | |
715 | return 0; | |
716 | } | |
717 | } | |
718 | ||
bec43661 | 719 | static int video_open(struct file *file) |
1da177e4 | 720 | { |
63b0d5ad LP |
721 | struct video_device *vdev = video_devdata(file); |
722 | struct cx8800_dev *dev = video_drvdata(file); | |
5401c2db | 723 | struct cx88_core *core = dev->core; |
1da177e4 | 724 | struct cx8800_fh *fh; |
1da177e4 LT |
725 | enum v4l2_buf_type type = 0; |
726 | int radio = 0; | |
727 | ||
63b0d5ad LP |
728 | switch (vdev->vfl_type) { |
729 | case VFL_TYPE_GRABBER: | |
730 | type = V4L2_BUF_TYPE_VIDEO_CAPTURE; | |
731 | break; | |
732 | case VFL_TYPE_VBI: | |
733 | type = V4L2_BUF_TYPE_VBI_CAPTURE; | |
734 | break; | |
735 | case VFL_TYPE_RADIO: | |
736 | radio = 1; | |
737 | break; | |
d56dc612 | 738 | } |
1da177e4 | 739 | |
50462eb0 LP |
740 | dprintk(1, "open dev=%s radio=%d type=%s\n", |
741 | video_device_node_name(vdev), radio, v4l2_type_names[type]); | |
1da177e4 LT |
742 | |
743 | /* allocate + initialize per filehandle data */ | |
7408187d | 744 | fh = kzalloc(sizeof(*fh),GFP_KERNEL); |
da497e30 | 745 | if (unlikely(!fh)) |
1da177e4 | 746 | return -ENOMEM; |
da497e30 | 747 | |
88bb42fb | 748 | v4l2_fh_init(&fh->fh, vdev); |
1da177e4 LT |
749 | file->private_data = fh; |
750 | fh->dev = dev; | |
1da177e4 | 751 | |
da497e30 | 752 | mutex_lock(&core->lock); |
da497e30 | 753 | |
0705135e GL |
754 | videobuf_queue_sg_init(&fh->vidq, &cx8800_video_qops, |
755 | &dev->pci->dev, &dev->slock, | |
1da177e4 LT |
756 | V4L2_BUF_TYPE_VIDEO_CAPTURE, |
757 | V4L2_FIELD_INTERLACED, | |
758 | sizeof(struct cx88_buffer), | |
08bff03e | 759 | fh, NULL); |
0705135e GL |
760 | videobuf_queue_sg_init(&fh->vbiq, &cx8800_vbi_qops, |
761 | &dev->pci->dev, &dev->slock, | |
1da177e4 LT |
762 | V4L2_BUF_TYPE_VBI_CAPTURE, |
763 | V4L2_FIELD_SEQ_TB, | |
764 | sizeof(struct cx88_buffer), | |
08bff03e | 765 | fh, NULL); |
1da177e4 | 766 | |
edbd138e | 767 | if (vdev->vfl_type == VFL_TYPE_RADIO) { |
1da177e4 | 768 | dprintk(1,"video_open: setting radio device\n"); |
6a59d64c TP |
769 | cx_write(MO_GP3_IO, core->board.radio.gpio3); |
770 | cx_write(MO_GP0_IO, core->board.radio.gpio0); | |
771 | cx_write(MO_GP1_IO, core->board.radio.gpio1); | |
772 | cx_write(MO_GP2_IO, core->board.radio.gpio2); | |
430189da DB |
773 | if (core->board.radio.audioroute) { |
774 | if(core->board.audio_chip && | |
775 | core->board.audio_chip == V4L2_IDENT_WM8775) { | |
5325b427 HV |
776 | call_all(core, audio, s_routing, |
777 | core->board.radio.audioroute, 0, 0); | |
430189da DB |
778 | } |
779 | /* "I2S ADC mode" */ | |
780 | core->tvaudio = WW_I2SADC; | |
781 | cx88_set_tvaudio(core); | |
782 | } else { | |
783 | /* FM Mode */ | |
784 | core->tvaudio = WW_FM; | |
785 | cx88_set_tvaudio(core); | |
786 | cx88_set_stereo(core,V4L2_TUNER_MODE_STEREO,1); | |
787 | } | |
b8341e1d | 788 | call_all(core, tuner, s_radio); |
1da177e4 LT |
789 | } |
790 | ||
8d115931 | 791 | core->users++; |
da497e30 | 792 | mutex_unlock(&core->lock); |
88bb42fb | 793 | v4l2_fh_add(&fh->fh); |
3e010845 | 794 | |
4ac97914 | 795 | return 0; |
1da177e4 LT |
796 | } |
797 | ||
798 | static ssize_t | |
f9e7a020 | 799 | video_read(struct file *file, char __user *data, size_t count, loff_t *ppos) |
1da177e4 | 800 | { |
edbd138e | 801 | struct video_device *vdev = video_devdata(file); |
1da177e4 LT |
802 | struct cx8800_fh *fh = file->private_data; |
803 | ||
edbd138e HV |
804 | switch (vdev->vfl_type) { |
805 | case VFL_TYPE_GRABBER: | |
1da177e4 LT |
806 | if (res_locked(fh->dev,RESOURCE_VIDEO)) |
807 | return -EBUSY; | |
808 | return videobuf_read_one(&fh->vidq, data, count, ppos, | |
809 | file->f_flags & O_NONBLOCK); | |
edbd138e | 810 | case VFL_TYPE_VBI: |
1da177e4 LT |
811 | if (!res_get(fh->dev,fh,RESOURCE_VBI)) |
812 | return -EBUSY; | |
813 | return videobuf_read_stream(&fh->vbiq, data, count, ppos, 1, | |
814 | file->f_flags & O_NONBLOCK); | |
815 | default: | |
816 | BUG(); | |
817 | return 0; | |
818 | } | |
819 | } | |
820 | ||
821 | static unsigned int | |
822 | video_poll(struct file *file, struct poll_table_struct *wait) | |
823 | { | |
edbd138e | 824 | struct video_device *vdev = video_devdata(file); |
1da177e4 LT |
825 | struct cx8800_fh *fh = file->private_data; |
826 | struct cx88_buffer *buf; | |
1a3c60a0 | 827 | unsigned int rc = v4l2_ctrl_poll(file, wait); |
1da177e4 | 828 | |
edbd138e | 829 | if (vdev->vfl_type == VFL_TYPE_VBI) { |
1da177e4 | 830 | if (!res_get(fh->dev,fh,RESOURCE_VBI)) |
1a3c60a0 HV |
831 | return rc | POLLERR; |
832 | return rc | videobuf_poll_stream(file, &fh->vbiq, wait); | |
1da177e4 | 833 | } |
9fd6418a | 834 | mutex_lock(&fh->vidq.vb_lock); |
1da177e4 LT |
835 | if (res_check(fh,RESOURCE_VIDEO)) { |
836 | /* streaming capture */ | |
837 | if (list_empty(&fh->vidq.stream)) | |
9fd6418a | 838 | goto done; |
1da177e4 LT |
839 | buf = list_entry(fh->vidq.stream.next,struct cx88_buffer,vb.stream); |
840 | } else { | |
841 | /* read() capture */ | |
842 | buf = (struct cx88_buffer*)fh->vidq.read_buf; | |
843 | if (NULL == buf) | |
9fd6418a | 844 | goto done; |
1da177e4 LT |
845 | } |
846 | poll_wait(file, &buf->vb.done, wait); | |
0fc0686e BP |
847 | if (buf->vb.state == VIDEOBUF_DONE || |
848 | buf->vb.state == VIDEOBUF_ERROR) | |
1a3c60a0 | 849 | rc |= POLLIN|POLLRDNORM; |
9fd6418a F |
850 | done: |
851 | mutex_unlock(&fh->vidq.vb_lock); | |
852 | return rc; | |
1da177e4 LT |
853 | } |
854 | ||
bec43661 | 855 | static int video_release(struct file *file) |
1da177e4 LT |
856 | { |
857 | struct cx8800_fh *fh = file->private_data; | |
858 | struct cx8800_dev *dev = fh->dev; | |
859 | ||
860 | /* turn off overlay */ | |
861 | if (res_check(fh, RESOURCE_OVERLAY)) { | |
862 | /* FIXME */ | |
863 | res_free(dev,fh,RESOURCE_OVERLAY); | |
864 | } | |
865 | ||
866 | /* stop video capture */ | |
867 | if (res_check(fh, RESOURCE_VIDEO)) { | |
868 | videobuf_queue_cancel(&fh->vidq); | |
869 | res_free(dev,fh,RESOURCE_VIDEO); | |
870 | } | |
871 | if (fh->vidq.read_buf) { | |
872 | buffer_release(&fh->vidq,fh->vidq.read_buf); | |
873 | kfree(fh->vidq.read_buf); | |
874 | } | |
875 | ||
876 | /* stop vbi capture */ | |
877 | if (res_check(fh, RESOURCE_VBI)) { | |
053fcb60 | 878 | videobuf_stop(&fh->vbiq); |
1da177e4 LT |
879 | res_free(dev,fh,RESOURCE_VBI); |
880 | } | |
881 | ||
882 | videobuf_mmap_free(&fh->vidq); | |
883 | videobuf_mmap_free(&fh->vbiq); | |
da497e30 MCC |
884 | |
885 | mutex_lock(&dev->core->lock); | |
88bb42fb HV |
886 | v4l2_fh_del(&fh->fh); |
887 | v4l2_fh_exit(&fh->fh); | |
1da177e4 LT |
888 | file->private_data = NULL; |
889 | kfree(fh); | |
e52e98a7 | 890 | |
8d115931 JN |
891 | dev->core->users--; |
892 | if (!dev->core->users) | |
622b828a | 893 | call_all(dev->core, core, s_power, 0); |
06f837ca | 894 | mutex_unlock(&dev->core->lock); |
e52e98a7 | 895 | |
1da177e4 LT |
896 | return 0; |
897 | } | |
898 | ||
899 | static int | |
900 | video_mmap(struct file *file, struct vm_area_struct * vma) | |
901 | { | |
edbd138e | 902 | return videobuf_mmap_mapper(get_queue(file), vma); |
1da177e4 LT |
903 | } |
904 | ||
905 | /* ------------------------------------------------------------------ */ | |
8d87cb9f | 906 | /* VIDEO CTRL IOCTLS */ |
1da177e4 | 907 | |
8c7cb12a HV |
908 | static int cx8800_s_vid_ctrl(struct v4l2_ctrl *ctrl) |
909 | { | |
910 | struct cx88_core *core = | |
911 | container_of(ctrl->handler, struct cx88_core, video_hdl); | |
912 | const struct cx88_ctrl *cc = ctrl->priv; | |
913 | u32 value, mask; | |
914 | ||
915 | mask = cc->mask; | |
916 | switch (ctrl->id) { | |
917 | case V4L2_CID_SATURATION: | |
918 | /* special v_sat handling */ | |
919 | ||
920 | value = ((ctrl->val - cc->off) << cc->shift) & cc->mask; | |
921 | ||
922 | if (core->tvnorm & V4L2_STD_SECAM) { | |
923 | /* For SECAM, both U and V sat should be equal */ | |
924 | value = value << 8 | value; | |
925 | } else { | |
926 | /* Keeps U Saturation proportional to V Sat */ | |
927 | value = (value * 0x5a) / 0x7f << 8 | value; | |
928 | } | |
929 | mask = 0xffff; | |
930 | break; | |
931 | case V4L2_CID_SHARPNESS: | |
932 | /* 0b000, 0b100, 0b101, 0b110, or 0b111 */ | |
933 | value = (ctrl->val < 1 ? 0 : ((ctrl->val + 3) << 7)); | |
934 | /* needs to be set for both fields */ | |
935 | cx_andor(MO_FILTER_EVEN, mask, value); | |
936 | break; | |
937 | case V4L2_CID_CHROMA_AGC: | |
938 | value = ((ctrl->val - cc->off) << cc->shift) & cc->mask; | |
939 | break; | |
940 | default: | |
941 | value = ((ctrl->val - cc->off) << cc->shift) & cc->mask; | |
942 | break; | |
943 | } | |
944 | dprintk(1, "set_control id=0x%X(%s) ctrl=0x%02x, reg=0x%02x val=0x%02x (mask 0x%02x)%s\n", | |
945 | ctrl->id, ctrl->name, ctrl->val, cc->reg, value, | |
946 | mask, cc->sreg ? " [shadowed]" : ""); | |
947 | if (cc->sreg) | |
948 | cx_sandor(cc->sreg, cc->reg, mask, value); | |
949 | else | |
950 | cx_andor(cc->reg, mask, value); | |
951 | return 0; | |
952 | } | |
953 | ||
954 | static int cx8800_s_aud_ctrl(struct v4l2_ctrl *ctrl) | |
1da177e4 | 955 | { |
bac63981 | 956 | struct cx88_core *core = |
8c7cb12a | 957 | container_of(ctrl->handler, struct cx88_core, audio_hdl); |
bac63981 | 958 | const struct cx88_ctrl *cc = ctrl->priv; |
70f00044 | 959 | u32 value,mask; |
6951803c LR |
960 | |
961 | /* Pass changes onto any WM8775 */ | |
962 | if (core->board.audio_chip == V4L2_IDENT_WM8775) { | |
bac63981 | 963 | switch (ctrl->id) { |
6951803c | 964 | case V4L2_CID_AUDIO_MUTE: |
bac63981 | 965 | wm8775_s_ctrl(core, ctrl->id, ctrl->val); |
6951803c LR |
966 | break; |
967 | case V4L2_CID_AUDIO_VOLUME: | |
bac63981 HV |
968 | wm8775_s_ctrl(core, ctrl->id, (ctrl->val) ? |
969 | (0x90 + ctrl->val) << 8 : 0); | |
6951803c LR |
970 | break; |
971 | case V4L2_CID_AUDIO_BALANCE: | |
bac63981 | 972 | wm8775_s_ctrl(core, ctrl->id, ctrl->val << 9); |
6951803c LR |
973 | break; |
974 | default: | |
6951803c LR |
975 | break; |
976 | } | |
6951803c LR |
977 | } |
978 | ||
bac63981 HV |
979 | mask = cc->mask; |
980 | switch (ctrl->id) { | |
1da177e4 | 981 | case V4L2_CID_AUDIO_BALANCE: |
bac63981 | 982 | value = (ctrl->val < 0x40) ? (0x7f - ctrl->val) : (ctrl->val - 0x40); |
1da177e4 LT |
983 | break; |
984 | case V4L2_CID_AUDIO_VOLUME: | |
bac63981 | 985 | value = 0x3f - (ctrl->val & 0x3f); |
1da177e4 | 986 | break; |
1da177e4 | 987 | default: |
bac63981 | 988 | value = ((ctrl->val - cc->off) << cc->shift) & cc->mask; |
1da177e4 LT |
989 | break; |
990 | } | |
6457af5f | 991 | dprintk(1,"set_control id=0x%X(%s) ctrl=0x%02x, reg=0x%02x val=0x%02x (mask 0x%02x)%s\n", |
bac63981 HV |
992 | ctrl->id, ctrl->name, ctrl->val, cc->reg, value, |
993 | mask, cc->sreg ? " [shadowed]" : ""); | |
994 | if (cc->sreg) | |
995 | cx_sandor(cc->sreg, cc->reg, mask, value); | |
996 | else | |
997 | cx_andor(cc->reg, mask, value); | |
1da177e4 LT |
998 | return 0; |
999 | } | |
1da177e4 LT |
1000 | |
1001 | /* ------------------------------------------------------------------ */ | |
8d87cb9f | 1002 | /* VIDEO IOCTLS */ |
1da177e4 | 1003 | |
78b526a4 | 1004 | static int vidioc_g_fmt_vid_cap(struct file *file, void *priv, |
8d87cb9f | 1005 | struct v4l2_format *f) |
1da177e4 | 1006 | { |
8d87cb9f | 1007 | struct cx8800_fh *fh = priv; |
c5a86144 | 1008 | struct cx8800_dev *dev = fh->dev; |
8d87cb9f | 1009 | |
c5a86144 HV |
1010 | f->fmt.pix.width = dev->width; |
1011 | f->fmt.pix.height = dev->height; | |
8d87cb9f | 1012 | f->fmt.pix.field = fh->vidq.field; |
c5a86144 | 1013 | f->fmt.pix.pixelformat = dev->fmt->fourcc; |
8d87cb9f | 1014 | f->fmt.pix.bytesperline = |
c5a86144 | 1015 | (f->fmt.pix.width * dev->fmt->depth) >> 3; |
8d87cb9f MCC |
1016 | f->fmt.pix.sizeimage = |
1017 | f->fmt.pix.height * f->fmt.pix.bytesperline; | |
c5a86144 | 1018 | f->fmt.pix.colorspace = V4L2_COLORSPACE_SMPTE170M; |
8d87cb9f | 1019 | return 0; |
1da177e4 LT |
1020 | } |
1021 | ||
78b526a4 | 1022 | static int vidioc_try_fmt_vid_cap(struct file *file, void *priv, |
8d87cb9f | 1023 | struct v4l2_format *f) |
1da177e4 | 1024 | { |
8d87cb9f | 1025 | struct cx88_core *core = ((struct cx8800_fh *)priv)->dev->core; |
2e4e98e7 | 1026 | const struct cx8800_fmt *fmt; |
8d87cb9f MCC |
1027 | enum v4l2_field field; |
1028 | unsigned int maxw, maxh; | |
e52e98a7 | 1029 | |
8d87cb9f MCC |
1030 | fmt = format_by_fourcc(f->fmt.pix.pixelformat); |
1031 | if (NULL == fmt) | |
1032 | return -EINVAL; | |
1da177e4 | 1033 | |
8d87cb9f MCC |
1034 | field = f->fmt.pix.field; |
1035 | maxw = norm_maxw(core->tvnorm); | |
1036 | maxh = norm_maxh(core->tvnorm); | |
1da177e4 | 1037 | |
8d87cb9f MCC |
1038 | if (V4L2_FIELD_ANY == field) { |
1039 | field = (f->fmt.pix.height > maxh/2) | |
1040 | ? V4L2_FIELD_INTERLACED | |
1041 | : V4L2_FIELD_BOTTOM; | |
1da177e4 | 1042 | } |
8d87cb9f MCC |
1043 | |
1044 | switch (field) { | |
1045 | case V4L2_FIELD_TOP: | |
1046 | case V4L2_FIELD_BOTTOM: | |
1047 | maxh = maxh / 2; | |
1048 | break; | |
1049 | case V4L2_FIELD_INTERLACED: | |
1050 | break; | |
1da177e4 LT |
1051 | default: |
1052 | return -EINVAL; | |
1053 | } | |
8d87cb9f MCC |
1054 | |
1055 | f->fmt.pix.field = field; | |
4b89945e TP |
1056 | v4l_bound_align_image(&f->fmt.pix.width, 48, maxw, 2, |
1057 | &f->fmt.pix.height, 32, maxh, 0, 0); | |
8d87cb9f MCC |
1058 | f->fmt.pix.bytesperline = |
1059 | (f->fmt.pix.width * fmt->depth) >> 3; | |
1060 | f->fmt.pix.sizeimage = | |
1061 | f->fmt.pix.height * f->fmt.pix.bytesperline; | |
1062 | ||
1063 | return 0; | |
1da177e4 LT |
1064 | } |
1065 | ||
78b526a4 | 1066 | static int vidioc_s_fmt_vid_cap(struct file *file, void *priv, |
8d87cb9f | 1067 | struct v4l2_format *f) |
1da177e4 | 1068 | { |
8d87cb9f | 1069 | struct cx8800_fh *fh = priv; |
c5a86144 | 1070 | struct cx8800_dev *dev = fh->dev; |
78b526a4 | 1071 | int err = vidioc_try_fmt_vid_cap (file,priv,f); |
8d87cb9f MCC |
1072 | |
1073 | if (0 != err) | |
1074 | return err; | |
c5a86144 HV |
1075 | dev->fmt = format_by_fourcc(f->fmt.pix.pixelformat); |
1076 | dev->width = f->fmt.pix.width; | |
1077 | dev->height = f->fmt.pix.height; | |
8d87cb9f MCC |
1078 | fh->vidq.field = f->fmt.pix.field; |
1079 | return 0; | |
1da177e4 LT |
1080 | } |
1081 | ||
902e197d HV |
1082 | void cx88_querycap(struct file *file, struct cx88_core *core, |
1083 | struct v4l2_capability *cap) | |
1084 | { | |
1085 | struct video_device *vdev = video_devdata(file); | |
1086 | ||
1087 | strlcpy(cap->card, core->board.name, sizeof(cap->card)); | |
1088 | cap->device_caps = V4L2_CAP_READWRITE | V4L2_CAP_STREAMING; | |
1089 | if (UNSET != core->board.tuner_type) | |
1090 | cap->device_caps |= V4L2_CAP_TUNER; | |
1091 | switch (vdev->vfl_type) { | |
1092 | case VFL_TYPE_RADIO: | |
1093 | cap->device_caps = V4L2_CAP_RADIO | V4L2_CAP_TUNER; | |
1094 | break; | |
1095 | case VFL_TYPE_GRABBER: | |
1096 | cap->device_caps |= V4L2_CAP_VIDEO_CAPTURE; | |
1097 | break; | |
1098 | case VFL_TYPE_VBI: | |
1099 | cap->device_caps |= V4L2_CAP_VBI_CAPTURE; | |
1100 | break; | |
1101 | } | |
1102 | cap->capabilities = cap->device_caps | V4L2_CAP_VIDEO_CAPTURE | | |
1103 | V4L2_CAP_VBI_CAPTURE | V4L2_CAP_DEVICE_CAPS; | |
1104 | if (core->board.radio.type == CX88_RADIO) | |
1105 | cap->capabilities |= V4L2_CAP_RADIO; | |
1106 | } | |
1107 | EXPORT_SYMBOL(cx88_querycap); | |
1108 | ||
1109 | static int vidioc_querycap(struct file *file, void *priv, | |
8d87cb9f | 1110 | struct v4l2_capability *cap) |
1da177e4 | 1111 | { |
8d87cb9f | 1112 | struct cx8800_dev *dev = ((struct cx8800_fh *)priv)->dev; |
1da177e4 | 1113 | struct cx88_core *core = dev->core; |
1da177e4 | 1114 | |
8d87cb9f | 1115 | strcpy(cap->driver, "cx8800"); |
902e197d HV |
1116 | sprintf(cap->bus_info, "PCI:%s", pci_name(dev->pci)); |
1117 | cx88_querycap(file, core, cap); | |
8d87cb9f MCC |
1118 | return 0; |
1119 | } | |
e52e98a7 | 1120 | |
78b526a4 | 1121 | static int vidioc_enum_fmt_vid_cap (struct file *file, void *priv, |
8d87cb9f MCC |
1122 | struct v4l2_fmtdesc *f) |
1123 | { | |
1124 | if (unlikely(f->index >= ARRAY_SIZE(formats))) | |
1125 | return -EINVAL; | |
1126 | ||
1127 | strlcpy(f->description,formats[f->index].name,sizeof(f->description)); | |
1128 | f->pixelformat = formats[f->index].fourcc; | |
1129 | ||
1130 | return 0; | |
1131 | } | |
1da177e4 | 1132 | |
8d87cb9f MCC |
1133 | static int vidioc_reqbufs (struct file *file, void *priv, struct v4l2_requestbuffers *p) |
1134 | { | |
edbd138e | 1135 | return videobuf_reqbufs(get_queue(file), p); |
8d87cb9f | 1136 | } |
e52e98a7 | 1137 | |
8d87cb9f MCC |
1138 | static int vidioc_querybuf (struct file *file, void *priv, struct v4l2_buffer *p) |
1139 | { | |
edbd138e | 1140 | return videobuf_querybuf(get_queue(file), p); |
8d87cb9f | 1141 | } |
e52e98a7 | 1142 | |
8d87cb9f MCC |
1143 | static int vidioc_qbuf (struct file *file, void *priv, struct v4l2_buffer *p) |
1144 | { | |
edbd138e | 1145 | return videobuf_qbuf(get_queue(file), p); |
8d87cb9f | 1146 | } |
e52e98a7 | 1147 | |
8d87cb9f MCC |
1148 | static int vidioc_dqbuf (struct file *file, void *priv, struct v4l2_buffer *p) |
1149 | { | |
edbd138e HV |
1150 | return videobuf_dqbuf(get_queue(file), p, |
1151 | file->f_flags & O_NONBLOCK); | |
8d87cb9f | 1152 | } |
e52e98a7 | 1153 | |
8d87cb9f MCC |
1154 | static int vidioc_streamon(struct file *file, void *priv, enum v4l2_buf_type i) |
1155 | { | |
edbd138e | 1156 | struct video_device *vdev = video_devdata(file); |
8d87cb9f MCC |
1157 | struct cx8800_fh *fh = priv; |
1158 | struct cx8800_dev *dev = fh->dev; | |
1159 | ||
edbd138e HV |
1160 | if ((vdev->vfl_type == VFL_TYPE_GRABBER && i != V4L2_BUF_TYPE_VIDEO_CAPTURE) || |
1161 | (vdev->vfl_type == VFL_TYPE_VBI && i != V4L2_BUF_TYPE_VBI_CAPTURE)) | |
8d87cb9f | 1162 | return -EINVAL; |
b058e3f3 | 1163 | |
edbd138e | 1164 | if (unlikely(!res_get(dev, fh, get_resource(file)))) |
8d87cb9f | 1165 | return -EBUSY; |
edbd138e | 1166 | return videobuf_streamon(get_queue(file)); |
8d87cb9f MCC |
1167 | } |
1168 | ||
1169 | static int vidioc_streamoff(struct file *file, void *priv, enum v4l2_buf_type i) | |
1170 | { | |
edbd138e | 1171 | struct video_device *vdev = video_devdata(file); |
8d87cb9f MCC |
1172 | struct cx8800_fh *fh = priv; |
1173 | struct cx8800_dev *dev = fh->dev; | |
1174 | int err, res; | |
1175 | ||
edbd138e HV |
1176 | if ((vdev->vfl_type == VFL_TYPE_GRABBER && i != V4L2_BUF_TYPE_VIDEO_CAPTURE) || |
1177 | (vdev->vfl_type == VFL_TYPE_VBI && i != V4L2_BUF_TYPE_VBI_CAPTURE)) | |
8d87cb9f MCC |
1178 | return -EINVAL; |
1179 | ||
edbd138e HV |
1180 | res = get_resource(file); |
1181 | err = videobuf_streamoff(get_queue(file)); | |
8d87cb9f MCC |
1182 | if (err < 0) |
1183 | return err; | |
1184 | res_free(dev,fh,res); | |
e52e98a7 MCC |
1185 | return 0; |
1186 | } | |
1187 | ||
48d68801 HV |
1188 | static int vidioc_g_std(struct file *file, void *priv, v4l2_std_id *tvnorm) |
1189 | { | |
1190 | struct cx88_core *core = ((struct cx8800_fh *)priv)->dev->core; | |
1191 | ||
1192 | *tvnorm = core->tvnorm; | |
1193 | return 0; | |
1194 | } | |
1195 | ||
63ab1bdc | 1196 | static int vidioc_s_std (struct file *file, void *priv, v4l2_std_id *tvnorms) |
e52e98a7 | 1197 | { |
8d87cb9f | 1198 | struct cx88_core *core = ((struct cx8800_fh *)priv)->dev->core; |
e52e98a7 | 1199 | |
8d87cb9f | 1200 | mutex_lock(&core->lock); |
63ab1bdc | 1201 | cx88_set_tvnorm(core,*tvnorms); |
8d87cb9f | 1202 | mutex_unlock(&core->lock); |
63ab1bdc | 1203 | |
8d87cb9f MCC |
1204 | return 0; |
1205 | } | |
1da177e4 | 1206 | |
8d87cb9f | 1207 | /* only one input in this sample driver */ |
54da49f5 | 1208 | int cx88_enum_input (struct cx88_core *core,struct v4l2_input *i) |
8d87cb9f | 1209 | { |
2e4e98e7 | 1210 | static const char * const iname[] = { |
8d87cb9f MCC |
1211 | [ CX88_VMUX_COMPOSITE1 ] = "Composite1", |
1212 | [ CX88_VMUX_COMPOSITE2 ] = "Composite2", | |
1213 | [ CX88_VMUX_COMPOSITE3 ] = "Composite3", | |
1214 | [ CX88_VMUX_COMPOSITE4 ] = "Composite4", | |
1215 | [ CX88_VMUX_SVIDEO ] = "S-Video", | |
1216 | [ CX88_VMUX_TELEVISION ] = "Television", | |
1217 | [ CX88_VMUX_CABLE ] = "Cable TV", | |
1218 | [ CX88_VMUX_DVB ] = "DVB", | |
1219 | [ CX88_VMUX_DEBUG ] = "for debug only", | |
1220 | }; | |
f3334bcb | 1221 | unsigned int n = i->index; |
1da177e4 | 1222 | |
8d87cb9f MCC |
1223 | if (n >= 4) |
1224 | return -EINVAL; | |
6a59d64c | 1225 | if (0 == INPUT(n).type) |
8d87cb9f | 1226 | return -EINVAL; |
8d87cb9f | 1227 | i->type = V4L2_INPUT_TYPE_CAMERA; |
6a59d64c TP |
1228 | strcpy(i->name,iname[INPUT(n).type]); |
1229 | if ((CX88_VMUX_TELEVISION == INPUT(n).type) || | |
473d8024 | 1230 | (CX88_VMUX_CABLE == INPUT(n).type)) { |
8d87cb9f | 1231 | i->type = V4L2_INPUT_TYPE_TUNER; |
473d8024 | 1232 | } |
f33e9868 | 1233 | i->std = CX88_NORMS; |
8d87cb9f MCC |
1234 | return 0; |
1235 | } | |
54da49f5 MCC |
1236 | EXPORT_SYMBOL(cx88_enum_input); |
1237 | ||
1238 | static int vidioc_enum_input (struct file *file, void *priv, | |
1239 | struct v4l2_input *i) | |
1240 | { | |
1241 | struct cx88_core *core = ((struct cx8800_fh *)priv)->dev->core; | |
1242 | return cx88_enum_input (core,i); | |
1243 | } | |
1da177e4 | 1244 | |
8d87cb9f MCC |
1245 | static int vidioc_g_input (struct file *file, void *priv, unsigned int *i) |
1246 | { | |
1247 | struct cx88_core *core = ((struct cx8800_fh *)priv)->dev->core; | |
1da177e4 | 1248 | |
8d87cb9f MCC |
1249 | *i = core->input; |
1250 | return 0; | |
1251 | } | |
1da177e4 | 1252 | |
8d87cb9f MCC |
1253 | static int vidioc_s_input (struct file *file, void *priv, unsigned int i) |
1254 | { | |
1255 | struct cx88_core *core = ((struct cx8800_fh *)priv)->dev->core; | |
1da177e4 | 1256 | |
8d87cb9f MCC |
1257 | if (i >= 4) |
1258 | return -EINVAL; | |
f33e9868 HV |
1259 | if (0 == INPUT(i).type) |
1260 | return -EINVAL; | |
1da177e4 | 1261 | |
8d87cb9f MCC |
1262 | mutex_lock(&core->lock); |
1263 | cx88_newstation(core); | |
e90311a1 | 1264 | cx88_video_mux(core,i); |
8d87cb9f MCC |
1265 | mutex_unlock(&core->lock); |
1266 | return 0; | |
1267 | } | |
1da177e4 | 1268 | |
8d87cb9f MCC |
1269 | static int vidioc_g_tuner (struct file *file, void *priv, |
1270 | struct v4l2_tuner *t) | |
1271 | { | |
1272 | struct cx88_core *core = ((struct cx8800_fh *)priv)->dev->core; | |
1273 | u32 reg; | |
1da177e4 | 1274 | |
6a59d64c | 1275 | if (unlikely(UNSET == core->board.tuner_type)) |
8d87cb9f | 1276 | return -EINVAL; |
243d8c0f MCC |
1277 | if (0 != t->index) |
1278 | return -EINVAL; | |
a82decf6 | 1279 | |
8d87cb9f | 1280 | strcpy(t->name, "Television"); |
8d87cb9f MCC |
1281 | t->capability = V4L2_TUNER_CAP_NORM; |
1282 | t->rangehigh = 0xffffffffUL; | |
f33e9868 | 1283 | call_all(core, tuner, g_tuner, t); |
a82decf6 | 1284 | |
8d87cb9f MCC |
1285 | cx88_get_stereo(core ,t); |
1286 | reg = cx_read(MO_DEVICE_STATUS); | |
1287 | t->signal = (reg & (1<<5)) ? 0xffff : 0x0000; | |
1288 | return 0; | |
1289 | } | |
41ef7c1e | 1290 | |
8d87cb9f MCC |
1291 | static int vidioc_s_tuner (struct file *file, void *priv, |
1292 | struct v4l2_tuner *t) | |
1293 | { | |
1294 | struct cx88_core *core = ((struct cx8800_fh *)priv)->dev->core; | |
41ef7c1e | 1295 | |
6a59d64c | 1296 | if (UNSET == core->board.tuner_type) |
8d87cb9f MCC |
1297 | return -EINVAL; |
1298 | if (0 != t->index) | |
1299 | return -EINVAL; | |
c5287ba1 | 1300 | |
8d87cb9f MCC |
1301 | cx88_set_stereo(core, t->audmode, 1); |
1302 | return 0; | |
1303 | } | |
902fc997 | 1304 | |
8d87cb9f MCC |
1305 | static int vidioc_g_frequency (struct file *file, void *priv, |
1306 | struct v4l2_frequency *f) | |
1307 | { | |
1308 | struct cx8800_fh *fh = priv; | |
1309 | struct cx88_core *core = fh->dev->core; | |
902fc997 | 1310 | |
6a59d64c | 1311 | if (unlikely(UNSET == core->board.tuner_type)) |
8d87cb9f | 1312 | return -EINVAL; |
f33e9868 HV |
1313 | if (f->tuner) |
1314 | return -EINVAL; | |
8d87cb9f | 1315 | |
8d87cb9f MCC |
1316 | f->frequency = core->freq; |
1317 | ||
b8341e1d | 1318 | call_all(core, tuner, g_frequency, f); |
1da177e4 | 1319 | |
1da177e4 LT |
1320 | return 0; |
1321 | } | |
1322 | ||
54da49f5 | 1323 | int cx88_set_freq (struct cx88_core *core, |
b530a447 | 1324 | const struct v4l2_frequency *f) |
1da177e4 | 1325 | { |
b530a447 HV |
1326 | struct v4l2_frequency new_freq = *f; |
1327 | ||
6a59d64c | 1328 | if (unlikely(UNSET == core->board.tuner_type)) |
8d87cb9f MCC |
1329 | return -EINVAL; |
1330 | if (unlikely(f->tuner != 0)) | |
1331 | return -EINVAL; | |
54da49f5 | 1332 | |
8d87cb9f | 1333 | mutex_lock(&core->lock); |
8d87cb9f | 1334 | cx88_newstation(core); |
b8341e1d | 1335 | call_all(core, tuner, s_frequency, f); |
b530a447 HV |
1336 | call_all(core, tuner, g_frequency, &new_freq); |
1337 | core->freq = new_freq.frequency; | |
c7b0ac05 | 1338 | |
8d87cb9f MCC |
1339 | /* When changing channels it is required to reset TVAUDIO */ |
1340 | msleep (10); | |
1341 | cx88_set_tvaudio(core); | |
c7b0ac05 | 1342 | |
8d87cb9f | 1343 | mutex_unlock(&core->lock); |
54da49f5 | 1344 | |
8d87cb9f | 1345 | return 0; |
1da177e4 | 1346 | } |
54da49f5 MCC |
1347 | EXPORT_SYMBOL(cx88_set_freq); |
1348 | ||
1349 | static int vidioc_s_frequency (struct file *file, void *priv, | |
b530a447 | 1350 | const struct v4l2_frequency *f) |
54da49f5 MCC |
1351 | { |
1352 | struct cx8800_fh *fh = priv; | |
1353 | struct cx88_core *core = fh->dev->core; | |
1354 | ||
edbd138e | 1355 | return cx88_set_freq(core, f); |
54da49f5 | 1356 | } |
1da177e4 | 1357 | |
f33e9868 HV |
1358 | static int vidioc_g_chip_ident(struct file *file, void *priv, |
1359 | struct v4l2_dbg_chip_ident *chip) | |
1360 | { | |
1361 | if (!v4l2_chip_match_host(&chip->match)) | |
1362 | return -EINVAL; | |
1363 | chip->revision = 0; | |
1364 | chip->ident = V4L2_IDENT_UNKNOWN; | |
1365 | return 0; | |
1366 | } | |
1367 | ||
dbbff48f TP |
1368 | #ifdef CONFIG_VIDEO_ADV_DEBUG |
1369 | static int vidioc_g_register (struct file *file, void *fh, | |
aecde8b5 | 1370 | struct v4l2_dbg_register *reg) |
dbbff48f TP |
1371 | { |
1372 | struct cx88_core *core = ((struct cx8800_fh*)fh)->dev->core; | |
1373 | ||
aecde8b5 | 1374 | if (!v4l2_chip_match_host(®->match)) |
dbbff48f TP |
1375 | return -EINVAL; |
1376 | /* cx2388x has a 24-bit register space */ | |
aecde8b5 HV |
1377 | reg->val = cx_read(reg->reg & 0xffffff); |
1378 | reg->size = 4; | |
dbbff48f TP |
1379 | return 0; |
1380 | } | |
1381 | ||
1382 | static int vidioc_s_register (struct file *file, void *fh, | |
aecde8b5 | 1383 | struct v4l2_dbg_register *reg) |
dbbff48f TP |
1384 | { |
1385 | struct cx88_core *core = ((struct cx8800_fh*)fh)->dev->core; | |
1386 | ||
aecde8b5 | 1387 | if (!v4l2_chip_match_host(®->match)) |
dbbff48f | 1388 | return -EINVAL; |
aecde8b5 | 1389 | cx_write(reg->reg & 0xffffff, reg->val); |
dbbff48f TP |
1390 | return 0; |
1391 | } | |
1392 | #endif | |
8d87cb9f MCC |
1393 | |
1394 | /* ----------------------------------------------------------- */ | |
1395 | /* RADIO ESPECIFIC IOCTLS */ | |
1da177e4 LT |
1396 | /* ----------------------------------------------------------- */ |
1397 | ||
8d87cb9f MCC |
1398 | static int radio_g_tuner (struct file *file, void *priv, |
1399 | struct v4l2_tuner *t) | |
1400 | { | |
1401 | struct cx88_core *core = ((struct cx8800_fh *)priv)->dev->core; | |
1da177e4 | 1402 | |
8d87cb9f MCC |
1403 | if (unlikely(t->index > 0)) |
1404 | return -EINVAL; | |
1da177e4 | 1405 | |
8d87cb9f | 1406 | strcpy(t->name, "Radio"); |
1da177e4 | 1407 | |
b8341e1d | 1408 | call_all(core, tuner, g_tuner, t); |
8d87cb9f MCC |
1409 | return 0; |
1410 | } | |
1da177e4 | 1411 | |
8d87cb9f | 1412 | /* FIXME: Should add a standard for radio */ |
a82decf6 | 1413 | |
8d87cb9f MCC |
1414 | static int radio_s_tuner (struct file *file, void *priv, |
1415 | struct v4l2_tuner *t) | |
1416 | { | |
1417 | struct cx88_core *core = ((struct cx8800_fh *)priv)->dev->core; | |
a82decf6 | 1418 | |
8d87cb9f MCC |
1419 | if (0 != t->index) |
1420 | return -EINVAL; | |
f33e9868 HV |
1421 | if (t->audmode > V4L2_TUNER_MODE_STEREO) |
1422 | t->audmode = V4L2_TUNER_MODE_STEREO; | |
1da177e4 | 1423 | |
b8341e1d | 1424 | call_all(core, tuner, s_tuner, t); |
1da177e4 | 1425 | |
8d87cb9f MCC |
1426 | return 0; |
1427 | } | |
1da177e4 | 1428 | |
1da177e4 LT |
1429 | /* ----------------------------------------------------------- */ |
1430 | ||
1431 | static void cx8800_vid_timeout(unsigned long data) | |
1432 | { | |
1433 | struct cx8800_dev *dev = (struct cx8800_dev*)data; | |
1434 | struct cx88_core *core = dev->core; | |
1435 | struct cx88_dmaqueue *q = &dev->vidq; | |
1436 | struct cx88_buffer *buf; | |
1437 | unsigned long flags; | |
1438 | ||
e52e98a7 | 1439 | cx88_sram_channel_dump(core, &cx88_sram_channels[SRAM_CH21]); |
1da177e4 LT |
1440 | |
1441 | cx_clear(MO_VID_DMACNTRL, 0x11); | |
1442 | cx_clear(VID_CAPTURE_CONTROL, 0x06); | |
1443 | ||
1444 | spin_lock_irqsave(&dev->slock,flags); | |
1445 | while (!list_empty(&q->active)) { | |
1446 | buf = list_entry(q->active.next, struct cx88_buffer, vb.queue); | |
1447 | list_del(&buf->vb.queue); | |
0fc0686e | 1448 | buf->vb.state = VIDEOBUF_ERROR; |
1da177e4 LT |
1449 | wake_up(&buf->vb.done); |
1450 | printk("%s/0: [%p/%d] timeout - dma=0x%08lx\n", core->name, | |
1451 | buf, buf->vb.i, (unsigned long)buf->risc.dma); | |
1452 | } | |
1453 | restart_video_queue(dev,q); | |
1454 | spin_unlock_irqrestore(&dev->slock,flags); | |
1455 | } | |
1456 | ||
2e4e98e7 | 1457 | static const char *cx88_vid_irqs[32] = { |
41ef7c1e MCC |
1458 | "y_risci1", "u_risci1", "v_risci1", "vbi_risc1", |
1459 | "y_risci2", "u_risci2", "v_risci2", "vbi_risc2", | |
1460 | "y_oflow", "u_oflow", "v_oflow", "vbi_oflow", | |
1461 | "y_sync", "u_sync", "v_sync", "vbi_sync", | |
1462 | "opc_err", "par_err", "rip_err", "pci_abort", | |
1463 | }; | |
1464 | ||
1da177e4 LT |
1465 | static void cx8800_vid_irq(struct cx8800_dev *dev) |
1466 | { | |
1467 | struct cx88_core *core = dev->core; | |
1468 | u32 status, mask, count; | |
1469 | ||
1470 | status = cx_read(MO_VID_INTSTAT); | |
1471 | mask = cx_read(MO_VID_INTMSK); | |
1472 | if (0 == (status & mask)) | |
1473 | return; | |
1474 | cx_write(MO_VID_INTSTAT, status); | |
1475 | if (irq_debug || (status & mask & ~0xff)) | |
1476 | cx88_print_irqbits(core->name, "irq vid", | |
66623a04 MCC |
1477 | cx88_vid_irqs, ARRAY_SIZE(cx88_vid_irqs), |
1478 | status, mask); | |
1da177e4 LT |
1479 | |
1480 | /* risc op code error */ | |
1481 | if (status & (1 << 16)) { | |
1482 | printk(KERN_WARNING "%s/0: video risc op code error\n",core->name); | |
1483 | cx_clear(MO_VID_DMACNTRL, 0x11); | |
1484 | cx_clear(VID_CAPTURE_CONTROL, 0x06); | |
e52e98a7 | 1485 | cx88_sram_channel_dump(core, &cx88_sram_channels[SRAM_CH21]); |
1da177e4 LT |
1486 | } |
1487 | ||
1488 | /* risc1 y */ | |
1489 | if (status & 0x01) { | |
1490 | spin_lock(&dev->slock); | |
1491 | count = cx_read(MO_VIDY_GPCNT); | |
e52e98a7 | 1492 | cx88_wakeup(core, &dev->vidq, count); |
1da177e4 LT |
1493 | spin_unlock(&dev->slock); |
1494 | } | |
1495 | ||
1496 | /* risc1 vbi */ | |
1497 | if (status & 0x08) { | |
1498 | spin_lock(&dev->slock); | |
1499 | count = cx_read(MO_VBI_GPCNT); | |
e52e98a7 | 1500 | cx88_wakeup(core, &dev->vbiq, count); |
1da177e4 LT |
1501 | spin_unlock(&dev->slock); |
1502 | } | |
1503 | ||
1504 | /* risc2 y */ | |
1505 | if (status & 0x10) { | |
1506 | dprintk(2,"stopper video\n"); | |
1507 | spin_lock(&dev->slock); | |
1508 | restart_video_queue(dev,&dev->vidq); | |
1509 | spin_unlock(&dev->slock); | |
1510 | } | |
1511 | ||
1512 | /* risc2 vbi */ | |
1513 | if (status & 0x80) { | |
1514 | dprintk(2,"stopper vbi\n"); | |
1515 | spin_lock(&dev->slock); | |
1516 | cx8800_restart_vbi_queue(dev,&dev->vbiq); | |
1517 | spin_unlock(&dev->slock); | |
1518 | } | |
1519 | } | |
1520 | ||
7d12e780 | 1521 | static irqreturn_t cx8800_irq(int irq, void *dev_id) |
1da177e4 LT |
1522 | { |
1523 | struct cx8800_dev *dev = dev_id; | |
1524 | struct cx88_core *core = dev->core; | |
1525 | u32 status; | |
1526 | int loop, handled = 0; | |
1527 | ||
1528 | for (loop = 0; loop < 10; loop++) { | |
8ddac9ee TP |
1529 | status = cx_read(MO_PCI_INTSTAT) & |
1530 | (core->pci_irqmask | PCI_INT_VIDINT); | |
1da177e4 LT |
1531 | if (0 == status) |
1532 | goto out; | |
1533 | cx_write(MO_PCI_INTSTAT, status); | |
1534 | handled = 1; | |
1535 | ||
1536 | if (status & core->pci_irqmask) | |
1537 | cx88_core_irq(core,status); | |
8ddac9ee | 1538 | if (status & PCI_INT_VIDINT) |
1da177e4 | 1539 | cx8800_vid_irq(dev); |
c2c1b415 | 1540 | } |
1da177e4 LT |
1541 | if (10 == loop) { |
1542 | printk(KERN_WARNING "%s/0: irq loop -- clearing mask\n", | |
1543 | core->name); | |
1544 | cx_write(MO_PCI_INTMSK,0); | |
1545 | } | |
1546 | ||
1547 | out: | |
1548 | return IRQ_RETVAL(handled); | |
1549 | } | |
1550 | ||
1551 | /* ----------------------------------------------------------- */ | |
1552 | /* exported stuff */ | |
1553 | ||
bec43661 | 1554 | static const struct v4l2_file_operations video_fops = |
1da177e4 LT |
1555 | { |
1556 | .owner = THIS_MODULE, | |
1557 | .open = video_open, | |
1558 | .release = video_release, | |
1559 | .read = video_read, | |
1560 | .poll = video_poll, | |
1561 | .mmap = video_mmap, | |
b6187264 | 1562 | .unlocked_ioctl = video_ioctl2, |
1da177e4 LT |
1563 | }; |
1564 | ||
a399810c | 1565 | static const struct v4l2_ioctl_ops video_ioctl_ops = { |
8d87cb9f | 1566 | .vidioc_querycap = vidioc_querycap, |
78b526a4 HV |
1567 | .vidioc_enum_fmt_vid_cap = vidioc_enum_fmt_vid_cap, |
1568 | .vidioc_g_fmt_vid_cap = vidioc_g_fmt_vid_cap, | |
1569 | .vidioc_try_fmt_vid_cap = vidioc_try_fmt_vid_cap, | |
1570 | .vidioc_s_fmt_vid_cap = vidioc_s_fmt_vid_cap, | |
8d87cb9f MCC |
1571 | .vidioc_reqbufs = vidioc_reqbufs, |
1572 | .vidioc_querybuf = vidioc_querybuf, | |
1573 | .vidioc_qbuf = vidioc_qbuf, | |
1574 | .vidioc_dqbuf = vidioc_dqbuf, | |
48d68801 | 1575 | .vidioc_g_std = vidioc_g_std, |
8d87cb9f MCC |
1576 | .vidioc_s_std = vidioc_s_std, |
1577 | .vidioc_enum_input = vidioc_enum_input, | |
1578 | .vidioc_g_input = vidioc_g_input, | |
1579 | .vidioc_s_input = vidioc_s_input, | |
8d87cb9f MCC |
1580 | .vidioc_streamon = vidioc_streamon, |
1581 | .vidioc_streamoff = vidioc_streamoff, | |
8d87cb9f MCC |
1582 | .vidioc_g_tuner = vidioc_g_tuner, |
1583 | .vidioc_s_tuner = vidioc_s_tuner, | |
1584 | .vidioc_g_frequency = vidioc_g_frequency, | |
1585 | .vidioc_s_frequency = vidioc_s_frequency, | |
1a3c60a0 HV |
1586 | .vidioc_subscribe_event = v4l2_ctrl_subscribe_event, |
1587 | .vidioc_unsubscribe_event = v4l2_event_unsubscribe, | |
f33e9868 | 1588 | .vidioc_g_chip_ident = vidioc_g_chip_ident, |
dbbff48f TP |
1589 | #ifdef CONFIG_VIDEO_ADV_DEBUG |
1590 | .vidioc_g_register = vidioc_g_register, | |
1591 | .vidioc_s_register = vidioc_s_register, | |
1592 | #endif | |
a399810c HV |
1593 | }; |
1594 | ||
2e4e98e7 | 1595 | static const struct video_device cx8800_video_template = { |
a399810c | 1596 | .name = "cx8800-video", |
a399810c | 1597 | .fops = &video_fops, |
a399810c | 1598 | .ioctl_ops = &video_ioctl_ops, |
63ab1bdc | 1599 | .tvnorms = CX88_NORMS, |
1da177e4 LT |
1600 | }; |
1601 | ||
f33e9868 HV |
1602 | static const struct v4l2_ioctl_ops vbi_ioctl_ops = { |
1603 | .vidioc_querycap = vidioc_querycap, | |
1604 | .vidioc_g_fmt_vbi_cap = cx8800_vbi_fmt, | |
1605 | .vidioc_try_fmt_vbi_cap = cx8800_vbi_fmt, | |
1606 | .vidioc_s_fmt_vbi_cap = cx8800_vbi_fmt, | |
1607 | .vidioc_reqbufs = vidioc_reqbufs, | |
1608 | .vidioc_querybuf = vidioc_querybuf, | |
1609 | .vidioc_qbuf = vidioc_qbuf, | |
1610 | .vidioc_dqbuf = vidioc_dqbuf, | |
48d68801 | 1611 | .vidioc_g_std = vidioc_g_std, |
f33e9868 HV |
1612 | .vidioc_s_std = vidioc_s_std, |
1613 | .vidioc_enum_input = vidioc_enum_input, | |
1614 | .vidioc_g_input = vidioc_g_input, | |
1615 | .vidioc_s_input = vidioc_s_input, | |
1616 | .vidioc_streamon = vidioc_streamon, | |
1617 | .vidioc_streamoff = vidioc_streamoff, | |
1618 | .vidioc_g_tuner = vidioc_g_tuner, | |
1619 | .vidioc_s_tuner = vidioc_s_tuner, | |
1620 | .vidioc_g_frequency = vidioc_g_frequency, | |
1621 | .vidioc_s_frequency = vidioc_s_frequency, | |
1622 | .vidioc_g_chip_ident = vidioc_g_chip_ident, | |
1623 | #ifdef CONFIG_VIDEO_ADV_DEBUG | |
1624 | .vidioc_g_register = vidioc_g_register, | |
1625 | .vidioc_s_register = vidioc_s_register, | |
1626 | #endif | |
1627 | }; | |
1628 | ||
1629 | static const struct video_device cx8800_vbi_template = { | |
1630 | .name = "cx8800-vbi", | |
1631 | .fops = &video_fops, | |
1632 | .ioctl_ops = &vbi_ioctl_ops, | |
1633 | .tvnorms = CX88_NORMS, | |
f33e9868 HV |
1634 | }; |
1635 | ||
bec43661 | 1636 | static const struct v4l2_file_operations radio_fops = |
1da177e4 LT |
1637 | { |
1638 | .owner = THIS_MODULE, | |
1639 | .open = video_open, | |
1a3c60a0 | 1640 | .poll = v4l2_ctrl_poll, |
1da177e4 | 1641 | .release = video_release, |
b6187264 | 1642 | .unlocked_ioctl = video_ioctl2, |
1da177e4 LT |
1643 | }; |
1644 | ||
a399810c | 1645 | static const struct v4l2_ioctl_ops radio_ioctl_ops = { |
902e197d | 1646 | .vidioc_querycap = vidioc_querycap, |
8d87cb9f | 1647 | .vidioc_g_tuner = radio_g_tuner, |
8d87cb9f | 1648 | .vidioc_s_tuner = radio_s_tuner, |
8d87cb9f MCC |
1649 | .vidioc_g_frequency = vidioc_g_frequency, |
1650 | .vidioc_s_frequency = vidioc_s_frequency, | |
1a3c60a0 HV |
1651 | .vidioc_subscribe_event = v4l2_ctrl_subscribe_event, |
1652 | .vidioc_unsubscribe_event = v4l2_event_unsubscribe, | |
f33e9868 | 1653 | .vidioc_g_chip_ident = vidioc_g_chip_ident, |
a75d2048 TP |
1654 | #ifdef CONFIG_VIDEO_ADV_DEBUG |
1655 | .vidioc_g_register = vidioc_g_register, | |
1656 | .vidioc_s_register = vidioc_s_register, | |
1657 | #endif | |
1da177e4 LT |
1658 | }; |
1659 | ||
2e4e98e7 | 1660 | static const struct video_device cx8800_radio_template = { |
a399810c | 1661 | .name = "cx8800-radio", |
a399810c | 1662 | .fops = &radio_fops, |
a399810c HV |
1663 | .ioctl_ops = &radio_ioctl_ops, |
1664 | }; | |
1665 | ||
8c7cb12a HV |
1666 | static const struct v4l2_ctrl_ops cx8800_ctrl_vid_ops = { |
1667 | .s_ctrl = cx8800_s_vid_ctrl, | |
1668 | }; | |
1669 | ||
1670 | static const struct v4l2_ctrl_ops cx8800_ctrl_aud_ops = { | |
1671 | .s_ctrl = cx8800_s_aud_ctrl, | |
bac63981 HV |
1672 | }; |
1673 | ||
1da177e4 LT |
1674 | /* ----------------------------------------------------------- */ |
1675 | ||
1676 | static void cx8800_unregister_video(struct cx8800_dev *dev) | |
1677 | { | |
1678 | if (dev->radio_dev) { | |
f0813b4c | 1679 | if (video_is_registered(dev->radio_dev)) |
1da177e4 LT |
1680 | video_unregister_device(dev->radio_dev); |
1681 | else | |
1682 | video_device_release(dev->radio_dev); | |
1683 | dev->radio_dev = NULL; | |
1684 | } | |
1685 | if (dev->vbi_dev) { | |
f0813b4c | 1686 | if (video_is_registered(dev->vbi_dev)) |
1da177e4 LT |
1687 | video_unregister_device(dev->vbi_dev); |
1688 | else | |
1689 | video_device_release(dev->vbi_dev); | |
1690 | dev->vbi_dev = NULL; | |
1691 | } | |
1692 | if (dev->video_dev) { | |
f0813b4c | 1693 | if (video_is_registered(dev->video_dev)) |
1da177e4 LT |
1694 | video_unregister_device(dev->video_dev); |
1695 | else | |
1696 | video_device_release(dev->video_dev); | |
1697 | dev->video_dev = NULL; | |
1698 | } | |
1699 | } | |
1700 | ||
4c62e976 GKH |
1701 | static int cx8800_initdev(struct pci_dev *pci_dev, |
1702 | const struct pci_device_id *pci_id) | |
1da177e4 LT |
1703 | { |
1704 | struct cx8800_dev *dev; | |
1705 | struct cx88_core *core; | |
1706 | int err; | |
bac63981 | 1707 | int i; |
1da177e4 | 1708 | |
7408187d | 1709 | dev = kzalloc(sizeof(*dev),GFP_KERNEL); |
1da177e4 LT |
1710 | if (NULL == dev) |
1711 | return -ENOMEM; | |
1da177e4 LT |
1712 | |
1713 | /* pci init */ | |
1714 | dev->pci = pci_dev; | |
1715 | if (pci_enable_device(pci_dev)) { | |
1716 | err = -EIO; | |
1717 | goto fail_free; | |
1718 | } | |
1719 | core = cx88_core_get(dev->pci); | |
1720 | if (NULL == core) { | |
1721 | err = -EINVAL; | |
1722 | goto fail_free; | |
1723 | } | |
1724 | dev->core = core; | |
1725 | ||
1726 | /* print pci info */ | |
abd34d8d | 1727 | dev->pci_rev = pci_dev->revision; |
4ac97914 MCC |
1728 | pci_read_config_byte(pci_dev, PCI_LATENCY_TIMER, &dev->pci_lat); |
1729 | printk(KERN_INFO "%s/0: found at %s, rev: %d, irq: %d, " | |
228aef63 | 1730 | "latency: %d, mmio: 0x%llx\n", core->name, |
1da177e4 | 1731 | pci_name(pci_dev), dev->pci_rev, pci_dev->irq, |
228aef63 | 1732 | dev->pci_lat,(unsigned long long)pci_resource_start(pci_dev,0)); |
1da177e4 LT |
1733 | |
1734 | pci_set_master(pci_dev); | |
284901a9 | 1735 | if (!pci_dma_supported(pci_dev,DMA_BIT_MASK(32))) { |
1da177e4 LT |
1736 | printk("%s/0: Oops: no 32bit PCI DMA ???\n",core->name); |
1737 | err = -EIO; | |
1738 | goto fail_core; | |
1739 | } | |
1740 | ||
1741 | /* initialize driver struct */ | |
1da177e4 | 1742 | spin_lock_init(&dev->slock); |
48d68801 | 1743 | core->tvnorm = V4L2_STD_NTSC_M; |
1da177e4 LT |
1744 | |
1745 | /* init video dma queues */ | |
1746 | INIT_LIST_HEAD(&dev->vidq.active); | |
1747 | INIT_LIST_HEAD(&dev->vidq.queued); | |
1748 | dev->vidq.timeout.function = cx8800_vid_timeout; | |
1749 | dev->vidq.timeout.data = (unsigned long)dev; | |
1750 | init_timer(&dev->vidq.timeout); | |
1751 | cx88_risc_stopper(dev->pci,&dev->vidq.stopper, | |
1752 | MO_VID_DMACNTRL,0x11,0x00); | |
1753 | ||
1754 | /* init vbi dma queues */ | |
1755 | INIT_LIST_HEAD(&dev->vbiq.active); | |
1756 | INIT_LIST_HEAD(&dev->vbiq.queued); | |
1757 | dev->vbiq.timeout.function = cx8800_vbi_timeout; | |
1758 | dev->vbiq.timeout.data = (unsigned long)dev; | |
1759 | init_timer(&dev->vbiq.timeout); | |
1760 | cx88_risc_stopper(dev->pci,&dev->vbiq.stopper, | |
1761 | MO_VID_DMACNTRL,0x88,0x00); | |
1762 | ||
1763 | /* get irq */ | |
1764 | err = request_irq(pci_dev->irq, cx8800_irq, | |
8076fe32 | 1765 | IRQF_SHARED | IRQF_DISABLED, core->name, dev); |
1da177e4 | 1766 | if (err < 0) { |
5772f813 | 1767 | printk(KERN_ERR "%s/0: can't get IRQ %d\n", |
1da177e4 LT |
1768 | core->name,pci_dev->irq); |
1769 | goto fail_core; | |
1770 | } | |
1771 | cx_set(MO_PCI_INTMSK, core->pci_irqmask); | |
1772 | ||
8c7cb12a HV |
1773 | for (i = 0; i < CX8800_AUD_CTLS; i++) { |
1774 | const struct cx88_ctrl *cc = &cx8800_aud_ctls[i]; | |
1775 | struct v4l2_ctrl *vc; | |
1776 | ||
1777 | vc = v4l2_ctrl_new_std(&core->audio_hdl, &cx8800_ctrl_aud_ops, | |
1778 | cc->id, cc->minimum, cc->maximum, cc->step, cc->default_value); | |
1779 | if (vc == NULL) { | |
1780 | err = core->audio_hdl.error; | |
1781 | goto fail_core; | |
1782 | } | |
1783 | vc->priv = (void *)cc; | |
1784 | } | |
1785 | ||
1786 | for (i = 0; i < CX8800_VID_CTLS; i++) { | |
1787 | const struct cx88_ctrl *cc = &cx8800_vid_ctls[i]; | |
bac63981 HV |
1788 | struct v4l2_ctrl *vc; |
1789 | ||
8c7cb12a | 1790 | vc = v4l2_ctrl_new_std(&core->video_hdl, &cx8800_ctrl_vid_ops, |
bac63981 HV |
1791 | cc->id, cc->minimum, cc->maximum, cc->step, cc->default_value); |
1792 | if (vc == NULL) { | |
8c7cb12a | 1793 | err = core->video_hdl.error; |
bac63981 HV |
1794 | goto fail_core; |
1795 | } | |
1796 | vc->priv = (void *)cc; | |
8c7cb12a HV |
1797 | if (vc->id == V4L2_CID_CHROMA_AGC) |
1798 | core->chroma_agc = vc; | |
bac63981 | 1799 | } |
34a6b7d0 | 1800 | v4l2_ctrl_add_handler(&core->video_hdl, &core->audio_hdl, NULL); |
bac63981 | 1801 | |
1da177e4 | 1802 | /* load and configure helper modules */ |
e52e98a7 | 1803 | |
6951803c LR |
1804 | if (core->board.audio_chip == V4L2_IDENT_WM8775) { |
1805 | struct i2c_board_info wm8775_info = { | |
1806 | .type = "wm8775", | |
1807 | .addr = 0x36 >> 1, | |
1808 | .platform_data = &core->wm8775_data, | |
1809 | }; | |
1810 | struct v4l2_subdev *sd; | |
1811 | ||
1812 | if (core->boardnr == CX88_BOARD_HAUPPAUGE_NOVASPLUS_S1) | |
1813 | core->wm8775_data.is_nova_s = true; | |
1814 | else | |
1815 | core->wm8775_data.is_nova_s = false; | |
1816 | ||
1817 | sd = v4l2_i2c_new_subdev_board(&core->v4l2_dev, &core->i2c_adap, | |
1818 | &wm8775_info, NULL); | |
bac63981 HV |
1819 | if (sd != NULL) { |
1820 | core->sd_wm8775 = sd; | |
6951803c | 1821 | sd->grp_id = WM8775_GID; |
bac63981 | 1822 | } |
6951803c | 1823 | } |
b8341e1d HV |
1824 | |
1825 | if (core->board.audio_chip == V4L2_IDENT_TVAUDIO) { | |
1826 | /* This probes for a tda9874 as is used on some | |
1827 | Pixelview Ultra boards. */ | |
9a1f8b34 LP |
1828 | v4l2_i2c_new_subdev(&core->v4l2_dev, &core->i2c_adap, |
1829 | "tvaudio", 0, I2C_ADDRS(0xb0 >> 1)); | |
b8341e1d | 1830 | } |
3057906d | 1831 | |
6fcecce7 MK |
1832 | switch (core->boardnr) { |
1833 | case CX88_BOARD_DVICO_FUSIONHDTV_5_GOLD: | |
b8341e1d | 1834 | case CX88_BOARD_DVICO_FUSIONHDTV_7_GOLD: { |
2e4e98e7 | 1835 | static const struct i2c_board_info rtc_info = { |
b8341e1d HV |
1836 | I2C_BOARD_INFO("isl1208", 0x6f) |
1837 | }; | |
1838 | ||
6fcecce7 | 1839 | request_module("rtc-isl1208"); |
b8341e1d HV |
1840 | core->i2c_rtc = i2c_new_device(&core->i2c_adap, &rtc_info); |
1841 | } | |
8efd2e28 MK |
1842 | /* break intentionally omitted */ |
1843 | case CX88_BOARD_DVICO_FUSIONHDTV_5_PCI_NANO: | |
1844 | request_module("ir-kbd-i2c"); | |
6fcecce7 MK |
1845 | } |
1846 | ||
121ec132 MCC |
1847 | /* Sets device info at pci_dev */ |
1848 | pci_set_drvdata(pci_dev, dev); | |
1849 | ||
c5a86144 HV |
1850 | dev->width = 320; |
1851 | dev->height = 240; | |
1852 | dev->fmt = format_by_fourcc(V4L2_PIX_FMT_BGR24); | |
1853 | ||
121ec132 MCC |
1854 | /* initial device configuration */ |
1855 | mutex_lock(&core->lock); | |
1856 | cx88_set_tvnorm(core, core->tvnorm); | |
8c7cb12a HV |
1857 | v4l2_ctrl_handler_setup(&core->video_hdl); |
1858 | v4l2_ctrl_handler_setup(&core->audio_hdl); | |
121ec132 MCC |
1859 | cx88_video_mux(core, 0); |
1860 | ||
1da177e4 LT |
1861 | /* register v4l devices */ |
1862 | dev->video_dev = cx88_vdev_init(core,dev->pci, | |
1863 | &cx8800_video_template,"video"); | |
63b0d5ad | 1864 | video_set_drvdata(dev->video_dev, dev); |
8c7cb12a | 1865 | dev->video_dev->ctrl_handler = &core->video_hdl; |
1da177e4 LT |
1866 | err = video_register_device(dev->video_dev,VFL_TYPE_GRABBER, |
1867 | video_nr[core->nr]); | |
1868 | if (err < 0) { | |
5772f813 | 1869 | printk(KERN_ERR "%s/0: can't register video device\n", |
1da177e4 LT |
1870 | core->name); |
1871 | goto fail_unreg; | |
1872 | } | |
38c7c036 LP |
1873 | printk(KERN_INFO "%s/0: registered device %s [v4l2]\n", |
1874 | core->name, video_device_node_name(dev->video_dev)); | |
1da177e4 LT |
1875 | |
1876 | dev->vbi_dev = cx88_vdev_init(core,dev->pci,&cx8800_vbi_template,"vbi"); | |
63b0d5ad | 1877 | video_set_drvdata(dev->vbi_dev, dev); |
1da177e4 LT |
1878 | err = video_register_device(dev->vbi_dev,VFL_TYPE_VBI, |
1879 | vbi_nr[core->nr]); | |
1880 | if (err < 0) { | |
5772f813 | 1881 | printk(KERN_ERR "%s/0: can't register vbi device\n", |
1da177e4 LT |
1882 | core->name); |
1883 | goto fail_unreg; | |
1884 | } | |
38c7c036 LP |
1885 | printk(KERN_INFO "%s/0: registered device %s\n", |
1886 | core->name, video_device_node_name(dev->vbi_dev)); | |
1da177e4 | 1887 | |
6a59d64c | 1888 | if (core->board.radio.type == CX88_RADIO) { |
1da177e4 LT |
1889 | dev->radio_dev = cx88_vdev_init(core,dev->pci, |
1890 | &cx8800_radio_template,"radio"); | |
63b0d5ad | 1891 | video_set_drvdata(dev->radio_dev, dev); |
8c7cb12a | 1892 | dev->radio_dev->ctrl_handler = &core->audio_hdl; |
1da177e4 LT |
1893 | err = video_register_device(dev->radio_dev,VFL_TYPE_RADIO, |
1894 | radio_nr[core->nr]); | |
1895 | if (err < 0) { | |
5772f813 | 1896 | printk(KERN_ERR "%s/0: can't register radio device\n", |
1da177e4 LT |
1897 | core->name); |
1898 | goto fail_unreg; | |
1899 | } | |
38c7c036 LP |
1900 | printk(KERN_INFO "%s/0: registered device %s\n", |
1901 | core->name, video_device_node_name(dev->radio_dev)); | |
1da177e4 LT |
1902 | } |
1903 | ||
1da177e4 | 1904 | /* start tvaudio thread */ |
6a59d64c | 1905 | if (core->board.tuner_type != TUNER_ABSENT) { |
1da177e4 | 1906 | core->kthread = kthread_run(cx88_audio_thread, core, "cx88 tvaudio"); |
32b78de7 CG |
1907 | if (IS_ERR(core->kthread)) { |
1908 | err = PTR_ERR(core->kthread); | |
5772f813 TP |
1909 | printk(KERN_ERR "%s/0: failed to create cx88 audio thread, err=%d\n", |
1910 | core->name, err); | |
32b78de7 CG |
1911 | } |
1912 | } | |
121ec132 MCC |
1913 | mutex_unlock(&core->lock); |
1914 | ||
1da177e4 LT |
1915 | return 0; |
1916 | ||
1917 | fail_unreg: | |
1918 | cx8800_unregister_video(dev); | |
1919 | free_irq(pci_dev->irq, dev); | |
121ec132 | 1920 | mutex_unlock(&core->lock); |
1da177e4 LT |
1921 | fail_core: |
1922 | cx88_core_put(core,dev->pci); | |
1923 | fail_free: | |
1924 | kfree(dev); | |
1925 | return err; | |
1926 | } | |
1927 | ||
4c62e976 | 1928 | static void cx8800_finidev(struct pci_dev *pci_dev) |
1da177e4 | 1929 | { |
4ac97914 | 1930 | struct cx8800_dev *dev = pci_get_drvdata(pci_dev); |
e52e98a7 | 1931 | struct cx88_core *core = dev->core; |
1da177e4 LT |
1932 | |
1933 | /* stop thread */ | |
e52e98a7 MCC |
1934 | if (core->kthread) { |
1935 | kthread_stop(core->kthread); | |
1936 | core->kthread = NULL; | |
1da177e4 LT |
1937 | } |
1938 | ||
b12203d2 | 1939 | if (core->ir) |
92f4fc10 | 1940 | cx88_ir_stop(core); |
b12203d2 | 1941 | |
e52e98a7 | 1942 | cx88_shutdown(core); /* FIXME */ |
1da177e4 LT |
1943 | pci_disable_device(pci_dev); |
1944 | ||
1945 | /* unregister stuff */ | |
1946 | ||
1947 | free_irq(pci_dev->irq, dev); | |
1948 | cx8800_unregister_video(dev); | |
1949 | pci_set_drvdata(pci_dev, NULL); | |
1950 | ||
1951 | /* free memory */ | |
1952 | btcx_riscmem_free(dev->pci,&dev->vidq.stopper); | |
e52e98a7 | 1953 | cx88_core_put(core,dev->pci); |
1da177e4 LT |
1954 | kfree(dev); |
1955 | } | |
1956 | ||
17bc98a4 | 1957 | #ifdef CONFIG_PM |
1da177e4 LT |
1958 | static int cx8800_suspend(struct pci_dev *pci_dev, pm_message_t state) |
1959 | { | |
b45009b0 | 1960 | struct cx8800_dev *dev = pci_get_drvdata(pci_dev); |
1da177e4 LT |
1961 | struct cx88_core *core = dev->core; |
1962 | ||
1963 | /* stop video+vbi capture */ | |
1964 | spin_lock(&dev->slock); | |
1965 | if (!list_empty(&dev->vidq.active)) { | |
5772f813 | 1966 | printk("%s/0: suspend video\n", core->name); |
1da177e4 LT |
1967 | stop_video_dma(dev); |
1968 | del_timer(&dev->vidq.timeout); | |
1969 | } | |
1970 | if (!list_empty(&dev->vbiq.active)) { | |
5772f813 | 1971 | printk("%s/0: suspend vbi\n", core->name); |
1da177e4 LT |
1972 | cx8800_stop_vbi_dma(dev); |
1973 | del_timer(&dev->vbiq.timeout); | |
1974 | } | |
1975 | spin_unlock(&dev->slock); | |
1976 | ||
13595a51 | 1977 | if (core->ir) |
92f4fc10 | 1978 | cx88_ir_stop(core); |
1da177e4 | 1979 | /* FIXME -- shutdown device */ |
e52e98a7 | 1980 | cx88_shutdown(core); |
1da177e4 LT |
1981 | |
1982 | pci_save_state(pci_dev); | |
1983 | if (0 != pci_set_power_state(pci_dev, pci_choose_state(pci_dev, state))) { | |
1984 | pci_disable_device(pci_dev); | |
1985 | dev->state.disabled = 1; | |
1986 | } | |
1987 | return 0; | |
1988 | } | |
1989 | ||
1990 | static int cx8800_resume(struct pci_dev *pci_dev) | |
1991 | { | |
b45009b0 | 1992 | struct cx8800_dev *dev = pci_get_drvdata(pci_dev); |
1da177e4 | 1993 | struct cx88_core *core = dev->core; |
08adb9e2 | 1994 | int err; |
1da177e4 LT |
1995 | |
1996 | if (dev->state.disabled) { | |
08adb9e2 MCC |
1997 | err=pci_enable_device(pci_dev); |
1998 | if (err) { | |
5772f813 TP |
1999 | printk(KERN_ERR "%s/0: can't enable device\n", |
2000 | core->name); | |
08adb9e2 MCC |
2001 | return err; |
2002 | } | |
2003 | ||
1da177e4 LT |
2004 | dev->state.disabled = 0; |
2005 | } | |
08adb9e2 MCC |
2006 | err= pci_set_power_state(pci_dev, PCI_D0); |
2007 | if (err) { | |
5772f813 | 2008 | printk(KERN_ERR "%s/0: can't set power state\n", core->name); |
08adb9e2 MCC |
2009 | pci_disable_device(pci_dev); |
2010 | dev->state.disabled = 1; | |
2011 | ||
2012 | return err; | |
2013 | } | |
1da177e4 LT |
2014 | pci_restore_state(pci_dev); |
2015 | ||
1da177e4 | 2016 | /* FIXME: re-initialize hardware */ |
e52e98a7 | 2017 | cx88_reset(core); |
13595a51 | 2018 | if (core->ir) |
92f4fc10 | 2019 | cx88_ir_start(core); |
13595a51 MCC |
2020 | |
2021 | cx_set(MO_PCI_INTMSK, core->pci_irqmask); | |
1da177e4 LT |
2022 | |
2023 | /* restart video+vbi capture */ | |
2024 | spin_lock(&dev->slock); | |
2025 | if (!list_empty(&dev->vidq.active)) { | |
5772f813 | 2026 | printk("%s/0: resume video\n", core->name); |
1da177e4 LT |
2027 | restart_video_queue(dev,&dev->vidq); |
2028 | } | |
2029 | if (!list_empty(&dev->vbiq.active)) { | |
5772f813 | 2030 | printk("%s/0: resume vbi\n", core->name); |
1da177e4 LT |
2031 | cx8800_restart_vbi_queue(dev,&dev->vbiq); |
2032 | } | |
2033 | spin_unlock(&dev->slock); | |
2034 | ||
2035 | return 0; | |
2036 | } | |
17bc98a4 | 2037 | #endif |
1da177e4 LT |
2038 | |
2039 | /* ----------------------------------------------------------- */ | |
2040 | ||
2e4e98e7 | 2041 | static const struct pci_device_id cx8800_pci_tbl[] = { |
1da177e4 LT |
2042 | { |
2043 | .vendor = 0x14f1, | |
2044 | .device = 0x8800, | |
b45009b0 MCC |
2045 | .subvendor = PCI_ANY_ID, |
2046 | .subdevice = PCI_ANY_ID, | |
1da177e4 LT |
2047 | },{ |
2048 | /* --- end of list --- */ | |
2049 | } | |
2050 | }; | |
2051 | MODULE_DEVICE_TABLE(pci, cx8800_pci_tbl); | |
2052 | ||
2053 | static struct pci_driver cx8800_pci_driver = { | |
b45009b0 MCC |
2054 | .name = "cx8800", |
2055 | .id_table = cx8800_pci_tbl, | |
2056 | .probe = cx8800_initdev, | |
4c62e976 | 2057 | .remove = cx8800_finidev, |
17bc98a4 | 2058 | #ifdef CONFIG_PM |
1da177e4 LT |
2059 | .suspend = cx8800_suspend, |
2060 | .resume = cx8800_resume, | |
17bc98a4 | 2061 | #endif |
1da177e4 LT |
2062 | }; |
2063 | ||
31d0f845 | 2064 | static int __init cx8800_init(void) |
1da177e4 | 2065 | { |
1990d50b MCC |
2066 | printk(KERN_INFO "cx88/0: cx2388x v4l2 driver version %s loaded\n", |
2067 | CX88_VERSION); | |
1da177e4 LT |
2068 | return pci_register_driver(&cx8800_pci_driver); |
2069 | } | |
2070 | ||
31d0f845 | 2071 | static void __exit cx8800_fini(void) |
1da177e4 LT |
2072 | { |
2073 | pci_unregister_driver(&cx8800_pci_driver); | |
2074 | } | |
2075 | ||
2076 | module_init(cx8800_init); | |
2077 | module_exit(cx8800_fini); |