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[media] ddbridge: add i2c_read_regs()
[mirror_ubuntu-artful-kernel.git] / drivers / media / pci / ddbridge / ddbridge-core.c
CommitLineData
ccad0457
RM		 1/*
2 * ddbridge.c: Digital Devices PCIe bridge driver
3 *
4 * Copyright (C) 2010-2011 Digital Devices GmbH
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 only, as published by the Free Software Foundation.
9 *
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
bcb63314
SA		 16 * To obtain the license, point your browser to
17 * http://www.gnu.org/copyleft/gpl.html
ccad0457
RM		 18 */
19
20#include <linux/module.h>
21#include <linux/init.h>
22#include <linux/interrupt.h>
23#include <linux/delay.h>
24#include <linux/slab.h>
25#include <linux/poll.h>
28d45a5d 26#include <linux/io.h>
ccad0457
RM		 27#include <linux/pci.h>
28#include <linux/pci_ids.h>
29#include <linux/timer.h>
ccad0457
RM		 30#include <linux/i2c.h>
31#include <linux/swab.h>
32#include <linux/vmalloc.h>
33#include "ddbridge.h"
34
35#include "ddbridge-regs.h"
36
37#include "tda18271c2dd.h"
38#include "stv6110x.h"
39#include "stv090x.h"
40#include "lnbh24.h"
41#include "drxk.h"
42
43DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr);
44
45/* MSI had problems with lost interrupts, fixed but needs testing */
46#undef CONFIG_PCI_MSI
47
48/******************************************************************************/
49
50static int i2c_read(struct i2c_adapter *adapter, u8 adr, u8 *val)
51{
52 struct i2c_msg msgs[1] = {{.addr = adr, .flags = I2C_M_RD,
4f1f3107 53 .buf = val, .len = 1 } };
ccad0457
RM		 54 return (i2c_transfer(adapter, msgs, 1) == 1) ? 0 : -1;
55}
56
6b1256b7
DS		 57static int i2c_read_regs(struct i2c_adapter *adapter,
58 u8 adr, u8 reg, u8 *val, u8 len)
ccad0457
RM		 59{
60 struct i2c_msg msgs[2] = {{.addr = adr, .flags = 0,
61 .buf = &reg, .len = 1 },
62 {.addr = adr, .flags = I2C_M_RD,
6b1256b7 63 .buf = val, .len = len } };
ccad0457
RM		 64 return (i2c_transfer(adapter, msgs, 2) == 2) ? 0 : -1;
65}
66
6b1256b7
DS		 67static int i2c_read_reg(struct i2c_adapter *adapter, u8 adr, u8 reg, u8 *val)
68{
69 return i2c_read_regs(adapter, adr, reg, val, 1);
70}
71
ccad0457
RM		 72static int i2c_read_reg16(struct i2c_adapter *adapter, u8 adr,
73 u16 reg, u8 *val)
74{
75 u8 msg[2] = {reg>>8, reg&0xff};
76 struct i2c_msg msgs[2] = {{.addr = adr, .flags = 0,
77 .buf = msg, .len = 2},
78 {.addr = adr, .flags = I2C_M_RD,
4f1f3107 79 .buf = val, .len = 1} };
ccad0457
RM		 80 return (i2c_transfer(adapter, msgs, 2) == 2) ? 0 : -1;
81}
82
83static int ddb_i2c_cmd(struct ddb_i2c *i2c, u32 adr, u32 cmd)
84{
85 struct ddb *dev = i2c->dev;
4bdbcb31 86 long stat;
ccad0457
RM		 87 u32 val;
88
89 i2c->done = 0;
90 ddbwritel((adr << 9) | cmd, i2c->regs + I2C_COMMAND);
91 stat = wait_event_timeout(i2c->wq, i2c->done == 1, HZ);
4bdbcb31 92 if (stat == 0) {
4f1f3107 93 printk(KERN_ERR "I2C timeout\n");
ccad0457
RM		 94 { /* MSI debugging*/
95 u32 istat = ddbreadl(INTERRUPT_STATUS);
4f1f3107 96 printk(KERN_ERR "IRS %08x\n", istat);
ccad0457
RM		 97 ddbwritel(istat, INTERRUPT_ACK);
98 }
99 return -EIO;
100 }
4f1f3107 101 val = ddbreadl(i2c->regs+I2C_COMMAND);
ccad0457
RM		 102 if (val & 0x70000)
103 return -EIO;
104 return 0;
105}
106
107static int ddb_i2c_master_xfer(struct i2c_adapter *adapter,
108 struct i2c_msg msg[], int num)
109{
110 struct ddb_i2c *i2c = (struct ddb_i2c *)i2c_get_adapdata(adapter);
111 struct ddb *dev = i2c->dev;
4f1f3107 112 u8 addr = 0;
ccad0457
RM		 113
114 if (num)
115 addr = msg[0].addr;
116
117 if (num == 2 && msg[1].flags & I2C_M_RD &&
118 !(msg[0].flags & I2C_M_RD)) {
119 memcpy_toio(dev->regs + I2C_TASKMEM_BASE + i2c->wbuf,
4f1f3107 120 msg[0].buf, msg[0].len);
ccad0457
RM		 121 ddbwritel(msg[0].len|(msg[1].len << 16),
122 i2c->regs+I2C_TASKLENGTH);
123 if (!ddb_i2c_cmd(i2c, addr, 1)) {
124 memcpy_fromio(msg[1].buf,
125 dev->regs + I2C_TASKMEM_BASE + i2c->rbuf,
126 msg[1].len);
127 return num;
128 }
129 }
130
131 if (num == 1 && !(msg[0].flags & I2C_M_RD)) {
4f1f3107 132 ddbcpyto(I2C_TASKMEM_BASE + i2c->wbuf, msg[0].buf, msg[0].len);
ccad0457
RM		 133 ddbwritel(msg[0].len, i2c->regs + I2C_TASKLENGTH);
134 if (!ddb_i2c_cmd(i2c, addr, 2))
135 return num;
136 }
137 if (num == 1 && (msg[0].flags & I2C_M_RD)) {
138 ddbwritel(msg[0].len << 16, i2c->regs + I2C_TASKLENGTH);
139 if (!ddb_i2c_cmd(i2c, addr, 3)) {
140 ddbcpyfrom(msg[0].buf,
141 I2C_TASKMEM_BASE + i2c->rbuf, msg[0].len);
142 return num;
143 }
144 }
145 return -EIO;
146}
147
148
149static u32 ddb_i2c_functionality(struct i2c_adapter *adap)
150{
151 return I2C_FUNC_SMBUS_EMUL;
152}
153
b5c00cc5 154static struct i2c_algorithm ddb_i2c_algo = {
ccad0457
RM		 155 .master_xfer = ddb_i2c_master_xfer,
156 .functionality = ddb_i2c_functionality,
157};
158
159static void ddb_i2c_release(struct ddb *dev)
160{
161 int i;
162 struct ddb_i2c *i2c;
163 struct i2c_adapter *adap;
164
165 for (i = 0; i < dev->info->port_num; i++) {
166 i2c = &dev->i2c[i];
167 adap = &i2c->adap;
168 i2c_del_adapter(adap);
169 }
170}
171
172static int ddb_i2c_init(struct ddb *dev)
173{
174 int i, j, stat = 0;
175 struct ddb_i2c *i2c;
176 struct i2c_adapter *adap;
177
178 for (i = 0; i < dev->info->port_num; i++) {
179 i2c = &dev->i2c[i];
180 i2c->dev = dev;
181 i2c->nr = i;
182 i2c->wbuf = i * (I2C_TASKMEM_SIZE / 4);
183 i2c->rbuf = i2c->wbuf + (I2C_TASKMEM_SIZE / 8);
184 i2c->regs = 0x80 + i * 0x20;
185 ddbwritel(I2C_SPEED_100, i2c->regs + I2C_TIMING);
186 ddbwritel((i2c->rbuf << 16) | i2c->wbuf,
187 i2c->regs + I2C_TASKADDRESS);
188 init_waitqueue_head(&i2c->wq);
189
190 adap = &i2c->adap;
191 i2c_set_adapdata(adap, i2c);
192#ifdef I2C_ADAP_CLASS_TV_DIGITAL
193 adap->class = I2C_ADAP_CLASS_TV_DIGITAL|I2C_CLASS_TV_ANALOG;
194#else
195#ifdef I2C_CLASS_TV_ANALOG
196 adap->class = I2C_CLASS_TV_ANALOG;
197#endif
198#endif
199 strcpy(adap->name, "ddbridge");
200 adap->algo = &ddb_i2c_algo;
201 adap->algo_data = (void *)i2c;
202 adap->dev.parent = &dev->pdev->dev;
203 stat = i2c_add_adapter(adap);
204 if (stat)
205 break;
206 }
207 if (stat)
208 for (j = 0; j < i; j++) {
209 i2c = &dev->i2c[j];
210 adap = &i2c->adap;
211 i2c_del_adapter(adap);
212 }
213 return stat;
214}
215
216
217/******************************************************************************/
218/******************************************************************************/
219/******************************************************************************/
220
4f1f3107 221#if 0
ccad0457
RM		 222static void set_table(struct ddb *dev, u32 off,
223 dma_addr_t *pbuf, u32 num)
224{
225 u32 i, base;
226 u64 mem;
227
228 base = DMA_BASE_ADDRESS_TABLE + off;
229 for (i = 0; i < num; i++) {
230 mem = pbuf[i];
231 ddbwritel(mem & 0xffffffff, base + i * 8);
232 ddbwritel(mem >> 32, base + i * 8 + 4);
233 }
234}
4f1f3107 235#endif
ccad0457
RM		 236
237static void ddb_address_table(struct ddb *dev)
238{
239 u32 i, j, base;
240 u64 mem;
241 dma_addr_t *pbuf;
242
243 for (i = 0; i < dev->info->port_num * 2; i++) {
244 base = DMA_BASE_ADDRESS_TABLE + i * 0x100;
245 pbuf = dev->input[i].pbuf;
246 for (j = 0; j < dev->input[i].dma_buf_num; j++) {
247 mem = pbuf[j];
248 ddbwritel(mem & 0xffffffff, base + j * 8);
249 ddbwritel(mem >> 32, base + j * 8 + 4);
250 }
251 }
252 for (i = 0; i < dev->info->port_num; i++) {
253 base = DMA_BASE_ADDRESS_TABLE + 0x800 + i * 0x100;
254 pbuf = dev->output[i].pbuf;
255 for (j = 0; j < dev->output[i].dma_buf_num; j++) {
256 mem = pbuf[j];
257 ddbwritel(mem & 0xffffffff, base + j * 8);
258 ddbwritel(mem >> 32, base + j * 8 + 4);
259 }
260 }
261}
262
263static void io_free(struct pci_dev *pdev, u8 **vbuf,
264 dma_addr_t *pbuf, u32 size, int num)
265{
266 int i;
267
268 for (i = 0; i < num; i++) {
269 if (vbuf[i]) {
270 pci_free_consistent(pdev, size, vbuf[i], pbuf[i]);
b5c00cc5 271 vbuf[i] = NULL;
ccad0457
RM		 272 }
273 }
274}
275
276static int io_alloc(struct pci_dev *pdev, u8 **vbuf,
277 dma_addr_t *pbuf, u32 size, int num)
278{
279 int i;
280
281 for (i = 0; i < num; i++) {
282 vbuf[i] = pci_alloc_consistent(pdev, size, &pbuf[i]);
283 if (!vbuf[i])
284 return -ENOMEM;
285 }
286 return 0;
287}
288
289static int ddb_buffers_alloc(struct ddb *dev)
290{
291 int i;
292 struct ddb_port *port;
293
294 for (i = 0; i < dev->info->port_num; i++) {
295 port = &dev->port[i];
296 switch (port->class) {
297 case DDB_PORT_TUNER:
298 if (io_alloc(dev->pdev, port->input[0]->vbuf,
299 port->input[0]->pbuf,
300 port->input[0]->dma_buf_size,
301 port->input[0]->dma_buf_num) < 0)
302 return -1;
303 if (io_alloc(dev->pdev, port->input[1]->vbuf,
304 port->input[1]->pbuf,
305 port->input[1]->dma_buf_size,
306 port->input[1]->dma_buf_num) < 0)
307 return -1;
308 break;
309 case DDB_PORT_CI:
310 if (io_alloc(dev->pdev, port->input[0]->vbuf,
311 port->input[0]->pbuf,
312 port->input[0]->dma_buf_size,
313 port->input[0]->dma_buf_num) < 0)
314 return -1;
315 if (io_alloc(dev->pdev, port->output->vbuf,
316 port->output->pbuf,
317 port->output->dma_buf_size,
318 port->output->dma_buf_num) < 0)
319 return -1;
320 break;
321 default:
322 break;
323 }
324 }
325 ddb_address_table(dev);
326 return 0;
327}
328
329static void ddb_buffers_free(struct ddb *dev)
330{
331 int i;
332 struct ddb_port *port;
333
334 for (i = 0; i < dev->info->port_num; i++) {
335 port = &dev->port[i];
336 io_free(dev->pdev, port->input[0]->vbuf,
337 port->input[0]->pbuf,
338 port->input[0]->dma_buf_size,
339 port->input[0]->dma_buf_num);
340 io_free(dev->pdev, port->input[1]->vbuf,
341 port->input[1]->pbuf,
342 port->input[1]->dma_buf_size,
343 port->input[1]->dma_buf_num);
344 io_free(dev->pdev, port->output->vbuf,
345 port->output->pbuf,
346 port->output->dma_buf_size,
347 port->output->dma_buf_num);
348 }
349}
350
351static void ddb_input_start(struct ddb_input *input)
352{
353 struct ddb *dev = input->port->dev;
354
355 spin_lock_irq(&input->lock);
356 input->cbuf = 0;
357 input->coff = 0;
358
359 /* reset */
360 ddbwritel(0, TS_INPUT_CONTROL(input->nr));
361 ddbwritel(2, TS_INPUT_CONTROL(input->nr));
362 ddbwritel(0, TS_INPUT_CONTROL(input->nr));
363
364 ddbwritel((1 << 16) |
365 (input->dma_buf_num << 11) |
366 (input->dma_buf_size >> 7),
367 DMA_BUFFER_SIZE(input->nr));
368 ddbwritel(0, DMA_BUFFER_ACK(input->nr));
369
370 ddbwritel(1, DMA_BASE_WRITE);
371 ddbwritel(3, DMA_BUFFER_CONTROL(input->nr));
372 ddbwritel(9, TS_INPUT_CONTROL(input->nr));
373 input->running = 1;
374 spin_unlock_irq(&input->lock);
375}
376
377static void ddb_input_stop(struct ddb_input *input)
378{
379 struct ddb *dev = input->port->dev;
380
381 spin_lock_irq(&input->lock);
382 ddbwritel(0, TS_INPUT_CONTROL(input->nr));
383 ddbwritel(0, DMA_BUFFER_CONTROL(input->nr));
384 input->running = 0;
385 spin_unlock_irq(&input->lock);
386}
387
388static void ddb_output_start(struct ddb_output *output)
389{
390 struct ddb *dev = output->port->dev;
391
392 spin_lock_irq(&output->lock);
393 output->cbuf = 0;
394 output->coff = 0;
395 ddbwritel(0, TS_OUTPUT_CONTROL(output->nr));
396 ddbwritel(2, TS_OUTPUT_CONTROL(output->nr));
397 ddbwritel(0, TS_OUTPUT_CONTROL(output->nr));
398 ddbwritel(0x3c, TS_OUTPUT_CONTROL(output->nr));
399 ddbwritel((1 << 16) |
400 (output->dma_buf_num << 11) |
401 (output->dma_buf_size >> 7),
402 DMA_BUFFER_SIZE(output->nr + 8));
403 ddbwritel(0, DMA_BUFFER_ACK(output->nr + 8));
404
405 ddbwritel(1, DMA_BASE_READ);
406 ddbwritel(3, DMA_BUFFER_CONTROL(output->nr + 8));
4f1f3107 407 /* ddbwritel(0xbd, TS_OUTPUT_CONTROL(output->nr)); */
ccad0457
RM		 408 ddbwritel(0x1d, TS_OUTPUT_CONTROL(output->nr));
409 output->running = 1;
410 spin_unlock_irq(&output->lock);
411}
412
413static void ddb_output_stop(struct ddb_output *output)
414{
415 struct ddb *dev = output->port->dev;
416
417 spin_lock_irq(&output->lock);
418 ddbwritel(0, TS_OUTPUT_CONTROL(output->nr));
419 ddbwritel(0, DMA_BUFFER_CONTROL(output->nr + 8));
420 output->running = 0;
421 spin_unlock_irq(&output->lock);
422}
423
424static u32 ddb_output_free(struct ddb_output *output)
425{
426 u32 idx, off, stat = output->stat;
427 s32 diff;
428
429 idx = (stat >> 11) & 0x1f;
430 off = (stat & 0x7ff) << 7;
431
432 if (output->cbuf != idx) {
433 if ((((output->cbuf + 1) % output->dma_buf_num) == idx) &&
434 (output->dma_buf_size - output->coff <= 188))
435 return 0;
436 return 188;
437 }
438 diff = off - output->coff;
439 if (diff <= 0 || diff > 188)
440 return 188;
441 return 0;
442}
443
4f1f3107 444static ssize_t ddb_output_write(struct ddb_output *output,
b5c00cc5 445 const __user u8 *buf, size_t count)
ccad0457
RM		 446{
447 struct ddb *dev = output->port->dev;
448 u32 idx, off, stat = output->stat;
449 u32 left = count, len;
450
451 idx = (stat >> 11) & 0x1f;
452 off = (stat & 0x7ff) << 7;
453
454 while (left) {
455 len = output->dma_buf_size - output->coff;
456 if ((((output->cbuf + 1) % output->dma_buf_num) == idx) &&
457 (off == 0)) {
4f1f3107 458 if (len <= 188)
ccad0457 459 break;
4f1f3107 460 len -= 188;
ccad0457
RM		 461 }
462 if (output->cbuf == idx) {
463 if (off > output->coff) {
464#if 1
465 len = off - output->coff;
466 len -= (len % 188);
467 if (len <= 188)
468
469#endif
470 break;
471 len -= 188;
472 }
473 }
474 if (len > left)
475 len = left;
476 if (copy_from_user(output->vbuf[output->cbuf] + output->coff,
477 buf, len))
478 return -EIO;
479 left -= len;
480 buf += len;
481 output->coff += len;
482 if (output->coff == output->dma_buf_size) {
483 output->coff = 0;
484 output->cbuf = ((output->cbuf + 1) % output->dma_buf_num);
485 }
486 ddbwritel((output->cbuf << 11) | (output->coff >> 7),
487 DMA_BUFFER_ACK(output->nr + 8));
488 }
489 return count - left;
490}
491
492static u32 ddb_input_avail(struct ddb_input *input)
493{
494 struct ddb *dev = input->port->dev;
495 u32 idx, off, stat = input->stat;
496 u32 ctrl = ddbreadl(DMA_BUFFER_CONTROL(input->nr));
497
498 idx = (stat >> 11) & 0x1f;
499 off = (stat & 0x7ff) << 7;
500
501 if (ctrl & 4) {
4f1f3107 502 printk(KERN_ERR "IA %d %d %08x\n", idx, off, ctrl);
ccad0457
RM		 503 ddbwritel(input->stat, DMA_BUFFER_ACK(input->nr));
504 return 0;
505 }
506 if (input->cbuf != idx)
507 return 188;
508 return 0;
509}
510
b5c00cc5 511static ssize_t ddb_input_read(struct ddb_input *input, __user u8 *buf, size_t count)
ccad0457
RM		 512{
513 struct ddb *dev = input->port->dev;
514 u32 left = count;
2122eaf6 515 u32 idx, free, stat = input->stat;
ccad0457
RM		 516 int ret;
517
518 idx = (stat >> 11) & 0x1f;
ccad0457
RM		 519
520 while (left) {
521 if (input->cbuf == idx)
522 return count - left;
523 free = input->dma_buf_size - input->coff;
524 if (free > left)
525 free = left;
526 ret = copy_to_user(buf, input->vbuf[input->cbuf] +
527 input->coff, free);
2122eaf6
HV		 528 if (ret)
529 return -EFAULT;
ccad0457
RM		 530 input->coff += free;
531 if (input->coff == input->dma_buf_size) {
532 input->coff = 0;
533 input->cbuf = (input->cbuf+1) % input->dma_buf_num;
534 }
535 left -= free;
536 ddbwritel((input->cbuf << 11) | (input->coff >> 7),
537 DMA_BUFFER_ACK(input->nr));
538 }
539 return count;
540}
541
542/******************************************************************************/
543/******************************************************************************/
544/******************************************************************************/
545
546#if 0
547static struct ddb_input *fe2input(struct ddb *dev, struct dvb_frontend *fe)
548{
549 int i;
550
551 for (i = 0; i < dev->info->port_num * 2; i++) {
4f1f3107 552 if (dev->input[i].fe == fe)
ccad0457
RM		 553 return &dev->input[i];
554 }
555 return NULL;
556}
557#endif
558
559static int drxk_gate_ctrl(struct dvb_frontend *fe, int enable)
560{
561 struct ddb_input *input = fe->sec_priv;
562 struct ddb_port *port = input->port;
563 int status;
564
565 if (enable) {
566 mutex_lock(&port->i2c_gate_lock);
567 status = input->gate_ctrl(fe, 1);
568 } else {
569 status = input->gate_ctrl(fe, 0);
570 mutex_unlock(&port->i2c_gate_lock);
571 }
572 return status;
573}
574
575static int demod_attach_drxk(struct ddb_input *input)
576{
577 struct i2c_adapter *i2c = &input->port->i2c->adap;
578 struct dvb_frontend *fe;
0fc55e81 579 struct drxk_config config;
ccad0457 580
0fc55e81 581 memset(&config, 0, sizeof(config));
da989e0b 582 config.microcode_name = "drxk_a3.mc";
9e23f50a 583 config.qam_demod_parameter_count = 4;
0fc55e81
MCC		 584 config.adr = 0x29 + (input->nr & 1);
585
fa4b2a17 586 fe = input->fe = dvb_attach(drxk_attach, &config, i2c);
ccad0457 587 if (!input->fe) {
4f1f3107 588 printk(KERN_ERR "No DRXK found!\n");
ccad0457
RM		 589 return -ENODEV;
590 }
591 fe->sec_priv = input;
592 input->gate_ctrl = fe->ops.i2c_gate_ctrl;
593 fe->ops.i2c_gate_ctrl = drxk_gate_ctrl;
594 return 0;
595}
596
597static int tuner_attach_tda18271(struct ddb_input *input)
598{
599 struct i2c_adapter *i2c = &input->port->i2c->adap;
600 struct dvb_frontend *fe;
601
602 if (input->fe->ops.i2c_gate_ctrl)
603 input->fe->ops.i2c_gate_ctrl(input->fe, 1);
604 fe = dvb_attach(tda18271c2dd_attach, input->fe, i2c, 0x60);
605 if (!fe) {
4f1f3107 606 printk(KERN_ERR "No TDA18271 found!\n");
ccad0457
RM		 607 return -ENODEV;
608 }
609 if (input->fe->ops.i2c_gate_ctrl)
610 input->fe->ops.i2c_gate_ctrl(input->fe, 0);
611 return 0;
612}
613
614/******************************************************************************/
615/******************************************************************************/
616/******************************************************************************/
617
618static struct stv090x_config stv0900 = {
619 .device = STV0900,
620 .demod_mode = STV090x_DUAL,
621 .clk_mode = STV090x_CLK_EXT,
622
623 .xtal = 27000000,
624 .address = 0x69,
625
626 .ts1_mode = STV090x_TSMODE_SERIAL_PUNCTURED,
627 .ts2_mode = STV090x_TSMODE_SERIAL_PUNCTURED,
628
629 .repeater_level = STV090x_RPTLEVEL_16,
630
631 .adc1_range = STV090x_ADC_1Vpp,
632 .adc2_range = STV090x_ADC_1Vpp,
633
634 .diseqc_envelope_mode = true,
635};
636
637static struct stv090x_config stv0900_aa = {
638 .device = STV0900,
639 .demod_mode = STV090x_DUAL,
640 .clk_mode = STV090x_CLK_EXT,
641
642 .xtal = 27000000,
643 .address = 0x68,
644
645 .ts1_mode = STV090x_TSMODE_SERIAL_PUNCTURED,
646 .ts2_mode = STV090x_TSMODE_SERIAL_PUNCTURED,
647
648 .repeater_level = STV090x_RPTLEVEL_16,
649
650 .adc1_range = STV090x_ADC_1Vpp,
651 .adc2_range = STV090x_ADC_1Vpp,
652
653 .diseqc_envelope_mode = true,
654};
655
656static struct stv6110x_config stv6110a = {
657 .addr = 0x60,
658 .refclk = 27000000,
659 .clk_div = 1,
660};
661
662static struct stv6110x_config stv6110b = {
663 .addr = 0x63,
664 .refclk = 27000000,
665 .clk_div = 1,
666};
667
668static int demod_attach_stv0900(struct ddb_input *input, int type)
669{
670 struct i2c_adapter *i2c = &input->port->i2c->adap;
671 struct stv090x_config *feconf = type ? &stv0900_aa : &stv0900;
672
4f1f3107
OE		 673 input->fe = dvb_attach(stv090x_attach, feconf, i2c,
674 (input->nr & 1) ? STV090x_DEMODULATOR_1
675 : STV090x_DEMODULATOR_0);
ccad0457 676 if (!input->fe) {
4f1f3107 677 printk(KERN_ERR "No STV0900 found!\n");
ccad0457
RM		 678 return -ENODEV;
679 }
680 if (!dvb_attach(lnbh24_attach, input->fe, i2c, 0,
681 0, (input->nr & 1) ?
682 (0x09 - type) : (0x0b - type))) {
4f1f3107 683 printk(KERN_ERR "No LNBH24 found!\n");
ccad0457
RM		 684 return -ENODEV;
685 }
686 return 0;
687}
688
689static int tuner_attach_stv6110(struct ddb_input *input, int type)
690{
691 struct i2c_adapter *i2c = &input->port->i2c->adap;
692 struct stv090x_config *feconf = type ? &stv0900_aa : &stv0900;
693 struct stv6110x_config *tunerconf = (input->nr & 1) ?
694 &stv6110b : &stv6110a;
242c5033 695 const struct stv6110x_devctl *ctl;
ccad0457
RM		 696
697 ctl = dvb_attach(stv6110x_attach, input->fe, tunerconf, i2c);
698 if (!ctl) {
4f1f3107 699 printk(KERN_ERR "No STV6110X found!\n");
ccad0457
RM		 700 return -ENODEV;
701 }
4f1f3107
OE		 702 printk(KERN_INFO "attach tuner input %d adr %02x\n",
703 input->nr, tunerconf->addr);
ccad0457
RM		 704
705 feconf->tuner_init = ctl->tuner_init;
706 feconf->tuner_sleep = ctl->tuner_sleep;
707 feconf->tuner_set_mode = ctl->tuner_set_mode;
708 feconf->tuner_set_frequency = ctl->tuner_set_frequency;
709 feconf->tuner_get_frequency = ctl->tuner_get_frequency;
710 feconf->tuner_set_bandwidth = ctl->tuner_set_bandwidth;
711 feconf->tuner_get_bandwidth = ctl->tuner_get_bandwidth;
712 feconf->tuner_set_bbgain = ctl->tuner_set_bbgain;
713 feconf->tuner_get_bbgain = ctl->tuner_get_bbgain;
714 feconf->tuner_set_refclk = ctl->tuner_set_refclk;
715 feconf->tuner_get_status = ctl->tuner_get_status;
716
717 return 0;
718}
719
805e6874 720static int my_dvb_dmx_ts_card_init(struct dvb_demux *dvbdemux, char *id,
ccad0457
RM		 721 int (*start_feed)(struct dvb_demux_feed *),
722 int (*stop_feed)(struct dvb_demux_feed *),
723 void *priv)
724{
725 dvbdemux->priv = priv;
726
727 dvbdemux->filternum = 256;
728 dvbdemux->feednum = 256;
729 dvbdemux->start_feed = start_feed;
730 dvbdemux->stop_feed = stop_feed;
731 dvbdemux->write_to_decoder = NULL;
732 dvbdemux->dmx.capabilities = (DMX_TS_FILTERING |
733 DMX_SECTION_FILTERING |
734 DMX_MEMORY_BASED_FILTERING);
735 return dvb_dmx_init(dvbdemux);
736}
737
805e6874 738static int my_dvb_dmxdev_ts_card_init(struct dmxdev *dmxdev,
ccad0457
RM		 739 struct dvb_demux *dvbdemux,
740 struct dmx_frontend *hw_frontend,
741 struct dmx_frontend *mem_frontend,
742 struct dvb_adapter *dvb_adapter)
743{
744 int ret;
745
746 dmxdev->filternum = 256;
747 dmxdev->demux = &dvbdemux->dmx;
748 dmxdev->capabilities = 0;
749 ret = dvb_dmxdev_init(dmxdev, dvb_adapter);
750 if (ret < 0)
751 return ret;
752
753 hw_frontend->source = DMX_FRONTEND_0;
754 dvbdemux->dmx.add_frontend(&dvbdemux->dmx, hw_frontend);
755 mem_frontend->source = DMX_MEMORY_FE;
756 dvbdemux->dmx.add_frontend(&dvbdemux->dmx, mem_frontend);
757 return dvbdemux->dmx.connect_frontend(&dvbdemux->dmx, hw_frontend);
758}
759
760static int start_feed(struct dvb_demux_feed *dvbdmxfeed)
761{
762 struct dvb_demux *dvbdmx = dvbdmxfeed->demux;
763 struct ddb_input *input = dvbdmx->priv;
764
765 if (!input->users)
766 ddb_input_start(input);
767
768 return ++input->users;
769}
770
771static int stop_feed(struct dvb_demux_feed *dvbdmxfeed)
772{
773 struct dvb_demux *dvbdmx = dvbdmxfeed->demux;
774 struct ddb_input *input = dvbdmx->priv;
775
776 if (--input->users)
777 return input->users;
778
779 ddb_input_stop(input);
780 return 0;
781}
782
783
784static void dvb_input_detach(struct ddb_input *input)
785{
786 struct dvb_adapter *adap = &input->adap;
787 struct dvb_demux *dvbdemux = &input->demux;
788
789 switch (input->attached) {
790 case 5:
791 if (input->fe2)
792 dvb_unregister_frontend(input->fe2);
793 if (input->fe) {
794 dvb_unregister_frontend(input->fe);
795 dvb_frontend_detach(input->fe);
796 input->fe = NULL;
797 }
06eeefe8 798 /* fall-through */
ccad0457
RM		 799 case 4:
800 dvb_net_release(&input->dvbnet);
06eeefe8 801 /* fall-through */
ccad0457
RM		 802 case 3:
803 dvbdemux->dmx.close(&dvbdemux->dmx);
804 dvbdemux->dmx.remove_frontend(&dvbdemux->dmx,
805 &input->hw_frontend);
806 dvbdemux->dmx.remove_frontend(&dvbdemux->dmx,
807 &input->mem_frontend);
808 dvb_dmxdev_release(&input->dmxdev);
06eeefe8 809 /* fall-through */
ccad0457
RM		 810 case 2:
811 dvb_dmx_release(&input->demux);
06eeefe8 812 /* fall-through */
ccad0457
RM		 813 case 1:
814 dvb_unregister_adapter(adap);
815 }
816 input->attached = 0;
817}
818
819static int dvb_input_attach(struct ddb_input *input)
820{
821 int ret;
822 struct ddb_port *port = input->port;
823 struct dvb_adapter *adap = &input->adap;
824 struct dvb_demux *dvbdemux = &input->demux;
825
4f1f3107 826 ret = dvb_register_adapter(adap, "DDBridge", THIS_MODULE,
ccad0457
RM		 827 &input->port->dev->pdev->dev,
828 adapter_nr);
829 if (ret < 0) {
935747ff 830 printk(KERN_ERR "ddbridge: Could not register adapter.Check if you enabled enough adapters in dvb-core!\n");
ccad0457
RM		 831 return ret;
832 }
833 input->attached = 1;
834
835 ret = my_dvb_dmx_ts_card_init(dvbdemux, "SW demux",
836 start_feed,
837 stop_feed, input);
838 if (ret < 0)
839 return ret;
840 input->attached = 2;
841
842 ret = my_dvb_dmxdev_ts_card_init(&input->dmxdev, &input->demux,
843 &input->hw_frontend,
844 &input->mem_frontend, adap);
845 if (ret < 0)
846 return ret;
847 input->attached = 3;
848
849 ret = dvb_net_init(adap, &input->dvbnet, input->dmxdev.demux);
850 if (ret < 0)
851 return ret;
852 input->attached = 4;
853
b5c00cc5 854 input->fe = NULL;
ccad0457
RM		 855 switch (port->type) {
856 case DDB_TUNER_DVBS_ST:
857 if (demod_attach_stv0900(input, 0) < 0)
858 return -ENODEV;
859 if (tuner_attach_stv6110(input, 0) < 0)
860 return -ENODEV;
861 if (input->fe) {
862 if (dvb_register_frontend(adap, input->fe) < 0)
863 return -ENODEV;
864 }
865 break;
866 case DDB_TUNER_DVBS_ST_AA:
867 if (demod_attach_stv0900(input, 1) < 0)
868 return -ENODEV;
869 if (tuner_attach_stv6110(input, 1) < 0)
870 return -ENODEV;
871 if (input->fe) {
872 if (dvb_register_frontend(adap, input->fe) < 0)
873 return -ENODEV;
874 }
875 break;
876 case DDB_TUNER_DVBCT_TR:
877 if (demod_attach_drxk(input) < 0)
878 return -ENODEV;
879 if (tuner_attach_tda18271(input) < 0)
880 return -ENODEV;
cdcb12e7
DC		 881 if (dvb_register_frontend(adap, input->fe) < 0)
882 return -ENODEV;
ccad0457
RM		 883 if (input->fe2) {
884 if (dvb_register_frontend(adap, input->fe2) < 0)
885 return -ENODEV;
4f1f3107 886 input->fe2->tuner_priv = input->fe->tuner_priv;
ccad0457
RM		 887 memcpy(&input->fe2->ops.tuner_ops,
888 &input->fe->ops.tuner_ops,
889 sizeof(struct dvb_tuner_ops));
890 }
891 break;
892 }
893 input->attached = 5;
894 return 0;
895}
896
897/****************************************************************************/
898/****************************************************************************/
899
b5c00cc5 900static ssize_t ts_write(struct file *file, const __user char *buf,
ccad0457
RM		 901 size_t count, loff_t *ppos)
902{
903 struct dvb_device *dvbdev = file->private_data;
904 struct ddb_output *output = dvbdev->priv;
905 size_t left = count;
906 int stat;
907
908 while (left) {
909 if (ddb_output_free(output) < 188) {
910 if (file->f_flags & O_NONBLOCK)
911 break;
912 if (wait_event_interruptible(
913 output->wq, ddb_output_free(output) >= 188) < 0)
914 break;
915 }
916 stat = ddb_output_write(output, buf, left);
917 if (stat < 0)
918 break;
919 buf += stat;
920 left -= stat;
921 }
922 return (left == count) ? -EAGAIN : (count - left);
923}
924
b5c00cc5 925static ssize_t ts_read(struct file *file, __user char *buf,
ccad0457
RM		 926 size_t count, loff_t *ppos)
927{
928 struct dvb_device *dvbdev = file->private_data;
929 struct ddb_output *output = dvbdev->priv;
930 struct ddb_input *input = output->port->input[0];
931 int left, read;
932
933 count -= count % 188;
934 left = count;
935 while (left) {
936 if (ddb_input_avail(input) < 188) {
937 if (file->f_flags & O_NONBLOCK)
938 break;
939 if (wait_event_interruptible(
940 input->wq, ddb_input_avail(input) >= 188) < 0)
941 break;
942 }
943 read = ddb_input_read(input, buf, left);
2122eaf6
HV		 944 if (read < 0)
945 return read;
ccad0457
RM		 946 left -= read;
947 buf += read;
948 }
949 return (left == count) ? -EAGAIN : (count - left);
950}
951
952static unsigned int ts_poll(struct file *file, poll_table *wait)
953{
4f1f3107 954 /*
ccad0457
RM		 955 struct dvb_device *dvbdev = file->private_data;
956 struct ddb_output *output = dvbdev->priv;
957 struct ddb_input *input = output->port->input[0];
4f1f3107 958 */
ccad0457
RM		 959 unsigned int mask = 0;
960
961#if 0
962 if (data_avail_to_read)
963 mask |= POLLIN | POLLRDNORM;
964 if (data_avail_to_write)
965 mask |= POLLOUT | POLLWRNORM;
966
967 poll_wait(file, &read_queue, wait);
968 poll_wait(file, &write_queue, wait);
969#endif
970 return mask;
971}
972
4f1f3107 973static const struct file_operations ci_fops = {
ccad0457
RM		 974 .owner = THIS_MODULE,
975 .read = ts_read,
976 .write = ts_write,
977 .open = dvb_generic_open,
978 .release = dvb_generic_release,
979 .poll = ts_poll,
ccad0457
RM		 980};
981
982static struct dvb_device dvbdev_ci = {
ccad0457
RM		 983 .readers = -1,
984 .writers = -1,
985 .users = -1,
986 .fops = &ci_fops,
987};
988
989/****************************************************************************/
990/****************************************************************************/
991/****************************************************************************/
992
993static void input_tasklet(unsigned long data)
994{
995 struct ddb_input *input = (struct ddb_input *) data;
996 struct ddb *dev = input->port->dev;
997
998 spin_lock(&input->lock);
999 if (!input->running) {
1000 spin_unlock(&input->lock);
1001 return;
1002 }
1003 input->stat = ddbreadl(DMA_BUFFER_CURRENT(input->nr));
1004
1005 if (input->port->class == DDB_PORT_TUNER) {
1006 if (4&ddbreadl(DMA_BUFFER_CONTROL(input->nr)))
4f1f3107 1007 printk(KERN_ERR "Overflow input %d\n", input->nr);
ccad0457
RM		 1008 while (input->cbuf != ((input->stat >> 11) & 0x1f)
1009 || (4&ddbreadl(DMA_BUFFER_CONTROL(input->nr)))) {
1010 dvb_dmx_swfilter_packets(&input->demux,
1011 input->vbuf[input->cbuf],
1012 input->dma_buf_size / 188);
1013
1014 input->cbuf = (input->cbuf + 1) % input->dma_buf_num;
1015 ddbwritel((input->cbuf << 11),
1016 DMA_BUFFER_ACK(input->nr));
1017 input->stat = ddbreadl(DMA_BUFFER_CURRENT(input->nr));
1018 }
1019 }
1020 if (input->port->class == DDB_PORT_CI)
1021 wake_up(&input->wq);
1022 spin_unlock(&input->lock);
1023}
1024
1025static void output_tasklet(unsigned long data)
1026{
1027 struct ddb_output *output = (struct ddb_output *) data;
1028 struct ddb *dev = output->port->dev;
1029
1030 spin_lock(&output->lock);
1031 if (!output->running) {
1032 spin_unlock(&output->lock);
1033 return;
1034 }
1035 output->stat = ddbreadl(DMA_BUFFER_CURRENT(output->nr + 8));
1036 wake_up(&output->wq);
1037 spin_unlock(&output->lock);
1038}
1039
1040
b5c00cc5 1041static struct cxd2099_cfg cxd_cfg = {
ccad0457
RM		 1042 .bitrate = 62000,
1043 .adr = 0x40,
1044 .polarity = 1,
1045 .clock_mode = 1,
1046};
1047
1048static int ddb_ci_attach(struct ddb_port *port)
1049{
1050 int ret;
1051
1052 ret = dvb_register_adapter(&port->output->adap,
1053 "DDBridge",
1054 THIS_MODULE,
1055 &port->dev->pdev->dev,
1056 adapter_nr);
1057 if (ret < 0)
1058 return ret;
1059 port->en = cxd2099_attach(&cxd_cfg, port, &port->i2c->adap);
1060 if (!port->en) {
1061 dvb_unregister_adapter(&port->output->adap);
1062 return -ENODEV;
1063 }
1064 ddb_input_start(port->input[0]);
1065 ddb_output_start(port->output);
1066 dvb_ca_en50221_init(&port->output->adap,
1067 port->en, 0, 1);
4f1f3107
OE		 1068 ret = dvb_register_device(&port->output->adap, &port->output->dev,
1069 &dvbdev_ci, (void *) port->output,
df2f94e5 1070 DVB_DEVICE_SEC, 0);
ccad0457
RM		 1071 return ret;
1072}
1073
1074static int ddb_port_attach(struct ddb_port *port)
1075{
1076 int ret = 0;
1077
1078 switch (port->class) {
1079 case DDB_PORT_TUNER:
1080 ret = dvb_input_attach(port->input[0]);
4f1f3107 1081 if (ret < 0)
ccad0457
RM		 1082 break;
1083 ret = dvb_input_attach(port->input[1]);
1084 break;
1085 case DDB_PORT_CI:
1086 ret = ddb_ci_attach(port);
1087 break;
1088 default:
1089 break;
1090 }
1091 if (ret < 0)
4f1f3107 1092 printk(KERN_ERR "port_attach on port %d failed\n", port->nr);
ccad0457
RM		 1093 return ret;
1094}
1095
1096static int ddb_ports_attach(struct ddb *dev)
1097{
1098 int i, ret = 0;
1099 struct ddb_port *port;
1100
1101 for (i = 0; i < dev->info->port_num; i++) {
1102 port = &dev->port[i];
1103 ret = ddb_port_attach(port);
1104 if (ret < 0)
1105 break;
1106 }
1107 return ret;
1108}
1109
1110static void ddb_ports_detach(struct ddb *dev)
1111{
1112 int i;
1113 struct ddb_port *port;
1114
1115 for (i = 0; i < dev->info->port_num; i++) {
1116 port = &dev->port[i];
1117 switch (port->class) {
1118 case DDB_PORT_TUNER:
1119 dvb_input_detach(port->input[0]);
1120 dvb_input_detach(port->input[1]);
1121 break;
1122 case DDB_PORT_CI:
ddc0085e 1123 dvb_unregister_device(port->output->dev);
ccad0457
RM		 1124 if (port->en) {
1125 ddb_input_stop(port->input[0]);
1126 ddb_output_stop(port->output);
1127 dvb_ca_en50221_release(port->en);
1128 kfree(port->en);
b5c00cc5 1129 port->en = NULL;
ccad0457
RM		 1130 dvb_unregister_adapter(&port->output->adap);
1131 }
1132 break;
1133 }
1134 }
1135}
1136
1137/****************************************************************************/
1138/****************************************************************************/
1139
1140static int port_has_ci(struct ddb_port *port)
1141{
1142 u8 val;
4f1f3107 1143 return i2c_read_reg(&port->i2c->adap, 0x40, 0, &val) ? 0 : 1;
ccad0457
RM		 1144}
1145
1146static int port_has_stv0900(struct ddb_port *port)
1147{
1148 u8 val;
1149 if (i2c_read_reg16(&port->i2c->adap, 0x69, 0xf100, &val) < 0)
1150 return 0;
1151 return 1;
1152}
1153
1154static int port_has_stv0900_aa(struct ddb_port *port)
1155{
1156 u8 val;
1157 if (i2c_read_reg16(&port->i2c->adap, 0x68, 0xf100, &val) < 0)
1158 return 0;
1159 return 1;
1160}
1161
1162static int port_has_drxks(struct ddb_port *port)
1163{
1164 u8 val;
1165 if (i2c_read(&port->i2c->adap, 0x29, &val) < 0)
1166 return 0;
1167 if (i2c_read(&port->i2c->adap, 0x2a, &val) < 0)
1168 return 0;
1169 return 1;
1170}
1171
1172static void ddb_port_probe(struct ddb_port *port)
1173{
1174 struct ddb *dev = port->dev;
1175 char *modname = "NO MODULE";
1176
1177 port->class = DDB_PORT_NONE;
1178
1179 if (port_has_ci(port)) {
1180 modname = "CI";
1181 port->class = DDB_PORT_CI;
1182 ddbwritel(I2C_SPEED_400, port->i2c->regs + I2C_TIMING);
1183 } else if (port_has_stv0900(port)) {
1184 modname = "DUAL DVB-S2";
1185 port->class = DDB_PORT_TUNER;
1186 port->type = DDB_TUNER_DVBS_ST;
1187 ddbwritel(I2C_SPEED_100, port->i2c->regs + I2C_TIMING);
1188 } else if (port_has_stv0900_aa(port)) {
1189 modname = "DUAL DVB-S2";
1190 port->class = DDB_PORT_TUNER;
1191 port->type = DDB_TUNER_DVBS_ST_AA;
1192 ddbwritel(I2C_SPEED_100, port->i2c->regs + I2C_TIMING);
1193 } else if (port_has_drxks(port)) {
1194 modname = "DUAL DVB-C/T";
1195 port->class = DDB_PORT_TUNER;
1196 port->type = DDB_TUNER_DVBCT_TR;
1197 ddbwritel(I2C_SPEED_400, port->i2c->regs + I2C_TIMING);
1198 }
4f1f3107
OE		 1199 printk(KERN_INFO "Port %d (TAB %d): %s\n",
1200 port->nr, port->nr+1, modname);
ccad0457
RM		 1201}
1202
1203static void ddb_input_init(struct ddb_port *port, int nr)
1204{
1205 struct ddb *dev = port->dev;
1206 struct ddb_input *input = &dev->input[nr];
1207
1208 input->nr = nr;
1209 input->port = port;
1210 input->dma_buf_num = INPUT_DMA_BUFS;
1211 input->dma_buf_size = INPUT_DMA_SIZE;
1212 ddbwritel(0, TS_INPUT_CONTROL(nr));
1213 ddbwritel(2, TS_INPUT_CONTROL(nr));
1214 ddbwritel(0, TS_INPUT_CONTROL(nr));
1215 ddbwritel(0, DMA_BUFFER_ACK(nr));
1216 tasklet_init(&input->tasklet, input_tasklet, (unsigned long) input);
1217 spin_lock_init(&input->lock);
1218 init_waitqueue_head(&input->wq);
1219}
1220
1221static void ddb_output_init(struct ddb_port *port, int nr)
1222{
1223 struct ddb *dev = port->dev;
1224 struct ddb_output *output = &dev->output[nr];
1225 output->nr = nr;
1226 output->port = port;
1227 output->dma_buf_num = OUTPUT_DMA_BUFS;
1228 output->dma_buf_size = OUTPUT_DMA_SIZE;
1229
1230 ddbwritel(0, TS_OUTPUT_CONTROL(nr));
1231 ddbwritel(2, TS_OUTPUT_CONTROL(nr));
1232 ddbwritel(0, TS_OUTPUT_CONTROL(nr));
1233 tasklet_init(&output->tasklet, output_tasklet, (unsigned long) output);
1234 init_waitqueue_head(&output->wq);
1235}
1236
1237static void ddb_ports_init(struct ddb *dev)
1238{
1239 int i;
1240 struct ddb_port *port;
1241
1242 for (i = 0; i < dev->info->port_num; i++) {
1243 port = &dev->port[i];
1244 port->dev = dev;
1245 port->nr = i;
1246 port->i2c = &dev->i2c[i];
1247 port->input[0] = &dev->input[2 * i];
1248 port->input[1] = &dev->input[2 * i + 1];
1249 port->output = &dev->output[i];
1250
1251 mutex_init(&port->i2c_gate_lock);
1252 ddb_port_probe(port);
1253 ddb_input_init(port, 2 * i);
1254 ddb_input_init(port, 2 * i + 1);
1255 ddb_output_init(port, i);
1256 }
1257}
1258
1259static void ddb_ports_release(struct ddb *dev)
1260{
1261 int i;
1262 struct ddb_port *port;
1263
1264 for (i = 0; i < dev->info->port_num; i++) {
1265 port = &dev->port[i];
1266 port->dev = dev;
1267 tasklet_kill(&port->input[0]->tasklet);
1268 tasklet_kill(&port->input[1]->tasklet);
1269 tasklet_kill(&port->output->tasklet);
1270 }
1271}
1272
1273/****************************************************************************/
1274/****************************************************************************/
1275/****************************************************************************/
1276
1277static void irq_handle_i2c(struct ddb *dev, int n)
1278{
1279 struct ddb_i2c *i2c = &dev->i2c[n];
1280
1281 i2c->done = 1;
1282 wake_up(&i2c->wq);
1283}
1284
1285static irqreturn_t irq_handler(int irq, void *dev_id)
1286{
1287 struct ddb *dev = (struct ddb *) dev_id;
1288 u32 s = ddbreadl(INTERRUPT_STATUS);
1289
1290 if (!s)
1291 return IRQ_NONE;
1292
1293 do {
1294 ddbwritel(s, INTERRUPT_ACK);
1295
4f1f3107
OE		 1296 if (s & 0x00000001)
1297 irq_handle_i2c(dev, 0);
1298 if (s & 0x00000002)
1299 irq_handle_i2c(dev, 1);
1300 if (s & 0x00000004)
1301 irq_handle_i2c(dev, 2);
1302 if (s & 0x00000008)
1303 irq_handle_i2c(dev, 3);
1304
1305 if (s & 0x00000100)
1306 tasklet_schedule(&dev->input[0].tasklet);
1307 if (s & 0x00000200)
1308 tasklet_schedule(&dev->input[1].tasklet);
1309 if (s & 0x00000400)
1310 tasklet_schedule(&dev->input[2].tasklet);
1311 if (s & 0x00000800)
1312 tasklet_schedule(&dev->input[3].tasklet);
1313 if (s & 0x00001000)
1314 tasklet_schedule(&dev->input[4].tasklet);
1315 if (s & 0x00002000)
1316 tasklet_schedule(&dev->input[5].tasklet);
1317 if (s & 0x00004000)
1318 tasklet_schedule(&dev->input[6].tasklet);
1319 if (s & 0x00008000)
1320 tasklet_schedule(&dev->input[7].tasklet);
1321
1322 if (s & 0x00010000)
1323 tasklet_schedule(&dev->output[0].tasklet);
1324 if (s & 0x00020000)
1325 tasklet_schedule(&dev->output[1].tasklet);
1326 if (s & 0x00040000)
1327 tasklet_schedule(&dev->output[2].tasklet);
1328 if (s & 0x00080000)
1329 tasklet_schedule(&dev->output[3].tasklet);
1330
1331 /* if (s & 0x000f0000) printk(KERN_DEBUG "%08x\n", istat); */
ccad0457
RM		 1332 } while ((s = ddbreadl(INTERRUPT_STATUS)));
1333
1334 return IRQ_HANDLED;
1335}
1336
1337/******************************************************************************/
1338/******************************************************************************/
1339/******************************************************************************/
1340
1341static int flashio(struct ddb *dev, u8 *wbuf, u32 wlen, u8 *rbuf, u32 rlen)
1342{
1343 u32 data, shift;
1344
1345 if (wlen > 4)
1346 ddbwritel(1, SPI_CONTROL);
1347 while (wlen > 4) {
1348 /* FIXME: check for big-endian */
1349 data = swab32(*(u32 *)wbuf);
1350 wbuf += 4;
1351 wlen -= 4;
1352 ddbwritel(data, SPI_DATA);
4f1f3107
OE		 1353 while (ddbreadl(SPI_CONTROL) & 0x0004)
1354 ;
ccad0457
RM		 1355 }
1356
1357 if (rlen)
1358 ddbwritel(0x0001 | ((wlen << (8 + 3)) & 0x1f00), SPI_CONTROL);
1359 else
1360 ddbwritel(0x0003 | ((wlen << (8 + 3)) & 0x1f00), SPI_CONTROL);
1361
4f1f3107 1362 data = 0;
ccad0457
RM		 1363 shift = ((4 - wlen) * 8);
1364 while (wlen) {
1365 data <<= 8;
1366 data |= *wbuf;
1367 wlen--;
1368 wbuf++;
1369 }
1370 if (shift)
1371 data <<= shift;
1372 ddbwritel(data, SPI_DATA);
4f1f3107
OE		 1373 while (ddbreadl(SPI_CONTROL) & 0x0004)
1374 ;
ccad0457
RM		 1375
1376 if (!rlen) {
1377 ddbwritel(0, SPI_CONTROL);
1378 return 0;
1379 }
1380 if (rlen > 4)
1381 ddbwritel(1, SPI_CONTROL);
1382
1383 while (rlen > 4) {
1384 ddbwritel(0xffffffff, SPI_DATA);
4f1f3107
OE		 1385 while (ddbreadl(SPI_CONTROL) & 0x0004)
1386 ;
ccad0457
RM		 1387 data = ddbreadl(SPI_DATA);
1388 *(u32 *) rbuf = swab32(data);
1389 rbuf += 4;
1390 rlen -= 4;
1391 }
1392 ddbwritel(0x0003 | ((rlen << (8 + 3)) & 0x1F00), SPI_CONTROL);
1393 ddbwritel(0xffffffff, SPI_DATA);
4f1f3107
OE		 1394 while (ddbreadl(SPI_CONTROL) & 0x0004)
1395 ;
ccad0457
RM		 1396
1397 data = ddbreadl(SPI_DATA);
1398 ddbwritel(0, SPI_CONTROL);
1399
1400 if (rlen < 4)
1401 data <<= ((4 - rlen) * 8);
1402
1403 while (rlen > 0) {
1404 *rbuf = ((data >> 24) & 0xff);
1405 data <<= 8;
1406 rbuf++;
1407 rlen--;
1408 }
1409 return 0;
1410}
1411
1412#define DDB_MAGIC 'd'
1413
1414struct ddb_flashio {
b5c00cc5 1415 __user __u8 *write_buf;
ccad0457 1416 __u32 write_len;
b5c00cc5 1417 __user __u8 *read_buf;
ccad0457
RM		 1418 __u32 read_len;
1419};
1420
1421#define IOCTL_DDB_FLASHIO _IOWR(DDB_MAGIC, 0x00, struct ddb_flashio)
1422
1423#define DDB_NAME "ddbridge"
1424
1425static u32 ddb_num;
1426static struct ddb *ddbs[32];
1427static struct class *ddb_class;
1428static int ddb_major;
1429
1430static int ddb_open(struct inode *inode, struct file *file)
1431{
1432 struct ddb *dev = ddbs[iminor(inode)];
1433
1434 file->private_data = dev;
1435 return 0;
1436}
1437
1438static long ddb_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
1439{
1440 struct ddb *dev = file->private_data;
b5c00cc5 1441 __user void *parg = (__user void *)arg;
e9013fb6 1442 int res;
ccad0457
RM		 1443
1444 switch (cmd) {
1445 case IOCTL_DDB_FLASHIO:
1446 {
1447 struct ddb_flashio fio;
1448 u8 *rbuf, *wbuf;
1449
1450 if (copy_from_user(&fio, parg, sizeof(fio)))
e9013fb6
DC		 1451 return -EFAULT;
1452
1453 if (fio.write_len > 1028 || fio.read_len > 1028)
1454 return -EINVAL;
1455 if (fio.write_len + fio.read_len > 1028)
1456 return -EINVAL;
1457
ccad0457 1458 wbuf = &dev->iobuf[0];
ccad0457 1459 rbuf = wbuf + fio.write_len;
e9013fb6
DC		 1460
1461 if (copy_from_user(wbuf, fio.write_buf, fio.write_len))
1462 return -EFAULT;
1463 res = flashio(dev, wbuf, fio.write_len, rbuf, fio.read_len);
1464 if (res)
1465 return res;
ccad0457 1466 if (copy_to_user(fio.read_buf, rbuf, fio.read_len))
e9013fb6 1467 return -EFAULT;
ccad0457
RM		 1468 break;
1469 }
1470 default:
e9013fb6 1471 return -ENOTTY;
ccad0457 1472 }
e9013fb6 1473 return 0;
ccad0457
RM		 1474}
1475
4f1f3107 1476static const struct file_operations ddb_fops = {
ccad0457
RM		 1477 .unlocked_ioctl = ddb_ioctl,
1478 .open = ddb_open,
1479};
1480
2c9ede55 1481static char *ddb_devnode(struct device *device, umode_t *mode)
ccad0457
RM		 1482{
1483 struct ddb *dev = dev_get_drvdata(device);
1484
1485 return kasprintf(GFP_KERNEL, "ddbridge/card%d", dev->nr);
1486}
1487
1488static int ddb_class_create(void)
1489{
4f1f3107
OE		 1490 ddb_major = register_chrdev(0, DDB_NAME, &ddb_fops);
1491 if (ddb_major < 0)
ccad0457
RM		 1492 return ddb_major;
1493
1494 ddb_class = class_create(THIS_MODULE, DDB_NAME);
1495 if (IS_ERR(ddb_class)) {
1496 unregister_chrdev(ddb_major, DDB_NAME);
f4e4a67a 1497 return PTR_ERR(ddb_class);
ccad0457
RM		 1498 }
1499 ddb_class->devnode = ddb_devnode;
1500 return 0;
1501}
1502
1503static void ddb_class_destroy(void)
1504{
1505 class_destroy(ddb_class);
1506 unregister_chrdev(ddb_major, DDB_NAME);
1507}
1508
1509static int ddb_device_create(struct ddb *dev)
1510{
1511 dev->nr = ddb_num++;
1512 dev->ddb_dev = device_create(ddb_class, NULL,
1513 MKDEV(ddb_major, dev->nr),
1514 dev, "ddbridge%d", dev->nr);
1515 ddbs[dev->nr] = dev;
1516 if (IS_ERR(dev->ddb_dev))
1517 return -1;
1518 return 0;
1519}
1520
1521static void ddb_device_destroy(struct ddb *dev)
1522{
1523 ddb_num--;
1524 if (IS_ERR(dev->ddb_dev))
1525 return;
1526 device_destroy(ddb_class, MKDEV(ddb_major, 0));
1527}
1528
1529
1530/****************************************************************************/
1531/****************************************************************************/
1532/****************************************************************************/
1533
1534static void ddb_unmap(struct ddb *dev)
1535{
1536 if (dev->regs)
1537 iounmap(dev->regs);
1538 vfree(dev);
1539}
1540
1541
4c62e976 1542static void ddb_remove(struct pci_dev *pdev)
ccad0457 1543{
1fbf86a0 1544 struct ddb *dev = pci_get_drvdata(pdev);
ccad0457
RM		 1545
1546 ddb_ports_detach(dev);
1547 ddb_i2c_release(dev);
1548
1549 ddbwritel(0, INTERRUPT_ENABLE);
1550 free_irq(dev->pdev->irq, dev);
1551#ifdef CONFIG_PCI_MSI
1552 if (dev->msi)
1553 pci_disable_msi(dev->pdev);
1554#endif
1555 ddb_ports_release(dev);
1556 ddb_buffers_free(dev);
1557 ddb_device_destroy(dev);
1558
1559 ddb_unmap(dev);
b5c00cc5 1560 pci_set_drvdata(pdev, NULL);
ccad0457
RM		 1561 pci_disable_device(pdev);
1562}
1563
1564
4c62e976 1565static int ddb_probe(struct pci_dev *pdev, const struct pci_device_id *id)
ccad0457
RM		 1566{
1567 struct ddb *dev;
4f1f3107 1568 int stat = 0;
ccad0457
RM		 1569 int irq_flag = IRQF_SHARED;
1570
4f1f3107 1571 if (pci_enable_device(pdev) < 0)
ccad0457
RM		 1572 return -ENODEV;
1573
20634fd1 1574 dev = vzalloc(sizeof(struct ddb));
ccad0457
RM		 1575 if (dev == NULL)
1576 return -ENOMEM;
ccad0457
RM		 1577
1578 dev->pdev = pdev;
1579 pci_set_drvdata(pdev, dev);
1580 dev->info = (struct ddb_info *) id->driver_data;
4f1f3107 1581 printk(KERN_INFO "DDBridge driver detected: %s\n", dev->info->name);
ccad0457 1582
4f1f3107
OE		 1583 dev->regs = ioremap(pci_resource_start(dev->pdev, 0),
1584 pci_resource_len(dev->pdev, 0));
ccad0457
RM		 1585 if (!dev->regs) {
1586 stat = -ENOMEM;
1587 goto fail;
1588 }
4f1f3107 1589 printk(KERN_INFO "HW %08x FW %08x\n", ddbreadl(0), ddbreadl(4));
ccad0457
RM		 1590
1591#ifdef CONFIG_PCI_MSI
1592 if (pci_msi_enabled())
1593 stat = pci_enable_msi(dev->pdev);
1594 if (stat) {
1595 printk(KERN_INFO ": MSI not available.\n");
1596 } else {
1597 irq_flag = 0;
1598 dev->msi = 1;
1599 }
1600#endif
4f1f3107
OE		 1601 stat = request_irq(dev->pdev->irq, irq_handler,
1602 irq_flag, "DDBridge", (void *) dev);
1603 if (stat < 0)
ccad0457
RM		 1604 goto fail1;
1605 ddbwritel(0, DMA_BASE_WRITE);
1606 ddbwritel(0, DMA_BASE_READ);
1607 ddbwritel(0xffffffff, INTERRUPT_ACK);
1608 ddbwritel(0xfff0f, INTERRUPT_ENABLE);
1609 ddbwritel(0, MSI1_ENABLE);
1610
1611 if (ddb_i2c_init(dev) < 0)
1612 goto fail1;
1613 ddb_ports_init(dev);
1614 if (ddb_buffers_alloc(dev) < 0) {
1615 printk(KERN_INFO ": Could not allocate buffer memory\n");
1616 goto fail2;
1617 }
1618 if (ddb_ports_attach(dev) < 0)
1619 goto fail3;
1620 ddb_device_create(dev);
1621 return 0;
1622
1623fail3:
1624 ddb_ports_detach(dev);
4f1f3107 1625 printk(KERN_ERR "fail3\n");
ccad0457
RM		 1626 ddb_ports_release(dev);
1627fail2:
4f1f3107 1628 printk(KERN_ERR "fail2\n");
ccad0457
RM		 1629 ddb_buffers_free(dev);
1630fail1:
4f1f3107 1631 printk(KERN_ERR "fail1\n");
ccad0457
RM		 1632 if (dev->msi)
1633 pci_disable_msi(dev->pdev);
25e057fd
TY		 1634 if (stat == 0)
1635 free_irq(dev->pdev->irq, dev);
ccad0457 1636fail:
4f1f3107 1637 printk(KERN_ERR "fail\n");
ccad0457 1638 ddb_unmap(dev);
b5c00cc5 1639 pci_set_drvdata(pdev, NULL);
ccad0457
RM		 1640 pci_disable_device(pdev);
1641 return -1;
1642}
1643
1644/******************************************************************************/
1645/******************************************************************************/
1646/******************************************************************************/
1647
db83d08d 1648static const struct ddb_info ddb_none = {
ccad0457
RM		 1649 .type = DDB_NONE,
1650 .name = "Digital Devices PCIe bridge",
1651};
1652
db83d08d 1653static const struct ddb_info ddb_octopus = {
ccad0457
RM		 1654 .type = DDB_OCTOPUS,
1655 .name = "Digital Devices Octopus DVB adapter",
1656 .port_num = 4,
1657};
1658
db83d08d 1659static const struct ddb_info ddb_octopus_le = {
ccad0457
RM		 1660 .type = DDB_OCTOPUS,
1661 .name = "Digital Devices Octopus LE DVB adapter",
1662 .port_num = 2,
1663};
1664
db83d08d 1665static const struct ddb_info ddb_octopus_mini = {
93961435
CR		 1666 .type = DDB_OCTOPUS,
1667 .name = "Digital Devices Octopus Mini",
1668 .port_num = 4,
1669};
1670
db83d08d 1671static const struct ddb_info ddb_v6 = {
ccad0457
RM		 1672 .type = DDB_OCTOPUS,
1673 .name = "Digital Devices Cine S2 V6 DVB adapter",
1674 .port_num = 3,
1675};
db83d08d 1676static const struct ddb_info ddb_v6_5 = {
93961435
CR		 1677 .type = DDB_OCTOPUS,
1678 .name = "Digital Devices Cine S2 V6.5 DVB adapter",
1679 .port_num = 4,
1680};
1681
db83d08d 1682static const struct ddb_info ddb_dvbct = {
93961435
CR		 1683 .type = DDB_OCTOPUS,
1684 .name = "Digital Devices DVBCT V6.1 DVB adapter",
1685 .port_num = 3,
1686};
1687
db83d08d 1688static const struct ddb_info ddb_satixS2v3 = {
93961435
CR		 1689 .type = DDB_OCTOPUS,
1690 .name = "Mystique SaTiX-S2 V3 DVB adapter",
1691 .port_num = 3,
1692};
1693
db83d08d 1694static const struct ddb_info ddb_octopusv3 = {
93961435
CR		 1695 .type = DDB_OCTOPUS,
1696 .name = "Digital Devices Octopus V3 DVB adapter",
1697 .port_num = 4,
1698};
ccad0457
RM		 1699
1700#define DDVID 0xdd01 /* Digital Devices Vendor ID */
1701
4f1f3107 1702#define DDB_ID(_vend, _dev, _subvend, _subdev, _driverdata) { \
ccad0457
RM		 1703 .vendor = _vend, .device = _dev, \
1704 .subvendor = _subvend, .subdevice = _subdev, \
1705 .driver_data = (unsigned long)&_driverdata }
1706
4c62e976 1707static const struct pci_device_id ddb_id_tbl[] = {
ccad0457
RM		 1708 DDB_ID(DDVID, 0x0002, DDVID, 0x0001, ddb_octopus),
1709 DDB_ID(DDVID, 0x0003, DDVID, 0x0001, ddb_octopus),
1710 DDB_ID(DDVID, 0x0003, DDVID, 0x0002, ddb_octopus_le),
93961435 1711 DDB_ID(DDVID, 0x0003, DDVID, 0x0010, ddb_octopus_mini),
ccad0457 1712 DDB_ID(DDVID, 0x0003, DDVID, 0x0020, ddb_v6),
93961435
CR		 1713 DDB_ID(DDVID, 0x0003, DDVID, 0x0021, ddb_v6_5),
1714 DDB_ID(DDVID, 0x0003, DDVID, 0x0030, ddb_dvbct),
1715 DDB_ID(DDVID, 0x0003, DDVID, 0xdb03, ddb_satixS2v3),
1716 DDB_ID(DDVID, 0x0005, DDVID, 0x0004, ddb_octopusv3),
ccad0457
RM		 1717 /* in case sub-ids got deleted in flash */
1718 DDB_ID(DDVID, 0x0003, PCI_ANY_ID, PCI_ANY_ID, ddb_none),
1719 {0}
1720};
1721MODULE_DEVICE_TABLE(pci, ddb_id_tbl);
1722
1723
1724static struct pci_driver ddb_pci_driver = {
1725 .name = "DDBridge",
1726 .id_table = ddb_id_tbl,
1727 .probe = ddb_probe,
4c62e976 1728 .remove = ddb_remove,
ccad0457
RM		 1729};
1730
1731static __init int module_init_ddbridge(void)
1732{
f4e4a67a
AK		 1733 int ret;
1734
935747ff 1735 printk(KERN_INFO "Digital Devices PCIE bridge driver, Copyright (C) 2010-11 Digital Devices GmbH\n");
f4e4a67a
AK		 1736
1737 ret = ddb_class_create();
1738 if (ret < 0)
1739 return ret;
1740 ret = pci_register_driver(&ddb_pci_driver);
1741 if (ret < 0)
1742 ddb_class_destroy();
1743 return ret;
ccad0457
RM		 1744}
1745
1746static __exit void module_exit_ddbridge(void)
1747{
1748 pci_unregister_driver(&ddb_pci_driver);
1749 ddb_class_destroy();
1750}
1751
1752module_init(module_init_ddbridge);
1753module_exit(module_exit_ddbridge);
1754
1755MODULE_DESCRIPTION("Digital Devices PCIe Bridge");
1756MODULE_AUTHOR("Ralph Metzler");
1757MODULE_LICENSE("GPL");
1758MODULE_VERSION("0.5");
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