projects / mirror_ubuntu-artful-kernel.git / blame
| Commit | Line | Data |
|---|---|---|
| ccad0457 RM |
1 | /* |
| 2 | * ddbridge-regs.h: Digital Devices PCIe bridge driver | |
| 3 | * | |
| 4 | * Copyright (C) 2010-2011 Digital Devices GmbH | |
| 5 | * | |
| 6 | * This program is free software; you can redistribute it and/or | |
| 7 | * modify it under the terms of the GNU General Public License | |
| 8 | * version 2 only, as published by the Free Software Foundation. | |
| 9 | * | |
| 10 | * | |
| 11 | * This program is distributed in the hope that it will be useful, | |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 14 | * GNU General Public License for more details. | |
| 15 | * | |
| bcb63314 SA |
16 | * To obtain the license, point your browser to |
| 17 | * http://www.gnu.org/copyleft/gpl.html | |
| ccad0457 RM |
18 | */ |
| 19 | ||
| 4f1f3107 | 20 | /* DD-DVBBridgeV1.h 273 2010-09-17 05:03:16Z manfred */ |
| ccad0457 | 21 | |
| 4f1f3107 | 22 | /* Register Definitions */ |
| ccad0457 RM |
23 | |
| 24 | #define CUR_REGISTERMAP_VERSION 0x10000 | |
| 25 | ||
| 26 | #define HARDWARE_VERSION 0x00 | |
| 27 | #define REGISTERMAP_VERSION 0x04 | |
| 28 | ||
| 4f1f3107 OE |
29 | /* ------------------------------------------------------------------------- */ |
| 30 | /* SPI Controller */ | |
| ccad0457 RM |
31 | |
| 32 | #define SPI_CONTROL 0x10 | |
| 33 | #define SPI_DATA 0x14 | |
| 34 | ||
| 4f1f3107 | 35 | /* ------------------------------------------------------------------------- */ |
| ccad0457 | 36 | |
| 4f1f3107 OE |
37 | /* Interrupt controller */ |
| 38 | /* How many MSI's are available depends on HW (Min 2 max 8) */ | |
| 39 | /* How many are usable also depends on Host platform */ | |
| ccad0457 RM |
40 | |
| 41 | #define INTERRUPT_BASE (0x40) | |
| 42 | ||
| 43 | #define INTERRUPT_ENABLE (INTERRUPT_BASE + 0x00) | |
| 44 | #define MSI0_ENABLE (INTERRUPT_BASE + 0x00) | |
| 45 | #define MSI1_ENABLE (INTERRUPT_BASE + 0x04) | |
| 46 | #define MSI2_ENABLE (INTERRUPT_BASE + 0x08) | |
| 47 | #define MSI3_ENABLE (INTERRUPT_BASE + 0x0C) | |
| 48 | #define MSI4_ENABLE (INTERRUPT_BASE + 0x10) | |
| 49 | #define MSI5_ENABLE (INTERRUPT_BASE + 0x14) | |
| 50 | #define MSI6_ENABLE (INTERRUPT_BASE + 0x18) | |
| 51 | #define MSI7_ENABLE (INTERRUPT_BASE + 0x1C) | |
| 52 | ||
| 53 | #define INTERRUPT_STATUS (INTERRUPT_BASE + 0x20) | |
| 54 | #define INTERRUPT_ACK (INTERRUPT_BASE + 0x20) | |
| 55 | ||
| 56 | #define INTMASK_I2C1 (0x00000001) | |
| 57 | #define INTMASK_I2C2 (0x00000002) | |
| 58 | #define INTMASK_I2C3 (0x00000004) | |
| 59 | #define INTMASK_I2C4 (0x00000008) | |
| 60 | ||
| 61 | #define INTMASK_CIRQ1 (0x00000010) | |
| 62 | #define INTMASK_CIRQ2 (0x00000020) | |
| 63 | #define INTMASK_CIRQ3 (0x00000040) | |
| 64 | #define INTMASK_CIRQ4 (0x00000080) | |
| 65 | ||
| 66 | #define INTMASK_TSINPUT1 (0x00000100) | |
| 67 | #define INTMASK_TSINPUT2 (0x00000200) | |
| 68 | #define INTMASK_TSINPUT3 (0x00000400) | |
| 69 | #define INTMASK_TSINPUT4 (0x00000800) | |
| 70 | #define INTMASK_TSINPUT5 (0x00001000) | |
| 71 | #define INTMASK_TSINPUT6 (0x00002000) | |
| 72 | #define INTMASK_TSINPUT7 (0x00004000) | |
| 73 | #define INTMASK_TSINPUT8 (0x00008000) | |
| 74 | ||
| 75 | #define INTMASK_TSOUTPUT1 (0x00010000) | |
| 76 | #define INTMASK_TSOUTPUT2 (0x00020000) | |
| 77 | #define INTMASK_TSOUTPUT3 (0x00040000) | |
| 78 | #define INTMASK_TSOUTPUT4 (0x00080000) | |
| 79 | ||
| 4f1f3107 OE |
80 | /* ------------------------------------------------------------------------- */ |
| 81 | /* I2C Master Controller */ | |
| ccad0457 | 82 | |
| 4f1f3107 | 83 | #define I2C_BASE (0x80) /* Byte offset */ |
| ccad0457 RM |
84 | |
| 85 | #define I2C_COMMAND (0x00) | |
| 86 | #define I2C_TIMING (0x04) | |
| 4f1f3107 OE |
87 | #define I2C_TASKLENGTH (0x08) /* High read, low write */ |
| 88 | #define I2C_TASKADDRESS (0x0C) /* High read, low write */ | |
| ccad0457 RM |
89 | |
| 90 | #define I2C_MONITOR (0x1C) | |
| 91 | ||
| 92 | #define I2C_BASE_1 (I2C_BASE + 0x00) | |
| 93 | #define I2C_BASE_2 (I2C_BASE + 0x20) | |
| 94 | #define I2C_BASE_3 (I2C_BASE + 0x40) | |
| 95 | #define I2C_BASE_4 (I2C_BASE + 0x60) | |
| 96 | ||
| 97 | #define I2C_BASE_N(i) (I2C_BASE + (i) * 0x20) | |
| 98 | ||
| 4f1f3107 | 99 | #define I2C_TASKMEM_BASE (0x1000) /* Byte offset */ |
| ccad0457 RM |
100 | #define I2C_TASKMEM_SIZE (0x1000) |
| 101 | ||
| 102 | #define I2C_SPEED_400 (0x04030404) | |
| 103 | #define I2C_SPEED_200 (0x09080909) | |
| 104 | #define I2C_SPEED_154 (0x0C0B0C0C) | |
| 105 | #define I2C_SPEED_100 (0x13121313) | |
| 106 | #define I2C_SPEED_77 (0x19181919) | |
| 107 | #define I2C_SPEED_50 (0x27262727) | |
| 108 | ||
| 109 | ||
| 4f1f3107 OE |
110 | /* ------------------------------------------------------------------------- */ |
| 111 | /* DMA Controller */ | |
| ccad0457 RM |
112 | |
| 113 | #define DMA_BASE_WRITE (0x100) | |
| 114 | #define DMA_BASE_READ (0x140) | |
| 115 | ||
| 4f1f3107 OE |
116 | #define DMA_CONTROL (0x00) /* 64 */ |
| 117 | #define DMA_ERROR (0x04) /* 65 ( only read instance ) */ | |
| 118 | ||
| 119 | #define DMA_DIAG_CONTROL (0x1C) /* 71 */ | |
| 120 | #define DMA_DIAG_PACKETCOUNTER_LOW (0x20) /* 72 */ | |
| 121 | #define DMA_DIAG_PACKETCOUNTER_HIGH (0x24) /* 73 */ | |
| 122 | #define DMA_DIAG_TIMECOUNTER_LOW (0x28) /* 74 */ | |
| 123 | #define DMA_DIAG_TIMECOUNTER_HIGH (0x2C) /* 75 */ | |
| 124 | #define DMA_DIAG_RECHECKCOUNTER (0x30) /* 76 ( Split completions on read ) */ | |
| 125 | #define DMA_DIAG_WAITTIMEOUTINIT (0x34) /* 77 */ | |
| 126 | #define DMA_DIAG_WAITOVERFLOWCOUNTER (0x38) /* 78 */ | |
| 127 | #define DMA_DIAG_WAITCOUNTER (0x3C) /* 79 */ | |
| 128 | ||
| 129 | /* ------------------------------------------------------------------------- */ | |
| 130 | /* DMA Buffer */ | |
| ccad0457 RM |
131 | |
| 132 | #define TS_INPUT_BASE (0x200) | |
| 133 | #define TS_INPUT_CONTROL(i) (TS_INPUT_BASE + (i) * 16 + 0x00) | |
| 134 | ||
| 135 | #define TS_OUTPUT_BASE (0x280) | |
| 136 | #define TS_OUTPUT_CONTROL(i) (TS_OUTPUT_BASE + (i) * 16 + 0x00) | |
| 137 | ||
| 138 | #define DMA_BUFFER_BASE (0x300) | |
| 139 | ||
| 140 | #define DMA_BUFFER_CONTROL(i) (DMA_BUFFER_BASE + (i) * 16 + 0x00) | |
| 141 | #define DMA_BUFFER_ACK(i) (DMA_BUFFER_BASE + (i) * 16 + 0x04) | |
| 142 | #define DMA_BUFFER_CURRENT(i) (DMA_BUFFER_BASE + (i) * 16 + 0x08) | |
| 143 | #define DMA_BUFFER_SIZE(i) (DMA_BUFFER_BASE + (i) * 16 + 0x0c) | |
| 144 | ||
| 145 | #define DMA_BASE_ADDRESS_TABLE (0x2000) | |
| 146 | #define DMA_BASE_ADDRESS_TABLE_ENTRIES (512) | |
| 147 |