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a611d0ca IL |
1 | /* |
2 | * dm1105.c - driver for DVB cards based on SDMC DM1105 PCI chip | |
3 | * | |
4 | * Copyright (C) 2008 Igor M. Liplianin <liplianin@me.by> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, write to the Free Software | |
18 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
19 | * | |
20 | */ | |
21 | ||
a611d0ca | 22 | #include <linux/i2c.h> |
0017505d | 23 | #include <linux/i2c-algo-bit.h> |
a611d0ca | 24 | #include <linux/init.h> |
a6b7a407 | 25 | #include <linux/interrupt.h> |
a611d0ca IL |
26 | #include <linux/kernel.h> |
27 | #include <linux/module.h> | |
28 | #include <linux/proc_fs.h> | |
29 | #include <linux/pci.h> | |
30 | #include <linux/dma-mapping.h> | |
5a0e3ad6 | 31 | #include <linux/slab.h> |
6bda9644 | 32 | #include <media/rc-core.h> |
a611d0ca IL |
33 | |
34 | #include "demux.h" | |
35 | #include "dmxdev.h" | |
36 | #include "dvb_demux.h" | |
37 | #include "dvb_frontend.h" | |
38 | #include "dvb_net.h" | |
39 | #include "dvbdev.h" | |
40 | #include "dvb-pll.h" | |
41 | ||
42 | #include "stv0299.h" | |
e4aab64c IL |
43 | #include "stv0288.h" |
44 | #include "stb6000.h" | |
04ad28c9 | 45 | #include "si21xx.h" |
35d9c427 | 46 | #include "cx24116.h" |
a611d0ca | 47 | #include "z0194a.h" |
73f0af44 | 48 | #include "ts2020.h" |
b4a0e816 | 49 | #include "ds3000.h" |
a611d0ca | 50 | |
727e625c MCC |
51 | #define MODULE_NAME "dm1105" |
52 | ||
d8300df9 IL |
53 | #define UNSET (-1U) |
54 | ||
0017505d IL |
55 | #define DM1105_BOARD_NOAUTO UNSET |
56 | #define DM1105_BOARD_UNKNOWN 0 | |
57 | #define DM1105_BOARD_DVBWORLD_2002 1 | |
58 | #define DM1105_BOARD_DVBWORLD_2004 2 | |
59 | #define DM1105_BOARD_AXESS_DM05 3 | |
60 | #define DM1105_BOARD_UNBRANDED_I2C_ON_GPIO 4 | |
d8300df9 | 61 | |
a611d0ca IL |
62 | /* ----------------------------------------------- */ |
63 | /* | |
64 | * PCI ID's | |
65 | */ | |
66 | #ifndef PCI_VENDOR_ID_TRIGEM | |
67 | #define PCI_VENDOR_ID_TRIGEM 0x109f | |
68 | #endif | |
519a4bdc IL |
69 | #ifndef PCI_VENDOR_ID_AXESS |
70 | #define PCI_VENDOR_ID_AXESS 0x195d | |
71 | #endif | |
a611d0ca IL |
72 | #ifndef PCI_DEVICE_ID_DM1105 |
73 | #define PCI_DEVICE_ID_DM1105 0x036f | |
74 | #endif | |
75 | #ifndef PCI_DEVICE_ID_DW2002 | |
76 | #define PCI_DEVICE_ID_DW2002 0x2002 | |
77 | #endif | |
78 | #ifndef PCI_DEVICE_ID_DW2004 | |
79 | #define PCI_DEVICE_ID_DW2004 0x2004 | |
80 | #endif | |
519a4bdc IL |
81 | #ifndef PCI_DEVICE_ID_DM05 |
82 | #define PCI_DEVICE_ID_DM05 0x1105 | |
83 | #endif | |
a611d0ca IL |
84 | /* ----------------------------------------------- */ |
85 | /* sdmc dm1105 registers */ | |
86 | ||
87 | /* TS Control */ | |
88 | #define DM1105_TSCTR 0x00 | |
89 | #define DM1105_DTALENTH 0x04 | |
90 | ||
91 | /* GPIO Interface */ | |
92 | #define DM1105_GPIOVAL 0x08 | |
93 | #define DM1105_GPIOCTR 0x0c | |
94 | ||
95 | /* PID serial number */ | |
96 | #define DM1105_PIDN 0x10 | |
97 | ||
98 | /* Odd-even secret key select */ | |
99 | #define DM1105_CWSEL 0x14 | |
100 | ||
101 | /* Host Command Interface */ | |
102 | #define DM1105_HOST_CTR 0x18 | |
103 | #define DM1105_HOST_AD 0x1c | |
104 | ||
105 | /* PCI Interface */ | |
106 | #define DM1105_CR 0x30 | |
107 | #define DM1105_RST 0x34 | |
108 | #define DM1105_STADR 0x38 | |
109 | #define DM1105_RLEN 0x3c | |
110 | #define DM1105_WRP 0x40 | |
111 | #define DM1105_INTCNT 0x44 | |
112 | #define DM1105_INTMAK 0x48 | |
113 | #define DM1105_INTSTS 0x4c | |
114 | ||
115 | /* CW Value */ | |
116 | #define DM1105_ODD 0x50 | |
117 | #define DM1105_EVEN 0x58 | |
118 | ||
119 | /* PID Value */ | |
120 | #define DM1105_PID 0x60 | |
121 | ||
122 | /* IR Control */ | |
123 | #define DM1105_IRCTR 0x64 | |
124 | #define DM1105_IRMODE 0x68 | |
125 | #define DM1105_SYSTEMCODE 0x6c | |
126 | #define DM1105_IRCODE 0x70 | |
127 | ||
128 | /* Unknown Values */ | |
129 | #define DM1105_ENCRYPT 0x74 | |
130 | #define DM1105_VER 0x7c | |
131 | ||
132 | /* I2C Interface */ | |
133 | #define DM1105_I2CCTR 0x80 | |
134 | #define DM1105_I2CSTS 0x81 | |
135 | #define DM1105_I2CDAT 0x82 | |
136 | #define DM1105_I2C_RA 0x83 | |
137 | /* ----------------------------------------------- */ | |
138 | /* Interrupt Mask Bits */ | |
139 | ||
140 | #define INTMAK_TSIRQM 0x01 | |
141 | #define INTMAK_HIRQM 0x04 | |
142 | #define INTMAK_IRM 0x08 | |
143 | #define INTMAK_ALLMASK (INTMAK_TSIRQM | \ | |
144 | INTMAK_HIRQM | \ | |
145 | INTMAK_IRM) | |
146 | #define INTMAK_NONEMASK 0x00 | |
147 | ||
148 | /* Interrupt Status Bits */ | |
149 | #define INTSTS_TSIRQ 0x01 | |
150 | #define INTSTS_HIRQ 0x04 | |
151 | #define INTSTS_IR 0x08 | |
152 | ||
153 | /* IR Control Bits */ | |
154 | #define DM1105_IR_EN 0x01 | |
155 | #define DM1105_SYS_CHK 0x02 | |
156 | #define DM1105_REP_FLG 0x08 | |
157 | ||
158 | /* EEPROM addr */ | |
159 | #define IIC_24C01_addr 0xa0 | |
160 | /* Max board count */ | |
161 | #define DM1105_MAX 0x04 | |
162 | ||
163 | #define DRIVER_NAME "dm1105" | |
0017505d | 164 | #define DM1105_I2C_GPIO_NAME "dm1105-gpio" |
a611d0ca IL |
165 | |
166 | #define DM1105_DMA_PACKETS 47 | |
167 | #define DM1105_DMA_PACKET_LENGTH (128*4) | |
168 | #define DM1105_DMA_BYTES (128 * 4 * DM1105_DMA_PACKETS) | |
169 | ||
0017505d IL |
170 | /* */ |
171 | #define GPIO08 (1 << 8) | |
172 | #define GPIO13 (1 << 13) | |
173 | #define GPIO14 (1 << 14) | |
174 | #define GPIO15 (1 << 15) | |
175 | #define GPIO16 (1 << 16) | |
176 | #define GPIO17 (1 << 17) | |
177 | #define GPIO_ALL 0x03ffff | |
178 | ||
a611d0ca | 179 | /* GPIO's for LNB power control */ |
0017505d IL |
180 | #define DM1105_LNB_MASK (GPIO_ALL & ~(GPIO14 | GPIO13)) |
181 | #define DM1105_LNB_OFF GPIO17 | |
182 | #define DM1105_LNB_13V (GPIO16 | GPIO08) | |
183 | #define DM1105_LNB_18V GPIO08 | |
a611d0ca | 184 | |
519a4bdc | 185 | /* GPIO's for LNB power control for Axess DM05 */ |
0017505d IL |
186 | #define DM05_LNB_MASK (GPIO_ALL & ~(GPIO14 | GPIO13)) |
187 | #define DM05_LNB_OFF GPIO17/* actually 13v */ | |
188 | #define DM05_LNB_13V GPIO17 | |
189 | #define DM05_LNB_18V (GPIO17 | GPIO16) | |
190 | ||
191 | /* GPIO's for LNB power control for unbranded with I2C on GPIO */ | |
192 | #define UNBR_LNB_MASK (GPIO17 | GPIO16) | |
193 | #define UNBR_LNB_OFF 0 | |
194 | #define UNBR_LNB_13V GPIO17 | |
195 | #define UNBR_LNB_18V (GPIO17 | GPIO16) | |
519a4bdc | 196 | |
d8300df9 IL |
197 | static unsigned int card[] = {[0 ... 3] = UNSET }; |
198 | module_param_array(card, int, NULL, 0444); | |
199 | MODULE_PARM_DESC(card, "card type"); | |
200 | ||
a611d0ca IL |
201 | static int ir_debug; |
202 | module_param(ir_debug, int, 0644); | |
203 | MODULE_PARM_DESC(ir_debug, "enable debugging information for IR decoding"); | |
204 | ||
d8300df9 IL |
205 | static unsigned int dm1105_devcount; |
206 | ||
a611d0ca IL |
207 | DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr); |
208 | ||
d8300df9 | 209 | struct dm1105_board { |
0017505d IL |
210 | char *name; |
211 | struct { | |
212 | u32 mask, off, v13, v18; | |
213 | } lnb; | |
214 | u32 gpio_scl, gpio_sda; | |
d8300df9 IL |
215 | }; |
216 | ||
217 | struct dm1105_subid { | |
218 | u16 subvendor; | |
219 | u16 subdevice; | |
220 | u32 card; | |
221 | }; | |
222 | ||
223 | static const struct dm1105_board dm1105_boards[] = { | |
224 | [DM1105_BOARD_UNKNOWN] = { | |
225 | .name = "UNKNOWN/GENERIC", | |
0017505d IL |
226 | .lnb = { |
227 | .mask = DM1105_LNB_MASK, | |
228 | .off = DM1105_LNB_OFF, | |
229 | .v13 = DM1105_LNB_13V, | |
230 | .v18 = DM1105_LNB_18V, | |
231 | }, | |
d8300df9 IL |
232 | }, |
233 | [DM1105_BOARD_DVBWORLD_2002] = { | |
234 | .name = "DVBWorld PCI 2002", | |
0017505d IL |
235 | .lnb = { |
236 | .mask = DM1105_LNB_MASK, | |
237 | .off = DM1105_LNB_OFF, | |
238 | .v13 = DM1105_LNB_13V, | |
239 | .v18 = DM1105_LNB_18V, | |
240 | }, | |
d8300df9 IL |
241 | }, |
242 | [DM1105_BOARD_DVBWORLD_2004] = { | |
243 | .name = "DVBWorld PCI 2004", | |
0017505d IL |
244 | .lnb = { |
245 | .mask = DM1105_LNB_MASK, | |
246 | .off = DM1105_LNB_OFF, | |
247 | .v13 = DM1105_LNB_13V, | |
248 | .v18 = DM1105_LNB_18V, | |
249 | }, | |
d8300df9 IL |
250 | }, |
251 | [DM1105_BOARD_AXESS_DM05] = { | |
252 | .name = "Axess/EasyTv DM05", | |
0017505d IL |
253 | .lnb = { |
254 | .mask = DM05_LNB_MASK, | |
255 | .off = DM05_LNB_OFF, | |
256 | .v13 = DM05_LNB_13V, | |
257 | .v18 = DM05_LNB_18V, | |
258 | }, | |
259 | }, | |
260 | [DM1105_BOARD_UNBRANDED_I2C_ON_GPIO] = { | |
261 | .name = "Unbranded DM1105 with i2c on GPIOs", | |
262 | .lnb = { | |
263 | .mask = UNBR_LNB_MASK, | |
264 | .off = UNBR_LNB_OFF, | |
265 | .v13 = UNBR_LNB_13V, | |
266 | .v18 = UNBR_LNB_18V, | |
267 | }, | |
268 | .gpio_scl = GPIO14, | |
269 | .gpio_sda = GPIO13, | |
d8300df9 IL |
270 | }, |
271 | }; | |
272 | ||
273 | static const struct dm1105_subid dm1105_subids[] = { | |
274 | { | |
275 | .subvendor = 0x0000, | |
276 | .subdevice = 0x2002, | |
277 | .card = DM1105_BOARD_DVBWORLD_2002, | |
278 | }, { | |
279 | .subvendor = 0x0001, | |
280 | .subdevice = 0x2002, | |
281 | .card = DM1105_BOARD_DVBWORLD_2002, | |
282 | }, { | |
283 | .subvendor = 0x0000, | |
284 | .subdevice = 0x2004, | |
285 | .card = DM1105_BOARD_DVBWORLD_2004, | |
286 | }, { | |
287 | .subvendor = 0x0001, | |
288 | .subdevice = 0x2004, | |
289 | .card = DM1105_BOARD_DVBWORLD_2004, | |
290 | }, { | |
291 | .subvendor = 0x195d, | |
292 | .subdevice = 0x1105, | |
293 | .card = DM1105_BOARD_AXESS_DM05, | |
294 | }, | |
295 | }; | |
296 | ||
297 | static void dm1105_card_list(struct pci_dev *pci) | |
298 | { | |
299 | int i; | |
300 | ||
301 | if (0 == pci->subsystem_vendor && | |
302 | 0 == pci->subsystem_device) { | |
303 | printk(KERN_ERR | |
304 | "dm1105: Your board has no valid PCI Subsystem ID\n" | |
305 | "dm1105: and thus can't be autodetected\n" | |
306 | "dm1105: Please pass card=<n> insmod option to\n" | |
307 | "dm1105: workaround that. Redirect complaints to\n" | |
308 | "dm1105: the vendor of the TV card. Best regards,\n" | |
309 | "dm1105: -- tux\n"); | |
310 | } else { | |
311 | printk(KERN_ERR | |
312 | "dm1105: Your board isn't known (yet) to the driver.\n" | |
313 | "dm1105: You can try to pick one of the existing\n" | |
314 | "dm1105: card configs via card=<n> insmod option.\n" | |
315 | "dm1105: Updating to the latest version might help\n" | |
316 | "dm1105: as well.\n"); | |
317 | } | |
318 | printk(KERN_ERR "Here is a list of valid choices for the card=<n> " | |
319 | "insmod option:\n"); | |
320 | for (i = 0; i < ARRAY_SIZE(dm1105_boards); i++) | |
321 | printk(KERN_ERR "dm1105: card=%d -> %s\n", | |
322 | i, dm1105_boards[i].name); | |
323 | } | |
324 | ||
a611d0ca IL |
325 | /* infrared remote control */ |
326 | struct infrared { | |
d8b4b582 | 327 | struct rc_dev *dev; |
a611d0ca | 328 | char input_phys[32]; |
b72857dd | 329 | struct work_struct work; |
a611d0ca IL |
330 | u32 ir_command; |
331 | }; | |
332 | ||
34d2f9bf | 333 | struct dm1105_dev { |
a611d0ca IL |
334 | /* pci */ |
335 | struct pci_dev *pdev; | |
336 | u8 __iomem *io_mem; | |
337 | ||
338 | /* ir */ | |
339 | struct infrared ir; | |
340 | ||
341 | /* dvb */ | |
342 | struct dmx_frontend hw_frontend; | |
343 | struct dmx_frontend mem_frontend; | |
344 | struct dmxdev dmxdev; | |
345 | struct dvb_adapter dvb_adapter; | |
346 | struct dvb_demux demux; | |
347 | struct dvb_frontend *fe; | |
348 | struct dvb_net dvbnet; | |
349 | unsigned int full_ts_users; | |
d8300df9 IL |
350 | unsigned int boardnr; |
351 | int nr; | |
a611d0ca IL |
352 | |
353 | /* i2c */ | |
354 | struct i2c_adapter i2c_adap; | |
0017505d IL |
355 | struct i2c_adapter i2c_bb_adap; |
356 | struct i2c_algo_bit_data i2c_bit; | |
a611d0ca | 357 | |
d1498ffc IL |
358 | /* irq */ |
359 | struct work_struct work; | |
519a4bdc IL |
360 | struct workqueue_struct *wq; |
361 | char wqn[16]; | |
d1498ffc | 362 | |
a611d0ca IL |
363 | /* dma */ |
364 | dma_addr_t dma_addr; | |
365 | unsigned char *ts_buf; | |
366 | u32 wrp; | |
d1498ffc | 367 | u32 nextwrp; |
a611d0ca IL |
368 | u32 buffer_size; |
369 | unsigned int PacketErrorCount; | |
370 | unsigned int dmarst; | |
371 | spinlock_t lock; | |
a611d0ca IL |
372 | }; |
373 | ||
34d2f9bf | 374 | #define dm_io_mem(reg) ((unsigned long)(&dev->io_mem[reg])) |
a611d0ca | 375 | |
5eb3291f IL |
376 | #define dm_readb(reg) inb(dm_io_mem(reg)) |
377 | #define dm_writeb(reg, value) outb((value), (dm_io_mem(reg))) | |
378 | ||
379 | #define dm_readw(reg) inw(dm_io_mem(reg)) | |
380 | #define dm_writew(reg, value) outw((value), (dm_io_mem(reg))) | |
381 | ||
382 | #define dm_readl(reg) inl(dm_io_mem(reg)) | |
383 | #define dm_writel(reg, value) outl((value), (dm_io_mem(reg))) | |
384 | ||
385 | #define dm_andorl(reg, mask, value) \ | |
386 | outl((inl(dm_io_mem(reg)) & ~(mask)) |\ | |
387 | ((value) & (mask)), (dm_io_mem(reg))) | |
388 | ||
389 | #define dm_setl(reg, bit) dm_andorl((reg), (bit), (bit)) | |
390 | #define dm_clearl(reg, bit) dm_andorl((reg), (bit), 0) | |
391 | ||
0017505d IL |
392 | /* The chip has 18 GPIOs. In HOST mode GPIO's used as 15 bit address lines, |
393 | so we can use only 3 GPIO's from GPIO15 to GPIO17. | |
394 | Here I don't check whether HOST is enebled as it is not implemented yet. | |
395 | */ | |
396 | static void dm1105_gpio_set(struct dm1105_dev *dev, u32 mask) | |
397 | { | |
398 | if (mask & 0xfffc0000) | |
399 | printk(KERN_ERR "%s: Only 18 GPIO's are allowed\n", __func__); | |
400 | ||
401 | if (mask & 0x0003ffff) | |
402 | dm_setl(DM1105_GPIOVAL, mask & 0x0003ffff); | |
403 | ||
404 | } | |
405 | ||
406 | static void dm1105_gpio_clear(struct dm1105_dev *dev, u32 mask) | |
407 | { | |
408 | if (mask & 0xfffc0000) | |
409 | printk(KERN_ERR "%s: Only 18 GPIO's are allowed\n", __func__); | |
410 | ||
411 | if (mask & 0x0003ffff) | |
412 | dm_clearl(DM1105_GPIOVAL, mask & 0x0003ffff); | |
413 | ||
414 | } | |
415 | ||
416 | static void dm1105_gpio_andor(struct dm1105_dev *dev, u32 mask, u32 val) | |
417 | { | |
418 | if (mask & 0xfffc0000) | |
419 | printk(KERN_ERR "%s: Only 18 GPIO's are allowed\n", __func__); | |
420 | ||
421 | if (mask & 0x0003ffff) | |
422 | dm_andorl(DM1105_GPIOVAL, mask & 0x0003ffff, val); | |
423 | ||
424 | } | |
425 | ||
426 | static u32 dm1105_gpio_get(struct dm1105_dev *dev, u32 mask) | |
427 | { | |
428 | if (mask & 0xfffc0000) | |
429 | printk(KERN_ERR "%s: Only 18 GPIO's are allowed\n", __func__); | |
430 | ||
431 | if (mask & 0x0003ffff) | |
432 | return dm_readl(DM1105_GPIOVAL) & mask & 0x0003ffff; | |
433 | ||
434 | return 0; | |
435 | } | |
436 | ||
437 | static void dm1105_gpio_enable(struct dm1105_dev *dev, u32 mask, int asoutput) | |
438 | { | |
439 | if (mask & 0xfffc0000) | |
440 | printk(KERN_ERR "%s: Only 18 GPIO's are allowed\n", __func__); | |
441 | ||
442 | if ((mask & 0x0003ffff) && asoutput) | |
443 | dm_clearl(DM1105_GPIOCTR, mask & 0x0003ffff); | |
444 | else if ((mask & 0x0003ffff) && !asoutput) | |
445 | dm_setl(DM1105_GPIOCTR, mask & 0x0003ffff); | |
446 | ||
447 | } | |
448 | ||
449 | static void dm1105_setline(struct dm1105_dev *dev, u32 line, int state) | |
450 | { | |
451 | if (state) | |
452 | dm1105_gpio_enable(dev, line, 0); | |
453 | else { | |
454 | dm1105_gpio_enable(dev, line, 1); | |
455 | dm1105_gpio_clear(dev, line); | |
456 | } | |
457 | } | |
458 | ||
459 | static void dm1105_setsda(void *data, int state) | |
460 | { | |
461 | struct dm1105_dev *dev = data; | |
462 | ||
463 | dm1105_setline(dev, dm1105_boards[dev->boardnr].gpio_sda, state); | |
464 | } | |
465 | ||
466 | static void dm1105_setscl(void *data, int state) | |
467 | { | |
468 | struct dm1105_dev *dev = data; | |
469 | ||
470 | dm1105_setline(dev, dm1105_boards[dev->boardnr].gpio_scl, state); | |
471 | } | |
472 | ||
473 | static int dm1105_getsda(void *data) | |
474 | { | |
475 | struct dm1105_dev *dev = data; | |
476 | ||
477 | return dm1105_gpio_get(dev, dm1105_boards[dev->boardnr].gpio_sda) | |
478 | ? 1 : 0; | |
479 | } | |
480 | ||
481 | static int dm1105_getscl(void *data) | |
482 | { | |
483 | struct dm1105_dev *dev = data; | |
484 | ||
485 | return dm1105_gpio_get(dev, dm1105_boards[dev->boardnr].gpio_scl) | |
486 | ? 1 : 0; | |
487 | } | |
488 | ||
a611d0ca IL |
489 | static int dm1105_i2c_xfer(struct i2c_adapter *i2c_adap, |
490 | struct i2c_msg *msgs, int num) | |
491 | { | |
34d2f9bf | 492 | struct dm1105_dev *dev ; |
a611d0ca IL |
493 | |
494 | int addr, rc, i, j, k, len, byte, data; | |
495 | u8 status; | |
496 | ||
34d2f9bf | 497 | dev = i2c_adap->algo_data; |
a611d0ca | 498 | for (i = 0; i < num; i++) { |
5eb3291f | 499 | dm_writeb(DM1105_I2CCTR, 0x00); |
a611d0ca IL |
500 | if (msgs[i].flags & I2C_M_RD) { |
501 | /* read bytes */ | |
502 | addr = msgs[i].addr << 1; | |
503 | addr |= 1; | |
5eb3291f | 504 | dm_writeb(DM1105_I2CDAT, addr); |
a611d0ca | 505 | for (byte = 0; byte < msgs[i].len; byte++) |
5eb3291f | 506 | dm_writeb(DM1105_I2CDAT + byte + 1, 0); |
a611d0ca | 507 | |
5eb3291f | 508 | dm_writeb(DM1105_I2CCTR, 0x81 + msgs[i].len); |
a611d0ca IL |
509 | for (j = 0; j < 55; j++) { |
510 | mdelay(10); | |
5eb3291f | 511 | status = dm_readb(DM1105_I2CSTS); |
a611d0ca IL |
512 | if ((status & 0xc0) == 0x40) |
513 | break; | |
514 | } | |
515 | if (j >= 55) | |
516 | return -1; | |
517 | ||
518 | for (byte = 0; byte < msgs[i].len; byte++) { | |
5eb3291f | 519 | rc = dm_readb(DM1105_I2CDAT + byte + 1); |
a611d0ca IL |
520 | if (rc < 0) |
521 | goto err; | |
522 | msgs[i].buf[byte] = rc; | |
523 | } | |
ed7c847a IL |
524 | } else if ((msgs[i].buf[0] == 0xf7) && (msgs[i].addr == 0x55)) { |
525 | /* prepaired for cx24116 firmware */ | |
526 | /* Write in small blocks */ | |
527 | len = msgs[i].len - 1; | |
528 | k = 1; | |
529 | do { | |
5eb3291f IL |
530 | dm_writeb(DM1105_I2CDAT, msgs[i].addr << 1); |
531 | dm_writeb(DM1105_I2CDAT + 1, 0xf7); | |
ed7c847a IL |
532 | for (byte = 0; byte < (len > 48 ? 48 : len); byte++) { |
533 | data = msgs[i].buf[k + byte]; | |
5eb3291f | 534 | dm_writeb(DM1105_I2CDAT + byte + 2, data); |
a611d0ca | 535 | } |
5eb3291f | 536 | dm_writeb(DM1105_I2CCTR, 0x82 + (len > 48 ? 48 : len)); |
a611d0ca IL |
537 | for (j = 0; j < 25; j++) { |
538 | mdelay(10); | |
5eb3291f | 539 | status = dm_readb(DM1105_I2CSTS); |
a611d0ca IL |
540 | if ((status & 0xc0) == 0x40) |
541 | break; | |
542 | } | |
543 | ||
544 | if (j >= 25) | |
545 | return -1; | |
ed7c847a IL |
546 | |
547 | k += 48; | |
548 | len -= 48; | |
549 | } while (len > 0); | |
550 | } else { | |
551 | /* write bytes */ | |
5eb3291f | 552 | dm_writeb(DM1105_I2CDAT, msgs[i].addr << 1); |
ed7c847a IL |
553 | for (byte = 0; byte < msgs[i].len; byte++) { |
554 | data = msgs[i].buf[byte]; | |
5eb3291f | 555 | dm_writeb(DM1105_I2CDAT + byte + 1, data); |
ed7c847a | 556 | } |
5eb3291f | 557 | dm_writeb(DM1105_I2CCTR, 0x81 + msgs[i].len); |
ed7c847a IL |
558 | for (j = 0; j < 25; j++) { |
559 | mdelay(10); | |
5eb3291f | 560 | status = dm_readb(DM1105_I2CSTS); |
ed7c847a IL |
561 | if ((status & 0xc0) == 0x40) |
562 | break; | |
a611d0ca | 563 | } |
ed7c847a IL |
564 | |
565 | if (j >= 25) | |
566 | return -1; | |
a611d0ca IL |
567 | } |
568 | } | |
569 | return num; | |
570 | err: | |
571 | return rc; | |
572 | } | |
573 | ||
574 | static u32 functionality(struct i2c_adapter *adap) | |
575 | { | |
576 | return I2C_FUNC_I2C; | |
577 | } | |
578 | ||
579 | static struct i2c_algorithm dm1105_algo = { | |
580 | .master_xfer = dm1105_i2c_xfer, | |
581 | .functionality = functionality, | |
582 | }; | |
583 | ||
34d2f9bf | 584 | static inline struct dm1105_dev *feed_to_dm1105_dev(struct dvb_demux_feed *feed) |
a611d0ca | 585 | { |
34d2f9bf | 586 | return container_of(feed->demux, struct dm1105_dev, demux); |
a611d0ca IL |
587 | } |
588 | ||
34d2f9bf | 589 | static inline struct dm1105_dev *frontend_to_dm1105_dev(struct dvb_frontend *fe) |
a611d0ca | 590 | { |
34d2f9bf | 591 | return container_of(fe->dvb, struct dm1105_dev, dvb_adapter); |
a611d0ca IL |
592 | } |
593 | ||
34d2f9bf | 594 | static int dm1105_set_voltage(struct dvb_frontend *fe, fe_sec_voltage_t voltage) |
a611d0ca | 595 | { |
34d2f9bf | 596 | struct dm1105_dev *dev = frontend_to_dm1105_dev(fe); |
a611d0ca | 597 | |
0017505d | 598 | dm1105_gpio_enable(dev, dm1105_boards[dev->boardnr].lnb.mask, 1); |
519a4bdc | 599 | if (voltage == SEC_VOLTAGE_18) |
0017505d IL |
600 | dm1105_gpio_andor(dev, |
601 | dm1105_boards[dev->boardnr].lnb.mask, | |
602 | dm1105_boards[dev->boardnr].lnb.v18); | |
d8300df9 | 603 | else if (voltage == SEC_VOLTAGE_13) |
0017505d IL |
604 | dm1105_gpio_andor(dev, |
605 | dm1105_boards[dev->boardnr].lnb.mask, | |
606 | dm1105_boards[dev->boardnr].lnb.v13); | |
d8300df9 | 607 | else |
0017505d IL |
608 | dm1105_gpio_andor(dev, |
609 | dm1105_boards[dev->boardnr].lnb.mask, | |
610 | dm1105_boards[dev->boardnr].lnb.off); | |
a611d0ca IL |
611 | |
612 | return 0; | |
613 | } | |
614 | ||
34d2f9bf | 615 | static void dm1105_set_dma_addr(struct dm1105_dev *dev) |
a611d0ca | 616 | { |
5eb3291f | 617 | dm_writel(DM1105_STADR, cpu_to_le32(dev->dma_addr)); |
a611d0ca IL |
618 | } |
619 | ||
4c62e976 | 620 | static int dm1105_dma_map(struct dm1105_dev *dev) |
a611d0ca | 621 | { |
34d2f9bf IL |
622 | dev->ts_buf = pci_alloc_consistent(dev->pdev, |
623 | 6 * DM1105_DMA_BYTES, | |
624 | &dev->dma_addr); | |
a611d0ca | 625 | |
34d2f9bf | 626 | return !dev->ts_buf; |
a611d0ca IL |
627 | } |
628 | ||
34d2f9bf | 629 | static void dm1105_dma_unmap(struct dm1105_dev *dev) |
a611d0ca | 630 | { |
34d2f9bf IL |
631 | pci_free_consistent(dev->pdev, |
632 | 6 * DM1105_DMA_BYTES, | |
633 | dev->ts_buf, | |
634 | dev->dma_addr); | |
a611d0ca IL |
635 | } |
636 | ||
34d2f9bf | 637 | static void dm1105_enable_irqs(struct dm1105_dev *dev) |
a611d0ca | 638 | { |
5eb3291f IL |
639 | dm_writeb(DM1105_INTMAK, INTMAK_ALLMASK); |
640 | dm_writeb(DM1105_CR, 1); | |
a611d0ca IL |
641 | } |
642 | ||
34d2f9bf | 643 | static void dm1105_disable_irqs(struct dm1105_dev *dev) |
a611d0ca | 644 | { |
5eb3291f IL |
645 | dm_writeb(DM1105_INTMAK, INTMAK_IRM); |
646 | dm_writeb(DM1105_CR, 0); | |
a611d0ca IL |
647 | } |
648 | ||
34d2f9bf | 649 | static int dm1105_start_feed(struct dvb_demux_feed *f) |
a611d0ca | 650 | { |
34d2f9bf | 651 | struct dm1105_dev *dev = feed_to_dm1105_dev(f); |
a611d0ca | 652 | |
34d2f9bf IL |
653 | if (dev->full_ts_users++ == 0) |
654 | dm1105_enable_irqs(dev); | |
a611d0ca IL |
655 | |
656 | return 0; | |
657 | } | |
658 | ||
34d2f9bf | 659 | static int dm1105_stop_feed(struct dvb_demux_feed *f) |
a611d0ca | 660 | { |
34d2f9bf | 661 | struct dm1105_dev *dev = feed_to_dm1105_dev(f); |
a611d0ca | 662 | |
34d2f9bf IL |
663 | if (--dev->full_ts_users == 0) |
664 | dm1105_disable_irqs(dev); | |
a611d0ca IL |
665 | |
666 | return 0; | |
667 | } | |
668 | ||
b72857dd IL |
669 | /* ir work handler */ |
670 | static void dm1105_emit_key(struct work_struct *work) | |
a611d0ca | 671 | { |
b72857dd | 672 | struct infrared *ir = container_of(work, struct infrared, work); |
a611d0ca IL |
673 | u32 ircom = ir->ir_command; |
674 | u8 data; | |
a611d0ca | 675 | |
d1498ffc IL |
676 | if (ir_debug) |
677 | printk(KERN_INFO "%s: received byte 0x%04x\n", __func__, ircom); | |
678 | ||
a611d0ca IL |
679 | data = (ircom >> 8) & 0x7f; |
680 | ||
ca86674b | 681 | rc_keydown(ir->dev, data, 0); |
a611d0ca IL |
682 | } |
683 | ||
d1498ffc IL |
684 | /* work handler */ |
685 | static void dm1105_dmx_buffer(struct work_struct *work) | |
686 | { | |
34d2f9bf | 687 | struct dm1105_dev *dev = container_of(work, struct dm1105_dev, work); |
d1498ffc | 688 | unsigned int nbpackets; |
34d2f9bf IL |
689 | u32 oldwrp = dev->wrp; |
690 | u32 nextwrp = dev->nextwrp; | |
d1498ffc | 691 | |
34d2f9bf IL |
692 | if (!((dev->ts_buf[oldwrp] == 0x47) && |
693 | (dev->ts_buf[oldwrp + 188] == 0x47) && | |
694 | (dev->ts_buf[oldwrp + 188 * 2] == 0x47))) { | |
695 | dev->PacketErrorCount++; | |
d1498ffc | 696 | /* bad packet found */ |
34d2f9bf IL |
697 | if ((dev->PacketErrorCount >= 2) && |
698 | (dev->dmarst == 0)) { | |
5eb3291f | 699 | dm_writeb(DM1105_RST, 1); |
34d2f9bf IL |
700 | dev->wrp = 0; |
701 | dev->PacketErrorCount = 0; | |
702 | dev->dmarst = 0; | |
d1498ffc IL |
703 | return; |
704 | } | |
705 | } | |
706 | ||
707 | if (nextwrp < oldwrp) { | |
34d2f9bf IL |
708 | memcpy(dev->ts_buf + dev->buffer_size, dev->ts_buf, nextwrp); |
709 | nbpackets = ((dev->buffer_size - oldwrp) + nextwrp) / 188; | |
d1498ffc IL |
710 | } else |
711 | nbpackets = (nextwrp - oldwrp) / 188; | |
712 | ||
34d2f9bf IL |
713 | dev->wrp = nextwrp; |
714 | dvb_dmx_swfilter_packets(&dev->demux, &dev->ts_buf[oldwrp], nbpackets); | |
d1498ffc IL |
715 | } |
716 | ||
34d2f9bf | 717 | static irqreturn_t dm1105_irq(int irq, void *dev_id) |
a611d0ca | 718 | { |
34d2f9bf | 719 | struct dm1105_dev *dev = dev_id; |
a611d0ca IL |
720 | |
721 | /* Read-Write INSTS Ack's Interrupt for DM1105 chip 16.03.2008 */ | |
5eb3291f IL |
722 | unsigned int intsts = dm_readb(DM1105_INTSTS); |
723 | dm_writeb(DM1105_INTSTS, intsts); | |
a611d0ca IL |
724 | |
725 | switch (intsts) { | |
726 | case INTSTS_TSIRQ: | |
727 | case (INTSTS_TSIRQ | INTSTS_IR): | |
5eb3291f | 728 | dev->nextwrp = dm_readl(DM1105_WRP) - dm_readl(DM1105_STADR); |
34d2f9bf | 729 | queue_work(dev->wq, &dev->work); |
a611d0ca IL |
730 | break; |
731 | case INTSTS_IR: | |
5eb3291f | 732 | dev->ir.ir_command = dm_readl(DM1105_IRCODE); |
34d2f9bf | 733 | schedule_work(&dev->ir.work); |
a611d0ca IL |
734 | break; |
735 | } | |
a611d0ca | 736 | |
d1498ffc | 737 | return IRQ_HANDLED; |
a611d0ca IL |
738 | } |
739 | ||
4c62e976 | 740 | static int dm1105_ir_init(struct dm1105_dev *dm1105) |
a611d0ca | 741 | { |
d8b4b582 | 742 | struct rc_dev *dev; |
b72857dd | 743 | int err = -ENOMEM; |
a611d0ca | 744 | |
d8b4b582 DH |
745 | dev = rc_allocate_device(); |
746 | if (!dev) | |
a611d0ca IL |
747 | return -ENOMEM; |
748 | ||
a611d0ca IL |
749 | snprintf(dm1105->ir.input_phys, sizeof(dm1105->ir.input_phys), |
750 | "pci-%s/ir0", pci_name(dm1105->pdev)); | |
751 | ||
d8b4b582 DH |
752 | dev->driver_name = MODULE_NAME; |
753 | dev->map_name = RC_MAP_DM1105_NEC; | |
754 | dev->driver_type = RC_DRIVER_SCANCODE; | |
755 | dev->input_name = "DVB on-card IR receiver"; | |
756 | dev->input_phys = dm1105->ir.input_phys; | |
757 | dev->input_id.bustype = BUS_PCI; | |
758 | dev->input_id.version = 1; | |
a611d0ca | 759 | if (dm1105->pdev->subsystem_vendor) { |
d8b4b582 DH |
760 | dev->input_id.vendor = dm1105->pdev->subsystem_vendor; |
761 | dev->input_id.product = dm1105->pdev->subsystem_device; | |
a611d0ca | 762 | } else { |
d8b4b582 DH |
763 | dev->input_id.vendor = dm1105->pdev->vendor; |
764 | dev->input_id.product = dm1105->pdev->device; | |
a611d0ca | 765 | } |
d8b4b582 | 766 | dev->dev.parent = &dm1105->pdev->dev; |
b72857dd IL |
767 | |
768 | INIT_WORK(&dm1105->ir.work, dm1105_emit_key); | |
769 | ||
d8b4b582 | 770 | err = rc_register_device(dev); |
15100d89 | 771 | if (err < 0) { |
d8b4b582 | 772 | rc_free_device(dev); |
15100d89 DH |
773 | return err; |
774 | } | |
a611d0ca | 775 | |
d8b4b582 | 776 | dm1105->ir.dev = dev; |
15100d89 | 777 | return 0; |
a611d0ca IL |
778 | } |
779 | ||
4c62e976 | 780 | static void dm1105_ir_exit(struct dm1105_dev *dm1105) |
a611d0ca | 781 | { |
d8b4b582 | 782 | rc_unregister_device(dm1105->ir.dev); |
a611d0ca IL |
783 | } |
784 | ||
4c62e976 | 785 | static int dm1105_hw_init(struct dm1105_dev *dev) |
a611d0ca | 786 | { |
34d2f9bf | 787 | dm1105_disable_irqs(dev); |
a611d0ca | 788 | |
5eb3291f | 789 | dm_writeb(DM1105_HOST_CTR, 0); |
a611d0ca IL |
790 | |
791 | /*DATALEN 188,*/ | |
5eb3291f | 792 | dm_writeb(DM1105_DTALENTH, 188); |
a611d0ca | 793 | /*TS_STRT TS_VALP MSBFIRST TS_MODE ALPAS TSPES*/ |
5eb3291f | 794 | dm_writew(DM1105_TSCTR, 0xc10a); |
a611d0ca IL |
795 | |
796 | /* map DMA and set address */ | |
34d2f9bf IL |
797 | dm1105_dma_map(dev); |
798 | dm1105_set_dma_addr(dev); | |
a611d0ca | 799 | /* big buffer */ |
5eb3291f IL |
800 | dm_writel(DM1105_RLEN, 5 * DM1105_DMA_BYTES); |
801 | dm_writeb(DM1105_INTCNT, 47); | |
a611d0ca IL |
802 | |
803 | /* IR NEC mode enable */ | |
5eb3291f IL |
804 | dm_writeb(DM1105_IRCTR, (DM1105_IR_EN | DM1105_SYS_CHK)); |
805 | dm_writeb(DM1105_IRMODE, 0); | |
806 | dm_writew(DM1105_SYSTEMCODE, 0); | |
a611d0ca IL |
807 | |
808 | return 0; | |
809 | } | |
810 | ||
34d2f9bf | 811 | static void dm1105_hw_exit(struct dm1105_dev *dev) |
a611d0ca | 812 | { |
34d2f9bf | 813 | dm1105_disable_irqs(dev); |
a611d0ca IL |
814 | |
815 | /* IR disable */ | |
5eb3291f IL |
816 | dm_writeb(DM1105_IRCTR, 0); |
817 | dm_writeb(DM1105_INTMAK, INTMAK_NONEMASK); | |
a611d0ca | 818 | |
34d2f9bf | 819 | dm1105_dma_unmap(dev); |
a611d0ca | 820 | } |
e4aab64c | 821 | |
d4305c68 IL |
822 | static struct stv0299_config sharp_z0194a_config = { |
823 | .demod_address = 0x68, | |
824 | .inittab = sharp_z0194a_inittab, | |
825 | .mclk = 88000000UL, | |
826 | .invert = 1, | |
827 | .skip_reinit = 0, | |
828 | .lock_output = STV0299_LOCKOUTPUT_1, | |
829 | .volt13_op0_op1 = STV0299_VOLT13_OP1, | |
830 | .min_delay_ms = 100, | |
831 | .set_symbol_rate = sharp_z0194a_set_symbol_rate, | |
832 | }; | |
833 | ||
a611d0ca IL |
834 | static struct stv0288_config earda_config = { |
835 | .demod_address = 0x68, | |
836 | .min_delay_ms = 100, | |
837 | }; | |
838 | ||
839 | static struct si21xx_config serit_config = { | |
840 | .demod_address = 0x68, | |
841 | .min_delay_ms = 100, | |
842 | ||
843 | }; | |
844 | ||
845 | static struct cx24116_config serit_sp2633_config = { | |
846 | .demod_address = 0x55, | |
847 | }; | |
a611d0ca | 848 | |
b4a0e816 IL |
849 | static struct ds3000_config dvbworld_ds3000_config = { |
850 | .demod_address = 0x68, | |
851 | }; | |
852 | ||
73f0af44 KD |
853 | static struct ts2020_config dvbworld_ts2020_config = { |
854 | .tuner_address = 0x60, | |
b858c331 | 855 | .clk_out_div = 1, |
73f0af44 KD |
856 | }; |
857 | ||
4c62e976 | 858 | static int frontend_init(struct dm1105_dev *dev) |
a611d0ca IL |
859 | { |
860 | int ret; | |
861 | ||
34d2f9bf | 862 | switch (dev->boardnr) { |
0017505d IL |
863 | case DM1105_BOARD_UNBRANDED_I2C_ON_GPIO: |
864 | dm1105_gpio_enable(dev, GPIO15, 1); | |
865 | dm1105_gpio_clear(dev, GPIO15); | |
866 | msleep(100); | |
867 | dm1105_gpio_set(dev, GPIO15); | |
868 | msleep(200); | |
869 | dev->fe = dvb_attach( | |
870 | stv0299_attach, &sharp_z0194a_config, | |
871 | &dev->i2c_bb_adap); | |
872 | if (dev->fe) { | |
873 | dev->fe->ops.set_voltage = dm1105_set_voltage; | |
874 | dvb_attach(dvb_pll_attach, dev->fe, 0x60, | |
875 | &dev->i2c_bb_adap, DVB_PLL_OPERA1); | |
876 | break; | |
877 | } | |
878 | ||
879 | dev->fe = dvb_attach( | |
880 | stv0288_attach, &earda_config, | |
881 | &dev->i2c_bb_adap); | |
882 | if (dev->fe) { | |
883 | dev->fe->ops.set_voltage = dm1105_set_voltage; | |
884 | dvb_attach(stb6000_attach, dev->fe, 0x61, | |
885 | &dev->i2c_bb_adap); | |
886 | break; | |
887 | } | |
888 | ||
889 | dev->fe = dvb_attach( | |
890 | si21xx_attach, &serit_config, | |
891 | &dev->i2c_bb_adap); | |
892 | if (dev->fe) | |
893 | dev->fe->ops.set_voltage = dm1105_set_voltage; | |
894 | break; | |
d8300df9 | 895 | case DM1105_BOARD_DVBWORLD_2004: |
34d2f9bf | 896 | dev->fe = dvb_attach( |
519a4bdc | 897 | cx24116_attach, &serit_sp2633_config, |
34d2f9bf IL |
898 | &dev->i2c_adap); |
899 | if (dev->fe) { | |
900 | dev->fe->ops.set_voltage = dm1105_set_voltage; | |
b4a0e816 IL |
901 | break; |
902 | } | |
903 | ||
34d2f9bf | 904 | dev->fe = dvb_attach( |
b4a0e816 | 905 | ds3000_attach, &dvbworld_ds3000_config, |
34d2f9bf | 906 | &dev->i2c_adap); |
73f0af44 KD |
907 | if (dev->fe) { |
908 | dvb_attach(ts2020_attach, dev->fe, | |
909 | &dvbworld_ts2020_config, &dev->i2c_adap); | |
34d2f9bf | 910 | dev->fe->ops.set_voltage = dm1105_set_voltage; |
73f0af44 | 911 | } |
a611d0ca | 912 | |
519a4bdc | 913 | break; |
d8300df9 IL |
914 | case DM1105_BOARD_DVBWORLD_2002: |
915 | case DM1105_BOARD_AXESS_DM05: | |
519a4bdc | 916 | default: |
34d2f9bf | 917 | dev->fe = dvb_attach( |
519a4bdc | 918 | stv0299_attach, &sharp_z0194a_config, |
34d2f9bf IL |
919 | &dev->i2c_adap); |
920 | if (dev->fe) { | |
921 | dev->fe->ops.set_voltage = dm1105_set_voltage; | |
922 | dvb_attach(dvb_pll_attach, dev->fe, 0x60, | |
923 | &dev->i2c_adap, DVB_PLL_OPERA1); | |
519a4bdc | 924 | break; |
a611d0ca | 925 | } |
e4aab64c | 926 | |
34d2f9bf | 927 | dev->fe = dvb_attach( |
519a4bdc | 928 | stv0288_attach, &earda_config, |
34d2f9bf IL |
929 | &dev->i2c_adap); |
930 | if (dev->fe) { | |
931 | dev->fe->ops.set_voltage = dm1105_set_voltage; | |
932 | dvb_attach(stb6000_attach, dev->fe, 0x61, | |
933 | &dev->i2c_adap); | |
519a4bdc | 934 | break; |
a611d0ca | 935 | } |
e4aab64c | 936 | |
34d2f9bf | 937 | dev->fe = dvb_attach( |
519a4bdc | 938 | si21xx_attach, &serit_config, |
34d2f9bf IL |
939 | &dev->i2c_adap); |
940 | if (dev->fe) | |
941 | dev->fe->ops.set_voltage = dm1105_set_voltage; | |
519a4bdc | 942 | |
a611d0ca IL |
943 | } |
944 | ||
34d2f9bf IL |
945 | if (!dev->fe) { |
946 | dev_err(&dev->pdev->dev, "could not attach frontend\n"); | |
a611d0ca IL |
947 | return -ENODEV; |
948 | } | |
949 | ||
34d2f9bf | 950 | ret = dvb_register_frontend(&dev->dvb_adapter, dev->fe); |
a611d0ca | 951 | if (ret < 0) { |
34d2f9bf IL |
952 | if (dev->fe->ops.release) |
953 | dev->fe->ops.release(dev->fe); | |
954 | dev->fe = NULL; | |
a611d0ca IL |
955 | return ret; |
956 | } | |
957 | ||
958 | return 0; | |
959 | } | |
960 | ||
4c62e976 | 961 | static void dm1105_read_mac(struct dm1105_dev *dev, u8 *mac) |
a611d0ca IL |
962 | { |
963 | static u8 command[1] = { 0x28 }; | |
964 | ||
965 | struct i2c_msg msg[] = { | |
519a4bdc IL |
966 | { |
967 | .addr = IIC_24C01_addr >> 1, | |
968 | .flags = 0, | |
969 | .buf = command, | |
970 | .len = 1 | |
971 | }, { | |
972 | .addr = IIC_24C01_addr >> 1, | |
973 | .flags = I2C_M_RD, | |
974 | .buf = mac, | |
975 | .len = 6 | |
976 | }, | |
a611d0ca IL |
977 | }; |
978 | ||
34d2f9bf IL |
979 | dm1105_i2c_xfer(&dev->i2c_adap, msg , 2); |
980 | dev_info(&dev->pdev->dev, "MAC %pM\n", mac); | |
a611d0ca IL |
981 | } |
982 | ||
4c62e976 | 983 | static int dm1105_probe(struct pci_dev *pdev, |
a611d0ca IL |
984 | const struct pci_device_id *ent) |
985 | { | |
34d2f9bf | 986 | struct dm1105_dev *dev; |
a611d0ca IL |
987 | struct dvb_adapter *dvb_adapter; |
988 | struct dvb_demux *dvbdemux; | |
989 | struct dmx_demux *dmx; | |
990 | int ret = -ENOMEM; | |
d8300df9 | 991 | int i; |
a611d0ca | 992 | |
34d2f9bf IL |
993 | dev = kzalloc(sizeof(struct dm1105_dev), GFP_KERNEL); |
994 | if (!dev) | |
d1498ffc | 995 | return -ENOMEM; |
a611d0ca | 996 | |
d8300df9 | 997 | /* board config */ |
34d2f9bf IL |
998 | dev->nr = dm1105_devcount; |
999 | dev->boardnr = UNSET; | |
1000 | if (card[dev->nr] < ARRAY_SIZE(dm1105_boards)) | |
1001 | dev->boardnr = card[dev->nr]; | |
1002 | for (i = 0; UNSET == dev->boardnr && | |
d8300df9 IL |
1003 | i < ARRAY_SIZE(dm1105_subids); i++) |
1004 | if (pdev->subsystem_vendor == | |
1005 | dm1105_subids[i].subvendor && | |
1006 | pdev->subsystem_device == | |
1007 | dm1105_subids[i].subdevice) | |
34d2f9bf | 1008 | dev->boardnr = dm1105_subids[i].card; |
d8300df9 | 1009 | |
34d2f9bf IL |
1010 | if (UNSET == dev->boardnr) { |
1011 | dev->boardnr = DM1105_BOARD_UNKNOWN; | |
d8300df9 IL |
1012 | dm1105_card_list(pdev); |
1013 | } | |
1014 | ||
1015 | dm1105_devcount++; | |
34d2f9bf IL |
1016 | dev->pdev = pdev; |
1017 | dev->buffer_size = 5 * DM1105_DMA_BYTES; | |
1018 | dev->PacketErrorCount = 0; | |
1019 | dev->dmarst = 0; | |
a611d0ca IL |
1020 | |
1021 | ret = pci_enable_device(pdev); | |
1022 | if (ret < 0) | |
1023 | goto err_kfree; | |
1024 | ||
284901a9 | 1025 | ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); |
a611d0ca IL |
1026 | if (ret < 0) |
1027 | goto err_pci_disable_device; | |
1028 | ||
1029 | pci_set_master(pdev); | |
1030 | ||
1031 | ret = pci_request_regions(pdev, DRIVER_NAME); | |
1032 | if (ret < 0) | |
1033 | goto err_pci_disable_device; | |
1034 | ||
34d2f9bf IL |
1035 | dev->io_mem = pci_iomap(pdev, 0, pci_resource_len(pdev, 0)); |
1036 | if (!dev->io_mem) { | |
a611d0ca IL |
1037 | ret = -EIO; |
1038 | goto err_pci_release_regions; | |
1039 | } | |
1040 | ||
34d2f9bf IL |
1041 | spin_lock_init(&dev->lock); |
1042 | pci_set_drvdata(pdev, dev); | |
a611d0ca | 1043 | |
34d2f9bf | 1044 | ret = dm1105_hw_init(dev); |
a611d0ca | 1045 | if (ret < 0) |
d1498ffc | 1046 | goto err_pci_iounmap; |
a611d0ca IL |
1047 | |
1048 | /* i2c */ | |
34d2f9bf IL |
1049 | i2c_set_adapdata(&dev->i2c_adap, dev); |
1050 | strcpy(dev->i2c_adap.name, DRIVER_NAME); | |
1051 | dev->i2c_adap.owner = THIS_MODULE; | |
34d2f9bf IL |
1052 | dev->i2c_adap.dev.parent = &pdev->dev; |
1053 | dev->i2c_adap.algo = &dm1105_algo; | |
1054 | dev->i2c_adap.algo_data = dev; | |
1055 | ret = i2c_add_adapter(&dev->i2c_adap); | |
a611d0ca IL |
1056 | |
1057 | if (ret < 0) | |
34d2f9bf | 1058 | goto err_dm1105_hw_exit; |
a611d0ca | 1059 | |
0017505d IL |
1060 | i2c_set_adapdata(&dev->i2c_bb_adap, dev); |
1061 | strcpy(dev->i2c_bb_adap.name, DM1105_I2C_GPIO_NAME); | |
1062 | dev->i2c_bb_adap.owner = THIS_MODULE; | |
1063 | dev->i2c_bb_adap.dev.parent = &pdev->dev; | |
1064 | dev->i2c_bb_adap.algo_data = &dev->i2c_bit; | |
1065 | dev->i2c_bit.data = dev; | |
1066 | dev->i2c_bit.setsda = dm1105_setsda; | |
1067 | dev->i2c_bit.setscl = dm1105_setscl; | |
1068 | dev->i2c_bit.getsda = dm1105_getsda; | |
1069 | dev->i2c_bit.getscl = dm1105_getscl; | |
1070 | dev->i2c_bit.udelay = 10; | |
1071 | dev->i2c_bit.timeout = 10; | |
1072 | ||
1073 | /* Raise SCL and SDA */ | |
1074 | dm1105_setsda(dev, 1); | |
1075 | dm1105_setscl(dev, 1); | |
1076 | ||
1077 | ret = i2c_bit_add_bus(&dev->i2c_bb_adap); | |
1078 | if (ret < 0) | |
1079 | goto err_i2c_del_adapter; | |
1080 | ||
a611d0ca | 1081 | /* dvb */ |
34d2f9bf | 1082 | ret = dvb_register_adapter(&dev->dvb_adapter, DRIVER_NAME, |
a611d0ca IL |
1083 | THIS_MODULE, &pdev->dev, adapter_nr); |
1084 | if (ret < 0) | |
0017505d | 1085 | goto err_i2c_del_adapters; |
a611d0ca | 1086 | |
34d2f9bf | 1087 | dvb_adapter = &dev->dvb_adapter; |
a611d0ca | 1088 | |
34d2f9bf | 1089 | dm1105_read_mac(dev, dvb_adapter->proposed_mac); |
a611d0ca | 1090 | |
34d2f9bf | 1091 | dvbdemux = &dev->demux; |
a611d0ca IL |
1092 | dvbdemux->filternum = 256; |
1093 | dvbdemux->feednum = 256; | |
34d2f9bf IL |
1094 | dvbdemux->start_feed = dm1105_start_feed; |
1095 | dvbdemux->stop_feed = dm1105_stop_feed; | |
a611d0ca IL |
1096 | dvbdemux->dmx.capabilities = (DMX_TS_FILTERING | |
1097 | DMX_SECTION_FILTERING | DMX_MEMORY_BASED_FILTERING); | |
1098 | ret = dvb_dmx_init(dvbdemux); | |
1099 | if (ret < 0) | |
1100 | goto err_dvb_unregister_adapter; | |
1101 | ||
1102 | dmx = &dvbdemux->dmx; | |
34d2f9bf IL |
1103 | dev->dmxdev.filternum = 256; |
1104 | dev->dmxdev.demux = dmx; | |
1105 | dev->dmxdev.capabilities = 0; | |
a611d0ca | 1106 | |
34d2f9bf | 1107 | ret = dvb_dmxdev_init(&dev->dmxdev, dvb_adapter); |
a611d0ca IL |
1108 | if (ret < 0) |
1109 | goto err_dvb_dmx_release; | |
1110 | ||
34d2f9bf | 1111 | dev->hw_frontend.source = DMX_FRONTEND_0; |
a611d0ca | 1112 | |
34d2f9bf | 1113 | ret = dmx->add_frontend(dmx, &dev->hw_frontend); |
a611d0ca IL |
1114 | if (ret < 0) |
1115 | goto err_dvb_dmxdev_release; | |
1116 | ||
34d2f9bf | 1117 | dev->mem_frontend.source = DMX_MEMORY_FE; |
a611d0ca | 1118 | |
34d2f9bf | 1119 | ret = dmx->add_frontend(dmx, &dev->mem_frontend); |
a611d0ca IL |
1120 | if (ret < 0) |
1121 | goto err_remove_hw_frontend; | |
1122 | ||
34d2f9bf | 1123 | ret = dmx->connect_frontend(dmx, &dev->hw_frontend); |
a611d0ca IL |
1124 | if (ret < 0) |
1125 | goto err_remove_mem_frontend; | |
1126 | ||
5584c641 JN |
1127 | ret = dvb_net_init(dvb_adapter, &dev->dvbnet, dmx); |
1128 | if (ret < 0) | |
1129 | goto err_disconnect_frontend; | |
1130 | ||
34d2f9bf | 1131 | ret = frontend_init(dev); |
a611d0ca | 1132 | if (ret < 0) |
e9966341 | 1133 | goto err_dvb_net; |
a611d0ca | 1134 | |
34d2f9bf | 1135 | dm1105_ir_init(dev); |
d1498ffc | 1136 | |
34d2f9bf IL |
1137 | INIT_WORK(&dev->work, dm1105_dmx_buffer); |
1138 | sprintf(dev->wqn, "%s/%d", dvb_adapter->name, dvb_adapter->num); | |
1139 | dev->wq = create_singlethread_workqueue(dev->wqn); | |
95d08126 PST |
1140 | if (!dev->wq) { |
1141 | ret = -ENOMEM; | |
519a4bdc | 1142 | goto err_dvb_net; |
95d08126 | 1143 | } |
d1498ffc | 1144 | |
34d2f9bf IL |
1145 | ret = request_irq(pdev->irq, dm1105_irq, IRQF_SHARED, |
1146 | DRIVER_NAME, dev); | |
d1498ffc | 1147 | if (ret < 0) |
519a4bdc | 1148 | goto err_workqueue; |
d1498ffc IL |
1149 | |
1150 | return 0; | |
a611d0ca | 1151 | |
519a4bdc | 1152 | err_workqueue: |
34d2f9bf | 1153 | destroy_workqueue(dev->wq); |
519a4bdc | 1154 | err_dvb_net: |
34d2f9bf | 1155 | dvb_net_release(&dev->dvbnet); |
a611d0ca IL |
1156 | err_disconnect_frontend: |
1157 | dmx->disconnect_frontend(dmx); | |
1158 | err_remove_mem_frontend: | |
34d2f9bf | 1159 | dmx->remove_frontend(dmx, &dev->mem_frontend); |
a611d0ca | 1160 | err_remove_hw_frontend: |
34d2f9bf | 1161 | dmx->remove_frontend(dmx, &dev->hw_frontend); |
a611d0ca | 1162 | err_dvb_dmxdev_release: |
34d2f9bf | 1163 | dvb_dmxdev_release(&dev->dmxdev); |
a611d0ca IL |
1164 | err_dvb_dmx_release: |
1165 | dvb_dmx_release(dvbdemux); | |
1166 | err_dvb_unregister_adapter: | |
1167 | dvb_unregister_adapter(dvb_adapter); | |
0017505d IL |
1168 | err_i2c_del_adapters: |
1169 | i2c_del_adapter(&dev->i2c_bb_adap); | |
a611d0ca | 1170 | err_i2c_del_adapter: |
34d2f9bf IL |
1171 | i2c_del_adapter(&dev->i2c_adap); |
1172 | err_dm1105_hw_exit: | |
1173 | dm1105_hw_exit(dev); | |
a611d0ca | 1174 | err_pci_iounmap: |
34d2f9bf | 1175 | pci_iounmap(pdev, dev->io_mem); |
a611d0ca IL |
1176 | err_pci_release_regions: |
1177 | pci_release_regions(pdev); | |
1178 | err_pci_disable_device: | |
1179 | pci_disable_device(pdev); | |
1180 | err_kfree: | |
1181 | pci_set_drvdata(pdev, NULL); | |
34d2f9bf | 1182 | kfree(dev); |
d1498ffc | 1183 | return ret; |
a611d0ca IL |
1184 | } |
1185 | ||
4c62e976 | 1186 | static void dm1105_remove(struct pci_dev *pdev) |
a611d0ca | 1187 | { |
34d2f9bf IL |
1188 | struct dm1105_dev *dev = pci_get_drvdata(pdev); |
1189 | struct dvb_adapter *dvb_adapter = &dev->dvb_adapter; | |
1190 | struct dvb_demux *dvbdemux = &dev->demux; | |
a611d0ca IL |
1191 | struct dmx_demux *dmx = &dvbdemux->dmx; |
1192 | ||
34d2f9bf | 1193 | dm1105_ir_exit(dev); |
a611d0ca | 1194 | dmx->close(dmx); |
34d2f9bf IL |
1195 | dvb_net_release(&dev->dvbnet); |
1196 | if (dev->fe) | |
1197 | dvb_unregister_frontend(dev->fe); | |
a611d0ca IL |
1198 | |
1199 | dmx->disconnect_frontend(dmx); | |
34d2f9bf IL |
1200 | dmx->remove_frontend(dmx, &dev->mem_frontend); |
1201 | dmx->remove_frontend(dmx, &dev->hw_frontend); | |
1202 | dvb_dmxdev_release(&dev->dmxdev); | |
a611d0ca IL |
1203 | dvb_dmx_release(dvbdemux); |
1204 | dvb_unregister_adapter(dvb_adapter); | |
34d2f9bf IL |
1205 | if (&dev->i2c_adap) |
1206 | i2c_del_adapter(&dev->i2c_adap); | |
a611d0ca | 1207 | |
34d2f9bf | 1208 | dm1105_hw_exit(dev); |
a611d0ca | 1209 | synchronize_irq(pdev->irq); |
34d2f9bf IL |
1210 | free_irq(pdev->irq, dev); |
1211 | pci_iounmap(pdev, dev->io_mem); | |
a611d0ca IL |
1212 | pci_release_regions(pdev); |
1213 | pci_disable_device(pdev); | |
1214 | pci_set_drvdata(pdev, NULL); | |
d8300df9 | 1215 | dm1105_devcount--; |
34d2f9bf | 1216 | kfree(dev); |
a611d0ca IL |
1217 | } |
1218 | ||
4c62e976 | 1219 | static struct pci_device_id dm1105_id_table[] = { |
a611d0ca IL |
1220 | { |
1221 | .vendor = PCI_VENDOR_ID_TRIGEM, | |
1222 | .device = PCI_DEVICE_ID_DM1105, | |
1223 | .subvendor = PCI_ANY_ID, | |
d8300df9 | 1224 | .subdevice = PCI_ANY_ID, |
519a4bdc IL |
1225 | }, { |
1226 | .vendor = PCI_VENDOR_ID_AXESS, | |
1227 | .device = PCI_DEVICE_ID_DM05, | |
d8300df9 IL |
1228 | .subvendor = PCI_ANY_ID, |
1229 | .subdevice = PCI_ANY_ID, | |
a611d0ca IL |
1230 | }, { |
1231 | /* empty */ | |
1232 | }, | |
1233 | }; | |
1234 | ||
1235 | MODULE_DEVICE_TABLE(pci, dm1105_id_table); | |
1236 | ||
1237 | static struct pci_driver dm1105_driver = { | |
1238 | .name = DRIVER_NAME, | |
1239 | .id_table = dm1105_id_table, | |
1240 | .probe = dm1105_probe, | |
4c62e976 | 1241 | .remove = dm1105_remove, |
a611d0ca IL |
1242 | }; |
1243 | ||
548006ce | 1244 | module_pci_driver(dm1105_driver); |
a611d0ca IL |
1245 | |
1246 | MODULE_AUTHOR("Igor M. Liplianin <liplianin@me.by>"); | |
1247 | MODULE_DESCRIPTION("SDMC DM1105 DVB driver"); | |
1248 | MODULE_LICENSE("GPL"); |