]>
Commit | Line | Data |
---|---|---|
717f4a5f MM |
1 | /*************************************************************************** |
2 | * Copyright (C) 2006-2010 by Marin Mitov * | |
3 | * mitov@issp.bas.bg * | |
4 | * * | |
5 | * This program is free software; you can redistribute it and/or modify * | |
6 | * it under the terms of the GNU General Public License as published by * | |
7 | * the Free Software Foundation; either version 2 of the License, or * | |
8 | * (at your option) any later version. * | |
9 | * * | |
10 | * This program is distributed in the hope that it will be useful, * | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of * | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * | |
13 | * GNU General Public License for more details. * | |
14 | * * | |
717f4a5f MM |
15 | ***************************************************************************/ |
16 | ||
99c97852 | 17 | #include <linux/module.h> |
d42bffb8 | 18 | #include <linux/stringify.h> |
7ec21181 | 19 | #include <linux/delay.h> |
d42bffb8 | 20 | #include <linux/kthread.h> |
dac95cb8 | 21 | #include <linux/slab.h> |
a57941c2 MM |
22 | #include <media/v4l2-dev.h> |
23 | #include <media/v4l2-ioctl.h> | |
0dcb953a | 24 | #include <media/v4l2-common.h> |
8ded351a | 25 | #include <media/videobuf2-dma-contig.h> |
d42bffb8 | 26 | |
cc11b140 | 27 | #include "dt3155.h" |
d42bffb8 | 28 | |
d42bffb8 MM |
29 | #define DT3155_DEVICE_ID 0x1223 |
30 | ||
d42bffb8 MM |
31 | /** |
32 | * read_i2c_reg - reads an internal i2c register | |
33 | * | |
34 | * @addr: dt3155 mmio base address | |
35 | * @index: index (internal address) of register to read | |
36 | * @data: pointer to byte the read data will be placed in | |
37 | * | |
38 | * returns: zero on success or error code | |
39 | * | |
40 | * This function starts reading the specified (by index) register | |
41 | * and busy waits for the process to finish. The result is placed | |
42 | * in a byte pointed by data. | |
43 | */ | |
6a11087b | 44 | static int read_i2c_reg(void __iomem *addr, u8 index, u8 *data) |
d42bffb8 MM |
45 | { |
46 | u32 tmp = index; | |
47 | ||
6a11087b | 48 | iowrite32((tmp << 17) | IIC_READ, addr + IIC_CSR2); |
d42bffb8 MM |
49 | mmiowb(); |
50 | udelay(45); /* wait at least 43 usec for NEW_CYCLE to clear */ | |
c94a2e47 HS |
51 | if (ioread32(addr + IIC_CSR2) & NEW_CYCLE) |
52 | return -EIO; /* error: NEW_CYCLE not cleared */ | |
d42bffb8 MM |
53 | tmp = ioread32(addr + IIC_CSR1); |
54 | if (tmp & DIRECT_ABORT) { | |
d42bffb8 MM |
55 | /* reset DIRECT_ABORT bit */ |
56 | iowrite32(DIRECT_ABORT, addr + IIC_CSR1); | |
c94a2e47 | 57 | return -EIO; /* error: DIRECT_ABORT set */ |
d42bffb8 | 58 | } |
6a11087b | 59 | *data = tmp >> 24; |
d42bffb8 MM |
60 | return 0; |
61 | } | |
62 | ||
63 | /** | |
64 | * write_i2c_reg - writes to an internal i2c register | |
65 | * | |
66 | * @addr: dt3155 mmio base address | |
67 | * @index: index (internal address) of register to read | |
68 | * @data: data to be written | |
69 | * | |
70 | * returns: zero on success or error code | |
71 | * | |
6a11087b | 72 | * This function starts writing the specified (by index) register |
d42bffb8 MM |
73 | * and busy waits for the process to finish. |
74 | */ | |
6a11087b | 75 | static int write_i2c_reg(void __iomem *addr, u8 index, u8 data) |
d42bffb8 MM |
76 | { |
77 | u32 tmp = index; | |
78 | ||
6a11087b | 79 | iowrite32((tmp << 17) | IIC_WRITE | data, addr + IIC_CSR2); |
d42bffb8 MM |
80 | mmiowb(); |
81 | udelay(65); /* wait at least 63 usec for NEW_CYCLE to clear */ | |
c94a2e47 HS |
82 | if (ioread32(addr + IIC_CSR2) & NEW_CYCLE) |
83 | return -EIO; /* error: NEW_CYCLE not cleared */ | |
d42bffb8 | 84 | if (ioread32(addr + IIC_CSR1) & DIRECT_ABORT) { |
d42bffb8 MM |
85 | /* reset DIRECT_ABORT bit */ |
86 | iowrite32(DIRECT_ABORT, addr + IIC_CSR1); | |
c94a2e47 | 87 | return -EIO; /* error: DIRECT_ABORT set */ |
d42bffb8 MM |
88 | } |
89 | return 0; | |
90 | } | |
91 | ||
92 | /** | |
93 | * write_i2c_reg_nowait - writes to an internal i2c register | |
94 | * | |
95 | * @addr: dt3155 mmio base address | |
96 | * @index: index (internal address) of register to read | |
97 | * @data: data to be written | |
98 | * | |
6a11087b | 99 | * This function starts writing the specified (by index) register |
d42bffb8 MM |
100 | * and then returns. |
101 | */ | |
2342df0e | 102 | static void write_i2c_reg_nowait(void __iomem *addr, u8 index, u8 data) |
d42bffb8 MM |
103 | { |
104 | u32 tmp = index; | |
105 | ||
6a11087b | 106 | iowrite32((tmp << 17) | IIC_WRITE | data, addr + IIC_CSR2); |
d42bffb8 MM |
107 | mmiowb(); |
108 | } | |
109 | ||
110 | /** | |
111 | * wait_i2c_reg - waits the read/write to finish | |
112 | * | |
113 | * @addr: dt3155 mmio base address | |
114 | * | |
115 | * returns: zero on success or error code | |
116 | * | |
6a11087b | 117 | * This function waits reading/writing to finish. |
d42bffb8 | 118 | */ |
2342df0e | 119 | static int wait_i2c_reg(void __iomem *addr) |
d42bffb8 MM |
120 | { |
121 | if (ioread32(addr + IIC_CSR2) & NEW_CYCLE) | |
122 | udelay(65); /* wait at least 63 usec for NEW_CYCLE to clear */ | |
c94a2e47 HS |
123 | if (ioread32(addr + IIC_CSR2) & NEW_CYCLE) |
124 | return -EIO; /* error: NEW_CYCLE not cleared */ | |
d42bffb8 | 125 | if (ioread32(addr + IIC_CSR1) & DIRECT_ABORT) { |
d42bffb8 MM |
126 | /* reset DIRECT_ABORT bit */ |
127 | iowrite32(DIRECT_ABORT, addr + IIC_CSR1); | |
c94a2e47 | 128 | return -EIO; /* error: DIRECT_ABORT set */ |
d42bffb8 MM |
129 | } |
130 | return 0; | |
131 | } | |
132 | ||
d42bffb8 | 133 | static int |
9556be12 HV |
134 | dt3155_queue_setup(struct vb2_queue *vq, const struct v4l2_format *fmt, |
135 | unsigned int *nbuffers, unsigned int *num_planes, | |
527f18be DC |
136 | unsigned int sizes[], void *alloc_ctxs[]) |
137 | ||
8ded351a | 138 | { |
9556be12 | 139 | struct dt3155_priv *pd = vb2_get_drv_priv(vq); |
5c9ede44 | 140 | unsigned size = pd->width * pd->height; |
8ded351a | 141 | |
9556be12 HV |
142 | if (vq->num_buffers + *nbuffers < 2) |
143 | *nbuffers = 2 - vq->num_buffers; | |
144 | if (fmt && fmt->fmt.pix.sizeimage < size) | |
145 | return -EINVAL; | |
8ded351a | 146 | *num_planes = 1; |
9556be12 HV |
147 | sizes[0] = fmt ? fmt->fmt.pix.sizeimage : size; |
148 | alloc_ctxs[0] = pd->alloc_ctx; | |
8ded351a MM |
149 | return 0; |
150 | } | |
151 | ||
6a11087b | 152 | static int dt3155_buf_prepare(struct vb2_buffer *vb) |
d42bffb8 | 153 | { |
5c9ede44 HV |
154 | struct dt3155_priv *pd = vb2_get_drv_priv(vb->vb2_queue); |
155 | ||
156 | vb2_set_plane_payload(vb, 0, pd->width * pd->height); | |
d42bffb8 MM |
157 | return 0; |
158 | } | |
159 | ||
9db8baff HV |
160 | static int dt3155_start_streaming(struct vb2_queue *q, unsigned count) |
161 | { | |
162 | struct dt3155_priv *pd = vb2_get_drv_priv(q); | |
2d700715 | 163 | struct vb2_buffer *vb = &pd->curr_buf->vb2_buf; |
9db8baff HV |
164 | dma_addr_t dma_addr; |
165 | ||
166 | pd->sequence = 0; | |
167 | dma_addr = vb2_dma_contig_plane_dma_addr(vb, 0); | |
168 | iowrite32(dma_addr, pd->regs + EVEN_DMA_START); | |
5c9ede44 HV |
169 | iowrite32(dma_addr + pd->width, pd->regs + ODD_DMA_START); |
170 | iowrite32(pd->width, pd->regs + EVEN_DMA_STRIDE); | |
171 | iowrite32(pd->width, pd->regs + ODD_DMA_STRIDE); | |
9db8baff HV |
172 | /* enable interrupts, clear all irq flags */ |
173 | iowrite32(FLD_START_EN | FLD_END_ODD_EN | FLD_START | | |
174 | FLD_END_EVEN | FLD_END_ODD, pd->regs + INT_CSR); | |
175 | iowrite32(FIFO_EN | SRST | FLD_CRPT_ODD | FLD_CRPT_EVEN | | |
176 | FLD_DN_ODD | FLD_DN_EVEN | CAP_CONT_EVEN | CAP_CONT_ODD, | |
177 | pd->regs + CSR1); | |
178 | wait_i2c_reg(pd->regs); | |
179 | write_i2c_reg(pd->regs, CONFIG, pd->config); | |
180 | write_i2c_reg(pd->regs, EVEN_CSR, CSR_ERROR | CSR_DONE); | |
181 | write_i2c_reg(pd->regs, ODD_CSR, CSR_ERROR | CSR_DONE); | |
182 | ||
183 | /* start the board */ | |
184 | write_i2c_reg(pd->regs, CSR2, pd->csr2 | BUSY_EVEN | BUSY_ODD); | |
185 | return 0; | |
186 | } | |
187 | ||
6a11087b | 188 | static void dt3155_stop_streaming(struct vb2_queue *q) |
d42bffb8 | 189 | { |
8ded351a MM |
190 | struct dt3155_priv *pd = vb2_get_drv_priv(q); |
191 | struct vb2_buffer *vb; | |
192 | ||
193 | spin_lock_irq(&pd->lock); | |
9db8baff HV |
194 | /* stop the board */ |
195 | write_i2c_reg_nowait(pd->regs, CSR2, pd->csr2); | |
196 | iowrite32(FIFO_EN | SRST | FLD_CRPT_ODD | FLD_CRPT_EVEN | | |
197 | FLD_DN_ODD | FLD_DN_EVEN, pd->regs + CSR1); | |
198 | /* disable interrupts, clear all irq flags */ | |
199 | iowrite32(FLD_START | FLD_END_EVEN | FLD_END_ODD, pd->regs + INT_CSR); | |
200 | spin_unlock_irq(&pd->lock); | |
201 | ||
202 | /* | |
203 | * It is not clear whether the DMA stops at once or whether it | |
204 | * will finish the current frame or field first. To be on the | |
205 | * safe side we wait a bit. | |
206 | */ | |
207 | msleep(45); | |
208 | ||
209 | spin_lock_irq(&pd->lock); | |
210 | if (pd->curr_buf) { | |
2d700715 | 211 | vb2_buffer_done(&pd->curr_buf->vb2_buf, VB2_BUF_STATE_ERROR); |
9db8baff HV |
212 | pd->curr_buf = NULL; |
213 | } | |
214 | ||
8ded351a MM |
215 | while (!list_empty(&pd->dmaq)) { |
216 | vb = list_first_entry(&pd->dmaq, typeof(*vb), done_entry); | |
217 | list_del(&vb->done_entry); | |
218 | vb2_buffer_done(vb, VB2_BUF_STATE_ERROR); | |
219 | } | |
220 | spin_unlock_irq(&pd->lock); | |
d42bffb8 MM |
221 | } |
222 | ||
6a11087b | 223 | static void dt3155_buf_queue(struct vb2_buffer *vb) |
d42bffb8 | 224 | { |
2d700715 | 225 | struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); |
8ded351a MM |
226 | struct dt3155_priv *pd = vb2_get_drv_priv(vb->vb2_queue); |
227 | ||
9db8baff | 228 | /* pd->vidq.streaming = 1 when dt3155_buf_queue() is invoked */ |
8ded351a MM |
229 | spin_lock_irq(&pd->lock); |
230 | if (pd->curr_buf) | |
231 | list_add_tail(&vb->done_entry, &pd->dmaq); | |
9db8baff | 232 | else |
2d700715 | 233 | pd->curr_buf = vbuf; |
8ded351a | 234 | spin_unlock_irq(&pd->lock); |
d42bffb8 MM |
235 | } |
236 | ||
5ae7437e | 237 | static const struct vb2_ops q_ops = { |
8ded351a | 238 | .queue_setup = dt3155_queue_setup, |
9556be12 HV |
239 | .wait_prepare = vb2_ops_wait_prepare, |
240 | .wait_finish = vb2_ops_wait_finish, | |
d42bffb8 | 241 | .buf_prepare = dt3155_buf_prepare, |
9db8baff | 242 | .start_streaming = dt3155_start_streaming, |
8ded351a | 243 | .stop_streaming = dt3155_stop_streaming, |
d42bffb8 | 244 | .buf_queue = dt3155_buf_queue, |
d42bffb8 MM |
245 | }; |
246 | ||
6a11087b | 247 | static irqreturn_t dt3155_irq_handler_even(int irq, void *dev_id) |
d42bffb8 MM |
248 | { |
249 | struct dt3155_priv *ipd = dev_id; | |
8ded351a | 250 | struct vb2_buffer *ivb; |
d42bffb8 MM |
251 | dma_addr_t dma_addr; |
252 | u32 tmp; | |
253 | ||
254 | tmp = ioread32(ipd->regs + INT_CSR) & (FLD_START | FLD_END_ODD); | |
255 | if (!tmp) | |
256 | return IRQ_NONE; /* not our irq */ | |
257 | if ((tmp & FLD_START) && !(tmp & FLD_END_ODD)) { | |
258 | iowrite32(FLD_START_EN | FLD_END_ODD_EN | FLD_START, | |
259 | ipd->regs + INT_CSR); | |
d42bffb8 MM |
260 | return IRQ_HANDLED; /* start of field irq */ |
261 | } | |
d42bffb8 MM |
262 | tmp = ioread32(ipd->regs + CSR1) & (FLD_CRPT_EVEN | FLD_CRPT_ODD); |
263 | if (tmp) { | |
d42bffb8 MM |
264 | iowrite32(FIFO_EN | SRST | FLD_CRPT_ODD | FLD_CRPT_EVEN | |
265 | FLD_DN_ODD | FLD_DN_EVEN | | |
266 | CAP_CONT_EVEN | CAP_CONT_ODD, | |
267 | ipd->regs + CSR1); | |
268 | mmiowb(); | |
269 | } | |
270 | ||
271 | spin_lock(&ipd->lock); | |
9db8baff | 272 | if (ipd->curr_buf && !list_empty(&ipd->dmaq)) { |
2d700715 JS |
273 | v4l2_get_timestamp(&ipd->curr_buf->timestamp); |
274 | ipd->curr_buf->sequence = ipd->sequence++; | |
275 | ipd->curr_buf->field = V4L2_FIELD_NONE; | |
276 | vb2_buffer_done(&ipd->curr_buf->vb2_buf, VB2_BUF_STATE_DONE); | |
9db8baff HV |
277 | |
278 | ivb = list_first_entry(&ipd->dmaq, typeof(*ivb), done_entry); | |
279 | list_del(&ivb->done_entry); | |
2d700715 | 280 | ipd->curr_buf = to_vb2_v4l2_buffer(ivb); |
9db8baff HV |
281 | dma_addr = vb2_dma_contig_plane_dma_addr(ivb, 0); |
282 | iowrite32(dma_addr, ipd->regs + EVEN_DMA_START); | |
5c9ede44 HV |
283 | iowrite32(dma_addr + ipd->width, ipd->regs + ODD_DMA_START); |
284 | iowrite32(ipd->width, ipd->regs + EVEN_DMA_STRIDE); | |
285 | iowrite32(ipd->width, ipd->regs + ODD_DMA_STRIDE); | |
9db8baff | 286 | mmiowb(); |
8ded351a MM |
287 | } |
288 | ||
d42bffb8 MM |
289 | /* enable interrupts, clear all irq flags */ |
290 | iowrite32(FLD_START_EN | FLD_END_ODD_EN | FLD_START | | |
291 | FLD_END_EVEN | FLD_END_ODD, ipd->regs + INT_CSR); | |
292 | spin_unlock(&ipd->lock); | |
293 | return IRQ_HANDLED; | |
d42bffb8 MM |
294 | } |
295 | ||
d42bffb8 MM |
296 | static const struct v4l2_file_operations dt3155_fops = { |
297 | .owner = THIS_MODULE, | |
9556be12 HV |
298 | .open = v4l2_fh_open, |
299 | .release = vb2_fop_release, | |
300 | .unlocked_ioctl = video_ioctl2, | |
301 | .read = vb2_fop_read, | |
302 | .mmap = vb2_fop_mmap, | |
303 | .poll = vb2_fop_poll | |
d42bffb8 MM |
304 | }; |
305 | ||
90874cd6 MCC |
306 | static int dt3155_querycap(struct file *filp, void *p, |
307 | struct v4l2_capability *cap) | |
d42bffb8 MM |
308 | { |
309 | struct dt3155_priv *pd = video_drvdata(filp); | |
310 | ||
311 | strcpy(cap->driver, DT3155_NAME); | |
312 | strcpy(cap->card, DT3155_NAME " frame grabber"); | |
313 | sprintf(cap->bus_info, "PCI:%s", pci_name(pd->pdev)); | |
57e774cc | 314 | cap->device_caps = V4L2_CAP_VIDEO_CAPTURE | |
a6e95144 | 315 | V4L2_CAP_STREAMING | V4L2_CAP_READWRITE; |
57e774cc | 316 | cap->capabilities = cap->device_caps | V4L2_CAP_DEVICE_CAPS; |
d42bffb8 MM |
317 | return 0; |
318 | } | |
319 | ||
90874cd6 MCC |
320 | static int dt3155_enum_fmt_vid_cap(struct file *filp, |
321 | void *p, struct v4l2_fmtdesc *f) | |
d42bffb8 | 322 | { |
44a38dfb | 323 | if (f->index) |
d42bffb8 | 324 | return -EINVAL; |
44a38dfb HV |
325 | f->pixelformat = V4L2_PIX_FMT_GREY; |
326 | strcpy(f->description, "8-bit Greyscale"); | |
d42bffb8 MM |
327 | return 0; |
328 | } | |
329 | ||
44a38dfb | 330 | static int dt3155_fmt_vid_cap(struct file *filp, void *p, struct v4l2_format *f) |
d42bffb8 | 331 | { |
5c9ede44 HV |
332 | struct dt3155_priv *pd = video_drvdata(filp); |
333 | ||
5c9ede44 HV |
334 | f->fmt.pix.width = pd->width; |
335 | f->fmt.pix.height = pd->height; | |
d42bffb8 MM |
336 | f->fmt.pix.pixelformat = V4L2_PIX_FMT_GREY; |
337 | f->fmt.pix.field = V4L2_FIELD_NONE; | |
338 | f->fmt.pix.bytesperline = f->fmt.pix.width; | |
339 | f->fmt.pix.sizeimage = f->fmt.pix.width * f->fmt.pix.height; | |
44a38dfb | 340 | f->fmt.pix.colorspace = V4L2_COLORSPACE_SMPTE170M; |
d42bffb8 MM |
341 | return 0; |
342 | } | |
343 | ||
6a11087b | 344 | static int dt3155_g_std(struct file *filp, void *p, v4l2_std_id *norm) |
d42bffb8 | 345 | { |
5c9ede44 HV |
346 | struct dt3155_priv *pd = video_drvdata(filp); |
347 | ||
348 | *norm = pd->std; | |
d42bffb8 MM |
349 | return 0; |
350 | } | |
351 | ||
6a11087b | 352 | static int dt3155_s_std(struct file *filp, void *p, v4l2_std_id norm) |
d42bffb8 | 353 | { |
5c9ede44 HV |
354 | struct dt3155_priv *pd = video_drvdata(filp); |
355 | ||
356 | if (pd->std == norm) | |
d42bffb8 | 357 | return 0; |
5c9ede44 HV |
358 | if (vb2_is_busy(&pd->vidq)) |
359 | return -EBUSY; | |
360 | pd->std = norm; | |
361 | if (pd->std & V4L2_STD_525_60) { | |
362 | pd->csr2 = VT_60HZ; | |
363 | pd->width = 640; | |
364 | pd->height = 480; | |
365 | } else { | |
366 | pd->csr2 = VT_50HZ; | |
367 | pd->width = 768; | |
368 | pd->height = 576; | |
369 | } | |
370 | return 0; | |
d42bffb8 MM |
371 | } |
372 | ||
90874cd6 MCC |
373 | static int dt3155_enum_input(struct file *filp, void *p, |
374 | struct v4l2_input *input) | |
d42bffb8 | 375 | { |
c34b7ef5 | 376 | if (input->index > 3) |
d42bffb8 | 377 | return -EINVAL; |
c34b7ef5 | 378 | if (input->index) |
90874cd6 MCC |
379 | snprintf(input->name, sizeof(input->name), "VID%d", |
380 | input->index); | |
c34b7ef5 HV |
381 | else |
382 | strlcpy(input->name, "J2/VID0", sizeof(input->name)); | |
d42bffb8 | 383 | input->type = V4L2_INPUT_TYPE_CAMERA; |
5c9ede44 HV |
384 | input->std = V4L2_STD_ALL; |
385 | input->status = 0; | |
d42bffb8 MM |
386 | return 0; |
387 | } | |
388 | ||
6a11087b | 389 | static int dt3155_g_input(struct file *filp, void *p, unsigned int *i) |
d42bffb8 | 390 | { |
c34b7ef5 HV |
391 | struct dt3155_priv *pd = video_drvdata(filp); |
392 | ||
393 | *i = pd->input; | |
d42bffb8 MM |
394 | return 0; |
395 | } | |
396 | ||
6a11087b | 397 | static int dt3155_s_input(struct file *filp, void *p, unsigned int i) |
d42bffb8 | 398 | { |
c34b7ef5 HV |
399 | struct dt3155_priv *pd = video_drvdata(filp); |
400 | ||
401 | if (i > 3) | |
d42bffb8 | 402 | return -EINVAL; |
c34b7ef5 HV |
403 | pd->input = i; |
404 | write_i2c_reg(pd->regs, AD_ADDR, AD_CMD_REG); | |
405 | write_i2c_reg(pd->regs, AD_CMD, (i << 6) | (i << 4) | SYNC_LVL_3); | |
d42bffb8 MM |
406 | return 0; |
407 | } | |
408 | ||
d42bffb8 | 409 | static const struct v4l2_ioctl_ops dt3155_ioctl_ops = { |
6a11087b HV |
410 | .vidioc_querycap = dt3155_querycap, |
411 | .vidioc_enum_fmt_vid_cap = dt3155_enum_fmt_vid_cap, | |
44a38dfb HV |
412 | .vidioc_try_fmt_vid_cap = dt3155_fmt_vid_cap, |
413 | .vidioc_g_fmt_vid_cap = dt3155_fmt_vid_cap, | |
414 | .vidioc_s_fmt_vid_cap = dt3155_fmt_vid_cap, | |
9556be12 HV |
415 | .vidioc_reqbufs = vb2_ioctl_reqbufs, |
416 | .vidioc_create_bufs = vb2_ioctl_create_bufs, | |
417 | .vidioc_querybuf = vb2_ioctl_querybuf, | |
418 | .vidioc_expbuf = vb2_ioctl_expbuf, | |
419 | .vidioc_qbuf = vb2_ioctl_qbuf, | |
420 | .vidioc_dqbuf = vb2_ioctl_dqbuf, | |
421 | .vidioc_streamon = vb2_ioctl_streamon, | |
422 | .vidioc_streamoff = vb2_ioctl_streamoff, | |
6a11087b HV |
423 | .vidioc_g_std = dt3155_g_std, |
424 | .vidioc_s_std = dt3155_s_std, | |
425 | .vidioc_enum_input = dt3155_enum_input, | |
426 | .vidioc_g_input = dt3155_g_input, | |
427 | .vidioc_s_input = dt3155_s_input, | |
d42bffb8 MM |
428 | }; |
429 | ||
168b5092 | 430 | static int dt3155_init_board(struct dt3155_priv *pd) |
d42bffb8 | 431 | { |
168b5092 | 432 | struct pci_dev *pdev = pd->pdev; |
d42bffb8 | 433 | int i; |
deb28978 | 434 | u8 tmp = 0; |
a57941c2 | 435 | |
8ded351a | 436 | pci_set_master(pdev); /* dt3155 needs it */ |
d42bffb8 MM |
437 | |
438 | /* resetting the adapter */ | |
deb28978 HV |
439 | iowrite32(ADDR_ERR_ODD | ADDR_ERR_EVEN | FLD_CRPT_ODD | FLD_CRPT_EVEN | |
440 | FLD_DN_ODD | FLD_DN_EVEN, pd->regs + CSR1); | |
d42bffb8 | 441 | mmiowb(); |
8ded351a | 442 | msleep(20); |
d42bffb8 | 443 | |
6a11087b | 444 | /* initializing adapter registers */ |
d42bffb8 MM |
445 | iowrite32(FIFO_EN | SRST, pd->regs + CSR1); |
446 | mmiowb(); | |
447 | iowrite32(0xEEEEEE01, pd->regs + EVEN_PIXEL_FMT); | |
448 | iowrite32(0xEEEEEE01, pd->regs + ODD_PIXEL_FMT); | |
449 | iowrite32(0x00000020, pd->regs + FIFO_TRIGER); | |
450 | iowrite32(0x00000103, pd->regs + XFER_MODE); | |
451 | iowrite32(0, pd->regs + RETRY_WAIT_CNT); | |
452 | iowrite32(0, pd->regs + INT_CSR); | |
453 | iowrite32(1, pd->regs + EVEN_FLD_MASK); | |
454 | iowrite32(1, pd->regs + ODD_FLD_MASK); | |
455 | iowrite32(0, pd->regs + MASK_LENGTH); | |
456 | iowrite32(0x0005007C, pd->regs + FIFO_FLAG_CNT); | |
457 | iowrite32(0x01010101, pd->regs + IIC_CLK_DUR); | |
458 | mmiowb(); | |
459 | ||
460 | /* verifying that we have a DT3155 board (not just a SAA7116 chip) */ | |
461 | read_i2c_reg(pd->regs, DT_ID, &tmp); | |
462 | if (tmp != DT3155_ID) | |
463 | return -ENODEV; | |
464 | ||
465 | /* initialize AD LUT */ | |
466 | write_i2c_reg(pd->regs, AD_ADDR, 0); | |
467 | for (i = 0; i < 256; i++) | |
468 | write_i2c_reg(pd->regs, AD_LUT, i); | |
469 | ||
470 | /* initialize ADC references */ | |
471 | /* FIXME: pos_ref & neg_ref depend on VT_50HZ */ | |
472 | write_i2c_reg(pd->regs, AD_ADDR, AD_CMD_REG); | |
473 | write_i2c_reg(pd->regs, AD_CMD, VIDEO_CNL_1 | SYNC_CNL_1 | SYNC_LVL_3); | |
474 | write_i2c_reg(pd->regs, AD_ADDR, AD_POS_REF); | |
475 | write_i2c_reg(pd->regs, AD_CMD, 34); | |
476 | write_i2c_reg(pd->regs, AD_ADDR, AD_NEG_REF); | |
477 | write_i2c_reg(pd->regs, AD_CMD, 0); | |
478 | ||
479 | /* initialize PM LUT */ | |
480 | write_i2c_reg(pd->regs, CONFIG, pd->config | PM_LUT_PGM); | |
481 | for (i = 0; i < 256; i++) { | |
482 | write_i2c_reg(pd->regs, PM_LUT_ADDR, i); | |
483 | write_i2c_reg(pd->regs, PM_LUT_DATA, i); | |
484 | } | |
485 | write_i2c_reg(pd->regs, CONFIG, pd->config | PM_LUT_PGM | PM_LUT_SEL); | |
486 | for (i = 0; i < 256; i++) { | |
487 | write_i2c_reg(pd->regs, PM_LUT_ADDR, i); | |
488 | write_i2c_reg(pd->regs, PM_LUT_DATA, i); | |
489 | } | |
490 | write_i2c_reg(pd->regs, CONFIG, pd->config); /* ACQ_MODE_EVEN */ | |
491 | ||
6dc8f382 | 492 | /* select channel 1 for input and set sync level */ |
d42bffb8 MM |
493 | write_i2c_reg(pd->regs, AD_ADDR, AD_CMD_REG); |
494 | write_i2c_reg(pd->regs, AD_CMD, VIDEO_CNL_1 | SYNC_CNL_1 | SYNC_LVL_3); | |
495 | ||
deb28978 HV |
496 | /* disable all irqs, clear all irq flags */ |
497 | iowrite32(FLD_START | FLD_END_EVEN | FLD_END_ODD, | |
498 | pd->regs + INT_CSR); | |
499 | ||
d42bffb8 MM |
500 | return 0; |
501 | } | |
502 | ||
503 | static struct video_device dt3155_vdev = { | |
504 | .name = DT3155_NAME, | |
505 | .fops = &dt3155_fops, | |
506 | .ioctl_ops = &dt3155_ioctl_ops, | |
507 | .minor = -1, | |
f91fccde | 508 | .release = video_device_release_empty, |
5c9ede44 | 509 | .tvnorms = V4L2_STD_ALL, |
d42bffb8 MM |
510 | }; |
511 | ||
6a11087b | 512 | static int dt3155_probe(struct pci_dev *pdev, const struct pci_device_id *id) |
d42bffb8 | 513 | { |
a57941c2 | 514 | int err; |
d42bffb8 MM |
515 | struct dt3155_priv *pd; |
516 | ||
68788979 | 517 | err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); |
c94a2e47 | 518 | if (err) |
a57941c2 | 519 | return -ENODEV; |
92afdc1b | 520 | pd = devm_kzalloc(&pdev->dev, sizeof(*pd), GFP_KERNEL); |
c94a2e47 | 521 | if (!pd) |
d42bffb8 | 522 | return -ENOMEM; |
92afdc1b | 523 | |
168b5092 HV |
524 | err = v4l2_device_register(&pdev->dev, &pd->v4l2_dev); |
525 | if (err) | |
526 | return err; | |
f91fccde | 527 | pd->vdev = dt3155_vdev; |
168b5092 | 528 | pd->vdev.v4l2_dev = &pd->v4l2_dev; |
f91fccde | 529 | video_set_drvdata(&pd->vdev, pd); /* for use in video_fops */ |
8ded351a | 530 | pd->pdev = pdev; |
5c9ede44 HV |
531 | pd->std = V4L2_STD_625_50; |
532 | pd->csr2 = VT_50HZ; | |
533 | pd->width = 768; | |
534 | pd->height = 576; | |
d42bffb8 | 535 | INIT_LIST_HEAD(&pd->dmaq); |
d42bffb8 | 536 | mutex_init(&pd->mux); |
f91fccde | 537 | pd->vdev.lock = &pd->mux; /* for locking v4l2_file_operations */ |
9556be12 HV |
538 | pd->vidq.type = V4L2_BUF_TYPE_VIDEO_CAPTURE; |
539 | pd->vidq.timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; | |
540 | pd->vidq.io_modes = VB2_MMAP | VB2_DMABUF | VB2_READ; | |
541 | pd->vidq.ops = &q_ops; | |
542 | pd->vidq.mem_ops = &vb2_dma_contig_memops; | |
543 | pd->vidq.drv_priv = pd; | |
544 | pd->vidq.min_buffers_needed = 2; | |
7c89a21b | 545 | pd->vidq.gfp_flags = GFP_DMA32; |
9556be12 HV |
546 | pd->vidq.lock = &pd->mux; /* for locking v4l2_file_operations */ |
547 | pd->vdev.queue = &pd->vidq; | |
548 | err = vb2_queue_init(&pd->vidq); | |
549 | if (err < 0) | |
550 | goto err_v4l2_dev_unreg; | |
551 | pd->alloc_ctx = vb2_dma_contig_init_ctx(&pdev->dev); | |
552 | if (IS_ERR(pd->alloc_ctx)) { | |
553 | dev_err(&pdev->dev, "Can't allocate buffer context"); | |
554 | err = PTR_ERR(pd->alloc_ctx); | |
555 | goto err_v4l2_dev_unreg; | |
556 | } | |
8ded351a | 557 | spin_lock_init(&pd->lock); |
5c9ede44 | 558 | pd->config = ACQ_MODE_EVEN; |
8ded351a | 559 | err = pci_enable_device(pdev); |
c94a2e47 | 560 | if (err) |
9556be12 | 561 | goto err_free_ctx; |
8ded351a | 562 | err = pci_request_region(pdev, 0, pci_name(pdev)); |
d42bffb8 | 563 | if (err) |
168b5092 | 564 | goto err_pci_disable; |
8ded351a | 565 | pd->regs = pci_iomap(pdev, 0, pci_resource_len(pd->pdev, 0)); |
aecf33db | 566 | if (!pd->regs) { |
d42bffb8 | 567 | err = -ENOMEM; |
168b5092 | 568 | goto err_free_reg; |
aecf33db | 569 | } |
168b5092 HV |
570 | err = dt3155_init_board(pd); |
571 | if (err) | |
572 | goto err_iounmap; | |
573 | err = request_irq(pd->pdev->irq, dt3155_irq_handler_even, | |
574 | IRQF_SHARED, DT3155_NAME, pd); | |
c94a2e47 | 575 | if (err) |
168b5092 | 576 | goto err_iounmap; |
f91fccde | 577 | err = video_register_device(&pd->vdev, VFL_TYPE_GRABBER, -1); |
a57941c2 | 578 | if (err) |
168b5092 | 579 | goto err_free_irq; |
f91fccde | 580 | dev_info(&pdev->dev, "/dev/video%i is ready\n", pd->vdev.minor); |
d42bffb8 MM |
581 | return 0; /* success */ |
582 | ||
168b5092 HV |
583 | err_free_irq: |
584 | free_irq(pd->pdev->irq, pd); | |
585 | err_iounmap: | |
8ded351a | 586 | pci_iounmap(pdev, pd->regs); |
168b5092 | 587 | err_free_reg: |
8ded351a | 588 | pci_release_region(pdev, 0); |
168b5092 | 589 | err_pci_disable: |
8ded351a | 590 | pci_disable_device(pdev); |
9556be12 HV |
591 | err_free_ctx: |
592 | vb2_dma_contig_cleanup_ctx(pd->alloc_ctx); | |
168b5092 HV |
593 | err_v4l2_dev_unreg: |
594 | v4l2_device_unregister(&pd->v4l2_dev); | |
d42bffb8 MM |
595 | return err; |
596 | } | |
597 | ||
6a11087b | 598 | static void dt3155_remove(struct pci_dev *pdev) |
d42bffb8 | 599 | { |
168b5092 | 600 | struct v4l2_device *v4l2_dev = pci_get_drvdata(pdev); |
90874cd6 MCC |
601 | struct dt3155_priv *pd = container_of(v4l2_dev, struct dt3155_priv, |
602 | v4l2_dev); | |
d42bffb8 | 603 | |
f91fccde | 604 | video_unregister_device(&pd->vdev); |
168b5092 | 605 | free_irq(pd->pdev->irq, pd); |
9556be12 | 606 | vb2_queue_release(&pd->vidq); |
168b5092 | 607 | v4l2_device_unregister(&pd->v4l2_dev); |
8ded351a MM |
608 | pci_iounmap(pdev, pd->regs); |
609 | pci_release_region(pdev, 0); | |
610 | pci_disable_device(pdev); | |
9556be12 | 611 | vb2_dma_contig_cleanup_ctx(pd->alloc_ctx); |
d42bffb8 MM |
612 | } |
613 | ||
41e043fc | 614 | static const struct pci_device_id pci_ids[] = { |
6fb0e403 | 615 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, DT3155_DEVICE_ID) }, |
d42bffb8 MM |
616 | { 0, /* zero marks the end */ }, |
617 | }; | |
618 | MODULE_DEVICE_TABLE(pci, pci_ids); | |
619 | ||
620 | static struct pci_driver pci_driver = { | |
621 | .name = DT3155_NAME, | |
622 | .id_table = pci_ids, | |
623 | .probe = dt3155_probe, | |
79fc8d89 | 624 | .remove = dt3155_remove, |
d42bffb8 MM |
625 | }; |
626 | ||
1a3acd3d | 627 | module_pci_driver(pci_driver); |
d42bffb8 MM |
628 | |
629 | MODULE_DESCRIPTION("video4linux pci-driver for dt3155 frame grabber"); | |
630 | MODULE_AUTHOR("Marin Mitov <mitov@issp.bas.bg>"); | |
631 | MODULE_VERSION(DT3155_VERSION); | |
632 | MODULE_LICENSE("GPL"); |