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UBUNTU: SAUCE: IPU driver release WW04
[mirror_ubuntu-jammy-kernel.git] / drivers / media / pci / intel / ipu-fw-isys.h
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WY		 1/* SPDX-License-Identifier: GPL-2.0 */
2/* Copyright (C) 2013 - 2020 Intel Corporation */
3
4#ifndef IPU_FW_ISYS_H
5#define IPU_FW_ISYS_H
6
7#include "ipu-fw-com.h"
8
9/* Max number of Input/Output Pins */
10#define IPU_MAX_IPINS 4
11
12#define IPU_MAX_OPINS ((IPU_MAX_IPINS) + 1)
13
14#define IPU6_STREAM_ID_MAX 16
9a5c4cef 15#define IPU6_NONSECURE_STREAM_ID_MAX 12
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WY		 16#define IPU6_DEV_SEND_QUEUE_SIZE (IPU6_STREAM_ID_MAX)
17#define IPU6_NOF_SRAM_BLOCKS_MAX (IPU6_STREAM_ID_MAX)
18#define IPU6_N_MAX_MSG_SEND_QUEUES (IPU6_STREAM_ID_MAX)
19#define IPU6SE_STREAM_ID_MAX 8
9a5c4cef 20#define IPU6SE_NONSECURE_STREAM_ID_MAX 4
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WY		 21#define IPU6SE_DEV_SEND_QUEUE_SIZE (IPU6SE_STREAM_ID_MAX)
22#define IPU6SE_NOF_SRAM_BLOCKS_MAX (IPU6SE_STREAM_ID_MAX)
23#define IPU6SE_N_MAX_MSG_SEND_QUEUES (IPU6SE_STREAM_ID_MAX)
24
25/* Single return queue for all streams/commands type */
26#define IPU_N_MAX_MSG_RECV_QUEUES 1
27/* Single device queue for high priority commands (bypass in-order queue) */
28#define IPU_N_MAX_DEV_SEND_QUEUES 1
29/* Single dedicated send queue for proxy interface */
30#define IPU_N_MAX_PROXY_SEND_QUEUES 1
31/* Single dedicated recv queue for proxy interface */
32#define IPU_N_MAX_PROXY_RECV_QUEUES 1
33/* Send queues layout */
34#define IPU_BASE_PROXY_SEND_QUEUES 0
35#define IPU_BASE_DEV_SEND_QUEUES \
36 (IPU_BASE_PROXY_SEND_QUEUES + IPU_N_MAX_PROXY_SEND_QUEUES)
37#define IPU_BASE_MSG_SEND_QUEUES \
38 (IPU_BASE_DEV_SEND_QUEUES + IPU_N_MAX_DEV_SEND_QUEUES)
39/* Recv queues layout */
40#define IPU_BASE_PROXY_RECV_QUEUES 0
41#define IPU_BASE_MSG_RECV_QUEUES \
42 (IPU_BASE_PROXY_RECV_QUEUES + IPU_N_MAX_PROXY_RECV_QUEUES)
43#define IPU_N_MAX_RECV_QUEUES \
44 (IPU_BASE_MSG_RECV_QUEUES + IPU_N_MAX_MSG_RECV_QUEUES)
45
46#define IPU6_N_MAX_SEND_QUEUES \
47 (IPU_BASE_MSG_SEND_QUEUES + IPU6_N_MAX_MSG_SEND_QUEUES)
48#define IPU6SE_N_MAX_SEND_QUEUES \
49 (IPU_BASE_MSG_SEND_QUEUES + IPU6SE_N_MAX_MSG_SEND_QUEUES)
50
51/* Max number of supported input pins routed in ISL */
52#define IPU_MAX_IPINS_IN_ISL 2
53
54/* Max number of planes for frame formats supported by the FW */
55#define IPU_PIN_PLANES_MAX 4
56
57/**
58 * enum ipu_fw_isys_resp_type
59 */
60enum ipu_fw_isys_resp_type {
61 IPU_FW_ISYS_RESP_TYPE_STREAM_OPEN_DONE = 0,
62 IPU_FW_ISYS_RESP_TYPE_STREAM_START_ACK,
63 IPU_FW_ISYS_RESP_TYPE_STREAM_START_AND_CAPTURE_ACK,
64 IPU_FW_ISYS_RESP_TYPE_STREAM_CAPTURE_ACK,
65 IPU_FW_ISYS_RESP_TYPE_STREAM_STOP_ACK,
66 IPU_FW_ISYS_RESP_TYPE_STREAM_FLUSH_ACK,
67 IPU_FW_ISYS_RESP_TYPE_STREAM_CLOSE_ACK,
68 IPU_FW_ISYS_RESP_TYPE_PIN_DATA_READY,
69 IPU_FW_ISYS_RESP_TYPE_PIN_DATA_WATERMARK,
70 IPU_FW_ISYS_RESP_TYPE_FRAME_SOF,
71 IPU_FW_ISYS_RESP_TYPE_FRAME_EOF,
72 IPU_FW_ISYS_RESP_TYPE_STREAM_START_AND_CAPTURE_DONE,
73 IPU_FW_ISYS_RESP_TYPE_STREAM_CAPTURE_DONE,
74 IPU_FW_ISYS_RESP_TYPE_PIN_DATA_SKIPPED,
75 IPU_FW_ISYS_RESP_TYPE_STREAM_CAPTURE_SKIPPED,
76 IPU_FW_ISYS_RESP_TYPE_FRAME_SOF_DISCARDED,
77 IPU_FW_ISYS_RESP_TYPE_FRAME_EOF_DISCARDED,
78 IPU_FW_ISYS_RESP_TYPE_STATS_DATA_READY,
79 N_IPU_FW_ISYS_RESP_TYPE
80};
81
82/**
83 * enum ipu_fw_isys_send_type
84 */
85enum ipu_fw_isys_send_type {
86 IPU_FW_ISYS_SEND_TYPE_STREAM_OPEN = 0,
87 IPU_FW_ISYS_SEND_TYPE_STREAM_START,
88 IPU_FW_ISYS_SEND_TYPE_STREAM_START_AND_CAPTURE,
89 IPU_FW_ISYS_SEND_TYPE_STREAM_CAPTURE,
90 IPU_FW_ISYS_SEND_TYPE_STREAM_STOP,
91 IPU_FW_ISYS_SEND_TYPE_STREAM_FLUSH,
92 IPU_FW_ISYS_SEND_TYPE_STREAM_CLOSE,
93 N_IPU_FW_ISYS_SEND_TYPE
94};
95
96/**
97 * enum ipu_fw_isys_queue_type
98 */
99enum ipu_fw_isys_queue_type {
100 IPU_FW_ISYS_QUEUE_TYPE_PROXY = 0,
101 IPU_FW_ISYS_QUEUE_TYPE_DEV,
102 IPU_FW_ISYS_QUEUE_TYPE_MSG,
103 N_IPU_FW_ISYS_QUEUE_TYPE
104};
105
106/**
107 * enum ipu_fw_isys_stream_source: Specifies a source for a stream
108 */
109enum ipu_fw_isys_stream_source {
110 IPU_FW_ISYS_STREAM_SRC_PORT_0 = 0,
111 IPU_FW_ISYS_STREAM_SRC_PORT_1,
112 IPU_FW_ISYS_STREAM_SRC_PORT_2,
113 IPU_FW_ISYS_STREAM_SRC_PORT_3,
114 IPU_FW_ISYS_STREAM_SRC_PORT_4,
115 IPU_FW_ISYS_STREAM_SRC_PORT_5,
116 IPU_FW_ISYS_STREAM_SRC_PORT_6,
117 IPU_FW_ISYS_STREAM_SRC_PORT_7,
118 IPU_FW_ISYS_STREAM_SRC_PORT_8,
119 IPU_FW_ISYS_STREAM_SRC_PORT_9,
120 IPU_FW_ISYS_STREAM_SRC_PORT_10,
121 IPU_FW_ISYS_STREAM_SRC_PORT_11,
122 IPU_FW_ISYS_STREAM_SRC_PORT_12,
123 IPU_FW_ISYS_STREAM_SRC_PORT_13,
124 IPU_FW_ISYS_STREAM_SRC_PORT_14,
125 IPU_FW_ISYS_STREAM_SRC_PORT_15,
126 IPU_FW_ISYS_STREAM_SRC_MIPIGEN_0,
127 IPU_FW_ISYS_STREAM_SRC_MIPIGEN_1,
128 IPU_FW_ISYS_STREAM_SRC_MIPIGEN_2,
129 IPU_FW_ISYS_STREAM_SRC_MIPIGEN_3,
130 IPU_FW_ISYS_STREAM_SRC_MIPIGEN_4,
131 IPU_FW_ISYS_STREAM_SRC_MIPIGEN_5,
132 IPU_FW_ISYS_STREAM_SRC_MIPIGEN_6,
133 IPU_FW_ISYS_STREAM_SRC_MIPIGEN_7,
134 IPU_FW_ISYS_STREAM_SRC_MIPIGEN_8,
135 IPU_FW_ISYS_STREAM_SRC_MIPIGEN_9,
136 N_IPU_FW_ISYS_STREAM_SRC
137};
138
139enum ipu_fw_isys_sensor_type {
140 /* non-snoopable to PSYS */
141 IPU_FW_ISYS_VC1_SENSOR_DATA = 0,
142 /* non-snoopable for PDAF */
143 IPU_FW_ISYS_VC1_SENSOR_PDAF,
144 /* snoopable to CPU */
145 IPU_FW_ISYS_VC0_SENSOR_METADATA,
146 /* snoopable to CPU */
147 IPU_FW_ISYS_VC0_SENSOR_DATA,
148 N_IPU_FW_ISYS_SENSOR_TYPE
149};
150
151enum ipu6se_fw_isys_sensor_info {
152 /* VC1 */
153 IPU6SE_FW_ISYS_SENSOR_DATA_1 = 1,
154 IPU6SE_FW_ISYS_SENSOR_DATA_2 = 2,
155 IPU6SE_FW_ISYS_SENSOR_DATA_3 = 3,
156 IPU6SE_FW_ISYS_SENSOR_PDAF_1 = 4,
157 IPU6SE_FW_ISYS_SENSOR_PDAF_2 = 4,
158 /* VC0 */
159 IPU6SE_FW_ISYS_SENSOR_METADATA = 5,
160 IPU6SE_FW_ISYS_SENSOR_DATA_4 = 6,
161 IPU6SE_FW_ISYS_SENSOR_DATA_5 = 7,
162 IPU6SE_FW_ISYS_SENSOR_DATA_6 = 8,
163 IPU6SE_FW_ISYS_SENSOR_DATA_7 = 9,
164 IPU6SE_FW_ISYS_SENSOR_DATA_8 = 10,
165 IPU6SE_FW_ISYS_SENSOR_DATA_9 = 11,
166 N_IPU6SE_FW_ISYS_SENSOR_INFO,
167 IPU6SE_FW_ISYS_VC1_SENSOR_DATA_START = IPU6SE_FW_ISYS_SENSOR_DATA_1,
168 IPU6SE_FW_ISYS_VC1_SENSOR_DATA_END = IPU6SE_FW_ISYS_SENSOR_DATA_3,
169 IPU6SE_FW_ISYS_VC0_SENSOR_DATA_START = IPU6SE_FW_ISYS_SENSOR_DATA_4,
170 IPU6SE_FW_ISYS_VC0_SENSOR_DATA_END = IPU6SE_FW_ISYS_SENSOR_DATA_9,
171 IPU6SE_FW_ISYS_VC1_SENSOR_PDAF_START = IPU6SE_FW_ISYS_SENSOR_PDAF_1,
172 IPU6SE_FW_ISYS_VC1_SENSOR_PDAF_END = IPU6SE_FW_ISYS_SENSOR_PDAF_2,
173};
174
175enum ipu6_fw_isys_sensor_info {
176 /* VC1 */
177 IPU6_FW_ISYS_SENSOR_DATA_1 = 1,
178 IPU6_FW_ISYS_SENSOR_DATA_2 = 2,
179 IPU6_FW_ISYS_SENSOR_DATA_3 = 3,
180 IPU6_FW_ISYS_SENSOR_DATA_4 = 4,
181 IPU6_FW_ISYS_SENSOR_DATA_5 = 5,
182 IPU6_FW_ISYS_SENSOR_DATA_6 = 6,
183 IPU6_FW_ISYS_SENSOR_DATA_7 = 7,
184 IPU6_FW_ISYS_SENSOR_DATA_8 = 8,
185 IPU6_FW_ISYS_SENSOR_DATA_9 = 9,
186 IPU6_FW_ISYS_SENSOR_DATA_10 = 10,
187 IPU6_FW_ISYS_SENSOR_PDAF_1 = 11,
188 IPU6_FW_ISYS_SENSOR_PDAF_2 = 12,
189 /* VC0 */
190 IPU6_FW_ISYS_SENSOR_METADATA = 13,
191 IPU6_FW_ISYS_SENSOR_DATA_11 = 14,
192 IPU6_FW_ISYS_SENSOR_DATA_12 = 15,
193 IPU6_FW_ISYS_SENSOR_DATA_13 = 16,
194 IPU6_FW_ISYS_SENSOR_DATA_14 = 17,
195 IPU6_FW_ISYS_SENSOR_DATA_15 = 18,
196 IPU6_FW_ISYS_SENSOR_DATA_16 = 19,
197 N_IPU6_FW_ISYS_SENSOR_INFO,
198 IPU6_FW_ISYS_VC1_SENSOR_DATA_START = IPU6_FW_ISYS_SENSOR_DATA_1,
199 IPU6_FW_ISYS_VC1_SENSOR_DATA_END = IPU6_FW_ISYS_SENSOR_DATA_10,
200 IPU6_FW_ISYS_VC0_SENSOR_DATA_START = IPU6_FW_ISYS_SENSOR_DATA_11,
201 IPU6_FW_ISYS_VC0_SENSOR_DATA_END = IPU6_FW_ISYS_SENSOR_DATA_16,
202 IPU6_FW_ISYS_VC1_SENSOR_PDAF_START = IPU6_FW_ISYS_SENSOR_PDAF_1,
203 IPU6_FW_ISYS_VC1_SENSOR_PDAF_END = IPU6_FW_ISYS_SENSOR_PDAF_2,
204};
205
206#define IPU_FW_ISYS_STREAM_SRC_CSI2_PORT0 IPU_FW_ISYS_STREAM_SRC_PORT_0
207#define IPU_FW_ISYS_STREAM_SRC_CSI2_PORT1 IPU_FW_ISYS_STREAM_SRC_PORT_1
208#define IPU_FW_ISYS_STREAM_SRC_CSI2_PORT2 IPU_FW_ISYS_STREAM_SRC_PORT_2
209#define IPU_FW_ISYS_STREAM_SRC_CSI2_PORT3 IPU_FW_ISYS_STREAM_SRC_PORT_3
210
211#define IPU_FW_ISYS_STREAM_SRC_CSI2_3PH_PORTA IPU_FW_ISYS_STREAM_SRC_PORT_4
212#define IPU_FW_ISYS_STREAM_SRC_CSI2_3PH_PORTB IPU_FW_ISYS_STREAM_SRC_PORT_5
213#define IPU_FW_ISYS_STREAM_SRC_CSI2_3PH_CPHY_PORT0 IPU_FW_ISYS_STREAM_SRC_PORT_6
214#define IPU_FW_ISYS_STREAM_SRC_CSI2_3PH_CPHY_PORT1 IPU_FW_ISYS_STREAM_SRC_PORT_7
215#define IPU_FW_ISYS_STREAM_SRC_CSI2_3PH_CPHY_PORT2 IPU_FW_ISYS_STREAM_SRC_PORT_8
216#define IPU_FW_ISYS_STREAM_SRC_CSI2_3PH_CPHY_PORT3 IPU_FW_ISYS_STREAM_SRC_PORT_9
217
218#define IPU_FW_ISYS_STREAM_SRC_MIPIGEN_PORT0 IPU_FW_ISYS_STREAM_SRC_MIPIGEN_0
219#define IPU_FW_ISYS_STREAM_SRC_MIPIGEN_PORT1 IPU_FW_ISYS_STREAM_SRC_MIPIGEN_1
220
221/**
222 * enum ipu_fw_isys_mipi_vc: MIPI csi2 spec
223 * supports up to 4 virtual per physical channel
224 */
225enum ipu_fw_isys_mipi_vc {
226 IPU_FW_ISYS_MIPI_VC_0 = 0,
227 IPU_FW_ISYS_MIPI_VC_1,
228 IPU_FW_ISYS_MIPI_VC_2,
229 IPU_FW_ISYS_MIPI_VC_3,
230 N_IPU_FW_ISYS_MIPI_VC
231};
232
233/**
234 * Supported Pixel Frame formats. Expandable if needed
235 */
236enum ipu_fw_isys_frame_format_type {
237 IPU_FW_ISYS_FRAME_FORMAT_NV11 = 0, /* 12 bit YUV 411, Y, UV plane */
238 IPU_FW_ISYS_FRAME_FORMAT_NV12, /* 12 bit YUV 420, Y, UV plane */
239 IPU_FW_ISYS_FRAME_FORMAT_NV12_16, /* 16 bit YUV 420, Y, UV plane */
240 IPU_FW_ISYS_FRAME_FORMAT_NV12_TILEY, /* 12 bit YUV 420,
241 * Intel proprietary tiled format,
242 * TileY
243 */
244 IPU_FW_ISYS_FRAME_FORMAT_NV16, /* 16 bit YUV 422, Y, UV plane */
245 IPU_FW_ISYS_FRAME_FORMAT_NV21, /* 12 bit YUV 420, Y, VU plane */
246 IPU_FW_ISYS_FRAME_FORMAT_NV61, /* 16 bit YUV 422, Y, VU plane */
247 IPU_FW_ISYS_FRAME_FORMAT_YV12, /* 12 bit YUV 420, Y, V, U plane */
248 IPU_FW_ISYS_FRAME_FORMAT_YV16, /* 16 bit YUV 422, Y, V, U plane */
249 IPU_FW_ISYS_FRAME_FORMAT_YUV420, /* 12 bit YUV 420, Y, U, V plane */
250 IPU_FW_ISYS_FRAME_FORMAT_YUV420_10, /* yuv420, 10 bits per subpixel */
251 IPU_FW_ISYS_FRAME_FORMAT_YUV420_12, /* yuv420, 12 bits per subpixel */
252 IPU_FW_ISYS_FRAME_FORMAT_YUV420_14, /* yuv420, 14 bits per subpixel */
253 IPU_FW_ISYS_FRAME_FORMAT_YUV420_16, /* yuv420, 16 bits per subpixel */
254 IPU_FW_ISYS_FRAME_FORMAT_YUV422, /* 16 bit YUV 422, Y, U, V plane */
255 IPU_FW_ISYS_FRAME_FORMAT_YUV422_16, /* yuv422, 16 bits per subpixel */
256 IPU_FW_ISYS_FRAME_FORMAT_UYVY, /* 16 bit YUV 422, UYVY interleaved */
257 IPU_FW_ISYS_FRAME_FORMAT_YUYV, /* 16 bit YUV 422, YUYV interleaved */
258 IPU_FW_ISYS_FRAME_FORMAT_YUV444, /* 24 bit YUV 444, Y, U, V plane */
259 IPU_FW_ISYS_FRAME_FORMAT_YUV_LINE, /* Internal format, 2 y lines
260 * followed by a uvinterleaved line
261 */
262 IPU_FW_ISYS_FRAME_FORMAT_RAW8, /* RAW8, 1 plane */
263 IPU_FW_ISYS_FRAME_FORMAT_RAW10, /* RAW10, 1 plane */
264 IPU_FW_ISYS_FRAME_FORMAT_RAW12, /* RAW12, 1 plane */
265 IPU_FW_ISYS_FRAME_FORMAT_RAW14, /* RAW14, 1 plane */
266 IPU_FW_ISYS_FRAME_FORMAT_RAW16, /* RAW16, 1 plane */
267 IPU_FW_ISYS_FRAME_FORMAT_RGB565, /* 16 bit RGB, 1 plane. Each 3 sub
268 * pixels are packed into one 16 bit
269 * value, 5 bits for R, 6 bits
270 * for G and 5 bits for B.
271 */
272
273 IPU_FW_ISYS_FRAME_FORMAT_PLANAR_RGB888, /* 24 bit RGB, 3 planes */
274 IPU_FW_ISYS_FRAME_FORMAT_RGBA888, /* 32 bit RGBA, 1 plane,
275 * A=Alpha (alpha is unused)
276 */
277 IPU_FW_ISYS_FRAME_FORMAT_QPLANE6, /* Internal, for advanced ISP */
278 IPU_FW_ISYS_FRAME_FORMAT_BINARY_8, /* byte stream, used for jpeg. */
279 N_IPU_FW_ISYS_FRAME_FORMAT
280};
281
282/* Temporary for driver compatibility */
283#define IPU_FW_ISYS_FRAME_FORMAT_RAW (IPU_FW_ISYS_FRAME_FORMAT_RAW16)
284
285enum ipu_fw_isys_mipi_compression_type {
286 IPU_FW_ISYS_MIPI_COMPRESSION_TYPE_NO_COMPRESSION = 0,
287 IPU_FW_ISYS_MIPI_COMPRESSION_TYPE_10_8_10_TYPE1,
288 IPU_FW_ISYS_MIPI_COMPRESSION_TYPE_10_8_10_TYPE2,
289 IPU_FW_ISYS_MIPI_COMPRESSION_TYPE_10_7_10_TYPE1,
290 IPU_FW_ISYS_MIPI_COMPRESSION_TYPE_10_7_10_TYPE2,
291 IPU_FW_ISYS_MIPI_COMPRESSION_TYPE_10_6_10_TYPE1,
292 IPU_FW_ISYS_MIPI_COMPRESSION_TYPE_10_6_10_TYPE2,
293 IPU_FW_ISYS_MIPI_COMPRESSION_TYPE_12_8_12_TYPE1,
294 IPU_FW_ISYS_MIPI_COMPRESSION_TYPE_12_8_12_TYPE2,
295 IPU_FW_ISYS_MIPI_COMPRESSION_TYPE_12_7_12_TYPE1,
296 IPU_FW_ISYS_MIPI_COMPRESSION_TYPE_12_7_12_TYPE2,
297 IPU_FW_ISYS_MIPI_COMPRESSION_TYPE_12_6_12_TYPE1,
298 IPU_FW_ISYS_MIPI_COMPRESSION_TYPE_12_6_12_TYPE2,
299 IPU_FW_ISYS_MIPI_COMPRESSION_TYPE_12_10_12_TYPE1,
300 IPU_FW_ISYS_MIPI_COMPRESSION_TYPE_12_10_12_TYPE2,
301 N_IPU_FW_ISYS_MIPI_COMPRESSION_TYPE,
302};
303
304/**
305 * Supported MIPI data type. Keep in sync array in ipu_fw_isys_private.c
306 */
307enum ipu_fw_isys_mipi_data_type {
308 /** SYNCHRONIZATION SHORT PACKET DATA TYPES */
309 IPU_FW_ISYS_MIPI_DATA_TYPE_FRAME_START_CODE = 0x00,
310 IPU_FW_ISYS_MIPI_DATA_TYPE_FRAME_END_CODE = 0x01,
311 IPU_FW_ISYS_MIPI_DATA_TYPE_LINE_START_CODE = 0x02, /* Optional */
312 IPU_FW_ISYS_MIPI_DATA_TYPE_LINE_END_CODE = 0x03, /* Optional */
313 /** Reserved 0x04-0x07 */
314 IPU_FW_ISYS_MIPI_DATA_TYPE_RESERVED_0x04 = 0x04,
315 IPU_FW_ISYS_MIPI_DATA_TYPE_RESERVED_0x05 = 0x05,
316 IPU_FW_ISYS_MIPI_DATA_TYPE_RESERVED_0x06 = 0x06,
317 IPU_FW_ISYS_MIPI_DATA_TYPE_RESERVED_0x07 = 0x07,
318 /** GENERIC SHORT PACKET DATA TYPES */
319 /** They are used to keep the timing information for
320 * the opening/closing of shutters,
321 * triggering of flashes and etc.
322 */
323 /* Generic Short Packet Codes 1 - 8 */
324 IPU_FW_ISYS_MIPI_DATA_TYPE_GENERIC_SHORT1 = 0x08,
325 IPU_FW_ISYS_MIPI_DATA_TYPE_GENERIC_SHORT2 = 0x09,
326 IPU_FW_ISYS_MIPI_DATA_TYPE_GENERIC_SHORT3 = 0x0A,
327 IPU_FW_ISYS_MIPI_DATA_TYPE_GENERIC_SHORT4 = 0x0B,
328 IPU_FW_ISYS_MIPI_DATA_TYPE_GENERIC_SHORT5 = 0x0C,
329 IPU_FW_ISYS_MIPI_DATA_TYPE_GENERIC_SHORT6 = 0x0D,
330 IPU_FW_ISYS_MIPI_DATA_TYPE_GENERIC_SHORT7 = 0x0E,
331 IPU_FW_ISYS_MIPI_DATA_TYPE_GENERIC_SHORT8 = 0x0F,
332 /** GENERIC LONG PACKET DATA TYPES */
333 IPU_FW_ISYS_MIPI_DATA_TYPE_NULL = 0x10,
334 IPU_FW_ISYS_MIPI_DATA_TYPE_BLANKING_DATA = 0x11,
335 /* Embedded 8-bit non Image Data */
336 IPU_FW_ISYS_MIPI_DATA_TYPE_EMBEDDED = 0x12,
337 /** Reserved 0x13-0x17 */
338 IPU_FW_ISYS_MIPI_DATA_TYPE_RESERVED_0x13 = 0x13,
339 IPU_FW_ISYS_MIPI_DATA_TYPE_RESERVED_0x14 = 0x14,
340 IPU_FW_ISYS_MIPI_DATA_TYPE_RESERVED_0x15 = 0x15,
341 IPU_FW_ISYS_MIPI_DATA_TYPE_RESERVED_0x16 = 0x16,
342 IPU_FW_ISYS_MIPI_DATA_TYPE_RESERVED_0x17 = 0x17,
343 /** YUV DATA TYPES */
344 /* 8 bits per subpixel */
345 IPU_FW_ISYS_MIPI_DATA_TYPE_YUV420_8 = 0x18,
346 /* 10 bits per subpixel */
347 IPU_FW_ISYS_MIPI_DATA_TYPE_YUV420_10 = 0x19,
348 /* 8 bits per subpixel */
349 IPU_FW_ISYS_MIPI_DATA_TYPE_YUV420_8_LEGACY = 0x1A,
350 /** Reserved 0x1B */
351 IPU_FW_ISYS_MIPI_DATA_TYPE_RESERVED_0x1B = 0x1B,
352 /* YUV420 8-bit Chroma Shifted Pixel Sampling) */
353 IPU_FW_ISYS_MIPI_DATA_TYPE_YUV420_8_SHIFT = 0x1C,
354 /* YUV420 8-bit (Chroma Shifted Pixel Sampling) */
355 IPU_FW_ISYS_MIPI_DATA_TYPE_YUV420_10_SHIFT = 0x1D,
356 /* UYVY..UVYV, 8 bits per subpixel */
357 IPU_FW_ISYS_MIPI_DATA_TYPE_YUV422_8 = 0x1E,
358 /* UYVY..UVYV, 10 bits per subpixel */
359 IPU_FW_ISYS_MIPI_DATA_TYPE_YUV422_10 = 0x1F,
360 /** RGB DATA TYPES */
361 /* BGR..BGR, 4 bits per subpixel */
362 IPU_FW_ISYS_MIPI_DATA_TYPE_RGB_444 = 0x20,
363 /* BGR..BGR, 5 bits per subpixel */
364 IPU_FW_ISYS_MIPI_DATA_TYPE_RGB_555 = 0x21,
365 /* BGR..BGR, 5 bits B and R, 6 bits G */
366 IPU_FW_ISYS_MIPI_DATA_TYPE_RGB_565 = 0x22,
367 /* BGR..BGR, 6 bits per subpixel */
368 IPU_FW_ISYS_MIPI_DATA_TYPE_RGB_666 = 0x23,
369 /* BGR..BGR, 8 bits per subpixel */
370 IPU_FW_ISYS_MIPI_DATA_TYPE_RGB_888 = 0x24,
371 /** Reserved 0x25-0x27 */
372 IPU_FW_ISYS_MIPI_DATA_TYPE_RESERVED_0x25 = 0x25,
373 IPU_FW_ISYS_MIPI_DATA_TYPE_RESERVED_0x26 = 0x26,
374 IPU_FW_ISYS_MIPI_DATA_TYPE_RESERVED_0x27 = 0x27,
375 /** RAW DATA TYPES */
376 /* RAW data, 6 - 14 bits per pixel */
377 IPU_FW_ISYS_MIPI_DATA_TYPE_RAW_6 = 0x28,
378 IPU_FW_ISYS_MIPI_DATA_TYPE_RAW_7 = 0x29,
379 IPU_FW_ISYS_MIPI_DATA_TYPE_RAW_8 = 0x2A,
380 IPU_FW_ISYS_MIPI_DATA_TYPE_RAW_10 = 0x2B,
381 IPU_FW_ISYS_MIPI_DATA_TYPE_RAW_12 = 0x2C,
382 IPU_FW_ISYS_MIPI_DATA_TYPE_RAW_14 = 0x2D,
383 /** Reserved 0x2E-2F are used with assigned meaning */
384 /* RAW data, 16 bits per pixel, not specified in CSI-MIPI standard */
385 IPU_FW_ISYS_MIPI_DATA_TYPE_RAW_16 = 0x2E,
386 /* Binary byte stream, which is target at JPEG,
387 * not specified in CSI-MIPI standard
388 */
389 IPU_FW_ISYS_MIPI_DATA_TYPE_BINARY_8 = 0x2F,
390
391 /** USER DEFINED 8-BIT DATA TYPES */
392 /** For example, the data transmitter (e.g. the SoC sensor)
393 * can keep the JPEG data as
394 * the User Defined Data Type 4 and the MPEG data as the
395 * User Defined Data Type 7.
396 */
397 IPU_FW_ISYS_MIPI_DATA_TYPE_USER_DEF1 = 0x30,
398 IPU_FW_ISYS_MIPI_DATA_TYPE_USER_DEF2 = 0x31,
399 IPU_FW_ISYS_MIPI_DATA_TYPE_USER_DEF3 = 0x32,
400 IPU_FW_ISYS_MIPI_DATA_TYPE_USER_DEF4 = 0x33,
401 IPU_FW_ISYS_MIPI_DATA_TYPE_USER_DEF5 = 0x34,
402 IPU_FW_ISYS_MIPI_DATA_TYPE_USER_DEF6 = 0x35,
403 IPU_FW_ISYS_MIPI_DATA_TYPE_USER_DEF7 = 0x36,
404 IPU_FW_ISYS_MIPI_DATA_TYPE_USER_DEF8 = 0x37,
405 /** Reserved 0x38-0x3F */
406 IPU_FW_ISYS_MIPI_DATA_TYPE_RESERVED_0x38 = 0x38,
407 IPU_FW_ISYS_MIPI_DATA_TYPE_RESERVED_0x39 = 0x39,
408 IPU_FW_ISYS_MIPI_DATA_TYPE_RESERVED_0x3A = 0x3A,
409 IPU_FW_ISYS_MIPI_DATA_TYPE_RESERVED_0x3B = 0x3B,
410 IPU_FW_ISYS_MIPI_DATA_TYPE_RESERVED_0x3C = 0x3C,
411 IPU_FW_ISYS_MIPI_DATA_TYPE_RESERVED_0x3D = 0x3D,
412 IPU_FW_ISYS_MIPI_DATA_TYPE_RESERVED_0x3E = 0x3E,
413 IPU_FW_ISYS_MIPI_DATA_TYPE_RESERVED_0x3F = 0x3F,
414
415 /* Keep always last and max value */
416 N_IPU_FW_ISYS_MIPI_DATA_TYPE = 0x40
417};
418
419/** enum ipu_fw_isys_pin_type: output pin buffer types.
420 * Buffers can be queued and de-queued to hand them over between IA and ISYS
421 */
422enum ipu_fw_isys_pin_type {
423 /* Captured as MIPI packets */
424 IPU_FW_ISYS_PIN_TYPE_MIPI = 0,
425 /* Captured through the RAW path */
426 IPU_FW_ISYS_PIN_TYPE_RAW_NS = 1,
427 /* Captured through the SoC path */
428 IPU_FW_ISYS_PIN_TYPE_RAW_SOC = 3,
429 /* Reserved for future use, maybe short packets */
430 IPU_FW_ISYS_PIN_TYPE_METADATA_0 = 4,
431 /* Reserved for future use */
432 IPU_FW_ISYS_PIN_TYPE_METADATA_1 = 5,
433 /* Keep always last and max value */
434 N_IPU_FW_ISYS_PIN_TYPE
435};
436
437/**
438 * enum ipu_fw_isys_mipi_store_mode. Describes if long MIPI packets reach
439 * MIPI SRAM with the long packet header or
440 * if not, then only option is to capture it with pin type MIPI.
441 */
442enum ipu_fw_isys_mipi_store_mode {
443 IPU_FW_ISYS_MIPI_STORE_MODE_NORMAL = 0,
444 IPU_FW_ISYS_MIPI_STORE_MODE_DISCARD_LONG_HEADER,
445 N_IPU_FW_ISYS_MIPI_STORE_MODE
446};
447
448/**
449 * ISYS capture mode and sensor enums
450 * Used for Tobii sensor, if doubt, use default value 0
451 */
452
453enum ipu_fw_isys_capture_mode {
454 IPU_FW_ISYS_CAPTURE_MODE_REGULAR = 0,
455 IPU_FW_ISYS_CAPTURE_MODE_BURST,
456 N_IPU_FW_ISYS_CAPTURE_MODE,
457};
458
459enum ipu_fw_isys_sensor_mode {
460 IPU_FW_ISYS_SENSOR_MODE_NORMAL = 0,
461 IPU_FW_ISYS_SENSOR_MODE_TOBII,
462 N_IPU_FW_ISYS_SENSOR_MODE,
463};
464
465/**
466 * enum ipu_fw_isys_error. Describes the error type detected by the FW
467 */
468enum ipu_fw_isys_error {
469 IPU_FW_ISYS_ERROR_NONE = 0, /* No details */
470 IPU_FW_ISYS_ERROR_FW_INTERNAL_CONSISTENCY, /* enum */
471 IPU_FW_ISYS_ERROR_HW_CONSISTENCY, /* enum */
472 IPU_FW_ISYS_ERROR_DRIVER_INVALID_COMMAND_SEQUENCE, /* enum */
473 IPU_FW_ISYS_ERROR_DRIVER_INVALID_DEVICE_CONFIGURATION, /* enum */
474 IPU_FW_ISYS_ERROR_DRIVER_INVALID_STREAM_CONFIGURATION, /* enum */
475 IPU_FW_ISYS_ERROR_DRIVER_INVALID_FRAME_CONFIGURATION, /* enum */
476 IPU_FW_ISYS_ERROR_INSUFFICIENT_RESOURCES, /* enum */
477 IPU_FW_ISYS_ERROR_HW_REPORTED_STR2MMIO, /* HW code */
478 IPU_FW_ISYS_ERROR_HW_REPORTED_SIG2CIO, /* HW code */
479 IPU_FW_ISYS_ERROR_SENSOR_FW_SYNC, /* enum */
480 IPU_FW_ISYS_ERROR_STREAM_IN_SUSPENSION, /* FW code */
481 IPU_FW_ISYS_ERROR_RESPONSE_QUEUE_FULL, /* FW code */
482 N_IPU_FW_ISYS_ERROR
483};
484
485/**
486 * enum ipu_fw_proxy_error. Describes the error type for
487 * the proxy detected by the FW
488 */
489enum ipu_fw_proxy_error {
490 IPU_FW_PROXY_ERROR_NONE = 0,
491 IPU_FW_PROXY_ERROR_INVALID_WRITE_REGION,
492 IPU_FW_PROXY_ERROR_INVALID_WRITE_OFFSET,
493 N_IPU_FW_PROXY_ERROR
494};
495
496struct ipu_isys;
497
498struct ipu6_fw_isys_buffer_partition_abi {
499 u32 num_gda_pages[IPU6_STREAM_ID_MAX];
500};
501
502struct ipu6_fw_isys_fw_config {
503 struct ipu6_fw_isys_buffer_partition_abi buffer_partition;
504 u32 num_send_queues[N_IPU_FW_ISYS_QUEUE_TYPE];
505 u32 num_recv_queues[N_IPU_FW_ISYS_QUEUE_TYPE];
506};
507
508struct ipu6se_fw_isys_buffer_partition_abi {
509 u32 num_gda_pages[IPU6SE_STREAM_ID_MAX];
510};
511
512struct ipu6se_fw_isys_fw_config {
513 struct ipu6se_fw_isys_buffer_partition_abi buffer_partition;
514 u32 num_send_queues[N_IPU_FW_ISYS_QUEUE_TYPE];
515 u32 num_recv_queues[N_IPU_FW_ISYS_QUEUE_TYPE];
516};
517
518/**
519 * struct ipu_fw_isys_resolution_abi: Generic resolution structure.
520 * @Width
521 * @Height
522 */
523struct ipu_fw_isys_resolution_abi {
524 u32 width;
525 u32 height;
526};
527
528/**
529 * struct ipu_fw_isys_output_pin_payload_abi
530 * @out_buf_id: Points to output pin buffer - buffer identifier
531 * @addr: Points to output pin buffer - CSS Virtual Address
532 * @compress: Request frame compression (1), or not (0)
533 */
534struct ipu_fw_isys_output_pin_payload_abi {
535 u64 out_buf_id;
536 u32 addr;
537 u32 compress;
538};
539
540/**
541 * struct ipu_fw_isys_output_pin_info_abi
542 * @output_res: output pin resolution
543 * @stride: output stride in Bytes (not valid for statistics)
544 * @watermark_in_lines: pin watermark level in lines
545 * @payload_buf_size: minimum size in Bytes of all buffers that will be
546 * supplied for capture on this pin
547 * @send_irq: assert if pin event should trigger irq
548 * @pt: pin type -real format "enum ipu_fw_isys_pin_type"
549 * @ft: frame format type -real format "enum ipu_fw_isys_frame_format_type"
550 * @input_pin_id: related input pin id
551 * @reserve_compression: reserve compression resources for pin
552 */
553struct ipu_fw_isys_output_pin_info_abi {
554 struct ipu_fw_isys_resolution_abi output_res;
555 u32 stride;
556 u32 watermark_in_lines;
557 u32 payload_buf_size;
558 u32 ts_offsets[IPU_PIN_PLANES_MAX];
559 u32 s2m_pixel_soc_pixel_remapping;
560 u32 csi_be_soc_pixel_remapping;
561 u8 send_irq;
562 u8 input_pin_id;
563 u8 pt;
564 u8 ft;
565 u8 reserved;
566 u8 reserve_compression;
567 u8 snoopable;
568 u8 error_handling_enable;
569 u32 sensor_type;
570};
571
572/**
573 * struct ipu_fw_isys_param_pin_abi
574 * @param_buf_id: Points to param port buffer - buffer identifier
575 * @addr: Points to param pin buffer - CSS Virtual Address
576 */
577struct ipu_fw_isys_param_pin_abi {
578 u64 param_buf_id;
579 u32 addr;
580};
581
582/**
583 * struct ipu_fw_isys_input_pin_info_abi
584 * @input_res: input resolution
585 * @dt: mipi data type ((enum ipu_fw_isys_mipi_data_type)
586 * @mipi_store_mode: defines if legacy long packet header will be stored or
587 * discarded if discarded, output pin pin type for this
588 * input pin can only be MIPI
589 * (enum ipu_fw_isys_mipi_store_mode)
590 * @bits_per_pix: native bits per pixel
591 * @mapped_dt: actual data type from sensor
592 * @mipi_decompression: defines which compression will be in mipi backend
593
594 * @crop_first_and_last_lines Control whether to crop the
595 * first and last line of the
596 * input image. Crop done by HW
597 * device.
598 * @capture_mode: mode of capture, regular or burst, default value is regular
599 */
600struct ipu_fw_isys_input_pin_info_abi {
601 struct ipu_fw_isys_resolution_abi input_res;
602 u8 dt;
603 u8 mipi_store_mode;
604 u8 bits_per_pix;
605 u8 mapped_dt;
606 u8 mipi_decompression;
607 u8 crop_first_and_last_lines;
608 u8 capture_mode;
609};
610
611/**
612 * struct ipu_fw_isys_cropping_abi - cropping coordinates
613 */
614struct ipu_fw_isys_cropping_abi {
615 s32 top_offset;
616 s32 left_offset;
617 s32 bottom_offset;
618 s32 right_offset;
619};
620
621/**
622 * struct ipu_fw_isys_stream_cfg_data_abi
623 * ISYS stream configuration data structure
624 * @crop: defines cropping resolution for the
625 * maximum number of input pins which can be cropped,
626 * it is directly mapped to the HW devices
627 * @input_pins: input pin descriptors
628 * @output_pins: output pin descriptors
629 * @compfmt: de-compression setting for User Defined Data
630 * @nof_input_pins: number of input pins
631 * @nof_output_pins: number of output pins
632 * @send_irq_sof_discarded: send irq on discarded frame sof response
633 * - if '1' it will override the send_resp_sof_discarded
634 * and send the response
635 * - if '0' the send_resp_sof_discarded will determine
636 * whether to send the response
637 * @send_irq_eof_discarded: send irq on discarded frame eof response
638 * - if '1' it will override the send_resp_eof_discarded
639 * and send the response
640 * - if '0' the send_resp_eof_discarded will determine
641 * whether to send the response
642 * @send_resp_sof_discarded: send response for discarded frame sof detected,
643 * used only when send_irq_sof_discarded is '0'
644 * @send_resp_eof_discarded: send response for discarded frame eof detected,
645 * used only when send_irq_eof_discarded is '0'
646 * @src: Stream source index e.g. MIPI_generator_0, CSI2-rx_1
647 * @vc: MIPI Virtual Channel (up to 4 virtual per physical channel)
648 * @isl_use: indicates whether stream requires ISL and how
649 * @sensor_type: type of connected sensor, tobii or others, default is 0
650 */
651struct ipu_fw_isys_stream_cfg_data_abi {
652 struct ipu_fw_isys_cropping_abi crop;
653 struct ipu_fw_isys_input_pin_info_abi input_pins[IPU_MAX_IPINS];
654 struct ipu_fw_isys_output_pin_info_abi output_pins[IPU_MAX_OPINS];
655 u32 compfmt;
656 u8 nof_input_pins;
657 u8 nof_output_pins;
658 u8 send_irq_sof_discarded;
659 u8 send_irq_eof_discarded;
660 u8 send_resp_sof_discarded;
661 u8 send_resp_eof_discarded;
662 u8 src;
663 u8 vc;
664 u8 isl_use;
665 u8 sensor_type;
666};
667
668/**
669 * struct ipu_fw_isys_frame_buff_set - frame buffer set
670 * @output_pins: output pin addresses
671 * @send_irq_sof: send irq on frame sof response
672 * - if '1' it will override the send_resp_sof and
673 * send the response
674 * - if '0' the send_resp_sof will determine whether to
675 * send the response
676 * @send_irq_eof: send irq on frame eof response
677 * - if '1' it will override the send_resp_eof and
678 * send the response
679 * - if '0' the send_resp_eof will determine whether to
680 * send the response
681 * @send_resp_sof: send response for frame sof detected,
682 * used only when send_irq_sof is '0'
683 * @send_resp_eof: send response for frame eof detected,
684 * used only when send_irq_eof is '0'
685 * @send_resp_capture_ack: send response for capture ack event
686 * @send_resp_capture_done: send response for capture done event
687 */
688struct ipu_fw_isys_frame_buff_set_abi {
689 struct ipu_fw_isys_output_pin_payload_abi output_pins[IPU_MAX_OPINS];
690 u8 send_irq_sof;
691 u8 send_irq_eof;
692 u8 send_irq_capture_ack;
693 u8 send_irq_capture_done;
694 u8 send_resp_sof;
695 u8 send_resp_eof;
696 u8 send_resp_capture_ack;
697 u8 send_resp_capture_done;
698 u8 reserved;
699};
700
701/**
702 * struct ipu_fw_isys_error_info_abi
703 * @error: error code if something went wrong
704 * @error_details: depending on error code, it may contain additional error info
705 */
706struct ipu_fw_isys_error_info_abi {
707 enum ipu_fw_isys_error error;
708 u32 error_details;
709};
710
711/**
712 * struct ipu_fw_isys_resp_info_comm
713 * @pin: this var is only valid for pin event related responses,
714 * contains pin addresses
715 * @error_info: error information from the FW
716 * @timestamp: Time information for event if available
717 * @stream_handle: stream id the response corresponds to
718 * @type: response type (enum ipu_fw_isys_resp_type)
719 * @pin_id: pin id that the pin payload corresponds to
720 */
721struct ipu_fw_isys_resp_info_abi {
722 u64 buf_id;
723 struct ipu_fw_isys_output_pin_payload_abi pin;
724 struct ipu_fw_isys_error_info_abi error_info;
725 u32 timestamp[2];
726 u8 stream_handle;
727 u8 type;
728 u8 pin_id;
729 u16 reserved;
730};
731
732/**
733 * struct ipu_fw_isys_proxy_error_info_comm
734 * @proxy_error: error code if something went wrong
735 * @proxy_error_details: depending on error code, it may contain additional
736 * error info
737 */
738struct ipu_fw_isys_proxy_error_info_abi {
739 enum ipu_fw_proxy_error error;
740 u32 error_details;
741};
742
743struct ipu_fw_isys_proxy_resp_info_abi {
744 u32 request_id;
745 struct ipu_fw_isys_proxy_error_info_abi error_info;
746};
747
748/**
749 * struct ipu_fw_proxy_write_queue_token
750 * @request_id: update id for the specific proxy write request
751 * @region_index: Region id for the proxy write request
752 * @offset: Offset of the write request according to the base address
753 * of the region
754 * @value: Value that is requested to be written with the proxy write request
755 */
756struct ipu_fw_proxy_write_queue_token {
757 u32 request_id;
758 u32 region_index;
759 u32 offset;
760 u32 value;
761};
762
763/* From here on type defines not coming from the ISYSAPI interface */
764
765/**
766 * struct ipu_fw_resp_queue_token
767 */
768struct ipu_fw_resp_queue_token {
769 struct ipu_fw_isys_resp_info_abi resp_info;
770};
771
772/**
773 * struct ipu_fw_send_queue_token
774 */
775struct ipu_fw_send_queue_token {
776 u64 buf_handle;
777 u32 payload;
778 u16 send_type;
779 u16 stream_id;
780};
781
782/**
783 * struct ipu_fw_proxy_resp_queue_token
784 */
785struct ipu_fw_proxy_resp_queue_token {
786 struct ipu_fw_isys_proxy_resp_info_abi proxy_resp_info;
787};
788
789/**
790 * struct ipu_fw_proxy_send_queue_token
791 */
792struct ipu_fw_proxy_send_queue_token {
793 u32 request_id;
794 u32 region_index;
795 u32 offset;
796 u32 value;
797};
798
799void ipu_fw_isys_set_params(struct ipu_fw_isys_stream_cfg_data_abi *stream_cfg);
800
801void ipu_fw_isys_dump_stream_cfg(struct device *dev,
802 struct ipu_fw_isys_stream_cfg_data_abi
803 *stream_cfg);
804void ipu_fw_isys_dump_frame_buff_set(struct device *dev,
805 struct ipu_fw_isys_frame_buff_set_abi *buf,
806 unsigned int outputs);
807int ipu_fw_isys_init(struct ipu_isys *isys, unsigned int num_streams);
808int ipu_fw_isys_close(struct ipu_isys *isys);
809int ipu_fw_isys_simple_cmd(struct ipu_isys *isys,
810 const unsigned int stream_handle,
811 enum ipu_fw_isys_send_type send_type);
812int ipu_fw_isys_complex_cmd(struct ipu_isys *isys,
813 const unsigned int stream_handle,
814 void *cpu_mapped_buf,
815 dma_addr_t dma_mapped_buf,
816 size_t size, enum ipu_fw_isys_send_type send_type);
817int ipu_fw_isys_send_proxy_token(struct ipu_isys *isys,
818 unsigned int req_id,
819 unsigned int index,
820 unsigned int offset, u32 value);
821void ipu_fw_isys_cleanup(struct ipu_isys *isys);
822struct ipu_fw_isys_resp_info_abi *
823ipu_fw_isys_get_resp(void *context, unsigned int queue,
824 struct ipu_fw_isys_resp_info_abi *response);
825void ipu_fw_isys_put_resp(void *context, unsigned int queue);
826#endif
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