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UBUNTU: SAUCE: intel ipu drivers first release
[mirror_ubuntu-jammy-kernel.git] / drivers / media / pci / intel / ipu-fw-isys.h
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f2efa4ee
WY		 1/* SPDX-License-Identifier: GPL-2.0 */
2/* Copyright (C) 2013 - 2020 Intel Corporation */
3
4#ifndef IPU_FW_ISYS_H
5#define IPU_FW_ISYS_H
6
7#include "ipu-fw-com.h"
8
9/* Max number of Input/Output Pins */
10#define IPU_MAX_IPINS 4
11
12#define IPU_MAX_OPINS ((IPU_MAX_IPINS) + 1)
13
14#define IPU6_STREAM_ID_MAX 16
15#define IPU6_DEV_SEND_QUEUE_SIZE (IPU6_STREAM_ID_MAX)
16#define IPU6_NOF_SRAM_BLOCKS_MAX (IPU6_STREAM_ID_MAX)
17#define IPU6_N_MAX_MSG_SEND_QUEUES (IPU6_STREAM_ID_MAX)
18#define IPU6SE_STREAM_ID_MAX 8
19#define IPU6SE_DEV_SEND_QUEUE_SIZE (IPU6SE_STREAM_ID_MAX)
20#define IPU6SE_NOF_SRAM_BLOCKS_MAX (IPU6SE_STREAM_ID_MAX)
21#define IPU6SE_N_MAX_MSG_SEND_QUEUES (IPU6SE_STREAM_ID_MAX)
22
23/* Single return queue for all streams/commands type */
24#define IPU_N_MAX_MSG_RECV_QUEUES 1
25/* Single device queue for high priority commands (bypass in-order queue) */
26#define IPU_N_MAX_DEV_SEND_QUEUES 1
27/* Single dedicated send queue for proxy interface */
28#define IPU_N_MAX_PROXY_SEND_QUEUES 1
29/* Single dedicated recv queue for proxy interface */
30#define IPU_N_MAX_PROXY_RECV_QUEUES 1
31/* Send queues layout */
32#define IPU_BASE_PROXY_SEND_QUEUES 0
33#define IPU_BASE_DEV_SEND_QUEUES \
34 (IPU_BASE_PROXY_SEND_QUEUES + IPU_N_MAX_PROXY_SEND_QUEUES)
35#define IPU_BASE_MSG_SEND_QUEUES \
36 (IPU_BASE_DEV_SEND_QUEUES + IPU_N_MAX_DEV_SEND_QUEUES)
37/* Recv queues layout */
38#define IPU_BASE_PROXY_RECV_QUEUES 0
39#define IPU_BASE_MSG_RECV_QUEUES \
40 (IPU_BASE_PROXY_RECV_QUEUES + IPU_N_MAX_PROXY_RECV_QUEUES)
41#define IPU_N_MAX_RECV_QUEUES \
42 (IPU_BASE_MSG_RECV_QUEUES + IPU_N_MAX_MSG_RECV_QUEUES)
43
44#define IPU6_N_MAX_SEND_QUEUES \
45 (IPU_BASE_MSG_SEND_QUEUES + IPU6_N_MAX_MSG_SEND_QUEUES)
46#define IPU6SE_N_MAX_SEND_QUEUES \
47 (IPU_BASE_MSG_SEND_QUEUES + IPU6SE_N_MAX_MSG_SEND_QUEUES)
48
49/* Max number of supported input pins routed in ISL */
50#define IPU_MAX_IPINS_IN_ISL 2
51
52/* Max number of planes for frame formats supported by the FW */
53#define IPU_PIN_PLANES_MAX 4
54
55/**
56 * enum ipu_fw_isys_resp_type
57 */
58enum ipu_fw_isys_resp_type {
59 IPU_FW_ISYS_RESP_TYPE_STREAM_OPEN_DONE = 0,
60 IPU_FW_ISYS_RESP_TYPE_STREAM_START_ACK,
61 IPU_FW_ISYS_RESP_TYPE_STREAM_START_AND_CAPTURE_ACK,
62 IPU_FW_ISYS_RESP_TYPE_STREAM_CAPTURE_ACK,
63 IPU_FW_ISYS_RESP_TYPE_STREAM_STOP_ACK,
64 IPU_FW_ISYS_RESP_TYPE_STREAM_FLUSH_ACK,
65 IPU_FW_ISYS_RESP_TYPE_STREAM_CLOSE_ACK,
66 IPU_FW_ISYS_RESP_TYPE_PIN_DATA_READY,
67 IPU_FW_ISYS_RESP_TYPE_PIN_DATA_WATERMARK,
68 IPU_FW_ISYS_RESP_TYPE_FRAME_SOF,
69 IPU_FW_ISYS_RESP_TYPE_FRAME_EOF,
70 IPU_FW_ISYS_RESP_TYPE_STREAM_START_AND_CAPTURE_DONE,
71 IPU_FW_ISYS_RESP_TYPE_STREAM_CAPTURE_DONE,
72 IPU_FW_ISYS_RESP_TYPE_PIN_DATA_SKIPPED,
73 IPU_FW_ISYS_RESP_TYPE_STREAM_CAPTURE_SKIPPED,
74 IPU_FW_ISYS_RESP_TYPE_FRAME_SOF_DISCARDED,
75 IPU_FW_ISYS_RESP_TYPE_FRAME_EOF_DISCARDED,
76 IPU_FW_ISYS_RESP_TYPE_STATS_DATA_READY,
77 N_IPU_FW_ISYS_RESP_TYPE
78};
79
80/**
81 * enum ipu_fw_isys_send_type
82 */
83enum ipu_fw_isys_send_type {
84 IPU_FW_ISYS_SEND_TYPE_STREAM_OPEN = 0,
85 IPU_FW_ISYS_SEND_TYPE_STREAM_START,
86 IPU_FW_ISYS_SEND_TYPE_STREAM_START_AND_CAPTURE,
87 IPU_FW_ISYS_SEND_TYPE_STREAM_CAPTURE,
88 IPU_FW_ISYS_SEND_TYPE_STREAM_STOP,
89 IPU_FW_ISYS_SEND_TYPE_STREAM_FLUSH,
90 IPU_FW_ISYS_SEND_TYPE_STREAM_CLOSE,
91 N_IPU_FW_ISYS_SEND_TYPE
92};
93
94/**
95 * enum ipu_fw_isys_queue_type
96 */
97enum ipu_fw_isys_queue_type {
98 IPU_FW_ISYS_QUEUE_TYPE_PROXY = 0,
99 IPU_FW_ISYS_QUEUE_TYPE_DEV,
100 IPU_FW_ISYS_QUEUE_TYPE_MSG,
101 N_IPU_FW_ISYS_QUEUE_TYPE
102};
103
104/**
105 * enum ipu_fw_isys_stream_source: Specifies a source for a stream
106 */
107enum ipu_fw_isys_stream_source {
108 IPU_FW_ISYS_STREAM_SRC_PORT_0 = 0,
109 IPU_FW_ISYS_STREAM_SRC_PORT_1,
110 IPU_FW_ISYS_STREAM_SRC_PORT_2,
111 IPU_FW_ISYS_STREAM_SRC_PORT_3,
112 IPU_FW_ISYS_STREAM_SRC_PORT_4,
113 IPU_FW_ISYS_STREAM_SRC_PORT_5,
114 IPU_FW_ISYS_STREAM_SRC_PORT_6,
115 IPU_FW_ISYS_STREAM_SRC_PORT_7,
116 IPU_FW_ISYS_STREAM_SRC_PORT_8,
117 IPU_FW_ISYS_STREAM_SRC_PORT_9,
118 IPU_FW_ISYS_STREAM_SRC_PORT_10,
119 IPU_FW_ISYS_STREAM_SRC_PORT_11,
120 IPU_FW_ISYS_STREAM_SRC_PORT_12,
121 IPU_FW_ISYS_STREAM_SRC_PORT_13,
122 IPU_FW_ISYS_STREAM_SRC_PORT_14,
123 IPU_FW_ISYS_STREAM_SRC_PORT_15,
124 IPU_FW_ISYS_STREAM_SRC_MIPIGEN_0,
125 IPU_FW_ISYS_STREAM_SRC_MIPIGEN_1,
126 IPU_FW_ISYS_STREAM_SRC_MIPIGEN_2,
127 IPU_FW_ISYS_STREAM_SRC_MIPIGEN_3,
128 IPU_FW_ISYS_STREAM_SRC_MIPIGEN_4,
129 IPU_FW_ISYS_STREAM_SRC_MIPIGEN_5,
130 IPU_FW_ISYS_STREAM_SRC_MIPIGEN_6,
131 IPU_FW_ISYS_STREAM_SRC_MIPIGEN_7,
132 IPU_FW_ISYS_STREAM_SRC_MIPIGEN_8,
133 IPU_FW_ISYS_STREAM_SRC_MIPIGEN_9,
134 N_IPU_FW_ISYS_STREAM_SRC
135};
136
137enum ipu_fw_isys_sensor_type {
138 /* non-snoopable to PSYS */
139 IPU_FW_ISYS_VC1_SENSOR_DATA = 0,
140 /* non-snoopable for PDAF */
141 IPU_FW_ISYS_VC1_SENSOR_PDAF,
142 /* snoopable to CPU */
143 IPU_FW_ISYS_VC0_SENSOR_METADATA,
144 /* snoopable to CPU */
145 IPU_FW_ISYS_VC0_SENSOR_DATA,
146 N_IPU_FW_ISYS_SENSOR_TYPE
147};
148
149enum ipu6se_fw_isys_sensor_info {
150 /* VC1 */
151 IPU6SE_FW_ISYS_SENSOR_DATA_1 = 1,
152 IPU6SE_FW_ISYS_SENSOR_DATA_2 = 2,
153 IPU6SE_FW_ISYS_SENSOR_DATA_3 = 3,
154 IPU6SE_FW_ISYS_SENSOR_PDAF_1 = 4,
155 IPU6SE_FW_ISYS_SENSOR_PDAF_2 = 4,
156 /* VC0 */
157 IPU6SE_FW_ISYS_SENSOR_METADATA = 5,
158 IPU6SE_FW_ISYS_SENSOR_DATA_4 = 6,
159 IPU6SE_FW_ISYS_SENSOR_DATA_5 = 7,
160 IPU6SE_FW_ISYS_SENSOR_DATA_6 = 8,
161 IPU6SE_FW_ISYS_SENSOR_DATA_7 = 9,
162 IPU6SE_FW_ISYS_SENSOR_DATA_8 = 10,
163 IPU6SE_FW_ISYS_SENSOR_DATA_9 = 11,
164 N_IPU6SE_FW_ISYS_SENSOR_INFO,
165 IPU6SE_FW_ISYS_VC1_SENSOR_DATA_START = IPU6SE_FW_ISYS_SENSOR_DATA_1,
166 IPU6SE_FW_ISYS_VC1_SENSOR_DATA_END = IPU6SE_FW_ISYS_SENSOR_DATA_3,
167 IPU6SE_FW_ISYS_VC0_SENSOR_DATA_START = IPU6SE_FW_ISYS_SENSOR_DATA_4,
168 IPU6SE_FW_ISYS_VC0_SENSOR_DATA_END = IPU6SE_FW_ISYS_SENSOR_DATA_9,
169 IPU6SE_FW_ISYS_VC1_SENSOR_PDAF_START = IPU6SE_FW_ISYS_SENSOR_PDAF_1,
170 IPU6SE_FW_ISYS_VC1_SENSOR_PDAF_END = IPU6SE_FW_ISYS_SENSOR_PDAF_2,
171};
172
173enum ipu6_fw_isys_sensor_info {
174 /* VC1 */
175 IPU6_FW_ISYS_SENSOR_DATA_1 = 1,
176 IPU6_FW_ISYS_SENSOR_DATA_2 = 2,
177 IPU6_FW_ISYS_SENSOR_DATA_3 = 3,
178 IPU6_FW_ISYS_SENSOR_DATA_4 = 4,
179 IPU6_FW_ISYS_SENSOR_DATA_5 = 5,
180 IPU6_FW_ISYS_SENSOR_DATA_6 = 6,
181 IPU6_FW_ISYS_SENSOR_DATA_7 = 7,
182 IPU6_FW_ISYS_SENSOR_DATA_8 = 8,
183 IPU6_FW_ISYS_SENSOR_DATA_9 = 9,
184 IPU6_FW_ISYS_SENSOR_DATA_10 = 10,
185 IPU6_FW_ISYS_SENSOR_PDAF_1 = 11,
186 IPU6_FW_ISYS_SENSOR_PDAF_2 = 12,
187 /* VC0 */
188 IPU6_FW_ISYS_SENSOR_METADATA = 13,
189 IPU6_FW_ISYS_SENSOR_DATA_11 = 14,
190 IPU6_FW_ISYS_SENSOR_DATA_12 = 15,
191 IPU6_FW_ISYS_SENSOR_DATA_13 = 16,
192 IPU6_FW_ISYS_SENSOR_DATA_14 = 17,
193 IPU6_FW_ISYS_SENSOR_DATA_15 = 18,
194 IPU6_FW_ISYS_SENSOR_DATA_16 = 19,
195 N_IPU6_FW_ISYS_SENSOR_INFO,
196 IPU6_FW_ISYS_VC1_SENSOR_DATA_START = IPU6_FW_ISYS_SENSOR_DATA_1,
197 IPU6_FW_ISYS_VC1_SENSOR_DATA_END = IPU6_FW_ISYS_SENSOR_DATA_10,
198 IPU6_FW_ISYS_VC0_SENSOR_DATA_START = IPU6_FW_ISYS_SENSOR_DATA_11,
199 IPU6_FW_ISYS_VC0_SENSOR_DATA_END = IPU6_FW_ISYS_SENSOR_DATA_16,
200 IPU6_FW_ISYS_VC1_SENSOR_PDAF_START = IPU6_FW_ISYS_SENSOR_PDAF_1,
201 IPU6_FW_ISYS_VC1_SENSOR_PDAF_END = IPU6_FW_ISYS_SENSOR_PDAF_2,
202};
203
204#define IPU_FW_ISYS_STREAM_SRC_CSI2_PORT0 IPU_FW_ISYS_STREAM_SRC_PORT_0
205#define IPU_FW_ISYS_STREAM_SRC_CSI2_PORT1 IPU_FW_ISYS_STREAM_SRC_PORT_1
206#define IPU_FW_ISYS_STREAM_SRC_CSI2_PORT2 IPU_FW_ISYS_STREAM_SRC_PORT_2
207#define IPU_FW_ISYS_STREAM_SRC_CSI2_PORT3 IPU_FW_ISYS_STREAM_SRC_PORT_3
208
209#define IPU_FW_ISYS_STREAM_SRC_CSI2_3PH_PORTA IPU_FW_ISYS_STREAM_SRC_PORT_4
210#define IPU_FW_ISYS_STREAM_SRC_CSI2_3PH_PORTB IPU_FW_ISYS_STREAM_SRC_PORT_5
211#define IPU_FW_ISYS_STREAM_SRC_CSI2_3PH_CPHY_PORT0 IPU_FW_ISYS_STREAM_SRC_PORT_6
212#define IPU_FW_ISYS_STREAM_SRC_CSI2_3PH_CPHY_PORT1 IPU_FW_ISYS_STREAM_SRC_PORT_7
213#define IPU_FW_ISYS_STREAM_SRC_CSI2_3PH_CPHY_PORT2 IPU_FW_ISYS_STREAM_SRC_PORT_8
214#define IPU_FW_ISYS_STREAM_SRC_CSI2_3PH_CPHY_PORT3 IPU_FW_ISYS_STREAM_SRC_PORT_9
215
216#define IPU_FW_ISYS_STREAM_SRC_MIPIGEN_PORT0 IPU_FW_ISYS_STREAM_SRC_MIPIGEN_0
217#define IPU_FW_ISYS_STREAM_SRC_MIPIGEN_PORT1 IPU_FW_ISYS_STREAM_SRC_MIPIGEN_1
218
219/**
220 * enum ipu_fw_isys_mipi_vc: MIPI csi2 spec
221 * supports up to 4 virtual per physical channel
222 */
223enum ipu_fw_isys_mipi_vc {
224 IPU_FW_ISYS_MIPI_VC_0 = 0,
225 IPU_FW_ISYS_MIPI_VC_1,
226 IPU_FW_ISYS_MIPI_VC_2,
227 IPU_FW_ISYS_MIPI_VC_3,
228 N_IPU_FW_ISYS_MIPI_VC
229};
230
231/**
232 * Supported Pixel Frame formats. Expandable if needed
233 */
234enum ipu_fw_isys_frame_format_type {
235 IPU_FW_ISYS_FRAME_FORMAT_NV11 = 0, /* 12 bit YUV 411, Y, UV plane */
236 IPU_FW_ISYS_FRAME_FORMAT_NV12, /* 12 bit YUV 420, Y, UV plane */
237 IPU_FW_ISYS_FRAME_FORMAT_NV12_16, /* 16 bit YUV 420, Y, UV plane */
238 IPU_FW_ISYS_FRAME_FORMAT_NV12_TILEY, /* 12 bit YUV 420,
239 * Intel proprietary tiled format,
240 * TileY
241 */
242 IPU_FW_ISYS_FRAME_FORMAT_NV16, /* 16 bit YUV 422, Y, UV plane */
243 IPU_FW_ISYS_FRAME_FORMAT_NV21, /* 12 bit YUV 420, Y, VU plane */
244 IPU_FW_ISYS_FRAME_FORMAT_NV61, /* 16 bit YUV 422, Y, VU plane */
245 IPU_FW_ISYS_FRAME_FORMAT_YV12, /* 12 bit YUV 420, Y, V, U plane */
246 IPU_FW_ISYS_FRAME_FORMAT_YV16, /* 16 bit YUV 422, Y, V, U plane */
247 IPU_FW_ISYS_FRAME_FORMAT_YUV420, /* 12 bit YUV 420, Y, U, V plane */
248 IPU_FW_ISYS_FRAME_FORMAT_YUV420_10, /* yuv420, 10 bits per subpixel */
249 IPU_FW_ISYS_FRAME_FORMAT_YUV420_12, /* yuv420, 12 bits per subpixel */
250 IPU_FW_ISYS_FRAME_FORMAT_YUV420_14, /* yuv420, 14 bits per subpixel */
251 IPU_FW_ISYS_FRAME_FORMAT_YUV420_16, /* yuv420, 16 bits per subpixel */
252 IPU_FW_ISYS_FRAME_FORMAT_YUV422, /* 16 bit YUV 422, Y, U, V plane */
253 IPU_FW_ISYS_FRAME_FORMAT_YUV422_16, /* yuv422, 16 bits per subpixel */
254 IPU_FW_ISYS_FRAME_FORMAT_UYVY, /* 16 bit YUV 422, UYVY interleaved */
255 IPU_FW_ISYS_FRAME_FORMAT_YUYV, /* 16 bit YUV 422, YUYV interleaved */
256 IPU_FW_ISYS_FRAME_FORMAT_YUV444, /* 24 bit YUV 444, Y, U, V plane */
257 IPU_FW_ISYS_FRAME_FORMAT_YUV_LINE, /* Internal format, 2 y lines
258 * followed by a uvinterleaved line
259 */
260 IPU_FW_ISYS_FRAME_FORMAT_RAW8, /* RAW8, 1 plane */
261 IPU_FW_ISYS_FRAME_FORMAT_RAW10, /* RAW10, 1 plane */
262 IPU_FW_ISYS_FRAME_FORMAT_RAW12, /* RAW12, 1 plane */
263 IPU_FW_ISYS_FRAME_FORMAT_RAW14, /* RAW14, 1 plane */
264 IPU_FW_ISYS_FRAME_FORMAT_RAW16, /* RAW16, 1 plane */
265 IPU_FW_ISYS_FRAME_FORMAT_RGB565, /* 16 bit RGB, 1 plane. Each 3 sub
266 * pixels are packed into one 16 bit
267 * value, 5 bits for R, 6 bits
268 * for G and 5 bits for B.
269 */
270
271 IPU_FW_ISYS_FRAME_FORMAT_PLANAR_RGB888, /* 24 bit RGB, 3 planes */
272 IPU_FW_ISYS_FRAME_FORMAT_RGBA888, /* 32 bit RGBA, 1 plane,
273 * A=Alpha (alpha is unused)
274 */
275 IPU_FW_ISYS_FRAME_FORMAT_QPLANE6, /* Internal, for advanced ISP */
276 IPU_FW_ISYS_FRAME_FORMAT_BINARY_8, /* byte stream, used for jpeg. */
277 N_IPU_FW_ISYS_FRAME_FORMAT
278};
279
280/* Temporary for driver compatibility */
281#define IPU_FW_ISYS_FRAME_FORMAT_RAW (IPU_FW_ISYS_FRAME_FORMAT_RAW16)
282
283enum ipu_fw_isys_mipi_compression_type {
284 IPU_FW_ISYS_MIPI_COMPRESSION_TYPE_NO_COMPRESSION = 0,
285 IPU_FW_ISYS_MIPI_COMPRESSION_TYPE_10_8_10_TYPE1,
286 IPU_FW_ISYS_MIPI_COMPRESSION_TYPE_10_8_10_TYPE2,
287 IPU_FW_ISYS_MIPI_COMPRESSION_TYPE_10_7_10_TYPE1,
288 IPU_FW_ISYS_MIPI_COMPRESSION_TYPE_10_7_10_TYPE2,
289 IPU_FW_ISYS_MIPI_COMPRESSION_TYPE_10_6_10_TYPE1,
290 IPU_FW_ISYS_MIPI_COMPRESSION_TYPE_10_6_10_TYPE2,
291 IPU_FW_ISYS_MIPI_COMPRESSION_TYPE_12_8_12_TYPE1,
292 IPU_FW_ISYS_MIPI_COMPRESSION_TYPE_12_8_12_TYPE2,
293 IPU_FW_ISYS_MIPI_COMPRESSION_TYPE_12_7_12_TYPE1,
294 IPU_FW_ISYS_MIPI_COMPRESSION_TYPE_12_7_12_TYPE2,
295 IPU_FW_ISYS_MIPI_COMPRESSION_TYPE_12_6_12_TYPE1,
296 IPU_FW_ISYS_MIPI_COMPRESSION_TYPE_12_6_12_TYPE2,
297 IPU_FW_ISYS_MIPI_COMPRESSION_TYPE_12_10_12_TYPE1,
298 IPU_FW_ISYS_MIPI_COMPRESSION_TYPE_12_10_12_TYPE2,
299 N_IPU_FW_ISYS_MIPI_COMPRESSION_TYPE,
300};
301
302/**
303 * Supported MIPI data type. Keep in sync array in ipu_fw_isys_private.c
304 */
305enum ipu_fw_isys_mipi_data_type {
306 /** SYNCHRONIZATION SHORT PACKET DATA TYPES */
307 IPU_FW_ISYS_MIPI_DATA_TYPE_FRAME_START_CODE = 0x00,
308 IPU_FW_ISYS_MIPI_DATA_TYPE_FRAME_END_CODE = 0x01,
309 IPU_FW_ISYS_MIPI_DATA_TYPE_LINE_START_CODE = 0x02, /* Optional */
310 IPU_FW_ISYS_MIPI_DATA_TYPE_LINE_END_CODE = 0x03, /* Optional */
311 /** Reserved 0x04-0x07 */
312 IPU_FW_ISYS_MIPI_DATA_TYPE_RESERVED_0x04 = 0x04,
313 IPU_FW_ISYS_MIPI_DATA_TYPE_RESERVED_0x05 = 0x05,
314 IPU_FW_ISYS_MIPI_DATA_TYPE_RESERVED_0x06 = 0x06,
315 IPU_FW_ISYS_MIPI_DATA_TYPE_RESERVED_0x07 = 0x07,
316 /** GENERIC SHORT PACKET DATA TYPES */
317 /** They are used to keep the timing information for
318 * the opening/closing of shutters,
319 * triggering of flashes and etc.
320 */
321 /* Generic Short Packet Codes 1 - 8 */
322 IPU_FW_ISYS_MIPI_DATA_TYPE_GENERIC_SHORT1 = 0x08,
323 IPU_FW_ISYS_MIPI_DATA_TYPE_GENERIC_SHORT2 = 0x09,
324 IPU_FW_ISYS_MIPI_DATA_TYPE_GENERIC_SHORT3 = 0x0A,
325 IPU_FW_ISYS_MIPI_DATA_TYPE_GENERIC_SHORT4 = 0x0B,
326 IPU_FW_ISYS_MIPI_DATA_TYPE_GENERIC_SHORT5 = 0x0C,
327 IPU_FW_ISYS_MIPI_DATA_TYPE_GENERIC_SHORT6 = 0x0D,
328 IPU_FW_ISYS_MIPI_DATA_TYPE_GENERIC_SHORT7 = 0x0E,
329 IPU_FW_ISYS_MIPI_DATA_TYPE_GENERIC_SHORT8 = 0x0F,
330 /** GENERIC LONG PACKET DATA TYPES */
331 IPU_FW_ISYS_MIPI_DATA_TYPE_NULL = 0x10,
332 IPU_FW_ISYS_MIPI_DATA_TYPE_BLANKING_DATA = 0x11,
333 /* Embedded 8-bit non Image Data */
334 IPU_FW_ISYS_MIPI_DATA_TYPE_EMBEDDED = 0x12,
335 /** Reserved 0x13-0x17 */
336 IPU_FW_ISYS_MIPI_DATA_TYPE_RESERVED_0x13 = 0x13,
337 IPU_FW_ISYS_MIPI_DATA_TYPE_RESERVED_0x14 = 0x14,
338 IPU_FW_ISYS_MIPI_DATA_TYPE_RESERVED_0x15 = 0x15,
339 IPU_FW_ISYS_MIPI_DATA_TYPE_RESERVED_0x16 = 0x16,
340 IPU_FW_ISYS_MIPI_DATA_TYPE_RESERVED_0x17 = 0x17,
341 /** YUV DATA TYPES */
342 /* 8 bits per subpixel */
343 IPU_FW_ISYS_MIPI_DATA_TYPE_YUV420_8 = 0x18,
344 /* 10 bits per subpixel */
345 IPU_FW_ISYS_MIPI_DATA_TYPE_YUV420_10 = 0x19,
346 /* 8 bits per subpixel */
347 IPU_FW_ISYS_MIPI_DATA_TYPE_YUV420_8_LEGACY = 0x1A,
348 /** Reserved 0x1B */
349 IPU_FW_ISYS_MIPI_DATA_TYPE_RESERVED_0x1B = 0x1B,
350 /* YUV420 8-bit Chroma Shifted Pixel Sampling) */
351 IPU_FW_ISYS_MIPI_DATA_TYPE_YUV420_8_SHIFT = 0x1C,
352 /* YUV420 8-bit (Chroma Shifted Pixel Sampling) */
353 IPU_FW_ISYS_MIPI_DATA_TYPE_YUV420_10_SHIFT = 0x1D,
354 /* UYVY..UVYV, 8 bits per subpixel */
355 IPU_FW_ISYS_MIPI_DATA_TYPE_YUV422_8 = 0x1E,
356 /* UYVY..UVYV, 10 bits per subpixel */
357 IPU_FW_ISYS_MIPI_DATA_TYPE_YUV422_10 = 0x1F,
358 /** RGB DATA TYPES */
359 /* BGR..BGR, 4 bits per subpixel */
360 IPU_FW_ISYS_MIPI_DATA_TYPE_RGB_444 = 0x20,
361 /* BGR..BGR, 5 bits per subpixel */
362 IPU_FW_ISYS_MIPI_DATA_TYPE_RGB_555 = 0x21,
363 /* BGR..BGR, 5 bits B and R, 6 bits G */
364 IPU_FW_ISYS_MIPI_DATA_TYPE_RGB_565 = 0x22,
365 /* BGR..BGR, 6 bits per subpixel */
366 IPU_FW_ISYS_MIPI_DATA_TYPE_RGB_666 = 0x23,
367 /* BGR..BGR, 8 bits per subpixel */
368 IPU_FW_ISYS_MIPI_DATA_TYPE_RGB_888 = 0x24,
369 /** Reserved 0x25-0x27 */
370 IPU_FW_ISYS_MIPI_DATA_TYPE_RESERVED_0x25 = 0x25,
371 IPU_FW_ISYS_MIPI_DATA_TYPE_RESERVED_0x26 = 0x26,
372 IPU_FW_ISYS_MIPI_DATA_TYPE_RESERVED_0x27 = 0x27,
373 /** RAW DATA TYPES */
374 /* RAW data, 6 - 14 bits per pixel */
375 IPU_FW_ISYS_MIPI_DATA_TYPE_RAW_6 = 0x28,
376 IPU_FW_ISYS_MIPI_DATA_TYPE_RAW_7 = 0x29,
377 IPU_FW_ISYS_MIPI_DATA_TYPE_RAW_8 = 0x2A,
378 IPU_FW_ISYS_MIPI_DATA_TYPE_RAW_10 = 0x2B,
379 IPU_FW_ISYS_MIPI_DATA_TYPE_RAW_12 = 0x2C,
380 IPU_FW_ISYS_MIPI_DATA_TYPE_RAW_14 = 0x2D,
381 /** Reserved 0x2E-2F are used with assigned meaning */
382 /* RAW data, 16 bits per pixel, not specified in CSI-MIPI standard */
383 IPU_FW_ISYS_MIPI_DATA_TYPE_RAW_16 = 0x2E,
384 /* Binary byte stream, which is target at JPEG,
385 * not specified in CSI-MIPI standard
386 */
387 IPU_FW_ISYS_MIPI_DATA_TYPE_BINARY_8 = 0x2F,
388
389 /** USER DEFINED 8-BIT DATA TYPES */
390 /** For example, the data transmitter (e.g. the SoC sensor)
391 * can keep the JPEG data as
392 * the User Defined Data Type 4 and the MPEG data as the
393 * User Defined Data Type 7.
394 */
395 IPU_FW_ISYS_MIPI_DATA_TYPE_USER_DEF1 = 0x30,
396 IPU_FW_ISYS_MIPI_DATA_TYPE_USER_DEF2 = 0x31,
397 IPU_FW_ISYS_MIPI_DATA_TYPE_USER_DEF3 = 0x32,
398 IPU_FW_ISYS_MIPI_DATA_TYPE_USER_DEF4 = 0x33,
399 IPU_FW_ISYS_MIPI_DATA_TYPE_USER_DEF5 = 0x34,
400 IPU_FW_ISYS_MIPI_DATA_TYPE_USER_DEF6 = 0x35,
401 IPU_FW_ISYS_MIPI_DATA_TYPE_USER_DEF7 = 0x36,
402 IPU_FW_ISYS_MIPI_DATA_TYPE_USER_DEF8 = 0x37,
403 /** Reserved 0x38-0x3F */
404 IPU_FW_ISYS_MIPI_DATA_TYPE_RESERVED_0x38 = 0x38,
405 IPU_FW_ISYS_MIPI_DATA_TYPE_RESERVED_0x39 = 0x39,
406 IPU_FW_ISYS_MIPI_DATA_TYPE_RESERVED_0x3A = 0x3A,
407 IPU_FW_ISYS_MIPI_DATA_TYPE_RESERVED_0x3B = 0x3B,
408 IPU_FW_ISYS_MIPI_DATA_TYPE_RESERVED_0x3C = 0x3C,
409 IPU_FW_ISYS_MIPI_DATA_TYPE_RESERVED_0x3D = 0x3D,
410 IPU_FW_ISYS_MIPI_DATA_TYPE_RESERVED_0x3E = 0x3E,
411 IPU_FW_ISYS_MIPI_DATA_TYPE_RESERVED_0x3F = 0x3F,
412
413 /* Keep always last and max value */
414 N_IPU_FW_ISYS_MIPI_DATA_TYPE = 0x40
415};
416
417/** enum ipu_fw_isys_pin_type: output pin buffer types.
418 * Buffers can be queued and de-queued to hand them over between IA and ISYS
419 */
420enum ipu_fw_isys_pin_type {
421 /* Captured as MIPI packets */
422 IPU_FW_ISYS_PIN_TYPE_MIPI = 0,
423 /* Captured through the RAW path */
424 IPU_FW_ISYS_PIN_TYPE_RAW_NS = 1,
425 /* Captured through the SoC path */
426 IPU_FW_ISYS_PIN_TYPE_RAW_SOC = 3,
427 /* Reserved for future use, maybe short packets */
428 IPU_FW_ISYS_PIN_TYPE_METADATA_0 = 4,
429 /* Reserved for future use */
430 IPU_FW_ISYS_PIN_TYPE_METADATA_1 = 5,
431 /* Keep always last and max value */
432 N_IPU_FW_ISYS_PIN_TYPE
433};
434
435/**
436 * enum ipu_fw_isys_mipi_store_mode. Describes if long MIPI packets reach
437 * MIPI SRAM with the long packet header or
438 * if not, then only option is to capture it with pin type MIPI.
439 */
440enum ipu_fw_isys_mipi_store_mode {
441 IPU_FW_ISYS_MIPI_STORE_MODE_NORMAL = 0,
442 IPU_FW_ISYS_MIPI_STORE_MODE_DISCARD_LONG_HEADER,
443 N_IPU_FW_ISYS_MIPI_STORE_MODE
444};
445
446/**
447 * ISYS capture mode and sensor enums
448 * Used for Tobii sensor, if doubt, use default value 0
449 */
450
451enum ipu_fw_isys_capture_mode {
452 IPU_FW_ISYS_CAPTURE_MODE_REGULAR = 0,
453 IPU_FW_ISYS_CAPTURE_MODE_BURST,
454 N_IPU_FW_ISYS_CAPTURE_MODE,
455};
456
457enum ipu_fw_isys_sensor_mode {
458 IPU_FW_ISYS_SENSOR_MODE_NORMAL = 0,
459 IPU_FW_ISYS_SENSOR_MODE_TOBII,
460 N_IPU_FW_ISYS_SENSOR_MODE,
461};
462
463/**
464 * enum ipu_fw_isys_error. Describes the error type detected by the FW
465 */
466enum ipu_fw_isys_error {
467 IPU_FW_ISYS_ERROR_NONE = 0, /* No details */
468 IPU_FW_ISYS_ERROR_FW_INTERNAL_CONSISTENCY, /* enum */
469 IPU_FW_ISYS_ERROR_HW_CONSISTENCY, /* enum */
470 IPU_FW_ISYS_ERROR_DRIVER_INVALID_COMMAND_SEQUENCE, /* enum */
471 IPU_FW_ISYS_ERROR_DRIVER_INVALID_DEVICE_CONFIGURATION, /* enum */
472 IPU_FW_ISYS_ERROR_DRIVER_INVALID_STREAM_CONFIGURATION, /* enum */
473 IPU_FW_ISYS_ERROR_DRIVER_INVALID_FRAME_CONFIGURATION, /* enum */
474 IPU_FW_ISYS_ERROR_INSUFFICIENT_RESOURCES, /* enum */
475 IPU_FW_ISYS_ERROR_HW_REPORTED_STR2MMIO, /* HW code */
476 IPU_FW_ISYS_ERROR_HW_REPORTED_SIG2CIO, /* HW code */
477 IPU_FW_ISYS_ERROR_SENSOR_FW_SYNC, /* enum */
478 IPU_FW_ISYS_ERROR_STREAM_IN_SUSPENSION, /* FW code */
479 IPU_FW_ISYS_ERROR_RESPONSE_QUEUE_FULL, /* FW code */
480 N_IPU_FW_ISYS_ERROR
481};
482
483/**
484 * enum ipu_fw_proxy_error. Describes the error type for
485 * the proxy detected by the FW
486 */
487enum ipu_fw_proxy_error {
488 IPU_FW_PROXY_ERROR_NONE = 0,
489 IPU_FW_PROXY_ERROR_INVALID_WRITE_REGION,
490 IPU_FW_PROXY_ERROR_INVALID_WRITE_OFFSET,
491 N_IPU_FW_PROXY_ERROR
492};
493
494struct ipu_isys;
495
496struct ipu6_fw_isys_buffer_partition_abi {
497 u32 num_gda_pages[IPU6_STREAM_ID_MAX];
498};
499
500struct ipu6_fw_isys_fw_config {
501 struct ipu6_fw_isys_buffer_partition_abi buffer_partition;
502 u32 num_send_queues[N_IPU_FW_ISYS_QUEUE_TYPE];
503 u32 num_recv_queues[N_IPU_FW_ISYS_QUEUE_TYPE];
504};
505
506struct ipu6se_fw_isys_buffer_partition_abi {
507 u32 num_gda_pages[IPU6SE_STREAM_ID_MAX];
508};
509
510struct ipu6se_fw_isys_fw_config {
511 struct ipu6se_fw_isys_buffer_partition_abi buffer_partition;
512 u32 num_send_queues[N_IPU_FW_ISYS_QUEUE_TYPE];
513 u32 num_recv_queues[N_IPU_FW_ISYS_QUEUE_TYPE];
514};
515
516/**
517 * struct ipu_fw_isys_resolution_abi: Generic resolution structure.
518 * @Width
519 * @Height
520 */
521struct ipu_fw_isys_resolution_abi {
522 u32 width;
523 u32 height;
524};
525
526/**
527 * struct ipu_fw_isys_output_pin_payload_abi
528 * @out_buf_id: Points to output pin buffer - buffer identifier
529 * @addr: Points to output pin buffer - CSS Virtual Address
530 * @compress: Request frame compression (1), or not (0)
531 */
532struct ipu_fw_isys_output_pin_payload_abi {
533 u64 out_buf_id;
534 u32 addr;
535 u32 compress;
536};
537
538/**
539 * struct ipu_fw_isys_output_pin_info_abi
540 * @output_res: output pin resolution
541 * @stride: output stride in Bytes (not valid for statistics)
542 * @watermark_in_lines: pin watermark level in lines
543 * @payload_buf_size: minimum size in Bytes of all buffers that will be
544 * supplied for capture on this pin
545 * @send_irq: assert if pin event should trigger irq
546 * @pt: pin type -real format "enum ipu_fw_isys_pin_type"
547 * @ft: frame format type -real format "enum ipu_fw_isys_frame_format_type"
548 * @input_pin_id: related input pin id
549 * @reserve_compression: reserve compression resources for pin
550 */
551struct ipu_fw_isys_output_pin_info_abi {
552 struct ipu_fw_isys_resolution_abi output_res;
553 u32 stride;
554 u32 watermark_in_lines;
555 u32 payload_buf_size;
556 u32 ts_offsets[IPU_PIN_PLANES_MAX];
557 u32 s2m_pixel_soc_pixel_remapping;
558 u32 csi_be_soc_pixel_remapping;
559 u8 send_irq;
560 u8 input_pin_id;
561 u8 pt;
562 u8 ft;
563 u8 reserved;
564 u8 reserve_compression;
565 u8 snoopable;
566 u8 error_handling_enable;
567 u32 sensor_type;
568};
569
570/**
571 * struct ipu_fw_isys_param_pin_abi
572 * @param_buf_id: Points to param port buffer - buffer identifier
573 * @addr: Points to param pin buffer - CSS Virtual Address
574 */
575struct ipu_fw_isys_param_pin_abi {
576 u64 param_buf_id;
577 u32 addr;
578};
579
580/**
581 * struct ipu_fw_isys_input_pin_info_abi
582 * @input_res: input resolution
583 * @dt: mipi data type ((enum ipu_fw_isys_mipi_data_type)
584 * @mipi_store_mode: defines if legacy long packet header will be stored or
585 * discarded if discarded, output pin pin type for this
586 * input pin can only be MIPI
587 * (enum ipu_fw_isys_mipi_store_mode)
588 * @bits_per_pix: native bits per pixel
589 * @mapped_dt: actual data type from sensor
590 * @mipi_decompression: defines which compression will be in mipi backend
591
592 * @crop_first_and_last_lines Control whether to crop the
593 * first and last line of the
594 * input image. Crop done by HW
595 * device.
596 * @capture_mode: mode of capture, regular or burst, default value is regular
597 */
598struct ipu_fw_isys_input_pin_info_abi {
599 struct ipu_fw_isys_resolution_abi input_res;
600 u8 dt;
601 u8 mipi_store_mode;
602 u8 bits_per_pix;
603 u8 mapped_dt;
604 u8 mipi_decompression;
605 u8 crop_first_and_last_lines;
606 u8 capture_mode;
607};
608
609/**
610 * struct ipu_fw_isys_cropping_abi - cropping coordinates
611 */
612struct ipu_fw_isys_cropping_abi {
613 s32 top_offset;
614 s32 left_offset;
615 s32 bottom_offset;
616 s32 right_offset;
617};
618
619/**
620 * struct ipu_fw_isys_stream_cfg_data_abi
621 * ISYS stream configuration data structure
622 * @crop: defines cropping resolution for the
623 * maximum number of input pins which can be cropped,
624 * it is directly mapped to the HW devices
625 * @input_pins: input pin descriptors
626 * @output_pins: output pin descriptors
627 * @compfmt: de-compression setting for User Defined Data
628 * @nof_input_pins: number of input pins
629 * @nof_output_pins: number of output pins
630 * @send_irq_sof_discarded: send irq on discarded frame sof response
631 * - if '1' it will override the send_resp_sof_discarded
632 * and send the response
633 * - if '0' the send_resp_sof_discarded will determine
634 * whether to send the response
635 * @send_irq_eof_discarded: send irq on discarded frame eof response
636 * - if '1' it will override the send_resp_eof_discarded
637 * and send the response
638 * - if '0' the send_resp_eof_discarded will determine
639 * whether to send the response
640 * @send_resp_sof_discarded: send response for discarded frame sof detected,
641 * used only when send_irq_sof_discarded is '0'
642 * @send_resp_eof_discarded: send response for discarded frame eof detected,
643 * used only when send_irq_eof_discarded is '0'
644 * @src: Stream source index e.g. MIPI_generator_0, CSI2-rx_1
645 * @vc: MIPI Virtual Channel (up to 4 virtual per physical channel)
646 * @isl_use: indicates whether stream requires ISL and how
647 * @sensor_type: type of connected sensor, tobii or others, default is 0
648 */
649struct ipu_fw_isys_stream_cfg_data_abi {
650 struct ipu_fw_isys_cropping_abi crop;
651 struct ipu_fw_isys_input_pin_info_abi input_pins[IPU_MAX_IPINS];
652 struct ipu_fw_isys_output_pin_info_abi output_pins[IPU_MAX_OPINS];
653 u32 compfmt;
654 u8 nof_input_pins;
655 u8 nof_output_pins;
656 u8 send_irq_sof_discarded;
657 u8 send_irq_eof_discarded;
658 u8 send_resp_sof_discarded;
659 u8 send_resp_eof_discarded;
660 u8 src;
661 u8 vc;
662 u8 isl_use;
663 u8 sensor_type;
664};
665
666/**
667 * struct ipu_fw_isys_frame_buff_set - frame buffer set
668 * @output_pins: output pin addresses
669 * @send_irq_sof: send irq on frame sof response
670 * - if '1' it will override the send_resp_sof and
671 * send the response
672 * - if '0' the send_resp_sof will determine whether to
673 * send the response
674 * @send_irq_eof: send irq on frame eof response
675 * - if '1' it will override the send_resp_eof and
676 * send the response
677 * - if '0' the send_resp_eof will determine whether to
678 * send the response
679 * @send_resp_sof: send response for frame sof detected,
680 * used only when send_irq_sof is '0'
681 * @send_resp_eof: send response for frame eof detected,
682 * used only when send_irq_eof is '0'
683 * @send_resp_capture_ack: send response for capture ack event
684 * @send_resp_capture_done: send response for capture done event
685 */
686struct ipu_fw_isys_frame_buff_set_abi {
687 struct ipu_fw_isys_output_pin_payload_abi output_pins[IPU_MAX_OPINS];
688 u8 send_irq_sof;
689 u8 send_irq_eof;
690 u8 send_irq_capture_ack;
691 u8 send_irq_capture_done;
692 u8 send_resp_sof;
693 u8 send_resp_eof;
694 u8 send_resp_capture_ack;
695 u8 send_resp_capture_done;
696 u8 reserved;
697};
698
699/**
700 * struct ipu_fw_isys_error_info_abi
701 * @error: error code if something went wrong
702 * @error_details: depending on error code, it may contain additional error info
703 */
704struct ipu_fw_isys_error_info_abi {
705 enum ipu_fw_isys_error error;
706 u32 error_details;
707};
708
709/**
710 * struct ipu_fw_isys_resp_info_comm
711 * @pin: this var is only valid for pin event related responses,
712 * contains pin addresses
713 * @error_info: error information from the FW
714 * @timestamp: Time information for event if available
715 * @stream_handle: stream id the response corresponds to
716 * @type: response type (enum ipu_fw_isys_resp_type)
717 * @pin_id: pin id that the pin payload corresponds to
718 */
719struct ipu_fw_isys_resp_info_abi {
720 u64 buf_id;
721 struct ipu_fw_isys_output_pin_payload_abi pin;
722 struct ipu_fw_isys_error_info_abi error_info;
723 u32 timestamp[2];
724 u8 stream_handle;
725 u8 type;
726 u8 pin_id;
727 u16 reserved;
728};
729
730/**
731 * struct ipu_fw_isys_proxy_error_info_comm
732 * @proxy_error: error code if something went wrong
733 * @proxy_error_details: depending on error code, it may contain additional
734 * error info
735 */
736struct ipu_fw_isys_proxy_error_info_abi {
737 enum ipu_fw_proxy_error error;
738 u32 error_details;
739};
740
741struct ipu_fw_isys_proxy_resp_info_abi {
742 u32 request_id;
743 struct ipu_fw_isys_proxy_error_info_abi error_info;
744};
745
746/**
747 * struct ipu_fw_proxy_write_queue_token
748 * @request_id: update id for the specific proxy write request
749 * @region_index: Region id for the proxy write request
750 * @offset: Offset of the write request according to the base address
751 * of the region
752 * @value: Value that is requested to be written with the proxy write request
753 */
754struct ipu_fw_proxy_write_queue_token {
755 u32 request_id;
756 u32 region_index;
757 u32 offset;
758 u32 value;
759};
760
761/* From here on type defines not coming from the ISYSAPI interface */
762
763/**
764 * struct ipu_fw_resp_queue_token
765 */
766struct ipu_fw_resp_queue_token {
767 struct ipu_fw_isys_resp_info_abi resp_info;
768};
769
770/**
771 * struct ipu_fw_send_queue_token
772 */
773struct ipu_fw_send_queue_token {
774 u64 buf_handle;
775 u32 payload;
776 u16 send_type;
777 u16 stream_id;
778};
779
780/**
781 * struct ipu_fw_proxy_resp_queue_token
782 */
783struct ipu_fw_proxy_resp_queue_token {
784 struct ipu_fw_isys_proxy_resp_info_abi proxy_resp_info;
785};
786
787/**
788 * struct ipu_fw_proxy_send_queue_token
789 */
790struct ipu_fw_proxy_send_queue_token {
791 u32 request_id;
792 u32 region_index;
793 u32 offset;
794 u32 value;
795};
796
797void ipu_fw_isys_set_params(struct ipu_fw_isys_stream_cfg_data_abi *stream_cfg);
798
799void ipu_fw_isys_dump_stream_cfg(struct device *dev,
800 struct ipu_fw_isys_stream_cfg_data_abi
801 *stream_cfg);
802void ipu_fw_isys_dump_frame_buff_set(struct device *dev,
803 struct ipu_fw_isys_frame_buff_set_abi *buf,
804 unsigned int outputs);
805int ipu_fw_isys_init(struct ipu_isys *isys, unsigned int num_streams);
806int ipu_fw_isys_close(struct ipu_isys *isys);
807int ipu_fw_isys_simple_cmd(struct ipu_isys *isys,
808 const unsigned int stream_handle,
809 enum ipu_fw_isys_send_type send_type);
810int ipu_fw_isys_complex_cmd(struct ipu_isys *isys,
811 const unsigned int stream_handle,
812 void *cpu_mapped_buf,
813 dma_addr_t dma_mapped_buf,
814 size_t size, enum ipu_fw_isys_send_type send_type);
815int ipu_fw_isys_send_proxy_token(struct ipu_isys *isys,
816 unsigned int req_id,
817 unsigned int index,
818 unsigned int offset, u32 value);
819void ipu_fw_isys_cleanup(struct ipu_isys *isys);
820struct ipu_fw_isys_resp_info_abi *
821ipu_fw_isys_get_resp(void *context, unsigned int queue,
822 struct ipu_fw_isys_resp_info_abi *response);
823void ipu_fw_isys_put_resp(void *context, unsigned int queue);
824#endif
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