[mirror_ubuntu-bionic-kernel.git] / drivers / media / pci / meye / meye.h

/*
 * Motion Eye video4linux driver for Sony Vaio PictureBook
 *
 * Copyright (C) 2001-2004 Stelian Pop <stelian@popies.net>
 *
 * Copyright (C) 2001-2002 Alcôve <www.alcove.com>
 *
 * Copyright (C) 2000 Andrew Tridgell <tridge@valinux.com>
 *
 * Earlier work by Werner Almesberger, Paul `Rusty' Russell and Paul Mackerras.
 *
 * Some parts borrowed from various video4linux drivers, especially
 * bttv-driver.c and zoran.c, see original files for credits.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#ifndef _MEYE_PRIV_H_
#define _MEYE_PRIV_H_

#define MEYE_DRIVER_MAJORVERSION	 1
#define MEYE_DRIVER_MINORVERSION	14

#define MEYE_DRIVER_VERSION __stringify(MEYE_DRIVER_MAJORVERSION) "." \
			    __stringify(MEYE_DRIVER_MINORVERSION)

#include <linux/types.h>
#include <linux/pci.h>
#include <linux/kfifo.h>
#include <media/v4l2-ctrls.h>

/****************************************************************************/
/* Motion JPEG chip registers                                               */
/****************************************************************************/

/* Motion JPEG chip PCI configuration registers */
#define MCHIP_PCI_POWER_CSR		0x54
#define MCHIP_PCI_MCORE_STATUS		0x60		/* see HIC_STATUS   */
#define MCHIP_PCI_HOSTUSEREQ_SET	0x64
#define MCHIP_PCI_HOSTUSEREQ_CLR	0x68
#define MCHIP_PCI_LOWPOWER_SET		0x6c
#define MCHIP_PCI_LOWPOWER_CLR		0x70
#define MCHIP_PCI_SOFTRESET_SET		0x74

/* Motion JPEG chip memory mapped registers */
#define MCHIP_MM_REGS			0x200		/* 512 bytes        */
#define MCHIP_REG_TIMEOUT		1000		/* reg access, ~us  */
#define MCHIP_MCC_VRJ_TIMEOUT		1000		/* MCC & VRJ access */

#define MCHIP_MM_PCI_MODE		0x00		/* PCI access mode */
#define MCHIP_MM_PCI_MODE_RETRY		0x00000001	/* retry mode */
#define MCHIP_MM_PCI_MODE_MASTER	0x00000002	/* master access */
#define MCHIP_MM_PCI_MODE_READ_LINE	0x00000004	/* read line */

#define MCHIP_MM_INTA			0x04		/* Int status/mask */
#define MCHIP_MM_INTA_MCC		0x00000001	/* MCC interrupt */
#define MCHIP_MM_INTA_VRJ		0x00000002	/* VRJ interrupt */
#define MCHIP_MM_INTA_HIC_1		0x00000004	/* one frame done */
#define MCHIP_MM_INTA_HIC_1_MASK	0x00000400	/* 1: enable */
#define MCHIP_MM_INTA_HIC_END		0x00000008	/* all frames done */
#define MCHIP_MM_INTA_HIC_END_MASK	0x00000800
#define MCHIP_MM_INTA_JPEG		0x00000010	/* decompress. error */
#define MCHIP_MM_INTA_JPEG_MASK		0x00001000
#define MCHIP_MM_INTA_CAPTURE		0x00000020	/* capture end */
#define MCHIP_MM_INTA_PCI_ERR		0x00000040	/* PCI error */
#define MCHIP_MM_INTA_PCI_ERR_MASK	0x00004000

#define MCHIP_MM_PT_ADDR		0x08		/* page table address*/
							/* n*4kB */
#define MCHIP_NB_PAGES			1024		/* pages for display */
#define MCHIP_NB_PAGES_MJPEG		256		/* pages for mjpeg */

#define MCHIP_MM_FIR(n)			(0x0c+(n)*4)	/* Frame info 0-3 */
#define MCHIP_MM_FIR_RDY		0x00000001	/* frame ready */
#define MCHIP_MM_FIR_FAILFR_MASK	0xf8000000	/* # of failed frames */
#define MCHIP_MM_FIR_FAILFR_SHIFT	27

	/* continuous comp/decomp mode */
#define MCHIP_MM_FIR_C_ENDL_MASK	0x000007fe	/* end DW [10] */
#define MCHIP_MM_FIR_C_ENDL_SHIFT	1
#define MCHIP_MM_FIR_C_ENDP_MASK	0x0007f800	/* end page [8] */
#define MCHIP_MM_FIR_C_ENDP_SHIFT	11
#define MCHIP_MM_FIR_C_STARTP_MASK	0x07f80000	/* start page [8] */
#define MCHIP_MM_FIR_C_STARTP_SHIFT	19

	/* continuous picture output mode */
#define MCHIP_MM_FIR_O_STARTP_MASK	0x7ffe0000	/* start page [10] */
#define MCHIP_MM_FIR_O_STARTP_SHIFT	17

#define MCHIP_MM_FIFO_DATA		0x1c		/* PCI TGT FIFO data */
#define MCHIP_MM_FIFO_STATUS		0x20		/* PCI TGT FIFO stat */
#define MCHIP_MM_FIFO_MASK		0x00000003
#define MCHIP_MM_FIFO_WAIT_OR_READY	0x00000002      /* Bits common to WAIT & READY*/
#define MCHIP_MM_FIFO_IDLE		0x0		/* HIC idle */
#define MCHIP_MM_FIFO_IDLE1		0x1		/* idem ??? */
#define	MCHIP_MM_FIFO_WAIT		0x2		/* wait request */
#define MCHIP_MM_FIFO_READY		0x3		/* data ready */

#define MCHIP_HIC_HOST_USEREQ		0x40		/* host uses MCORE */

#define MCHIP_HIC_TP_BUSY		0x44		/* taking picture */

#define MCHIP_HIC_PIC_SAVED		0x48		/* pic in SDRAM */

#define MCHIP_HIC_LOWPOWER		0x4c		/* clock stopped */

#define MCHIP_HIC_CTL			0x50		/* HIC control */
#define MCHIP_HIC_CTL_SOFT_RESET	0x00000001	/* MCORE reset */
#define MCHIP_HIC_CTL_MCORE_RDY		0x00000002	/* MCORE ready */

#define MCHIP_HIC_CMD			0x54		/* HIC command */
#define MCHIP_HIC_CMD_BITS		0x00000003      /* cmd width=[1:0]*/
#define MCHIP_HIC_CMD_NOOP		0x0
#define MCHIP_HIC_CMD_START		0x1
#define MCHIP_HIC_CMD_STOP		0x2

#define MCHIP_HIC_MODE			0x58
#define MCHIP_HIC_MODE_NOOP		0x0
#define MCHIP_HIC_MODE_STILL_CAP	0x1		/* still pic capt */
#define MCHIP_HIC_MODE_DISPLAY		0x2		/* display */
#define MCHIP_HIC_MODE_STILL_COMP	0x3		/* still pic comp. */
#define MCHIP_HIC_MODE_STILL_DECOMP	0x4		/* still pic decomp. */
#define MCHIP_HIC_MODE_CONT_COMP	0x5		/* cont capt+comp */
#define MCHIP_HIC_MODE_CONT_DECOMP	0x6		/* cont decomp+disp */
#define MCHIP_HIC_MODE_STILL_OUT	0x7		/* still pic output */
#define MCHIP_HIC_MODE_CONT_OUT		0x8		/* cont output */

#define MCHIP_HIC_STATUS		0x5c
#define MCHIP_HIC_STATUS_MCC_RDY	0x00000001	/* MCC reg acc ok */
#define MCHIP_HIC_STATUS_VRJ_RDY	0x00000002	/* VRJ reg acc ok */
#define MCHIP_HIC_STATUS_IDLE           0x00000003
#define MCHIP_HIC_STATUS_CAPDIS		0x00000004	/* cap/disp in prog */
#define MCHIP_HIC_STATUS_COMPDEC	0x00000008	/* (de)comp in prog */
#define MCHIP_HIC_STATUS_BUSY		0x00000010	/* HIC busy */

#define MCHIP_HIC_S_RATE		0x60		/* MJPEG # frames */

#define MCHIP_HIC_PCI_VFMT		0x64		/* video format */
#define MCHIP_HIC_PCI_VFMT_YVYU		0x00000001	/* 0: V Y' U Y */
							/* 1: Y' V Y U */

#define MCHIP_MCC_CMD			0x80		/* MCC commands */
#define MCHIP_MCC_CMD_INITIAL		0x0		/* idle ? */
#define MCHIP_MCC_CMD_IIC_START_SET	0x1
#define MCHIP_MCC_CMD_IIC_END_SET	0x2
#define MCHIP_MCC_CMD_FM_WRITE		0x3		/* frame memory */
#define MCHIP_MCC_CMD_FM_READ		0x4
#define MCHIP_MCC_CMD_FM_STOP		0x5
#define MCHIP_MCC_CMD_CAPTURE		0x6
#define MCHIP_MCC_CMD_DISPLAY		0x7
#define MCHIP_MCC_CMD_END_DISP		0x8
#define MCHIP_MCC_CMD_STILL_COMP	0x9
#define MCHIP_MCC_CMD_STILL_DECOMP	0xa
#define MCHIP_MCC_CMD_STILL_OUTPUT	0xb
#define MCHIP_MCC_CMD_CONT_OUTPUT	0xc
#define MCHIP_MCC_CMD_CONT_COMP		0xd
#define MCHIP_MCC_CMD_CONT_DECOMP	0xe
#define MCHIP_MCC_CMD_RESET		0xf		/* MCC reset */

#define MCHIP_MCC_IIC_WR		0x84

#define MCHIP_MCC_MCC_WR		0x88

#define MCHIP_MCC_MCC_RD		0x8c

#define MCHIP_MCC_STATUS		0x90
#define MCHIP_MCC_STATUS_CAPT		0x00000001	/* capturing */
#define MCHIP_MCC_STATUS_DISP		0x00000002	/* displaying */
#define MCHIP_MCC_STATUS_COMP		0x00000004	/* compressing */
#define MCHIP_MCC_STATUS_DECOMP		0x00000008	/* decompressing */
#define MCHIP_MCC_STATUS_MCC_WR		0x00000010	/* register ready */
#define MCHIP_MCC_STATUS_MCC_RD		0x00000020	/* register ready */
#define MCHIP_MCC_STATUS_IIC_WR		0x00000040	/* register ready */
#define MCHIP_MCC_STATUS_OUTPUT		0x00000080	/* output in prog */

#define MCHIP_MCC_SIG_POLARITY		0x94
#define MCHIP_MCC_SIG_POL_VS_H		0x00000001	/* VS active-high */
#define MCHIP_MCC_SIG_POL_HS_H		0x00000002	/* HS active-high */
#define MCHIP_MCC_SIG_POL_DOE_H		0x00000004	/* DOE active-high */

#define MCHIP_MCC_IRQ			0x98
#define MCHIP_MCC_IRQ_CAPDIS_STRT	0x00000001	/* cap/disp started */
#define MCHIP_MCC_IRQ_CAPDIS_STRT_MASK	0x00000010
#define MCHIP_MCC_IRQ_CAPDIS_END	0x00000002	/* cap/disp ended */
#define MCHIP_MCC_IRQ_CAPDIS_END_MASK	0x00000020
#define MCHIP_MCC_IRQ_COMPDEC_STRT	0x00000004	/* (de)comp started */
#define MCHIP_MCC_IRQ_COMPDEC_STRT_MASK	0x00000040
#define MCHIP_MCC_IRQ_COMPDEC_END	0x00000008	/* (de)comp ended */
#define MCHIP_MCC_IRQ_COMPDEC_END_MASK	0x00000080

#define MCHIP_MCC_HSTART		0x9c		/* video in */
#define MCHIP_MCC_VSTART		0xa0
#define MCHIP_MCC_HCOUNT		0xa4
#define MCHIP_MCC_VCOUNT		0xa8
#define MCHIP_MCC_R_XBASE		0xac		/* capt/disp */
#define MCHIP_MCC_R_YBASE		0xb0
#define MCHIP_MCC_R_XRANGE		0xb4
#define MCHIP_MCC_R_YRANGE		0xb8
#define MCHIP_MCC_B_XBASE		0xbc		/* comp/decomp */
#define MCHIP_MCC_B_YBASE		0xc0
#define MCHIP_MCC_B_XRANGE		0xc4
#define MCHIP_MCC_B_YRANGE		0xc8

#define MCHIP_MCC_R_SAMPLING		0xcc		/* 1: 1:4 */

#define MCHIP_VRJ_CMD			0x100		/* VRJ commands */

/* VRJ registers (see table 12.2.4) */
#define MCHIP_VRJ_COMPRESSED_DATA	0x1b0
#define MCHIP_VRJ_PIXEL_DATA		0x1b8

#define MCHIP_VRJ_BUS_MODE		0x100
#define MCHIP_VRJ_SIGNAL_ACTIVE_LEVEL	0x108
#define MCHIP_VRJ_PDAT_USE		0x110
#define MCHIP_VRJ_MODE_SPECIFY		0x118
#define MCHIP_VRJ_LIMIT_COMPRESSED_LO	0x120
#define MCHIP_VRJ_LIMIT_COMPRESSED_HI	0x124
#define MCHIP_VRJ_COMP_DATA_FORMAT	0x128
#define MCHIP_VRJ_TABLE_DATA		0x140
#define MCHIP_VRJ_RESTART_INTERVAL	0x148
#define MCHIP_VRJ_NUM_LINES		0x150
#define MCHIP_VRJ_NUM_PIXELS		0x158
#define MCHIP_VRJ_NUM_COMPONENTS	0x160
#define MCHIP_VRJ_SOF1			0x168
#define MCHIP_VRJ_SOF2			0x170
#define MCHIP_VRJ_SOF3			0x178
#define MCHIP_VRJ_SOF4			0x180
#define MCHIP_VRJ_SOS			0x188
#define MCHIP_VRJ_SOFT_RESET		0x190

#define MCHIP_VRJ_STATUS		0x1c0
#define MCHIP_VRJ_STATUS_BUSY		0x00001
#define MCHIP_VRJ_STATUS_COMP_ACCESS	0x00002
#define MCHIP_VRJ_STATUS_PIXEL_ACCESS	0x00004
#define MCHIP_VRJ_STATUS_ERROR		0x00008

#define MCHIP_VRJ_IRQ_FLAG		0x1c8
#define MCHIP_VRJ_ERROR_REPORT		0x1d8

#define MCHIP_VRJ_START_COMMAND		0x1a0

/****************************************************************************/
/* Driver definitions.                                                      */
/****************************************************************************/

/* Sony Programmable I/O Controller for accessing the camera commands */
#include <linux/sony-laptop.h>

/* private API definitions */
#include <linux/meye.h>
#include <linux/mutex.h>


/* Enable jpg software correction */
#define MEYE_JPEG_CORRECTION	1

/* Maximum size of a buffer */
#define MEYE_MAX_BUFSIZE	614400	/* 640 * 480 * 2 */

/* Maximum number of buffers */
#define MEYE_MAX_BUFNBRS	32

/* State of a buffer */
#define MEYE_BUF_UNUSED	0	/* not used */
#define MEYE_BUF_USING	1	/* currently grabbing / playing */
#define MEYE_BUF_DONE	2	/* done */

/* grab buffer */
struct meye_grab_buffer {
	int state;			/* state of buffer */
	unsigned long size;		/* size of jpg frame */
	struct timeval timestamp;	/* timestamp */
	unsigned long sequence;		/* sequence number */
};

/* size of kfifos containings buffer indices */
#define MEYE_QUEUE_SIZE	MEYE_MAX_BUFNBRS

/* Motion Eye device structure */
struct meye {
	struct v4l2_device v4l2_dev;	/* Main v4l2_device struct */
	struct v4l2_ctrl_handler hdl;
	struct pci_dev *mchip_dev;	/* pci device */
	u8 mchip_irq;			/* irq */
	u8 mchip_mode;			/* actual mchip mode: HIC_MODE... */
	u8 mchip_fnum;			/* current mchip frame number */
	unsigned char __iomem *mchip_mmregs;/* mchip: memory mapped registers */
	u8 *mchip_ptable[MCHIP_NB_PAGES];/* mchip: ptable */
	void *mchip_ptable_toc;		/* mchip: ptable toc */
	dma_addr_t mchip_dmahandle;	/* mchip: dma handle to ptable toc */
	unsigned char *grab_fbuffer;	/* capture framebuffer */
	unsigned char *grab_temp;	/* temporary buffer */
					/* list of buffers */
	struct meye_grab_buffer grab_buffer[MEYE_MAX_BUFNBRS];
	int vma_use_count[MEYE_MAX_BUFNBRS]; /* mmap count */
	struct mutex lock;		/* mutex for open/mmap... */
	struct kfifo grabq;		/* queue for buffers to be grabbed */
	spinlock_t grabq_lock;		/* lock protecting the queue */
	struct kfifo doneq;		/* queue for grabbed buffers */
	spinlock_t doneq_lock;		/* lock protecting the queue */
	wait_queue_head_t proc_list;	/* wait queue */
	struct video_device vdev;	/* video device parameters */
	u16 brightness;
	u16 hue;
	u16 contrast;
	u16 colour;
	struct meye_params params;	/* additional parameters */
	unsigned long in_use;		/* set to 1 if the device is in use */
#ifdef CONFIG_PM
	u8 pm_mchip_mode;		/* old mchip mode */
#endif
};

#endif
Commit	Line	Data
1da177e4 LT	1	/*
	2	* Motion Eye video4linux driver for Sony Vaio PictureBook
	3	*
	4	* Copyright (C) 2001-2004 Stelian Pop <stelian@popies.net>
	5	*
96de0e25	6	* Copyright (C) 2001-2002 Alcôve <www.alcove.com>
1da177e4 LT	7	*
	8	* Copyright (C) 2000 Andrew Tridgell <tridge@valinux.com>
	9	*
	10	* Earlier work by Werner Almesberger, Paul `Rusty' Russell and Paul Mackerras.
	11	*
	12	* Some parts borrowed from various video4linux drivers, especially
	13	* bttv-driver.c and zoran.c, see original files for credits.
	14	*
	15	* This program is free software; you can redistribute it and/or modify
	16	* it under the terms of the GNU General Public License as published by
	17	* the Free Software Foundation; either version 2 of the License, or
	18	* (at your option) any later version.
	19	*
	20	* This program is distributed in the hope that it will be useful,
	21	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	22	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	23	* GNU General Public License for more details.
1da177e4 LT	24	*/
	25
	26	#ifndef _MEYE_PRIV_H_
	27	#define _MEYE_PRIV_H_
	28
	29	#define MEYE_DRIVER_MAJORVERSION 1
51270617	30	#define MEYE_DRIVER_MINORVERSION 14
1da177e4 LT	31
	32	#define MEYE_DRIVER_VERSION __stringify(MEYE_DRIVER_MAJORVERSION) "." \
	33	__stringify(MEYE_DRIVER_MINORVERSION)
	34
1da177e4 LT	35	#include <linux/types.h>
	36	#include <linux/pci.h>
	37	#include <linux/kfifo.h>
ed986d1f	38	#include <media/v4l2-ctrls.h>
1da177e4 LT	39
	40	/****************************************************************************/
	41	/* Motion JPEG chip registers */
	42	/****************************************************************************/
	43
	44	/* Motion JPEG chip PCI configuration registers */
	45	#define MCHIP_PCI_POWER_CSR 0x54
	46	#define MCHIP_PCI_MCORE_STATUS 0x60 /* see HIC_STATUS */
	47	#define MCHIP_PCI_HOSTUSEREQ_SET 0x64
	48	#define MCHIP_PCI_HOSTUSEREQ_CLR 0x68
	49	#define MCHIP_PCI_LOWPOWER_SET 0x6c
	50	#define MCHIP_PCI_LOWPOWER_CLR 0x70
	51	#define MCHIP_PCI_SOFTRESET_SET 0x74
	52
	53	/* Motion JPEG chip memory mapped registers */
	54	#define MCHIP_MM_REGS 0x200 /* 512 bytes */
	55	#define MCHIP_REG_TIMEOUT 1000 /* reg access, ~us */
	56	#define MCHIP_MCC_VRJ_TIMEOUT 1000 /* MCC & VRJ access */
	57
	58	#define MCHIP_MM_PCI_MODE 0x00 /* PCI access mode */
	59	#define MCHIP_MM_PCI_MODE_RETRY 0x00000001 /* retry mode */
	60	#define MCHIP_MM_PCI_MODE_MASTER 0x00000002 /* master access */
	61	#define MCHIP_MM_PCI_MODE_READ_LINE 0x00000004 /* read line */
	62
	63	#define MCHIP_MM_INTA 0x04 /* Int status/mask */
	64	#define MCHIP_MM_INTA_MCC 0x00000001 /* MCC interrupt */
	65	#define MCHIP_MM_INTA_VRJ 0x00000002 /* VRJ interrupt */
	66	#define MCHIP_MM_INTA_HIC_1 0x00000004 /* one frame done */
	67	#define MCHIP_MM_INTA_HIC_1_MASK 0x00000400 /* 1: enable */
	68	#define MCHIP_MM_INTA_HIC_END 0x00000008 /* all frames done */
	69	#define MCHIP_MM_INTA_HIC_END_MASK 0x00000800
	70	#define MCHIP_MM_INTA_JPEG 0x00000010 /* decompress. error */
	71	#define MCHIP_MM_INTA_JPEG_MASK 0x00001000
	72	#define MCHIP_MM_INTA_CAPTURE 0x00000020 /* capture end */
	73	#define MCHIP_MM_INTA_PCI_ERR 0x00000040 /* PCI error */
	74	#define MCHIP_MM_INTA_PCI_ERR_MASK 0x00004000
	75
	76	#define MCHIP_MM_PT_ADDR 0x08 /* page table address*/
	77	/* n4kB /
	78	#define MCHIP_NB_PAGES 1024 /* pages for display */
	79	#define MCHIP_NB_PAGES_MJPEG 256 /* pages for mjpeg */
	80
	81	#define MCHIP_MM_FIR(n) (0x0c+(n)4) / Frame info 0-3 */
	82	#define MCHIP_MM_FIR_RDY 0x00000001 /* frame ready */
	83	#define MCHIP_MM_FIR_FAILFR_MASK 0xf8000000 /* # of failed frames */
	84	#define MCHIP_MM_FIR_FAILFR_SHIFT 27
	85
	86	/* continuous comp/decomp mode */
	87	#define MCHIP_MM_FIR_C_ENDL_MASK 0x000007fe /* end DW [10] */
	88	#define MCHIP_MM_FIR_C_ENDL_SHIFT 1
	89	#define MCHIP_MM_FIR_C_ENDP_MASK 0x0007f800 /* end page [8] */
	90	#define MCHIP_MM_FIR_C_ENDP_SHIFT 11
	91	#define MCHIP_MM_FIR_C_STARTP_MASK 0x07f80000 /* start page [8] */
	92	#define MCHIP_MM_FIR_C_STARTP_SHIFT 19
	93
	94	/* continuous picture output mode */
	95	#define MCHIP_MM_FIR_O_STARTP_MASK 0x7ffe0000 /* start page [10] */
	96	#define MCHIP_MM_FIR_O_STARTP_SHIFT 17
	97
	98	#define MCHIP_MM_FIFO_DATA 0x1c /* PCI TGT FIFO data */
	99	#define MCHIP_MM_FIFO_STATUS 0x20 /* PCI TGT FIFO stat */
	100	#define MCHIP_MM_FIFO_MASK 0x00000003
	101	#define MCHIP_MM_FIFO_WAIT_OR_READY 0x00000002 /* Bits common to WAIT & READY*/
	102	#define MCHIP_MM_FIFO_IDLE 0x0 /* HIC idle */
103	#define MCHIP_MM_FIFO_IDLE1 0x1 /* idem ??? */
104	#define MCHIP_MM_FIFO_WAIT 0x2 /* wait request */
105	#define MCHIP_MM_FIFO_READY 0x3 /* data ready */
106
107	#define MCHIP_HIC_HOST_USEREQ 0x40 /* host uses MCORE */
108
109	#define MCHIP_HIC_TP_BUSY 0x44 /* taking picture */
110
111	#define MCHIP_HIC_PIC_SAVED 0x48 /* pic in SDRAM */
112
113	#define MCHIP_HIC_LOWPOWER 0x4c /* clock stopped */
114
115	#define MCHIP_HIC_CTL 0x50 /* HIC control */
116	#define MCHIP_HIC_CTL_SOFT_RESET 0x00000001 /* MCORE reset */
117	#define MCHIP_HIC_CTL_MCORE_RDY 0x00000002 /* MCORE ready */
118
119	#define MCHIP_HIC_CMD 0x54 /* HIC command */
120	#define MCHIP_HIC_CMD_BITS 0x00000003 /* cmd width=[1:0]*/
121	#define MCHIP_HIC_CMD_NOOP 0x0
122	#define MCHIP_HIC_CMD_START 0x1
123	#define MCHIP_HIC_CMD_STOP 0x2
124
125	#define MCHIP_HIC_MODE 0x58
126	#define MCHIP_HIC_MODE_NOOP 0x0
127	#define MCHIP_HIC_MODE_STILL_CAP 0x1 /* still pic capt */
128	#define MCHIP_HIC_MODE_DISPLAY 0x2 /* display */
129	#define MCHIP_HIC_MODE_STILL_COMP 0x3 /* still pic comp. */
130	#define MCHIP_HIC_MODE_STILL_DECOMP 0x4 /* still pic decomp. */
131	#define MCHIP_HIC_MODE_CONT_COMP 0x5 /* cont capt+comp */
132	#define MCHIP_HIC_MODE_CONT_DECOMP 0x6 /* cont decomp+disp */
133	#define MCHIP_HIC_MODE_STILL_OUT 0x7 /* still pic output */
134	#define MCHIP_HIC_MODE_CONT_OUT 0x8 /* cont output */
135
136	#define MCHIP_HIC_STATUS 0x5c
137	#define MCHIP_HIC_STATUS_MCC_RDY 0x00000001 /* MCC reg acc ok */
138	#define MCHIP_HIC_STATUS_VRJ_RDY 0x00000002 /* VRJ reg acc ok */
139	#define MCHIP_HIC_STATUS_IDLE 0x00000003
140	#define MCHIP_HIC_STATUS_CAPDIS 0x00000004 /* cap/disp in prog */
141	#define MCHIP_HIC_STATUS_COMPDEC 0x00000008 /* (de)comp in prog */
142	#define MCHIP_HIC_STATUS_BUSY 0x00000010 /* HIC busy */
143
144	#define MCHIP_HIC_S_RATE 0x60 /* MJPEG # frames */
145
146	#define MCHIP_HIC_PCI_VFMT 0x64 /* video format */
147	#define MCHIP_HIC_PCI_VFMT_YVYU 0x00000001 /* 0: V Y' U Y */
148	/* 1: Y' V Y U */
149
150	#define MCHIP_MCC_CMD 0x80 /* MCC commands */
151	#define MCHIP_MCC_CMD_INITIAL 0x0 /* idle ? */
152	#define MCHIP_MCC_CMD_IIC_START_SET 0x1
153	#define MCHIP_MCC_CMD_IIC_END_SET 0x2
154	#define MCHIP_MCC_CMD_FM_WRITE 0x3 /* frame memory */
155	#define MCHIP_MCC_CMD_FM_READ 0x4
156	#define MCHIP_MCC_CMD_FM_STOP 0x5
157	#define MCHIP_MCC_CMD_CAPTURE 0x6
158	#define MCHIP_MCC_CMD_DISPLAY 0x7
159	#define MCHIP_MCC_CMD_END_DISP 0x8
160	#define MCHIP_MCC_CMD_STILL_COMP 0x9
161	#define MCHIP_MCC_CMD_STILL_DECOMP 0xa
162	#define MCHIP_MCC_CMD_STILL_OUTPUT 0xb
163	#define MCHIP_MCC_CMD_CONT_OUTPUT 0xc
164	#define MCHIP_MCC_CMD_CONT_COMP 0xd
165	#define MCHIP_MCC_CMD_CONT_DECOMP 0xe
166	#define MCHIP_MCC_CMD_RESET 0xf /* MCC reset */
167
168	#define MCHIP_MCC_IIC_WR 0x84
169
170	#define MCHIP_MCC_MCC_WR 0x88
171
172	#define MCHIP_MCC_MCC_RD 0x8c
173
174	#define MCHIP_MCC_STATUS 0x90
175	#define MCHIP_MCC_STATUS_CAPT 0x00000001 /* capturing */
176	#define MCHIP_MCC_STATUS_DISP 0x00000002 /* displaying */
177	#define MCHIP_MCC_STATUS_COMP 0x00000004 /* compressing */
178	#define MCHIP_MCC_STATUS_DECOMP 0x00000008 /* decompressing */
179	#define MCHIP_MCC_STATUS_MCC_WR 0x00000010 /* register ready */
180	#define MCHIP_MCC_STATUS_MCC_RD 0x00000020 /* register ready */
181	#define MCHIP_MCC_STATUS_IIC_WR 0x00000040 /* register ready */
182	#define MCHIP_MCC_STATUS_OUTPUT 0x00000080 /* output in prog */
183
184	#define MCHIP_MCC_SIG_POLARITY 0x94
185	#define MCHIP_MCC_SIG_POL_VS_H 0x00000001 /* VS active-high */
186	#define MCHIP_MCC_SIG_POL_HS_H 0x00000002 /* HS active-high */
187	#define MCHIP_MCC_SIG_POL_DOE_H 0x00000004 /* DOE active-high */
188
189	#define MCHIP_MCC_IRQ 0x98
190	#define MCHIP_MCC_IRQ_CAPDIS_STRT 0x00000001 /* cap/disp started */
191	#define MCHIP_MCC_IRQ_CAPDIS_STRT_MASK 0x00000010
192	#define MCHIP_MCC_IRQ_CAPDIS_END 0x00000002 /* cap/disp ended */
193	#define MCHIP_MCC_IRQ_CAPDIS_END_MASK 0x00000020
194	#define MCHIP_MCC_IRQ_COMPDEC_STRT 0x00000004 /* (de)comp started */
195	#define MCHIP_MCC_IRQ_COMPDEC_STRT_MASK 0x00000040
196	#define MCHIP_MCC_IRQ_COMPDEC_END 0x00000008 /* (de)comp ended */
197	#define MCHIP_MCC_IRQ_COMPDEC_END_MASK 0x00000080
198
199	#define MCHIP_MCC_HSTART 0x9c /* video in */
200	#define MCHIP_MCC_VSTART 0xa0
201	#define MCHIP_MCC_HCOUNT 0xa4
202	#define MCHIP_MCC_VCOUNT 0xa8
203	#define MCHIP_MCC_R_XBASE 0xac /* capt/disp */
204	#define MCHIP_MCC_R_YBASE 0xb0
205	#define MCHIP_MCC_R_XRANGE 0xb4
206	#define MCHIP_MCC_R_YRANGE 0xb8
207	#define MCHIP_MCC_B_XBASE 0xbc /* comp/decomp */
208	#define MCHIP_MCC_B_YBASE 0xc0
209	#define MCHIP_MCC_B_XRANGE 0xc4
210	#define MCHIP_MCC_B_YRANGE 0xc8
211
212	#define MCHIP_MCC_R_SAMPLING 0xcc /* 1: 1:4 */
213
214	#define MCHIP_VRJ_CMD 0x100 /* VRJ commands */
215
216	/* VRJ registers (see table 12.2.4) */
217	#define MCHIP_VRJ_COMPRESSED_DATA 0x1b0
218	#define MCHIP_VRJ_PIXEL_DATA 0x1b8
219
220	#define MCHIP_VRJ_BUS_MODE 0x100
221	#define MCHIP_VRJ_SIGNAL_ACTIVE_LEVEL 0x108
222	#define MCHIP_VRJ_PDAT_USE 0x110
223	#define MCHIP_VRJ_MODE_SPECIFY 0x118
224	#define MCHIP_VRJ_LIMIT_COMPRESSED_LO 0x120
225	#define MCHIP_VRJ_LIMIT_COMPRESSED_HI 0x124
226	#define MCHIP_VRJ_COMP_DATA_FORMAT 0x128
227	#define MCHIP_VRJ_TABLE_DATA 0x140
228	#define MCHIP_VRJ_RESTART_INTERVAL 0x148
229	#define MCHIP_VRJ_NUM_LINES 0x150
230	#define MCHIP_VRJ_NUM_PIXELS 0x158
231	#define MCHIP_VRJ_NUM_COMPONENTS 0x160
232	#define MCHIP_VRJ_SOF1 0x168
233	#define MCHIP_VRJ_SOF2 0x170
234	#define MCHIP_VRJ_SOF3 0x178
235	#define MCHIP_VRJ_SOF4 0x180
236	#define MCHIP_VRJ_SOS 0x188
237	#define MCHIP_VRJ_SOFT_RESET 0x190
238
239	#define MCHIP_VRJ_STATUS 0x1c0
240	#define MCHIP_VRJ_STATUS_BUSY 0x00001
241	#define MCHIP_VRJ_STATUS_COMP_ACCESS 0x00002
242	#define MCHIP_VRJ_STATUS_PIXEL_ACCESS 0x00004
243	#define MCHIP_VRJ_STATUS_ERROR 0x00008
244
245	#define MCHIP_VRJ_IRQ_FLAG 0x1c8
246	#define MCHIP_VRJ_ERROR_REPORT 0x1d8
247
248	#define MCHIP_VRJ_START_COMMAND 0x1a0
249
250	/****************************************************************************/
251	/* Driver definitions. */
252	/****************************************************************************/
253
254	/* Sony Programmable I/O Controller for accessing the camera commands */
cbefb762	255	#include <linux/sony-laptop.h>
1da177e4 LT	256
	257	/* private API definitions */
	258	#include <linux/meye.h>
3593cab5 IM	259	#include <linux/mutex.h>
3593cab5 IM	260
1da177e4 LT	261
	262	/* Enable jpg software correction */
	263	#define MEYE_JPEG_CORRECTION 1
	264
	265	/* Maximum size of a buffer */
	266	#define MEYE_MAX_BUFSIZE 614400 /* 640 * 480 * 2 */
	267
	268	/* Maximum number of buffers */
	269	#define MEYE_MAX_BUFNBRS 32
	270
	271	/* State of a buffer */
	272	#define MEYE_BUF_UNUSED 0 /* not used */
	273	#define MEYE_BUF_USING 1 /* currently grabbing / playing */
	274	#define MEYE_BUF_DONE 2 /* done */
	275
	276	/* grab buffer */
	277	struct meye_grab_buffer {
	278	int state; /* state of buffer */
	279	unsigned long size; /* size of jpg frame */
	280	struct timeval timestamp; /* timestamp */
	281	unsigned long sequence; /* sequence number */
	282	};
	283
	284	/* size of kfifos containings buffer indices */
	285	#define MEYE_QUEUE_SIZE MEYE_MAX_BUFNBRS
	286
	287	/* Motion Eye device structure */
	288	struct meye {
51270617	289	struct v4l2_device v4l2_dev; /* Main v4l2_device struct */
ed986d1f	290	struct v4l2_ctrl_handler hdl;
1da177e4 LT	291	struct pci_dev mchip_dev; / pci device */
	292	u8 mchip_irq; /* irq */
	293	u8 mchip_mode; /* actual mchip mode: HIC_MODE... */
	294	u8 mchip_fnum; /* current mchip frame number */
	295	unsigned char __iomem mchip_mmregs;/ mchip: memory mapped registers */
	296	u8 mchip_ptable[MCHIP_NB_PAGES];/ mchip: ptable */
	297	void mchip_ptable_toc; / mchip: ptable toc */
	298	dma_addr_t mchip_dmahandle; /* mchip: dma handle to ptable toc */
	299	unsigned char grab_fbuffer; / capture framebuffer */
	300	unsigned char grab_temp; / temporary buffer */
	301	/* list of buffers */
	302	struct meye_grab_buffer grab_buffer[MEYE_MAX_BUFNBRS];
	303	int vma_use_count[MEYE_MAX_BUFNBRS]; /* mmap count */
3593cab5	304	struct mutex lock; /* mutex for open/mmap... */
45465487	305	struct kfifo grabq; /* queue for buffers to be grabbed */
1da177e4	306	spinlock_t grabq_lock; /* lock protecting the queue */
45465487	307	struct kfifo doneq; /* queue for grabbed buffers */
1da177e4 LT	308	spinlock_t doneq_lock; /* lock protecting the queue */
1da177e4 LT	309	wait_queue_head_t proc_list; /* wait queue */
e239129c	310	struct video_device vdev; /* video device parameters */
51270617 HV	311	u16 brightness;
	312	u16 hue;
	313	u16 contrast;
	314	u16 colour;
1da177e4	315	struct meye_params params; /* additional parameters */
7d43cd53	316	unsigned long in_use; /* set to 1 if the device is in use */
1da177e4 LT	317	#ifdef CONFIG_PM
	318	u8 pm_mchip_mode; /* old mchip mode */
	319	#endif
	320	};
	321
	322	#endif