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[mirror_ubuntu-artful-kernel.git] / drivers / media / pci / pluto2 / pluto2.c
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c7cadb3a
AO		 1/*
2 * pluto2.c - Satelco Easywatch Mobile Terrestrial Receiver [DVB-T]
3 *
4 * Copyright (C) 2005 Andreas Oberritter <obi@linuxtv.org>
5 *
6 * based on pluto2.c 1.10 - http://instinct-wp8.no-ip.org/pluto/
7 * by Dany Salman <salmandany@yahoo.fr>
8 * Copyright (c) 2004 TDF
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
c7cadb3a
AO		 20 */
21
22#include <linux/i2c.h>
23#include <linux/i2c-algo-bit.h>
24#include <linux/init.h>
a6b7a407 25#include <linux/interrupt.h>
c7cadb3a
AO		 26#include <linux/kernel.h>
27#include <linux/module.h>
28#include <linux/pci.h>
29#include <linux/dma-mapping.h>
5a0e3ad6 30#include <linux/slab.h>
c7cadb3a
AO		 31
32#include "demux.h"
33#include "dmxdev.h"
34#include "dvb_demux.h"
35#include "dvb_frontend.h"
36#include "dvb_net.h"
37#include "dvbdev.h"
38#include "tda1004x.h"
39
78e92006
JG		 40DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr);
41
c7cadb3a
AO		 42#define DRIVER_NAME "pluto2"
43
44#define REG_PIDn(n) ((n) << 2) /* PID n pattern registers */
45#define REG_PCAR 0x0020 /* PC address register */
46#define REG_TSCR 0x0024 /* TS ctrl & status */
47#define REG_MISC 0x0028 /* miscellaneous */
48#define REG_MMAC 0x002c /* MSB MAC address */
49#define REG_IMAC 0x0030 /* ISB MAC address */
50#define REG_LMAC 0x0034 /* LSB MAC address */
51#define REG_SPID 0x0038 /* SPI data */
52#define REG_SLCS 0x003c /* serial links ctrl/status */
53
54#define PID0_NOFIL (0x0001 << 16)
55#define PIDn_ENP (0x0001 << 15)
56#define PID0_END (0x0001 << 14)
57#define PID0_AFIL (0x0001 << 13)
58#define PIDn_PID (0x1fff << 0)
59
60#define TSCR_NBPACKETS (0x00ff << 24)
61#define TSCR_DEM (0x0001 << 17)
62#define TSCR_DE (0x0001 << 16)
63#define TSCR_RSTN (0x0001 << 15)
64#define TSCR_MSKO (0x0001 << 14)
65#define TSCR_MSKA (0x0001 << 13)
66#define TSCR_MSKL (0x0001 << 12)
67#define TSCR_OVR (0x0001 << 11)
68#define TSCR_AFUL (0x0001 << 10)
69#define TSCR_LOCK (0x0001 << 9)
70#define TSCR_IACK (0x0001 << 8)
71#define TSCR_ADEF (0x007f << 0)
72
73#define MISC_DVR (0x0fff << 4)
74#define MISC_ALED (0x0001 << 3)
75#define MISC_FRST (0x0001 << 2)
76#define MISC_LED1 (0x0001 << 1)
77#define MISC_LED0 (0x0001 << 0)
78
79#define SPID_SPIDR (0x00ff << 0)
80
81#define SLCS_SCL (0x0001 << 7)
82#define SLCS_SDA (0x0001 << 6)
83#define SLCS_CSN (0x0001 << 2)
84#define SLCS_OVR (0x0001 << 1)
85#define SLCS_SWC (0x0001 << 0)
86
87#define TS_DMA_PACKETS (8)
88#define TS_DMA_BYTES (188 * TS_DMA_PACKETS)
89
90#define I2C_ADDR_TDA10046 0x10
91#define I2C_ADDR_TUA6034 0xc2
92#define NHWFILTERS 8
93
94struct pluto {
95 /* pci */
96 struct pci_dev *pdev;
97 u8 __iomem *io_mem;
98
99 /* dvb */
100 struct dmx_frontend hw_frontend;
101 struct dmx_frontend mem_frontend;
102 struct dmxdev dmxdev;
103 struct dvb_adapter dvb_adapter;
104 struct dvb_demux demux;
105 struct dvb_frontend *fe;
106 struct dvb_net dvbnet;
107 unsigned int full_ts_users;
108 unsigned int users;
109
110 /* i2c */
111 struct i2c_algo_bit_data i2c_bit;
112 struct i2c_adapter i2c_adap;
113 unsigned int i2cbug;
114
115 /* irq */
116 unsigned int overflow;
0b61dca2 117 unsigned int dead;
c7cadb3a
AO		 118
119 /* dma */
120 dma_addr_t dma_addr;
121 u8 dma_buf[TS_DMA_BYTES];
122 u8 dummy[4096];
123};
124
125static inline struct pluto *feed_to_pluto(struct dvb_demux_feed *feed)
126{
127 return container_of(feed->demux, struct pluto, demux);
128}
129
130static inline struct pluto *frontend_to_pluto(struct dvb_frontend *fe)
131{
132 return container_of(fe->dvb, struct pluto, dvb_adapter);
133}
134
135static inline u32 pluto_readreg(struct pluto *pluto, u32 reg)
136{
137 return readl(&pluto->io_mem[reg]);
138}
139
140static inline void pluto_writereg(struct pluto *pluto, u32 reg, u32 val)
141{
142 writel(val, &pluto->io_mem[reg]);
143}
144
145static inline void pluto_rw(struct pluto *pluto, u32 reg, u32 mask, u32 bits)
146{
147 u32 val = readl(&pluto->io_mem[reg]);
148 val &= ~mask;
149 val |= bits;
150 writel(val, &pluto->io_mem[reg]);
151}
152
1489f90a
AO		 153static void pluto_write_tscr(struct pluto *pluto, u32 val)
154{
155 /* set the number of packets */
156 val &= ~TSCR_ADEF;
157 val |= TS_DMA_PACKETS / 2;
158
159 pluto_writereg(pluto, REG_TSCR, val);
160}
161
c7cadb3a
AO		 162static void pluto_setsda(void *data, int state)
163{
164 struct pluto *pluto = data;
165
166 if (state)
167 pluto_rw(pluto, REG_SLCS, SLCS_SDA, SLCS_SDA);
168 else
169 pluto_rw(pluto, REG_SLCS, SLCS_SDA, 0);
170}
171
172static void pluto_setscl(void *data, int state)
173{
174 struct pluto *pluto = data;
175
176 if (state)
177 pluto_rw(pluto, REG_SLCS, SLCS_SCL, SLCS_SCL);
178 else
179 pluto_rw(pluto, REG_SLCS, SLCS_SCL, 0);
180
181 /* try to detect i2c_inb() to workaround hardware bug:
182 * reset SDA to high after SCL has been set to low */
183 if ((state) && (pluto->i2cbug == 0)) {
184 pluto->i2cbug = 1;
185 } else {
186 if ((!state) && (pluto->i2cbug == 1))
187 pluto_setsda(pluto, 1);
188 pluto->i2cbug = 0;
189 }
190}
191
192static int pluto_getsda(void *data)
193{
194 struct pluto *pluto = data;
195
196 return pluto_readreg(pluto, REG_SLCS) & SLCS_SDA;
197}
198
199static int pluto_getscl(void *data)
200{
201 struct pluto *pluto = data;
202
203 return pluto_readreg(pluto, REG_SLCS) & SLCS_SCL;
204}
205
206static void pluto_reset_frontend(struct pluto *pluto, int reenable)
207{
208 u32 val = pluto_readreg(pluto, REG_MISC);
209
210 if (val & MISC_FRST) {
211 val &= ~MISC_FRST;
212 pluto_writereg(pluto, REG_MISC, val);
213 }
214 if (reenable) {
215 val |= MISC_FRST;
216 pluto_writereg(pluto, REG_MISC, val);
217 }
218}
219
220static void pluto_reset_ts(struct pluto *pluto, int reenable)
221{
222 u32 val = pluto_readreg(pluto, REG_TSCR);
223
224 if (val & TSCR_RSTN) {
225 val &= ~TSCR_RSTN;
1489f90a 226 pluto_write_tscr(pluto, val);
c7cadb3a
AO		 227 }
228 if (reenable) {
229 val |= TSCR_RSTN;
1489f90a 230 pluto_write_tscr(pluto, val);
c7cadb3a
AO		 231 }
232}
233
234static void pluto_set_dma_addr(struct pluto *pluto)
235{
67778b32 236 pluto_writereg(pluto, REG_PCAR, pluto->dma_addr);
c7cadb3a
AO		 237}
238
4c62e976 239static int pluto_dma_map(struct pluto *pluto)
c7cadb3a
AO		 240{
241 pluto->dma_addr = pci_map_single(pluto->pdev, pluto->dma_buf,
242 TS_DMA_BYTES, PCI_DMA_FROMDEVICE);
243
8d8bb39b 244 return pci_dma_mapping_error(pluto->pdev, pluto->dma_addr);
c7cadb3a
AO		 245}
246
247static void pluto_dma_unmap(struct pluto *pluto)
248{
249 pci_unmap_single(pluto->pdev, pluto->dma_addr,
250 TS_DMA_BYTES, PCI_DMA_FROMDEVICE);
251}
252
253static int pluto_start_feed(struct dvb_demux_feed *f)
254{
255 struct pluto *pluto = feed_to_pluto(f);
256
257 /* enable PID filtering */
258 if (pluto->users++ == 0)
259 pluto_rw(pluto, REG_PIDn(0), PID0_AFIL | PID0_NOFIL, 0);
260
261 if ((f->pid < 0x2000) && (f->index < NHWFILTERS))
262 pluto_rw(pluto, REG_PIDn(f->index), PIDn_ENP | PIDn_PID, PIDn_ENP | f->pid);
263 else if (pluto->full_ts_users++ == 0)
264 pluto_rw(pluto, REG_PIDn(0), PID0_NOFIL, PID0_NOFIL);
265
266 return 0;
267}
268
269static int pluto_stop_feed(struct dvb_demux_feed *f)
270{
271 struct pluto *pluto = feed_to_pluto(f);
272
273 /* disable PID filtering */
274 if (--pluto->users == 0)
275 pluto_rw(pluto, REG_PIDn(0), PID0_AFIL, PID0_AFIL);
276
277 if ((f->pid < 0x2000) && (f->index < NHWFILTERS))
278 pluto_rw(pluto, REG_PIDn(f->index), PIDn_ENP | PIDn_PID, 0x1fff);
279 else if (--pluto->full_ts_users == 0)
280 pluto_rw(pluto, REG_PIDn(0), PID0_NOFIL, 0);
281
282 return 0;
283}
284
285static void pluto_dma_end(struct pluto *pluto, unsigned int nbpackets)
286{
287 /* synchronize the DMA transfer with the CPU
288 * first so that we see updated contents. */
289 pci_dma_sync_single_for_cpu(pluto->pdev, pluto->dma_addr,
290 TS_DMA_BYTES, PCI_DMA_FROMDEVICE);
291
292 /* Workaround for broken hardware:
293 * [1] On startup NBPACKETS seems to contain an uninitialized value,
25985edc 294 * but no packets have been transferred.
c7cadb3a 295 * [2] Sometimes (actually very often) NBPACKETS stays at zero
25985edc 296 * although one packet has been transferred.
4d845170 297 * [3] Sometimes (actually rarely), the card gets into an erroneous
298 * mode where it continuously generates interrupts, claiming it
25985edc
LDM		 299 * has received nbpackets>TS_DMA_PACKETS packets, but no packet
300 * has been transferred. Only a reset seems to solve this
c7cadb3a
AO		 301 */
302 if ((nbpackets == 0) || (nbpackets > TS_DMA_PACKETS)) {
6573dd75 303 unsigned int i = 0;
c7cadb3a
AO		 304 while (pluto->dma_buf[i] == 0x47)
305 i += 188;
6573dd75 306 nbpackets = i / 188;
4d845170 307 if (i == 0) {
308 pluto_reset_ts(pluto, 1);
309 dev_printk(KERN_DEBUG, &pluto->pdev->dev, "resetting TS because of invalid packet counter\n");
310 }
c7cadb3a
AO		 311 }
312
313 dvb_dmx_swfilter_packets(&pluto->demux, pluto->dma_buf, nbpackets);
314
315 /* clear the dma buffer. this is needed to be able to identify
316 * new valid ts packets above */
317 memset(pluto->dma_buf, 0, nbpackets * 188);
318
319 /* reset the dma address */
320 pluto_set_dma_addr(pluto);
321
322 /* sync the buffer and give it back to the card */
323 pci_dma_sync_single_for_device(pluto->pdev, pluto->dma_addr,
324 TS_DMA_BYTES, PCI_DMA_FROMDEVICE);
325}
326
7d12e780 327static irqreturn_t pluto_irq(int irq, void *dev_id)
c7cadb3a
AO		 328{
329 struct pluto *pluto = dev_id;
330 u32 tscr;
331
25985edc 332 /* check whether an interrupt occurred on this device */
c7cadb3a
AO		 333 tscr = pluto_readreg(pluto, REG_TSCR);
334 if (!(tscr & (TSCR_DE | TSCR_OVR)))
335 return IRQ_NONE;
336
337 if (tscr == 0xffffffff) {
0b61dca2
AC		 338 if (pluto->dead == 0)
339 dev_err(&pluto->pdev->dev, "card has hung or been ejected.\n");
340 /* It's dead Jim */
341 pluto->dead = 1;
c7cadb3a
AO		 342 return IRQ_HANDLED;
343 }
344
345 /* dma end interrupt */
346 if (tscr & TSCR_DE) {
347 pluto_dma_end(pluto, (tscr & TSCR_NBPACKETS) >> 24);
348 /* overflow interrupt */
349 if (tscr & TSCR_OVR)
350 pluto->overflow++;
351 if (pluto->overflow) {
352 dev_err(&pluto->pdev->dev, "overflow irq (%d)\n",
353 pluto->overflow);
354 pluto_reset_ts(pluto, 1);
355 pluto->overflow = 0;
356 }
357 } else if (tscr & TSCR_OVR) {
358 pluto->overflow++;
359 }
360
361 /* ACK the interrupt */
1489f90a 362 pluto_write_tscr(pluto, tscr | TSCR_IACK);
c7cadb3a
AO		 363
364 return IRQ_HANDLED;
365}
366
4c62e976 367static void pluto_enable_irqs(struct pluto *pluto)
c7cadb3a
AO		 368{
369 u32 val = pluto_readreg(pluto, REG_TSCR);
370
c7cadb3a
AO		 371 /* disable AFUL and LOCK interrupts */
372 val |= (TSCR_MSKA | TSCR_MSKL);
373 /* enable DMA and OVERFLOW interrupts */
374 val &= ~(TSCR_DEM | TSCR_MSKO);
375 /* clear pending interrupts */
376 val |= TSCR_IACK;
377
1489f90a 378 pluto_write_tscr(pluto, val);
c7cadb3a
AO		 379}
380
381static void pluto_disable_irqs(struct pluto *pluto)
382{
383 u32 val = pluto_readreg(pluto, REG_TSCR);
384
385 /* disable all interrupts */
386 val |= (TSCR_DEM | TSCR_MSKO | TSCR_MSKA | TSCR_MSKL);
387 /* clear pending interrupts */
388 val |= TSCR_IACK;
389
1489f90a 390 pluto_write_tscr(pluto, val);
c7cadb3a
AO		 391}
392
4c62e976 393static int pluto_hw_init(struct pluto *pluto)
c7cadb3a
AO		 394{
395 pluto_reset_frontend(pluto, 1);
396
397 /* set automatic LED control by FPGA */
398 pluto_rw(pluto, REG_MISC, MISC_ALED, MISC_ALED);
399
f58c91ce 400 /* set data endianness */
c7cadb3a
AO		 401#ifdef __LITTLE_ENDIAN
402 pluto_rw(pluto, REG_PIDn(0), PID0_END, PID0_END);
403#else
404 pluto_rw(pluto, REG_PIDn(0), PID0_END, 0);
405#endif
406 /* map DMA and set address */
407 pluto_dma_map(pluto);
408 pluto_set_dma_addr(pluto);
409
410 /* enable interrupts */
411 pluto_enable_irqs(pluto);
412
413 /* reset TS logic */
414 pluto_reset_ts(pluto, 1);
415
416 return 0;
417}
418
419static void pluto_hw_exit(struct pluto *pluto)
420{
421 /* disable interrupts */
422 pluto_disable_irqs(pluto);
423
424 pluto_reset_ts(pluto, 0);
425
426 /* LED: disable automatic control, enable yellow, disable green */
427 pluto_rw(pluto, REG_MISC, MISC_ALED | MISC_LED1 | MISC_LED0, MISC_LED1);
428
429 /* unmap DMA */
430 pluto_dma_unmap(pluto);
431
432 pluto_reset_frontend(pluto, 0);
433}
434
435static inline u32 divide(u32 numerator, u32 denominator)
436{
437 if (denominator == 0)
438 return ~0;
439
75b697f7 440 return DIV_ROUND_CLOSEST(numerator, denominator);
c7cadb3a
AO		 441}
442
443/* LG Innotek TDTE-E001P (Infineon TUA6034) */
14d24d14 444static int lg_tdtpe001p_tuner_set_params(struct dvb_frontend *fe)
c7cadb3a 445{
2f786bbe 446 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
c7cadb3a
AO		 447 struct pluto *pluto = frontend_to_pluto(fe);
448 struct i2c_msg msg;
449 int ret;
450 u8 buf[4];
451 u32 div;
452
453 // Fref = 166.667 Hz
454 // Fref * 3 = 500.000 Hz
455 // IF = 36166667
456 // IF / Fref = 217
457 //div = divide(p->frequency + 36166667, 166667);
458 div = divide(p->frequency * 3, 500000) + 217;
459 buf[0] = (div >> 8) & 0x7f;
460 buf[1] = (div >> 0) & 0xff;
461
462 if (p->frequency < 611000000)
463 buf[2] = 0xb4;
464 else if (p->frequency < 811000000)
465 buf[2] = 0xbc;
466 else
467 buf[2] = 0xf4;
468
469 // VHF: 174-230 MHz
470 // center: 350 MHz
471 // UHF: 470-862 MHz
472 if (p->frequency < 350000000)
473 buf[3] = 0x02;
474 else
475 buf[3] = 0x04;
476
2f786bbe 477 if (p->bandwidth_hz == 8000000)
c7cadb3a
AO		 478 buf[3] |= 0x08;
479
c7cadb3a
AO		 480 msg.addr = I2C_ADDR_TUA6034 >> 1;
481 msg.flags = 0;
482 msg.buf = buf;
483 msg.len = sizeof(buf);
484
dea74869
PB		 485 if (fe->ops.i2c_gate_ctrl)
486 fe->ops.i2c_gate_ctrl(fe, 1);
c7cadb3a
AO		 487 ret = i2c_transfer(&pluto->i2c_adap, &msg, 1);
488 if (ret < 0)
489 return ret;
490 else if (ret == 0)
491 return -EREMOTEIO;
492
493 return 0;
494}
495
496static int pluto2_request_firmware(struct dvb_frontend *fe,
497 const struct firmware **fw, char *name)
498{
499 struct pluto *pluto = frontend_to_pluto(fe);
500
501 return request_firmware(fw, name, &pluto->pdev->dev);
502}
503
4c62e976 504static struct tda1004x_config pluto2_fe_config = {
c7cadb3a
AO		 505 .demod_address = I2C_ADDR_TDA10046 >> 1,
506 .invert = 1,
507 .invert_oclk = 0,
508 .xtal_freq = TDA10046_XTAL_16M,
509 .agc_config = TDA10046_AGC_DEFAULT,
510 .if_freq = TDA10046_FREQ_3617,
c7cadb3a
AO		 511 .request_firmware = pluto2_request_firmware,
512};
513
4c62e976 514static int frontend_init(struct pluto *pluto)
c7cadb3a
AO		 515{
516 int ret;
517
518 pluto->fe = tda10046_attach(&pluto2_fe_config, &pluto->i2c_adap);
519 if (!pluto->fe) {
520 dev_err(&pluto->pdev->dev, "could not attach frontend\n");
521 return -ENODEV;
522 }
dea74869 523 pluto->fe->ops.tuner_ops.set_params = lg_tdtpe001p_tuner_set_params;
c7cadb3a
AO		 524
525 ret = dvb_register_frontend(&pluto->dvb_adapter, pluto->fe);
526 if (ret < 0) {
dea74869
PB		 527 if (pluto->fe->ops.release)
528 pluto->fe->ops.release(pluto->fe);
c7cadb3a
AO		 529 return ret;
530 }
531
532 return 0;
533}
534
4c62e976 535static void pluto_read_rev(struct pluto *pluto)
c7cadb3a
AO		 536{
537 u32 val = pluto_readreg(pluto, REG_MISC) & MISC_DVR;
538 dev_info(&pluto->pdev->dev, "board revision %d.%d\n",
539 (val >> 12) & 0x0f, (val >> 4) & 0xff);
540}
541
4c62e976 542static void pluto_read_mac(struct pluto *pluto, u8 *mac)
c7cadb3a
AO		 543{
544 u32 val = pluto_readreg(pluto, REG_MMAC);
545 mac[0] = (val >> 8) & 0xff;
546 mac[1] = (val >> 0) & 0xff;
547
548 val = pluto_readreg(pluto, REG_IMAC);
549 mac[2] = (val >> 8) & 0xff;
550 mac[3] = (val >> 0) & 0xff;
551
552 val = pluto_readreg(pluto, REG_LMAC);
553 mac[4] = (val >> 8) & 0xff;
554 mac[5] = (val >> 0) & 0xff;
555
7c510e4b 556 dev_info(&pluto->pdev->dev, "MAC %pM\n", mac);
c7cadb3a
AO		 557}
558
4c62e976 559static int pluto_read_serial(struct pluto *pluto)
c7cadb3a
AO		 560{
561 struct pci_dev *pdev = pluto->pdev;
562 unsigned int i, j;
563 u8 __iomem *cis;
564
565 cis = pci_iomap(pdev, 1, 0);
566 if (!cis)
567 return -EIO;
568
569 dev_info(&pdev->dev, "S/N ");
570
571 for (i = 0xe0; i < 0x100; i += 4) {
572 u32 val = readl(&cis[i]);
573 for (j = 0; j < 32; j += 8) {
574 if ((val & 0xff) == 0xff)
575 goto out;
7c66e121 576 printk(KERN_CONT "%c", val & 0xff);
c7cadb3a
AO		 577 val >>= 8;
578 }
579 }
580out:
7c66e121 581 printk(KERN_CONT "\n");
c7cadb3a
AO		 582 pci_iounmap(pdev, cis);
583
584 return 0;
585}
586
4c62e976 587static int pluto2_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
c7cadb3a
AO		 588{
589 struct pluto *pluto;
590 struct dvb_adapter *dvb_adapter;
591 struct dvb_demux *dvbdemux;
592 struct dmx_demux *dmx;
593 int ret = -ENOMEM;
594
7408187d 595 pluto = kzalloc(sizeof(struct pluto), GFP_KERNEL);
c7cadb3a
AO		 596 if (!pluto)
597 goto out;
598
c7cadb3a
AO		 599 pluto->pdev = pdev;
600
601 ret = pci_enable_device(pdev);
602 if (ret < 0)
603 goto err_kfree;
604
605 /* enable interrupts */
606 pci_write_config_dword(pdev, 0x6c, 0x8000);
607
284901a9 608 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
c7cadb3a
AO		 609 if (ret < 0)
610 goto err_pci_disable_device;
611
612 pci_set_master(pdev);
613
614 ret = pci_request_regions(pdev, DRIVER_NAME);
615 if (ret < 0)
616 goto err_pci_disable_device;
617
618 pluto->io_mem = pci_iomap(pdev, 0, 0x40);
619 if (!pluto->io_mem) {
620 ret = -EIO;
621 goto err_pci_release_regions;
622 }
623
624 pci_set_drvdata(pdev, pluto);
625
8076fe32 626 ret = request_irq(pdev->irq, pluto_irq, IRQF_SHARED, DRIVER_NAME, pluto);
c7cadb3a
AO		 627 if (ret < 0)
628 goto err_pci_iounmap;
629
630 ret = pluto_hw_init(pluto);
631 if (ret < 0)
632 goto err_free_irq;
633
634 /* i2c */
635 i2c_set_adapdata(&pluto->i2c_adap, pluto);
636 strcpy(pluto->i2c_adap.name, DRIVER_NAME);
637 pluto->i2c_adap.owner = THIS_MODULE;
c7cadb3a
AO		 638 pluto->i2c_adap.dev.parent = &pdev->dev;
639 pluto->i2c_adap.algo_data = &pluto->i2c_bit;
640 pluto->i2c_bit.data = pluto;
641 pluto->i2c_bit.setsda = pluto_setsda;
642 pluto->i2c_bit.setscl = pluto_setscl;
643 pluto->i2c_bit.getsda = pluto_getsda;
644 pluto->i2c_bit.getscl = pluto_getscl;
645 pluto->i2c_bit.udelay = 10;
646 pluto->i2c_bit.timeout = 10;
647
648 /* Raise SCL and SDA */
649 pluto_setsda(pluto, 1);
650 pluto_setscl(pluto, 1);
651
652 ret = i2c_bit_add_bus(&pluto->i2c_adap);
653 if (ret < 0)
654 goto err_pluto_hw_exit;
655
656 /* dvb */
78e92006
JG		 657 ret = dvb_register_adapter(&pluto->dvb_adapter, DRIVER_NAME,
658 THIS_MODULE, &pdev->dev, adapter_nr);
c7cadb3a 659 if (ret < 0)
3269711b 660 goto err_i2c_del_adapter;
c7cadb3a
AO		 661
662 dvb_adapter = &pluto->dvb_adapter;
663
664 pluto_read_rev(pluto);
665 pluto_read_serial(pluto);
666 pluto_read_mac(pluto, dvb_adapter->proposed_mac);
667
668 dvbdemux = &pluto->demux;
669 dvbdemux->filternum = 256;
670 dvbdemux->feednum = 256;
671 dvbdemux->start_feed = pluto_start_feed;
672 dvbdemux->stop_feed = pluto_stop_feed;
673 dvbdemux->dmx.capabilities = (DMX_TS_FILTERING |
674 DMX_SECTION_FILTERING | DMX_MEMORY_BASED_FILTERING);
675 ret = dvb_dmx_init(dvbdemux);
676 if (ret < 0)
677 goto err_dvb_unregister_adapter;
678
679 dmx = &dvbdemux->dmx;
680
681 pluto->hw_frontend.source = DMX_FRONTEND_0;
682 pluto->mem_frontend.source = DMX_MEMORY_FE;
683 pluto->dmxdev.filternum = NHWFILTERS;
684 pluto->dmxdev.demux = dmx;
685
686 ret = dvb_dmxdev_init(&pluto->dmxdev, dvb_adapter);
687 if (ret < 0)
688 goto err_dvb_dmx_release;
689
690 ret = dmx->add_frontend(dmx, &pluto->hw_frontend);
691 if (ret < 0)
692 goto err_dvb_dmxdev_release;
693
694 ret = dmx->add_frontend(dmx, &pluto->mem_frontend);
695 if (ret < 0)
696 goto err_remove_hw_frontend;
697
698 ret = dmx->connect_frontend(dmx, &pluto->hw_frontend);
699 if (ret < 0)
700 goto err_remove_mem_frontend;
701
702 ret = frontend_init(pluto);
703 if (ret < 0)
704 goto err_disconnect_frontend;
705
706 dvb_net_init(dvb_adapter, &pluto->dvbnet, dmx);
707out:
708 return ret;
709
710err_disconnect_frontend:
711 dmx->disconnect_frontend(dmx);
712err_remove_mem_frontend:
713 dmx->remove_frontend(dmx, &pluto->mem_frontend);
714err_remove_hw_frontend:
715 dmx->remove_frontend(dmx, &pluto->hw_frontend);
716err_dvb_dmxdev_release:
717 dvb_dmxdev_release(&pluto->dmxdev);
718err_dvb_dmx_release:
719 dvb_dmx_release(dvbdemux);
720err_dvb_unregister_adapter:
721 dvb_unregister_adapter(dvb_adapter);
3269711b
JD		 722err_i2c_del_adapter:
723 i2c_del_adapter(&pluto->i2c_adap);
c7cadb3a
AO		 724err_pluto_hw_exit:
725 pluto_hw_exit(pluto);
726err_free_irq:
727 free_irq(pdev->irq, pluto);
728err_pci_iounmap:
729 pci_iounmap(pdev, pluto->io_mem);
730err_pci_release_regions:
731 pci_release_regions(pdev);
732err_pci_disable_device:
733 pci_disable_device(pdev);
734err_kfree:
c7cadb3a
AO		 735 kfree(pluto);
736 goto out;
737}
738
4c62e976 739static void pluto2_remove(struct pci_dev *pdev)
c7cadb3a
AO		 740{
741 struct pluto *pluto = pci_get_drvdata(pdev);
742 struct dvb_adapter *dvb_adapter = &pluto->dvb_adapter;
743 struct dvb_demux *dvbdemux = &pluto->demux;
744 struct dmx_demux *dmx = &dvbdemux->dmx;
745
746 dmx->close(dmx);
747 dvb_net_release(&pluto->dvbnet);
748 if (pluto->fe)
749 dvb_unregister_frontend(pluto->fe);
750
751 dmx->disconnect_frontend(dmx);
752 dmx->remove_frontend(dmx, &pluto->mem_frontend);
753 dmx->remove_frontend(dmx, &pluto->hw_frontend);
754 dvb_dmxdev_release(&pluto->dmxdev);
755 dvb_dmx_release(dvbdemux);
756 dvb_unregister_adapter(dvb_adapter);
3269711b 757 i2c_del_adapter(&pluto->i2c_adap);
c7cadb3a
AO		 758 pluto_hw_exit(pluto);
759 free_irq(pdev->irq, pluto);
760 pci_iounmap(pdev, pluto->io_mem);
761 pci_release_regions(pdev);
762 pci_disable_device(pdev);
c7cadb3a
AO		 763 kfree(pluto);
764}
765
766#ifndef PCI_VENDOR_ID_SCM
767#define PCI_VENDOR_ID_SCM 0x0432
768#endif
769#ifndef PCI_DEVICE_ID_PLUTO2
770#define PCI_DEVICE_ID_PLUTO2 0x0001
771#endif
772
4c62e976 773static struct pci_device_id pluto2_id_table[] = {
c7cadb3a
AO		 774 {
775 .vendor = PCI_VENDOR_ID_SCM,
776 .device = PCI_DEVICE_ID_PLUTO2,
777 .subvendor = PCI_ANY_ID,
778 .subdevice = PCI_ANY_ID,
779 }, {
780 /* empty */
781 },
782};
783
784MODULE_DEVICE_TABLE(pci, pluto2_id_table);
785
786static struct pci_driver pluto2_driver = {
787 .name = DRIVER_NAME,
788 .id_table = pluto2_id_table,
789 .probe = pluto2_probe,
4c62e976 790 .remove = pluto2_remove,
c7cadb3a
AO		 791};
792
6eb2fb31 793module_pci_driver(pluto2_driver);
c7cadb3a
AO		 794
795MODULE_AUTHOR("Andreas Oberritter <obi@linuxtv.org>");
796MODULE_DESCRIPTION("Pluto2 driver");
797MODULE_LICENSE("GPL");
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