[mirror_ubuntu-artful-kernel.git] / drivers / media / pci / saa7134 / saa7134-ts.c

/*
 *
 * device driver for philips saa7134 based TV cards
 * video4linux video interface
 *
 * (c) 2001,02 Gerd Knorr <kraxel@bytesex.org> [SuSE Labs]
 *
 *  This program is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License as published by
 *  the Free Software Foundation; either version 2 of the License, or
 *  (at your option) any later version.
 *
 *  This program is distributed in the hope that it will be useful,
 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *  GNU General Public License for more details.
 */

#include "saa7134.h"
#include "saa7134-reg.h"

#include <linux/init.h>
#include <linux/list.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/delay.h>

/* ------------------------------------------------------------------ */

static unsigned int ts_debug;
module_param(ts_debug, int, 0644);
MODULE_PARM_DESC(ts_debug,"enable debug messages [ts]");

#define ts_dbg(fmt, arg...) do { \
	if (ts_debug) \
		printk(KERN_DEBUG pr_fmt("ts: " fmt), ## arg); \
	} while (0)

/* ------------------------------------------------------------------ */
static int buffer_activate(struct saa7134_dev *dev,
			   struct saa7134_buf *buf,
			   struct saa7134_buf *next)
{

	ts_dbg("buffer_activate [%p]", buf);
	buf->top_seen = 0;

	if (!dev->ts_started)
		dev->ts_field = V4L2_FIELD_TOP;

	if (NULL == next)
		next = buf;
	if (V4L2_FIELD_TOP == dev->ts_field) {
		ts_dbg("- [top]     buf=%p next=%p\n", buf, next);
		saa_writel(SAA7134_RS_BA1(5),saa7134_buffer_base(buf));
		saa_writel(SAA7134_RS_BA2(5),saa7134_buffer_base(next));
		dev->ts_field = V4L2_FIELD_BOTTOM;
	} else {
		ts_dbg("- [bottom]  buf=%p next=%p\n", buf, next);
		saa_writel(SAA7134_RS_BA1(5),saa7134_buffer_base(next));
		saa_writel(SAA7134_RS_BA2(5),saa7134_buffer_base(buf));
		dev->ts_field = V4L2_FIELD_TOP;
	}

	/* start DMA */
	saa7134_set_dmabits(dev);

	mod_timer(&dev->ts_q.timeout, jiffies+TS_BUFFER_TIMEOUT);

	if (!dev->ts_started)
		saa7134_ts_start(dev);

	return 0;
}

int saa7134_ts_buffer_init(struct vb2_buffer *vb2)
{
	struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb2);
	struct saa7134_dmaqueue *dmaq = vb2->vb2_queue->drv_priv;
	struct saa7134_buf *buf = container_of(vbuf, struct saa7134_buf, vb2);

	dmaq->curr = NULL;
	buf->activate = buffer_activate;

	return 0;
}
EXPORT_SYMBOL_GPL(saa7134_ts_buffer_init);

int saa7134_ts_buffer_prepare(struct vb2_buffer *vb2)
{
	struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb2);
	struct saa7134_dmaqueue *dmaq = vb2->vb2_queue->drv_priv;
	struct saa7134_dev *dev = dmaq->dev;
	struct saa7134_buf *buf = container_of(vbuf, struct saa7134_buf, vb2);
	struct sg_table *dma = vb2_dma_sg_plane_desc(vb2, 0);
	unsigned int lines, llength, size;

	ts_dbg("buffer_prepare [%p]\n", buf);

	llength = TS_PACKET_SIZE;
	lines = dev->ts.nr_packets;

	size = lines * llength;
	if (vb2_plane_size(vb2, 0) < size)
		return -EINVAL;

	vb2_set_plane_payload(vb2, 0, size);
	vbuf->field = dev->field;

	return saa7134_pgtable_build(dev->pci, &dmaq->pt, dma->sgl, dma->nents,
				    saa7134_buffer_startpage(buf));
}
EXPORT_SYMBOL_GPL(saa7134_ts_buffer_prepare);

int saa7134_ts_queue_setup(struct vb2_queue *q,
			   unsigned int *nbuffers, unsigned int *nplanes,
			   unsigned int sizes[], struct device *alloc_devs[])
{
	struct saa7134_dmaqueue *dmaq = q->drv_priv;
	struct saa7134_dev *dev = dmaq->dev;
	int size = TS_PACKET_SIZE * dev->ts.nr_packets;

	if (0 == *nbuffers)
		*nbuffers = dev->ts.nr_bufs;
	*nbuffers = saa7134_buffer_count(size, *nbuffers);
	if (*nbuffers < 3)
		*nbuffers = 3;
	*nplanes = 1;
	sizes[0] = size;
	return 0;
}
EXPORT_SYMBOL_GPL(saa7134_ts_queue_setup);

int saa7134_ts_start_streaming(struct vb2_queue *vq, unsigned int count)
{
	struct saa7134_dmaqueue *dmaq = vq->drv_priv;
	struct saa7134_dev *dev = dmaq->dev;

	/*
	 * Planar video capture and TS share the same DMA channel,
	 * so only one can be active at a time.
	 */
	if (vb2_is_busy(&dev->video_vbq) && dev->fmt->planar) {
		struct saa7134_buf *buf, *tmp;

		list_for_each_entry_safe(buf, tmp, &dmaq->queue, entry) {
			list_del(&buf->entry);
			vb2_buffer_done(&buf->vb2.vb2_buf,
					VB2_BUF_STATE_QUEUED);
		}
		if (dmaq->curr) {
			vb2_buffer_done(&dmaq->curr->vb2.vb2_buf,
					VB2_BUF_STATE_QUEUED);
			dmaq->curr = NULL;
		}
		return -EBUSY;
	}
	dmaq->seq_nr = 0;
	return 0;
}
EXPORT_SYMBOL_GPL(saa7134_ts_start_streaming);

void saa7134_ts_stop_streaming(struct vb2_queue *vq)
{
	struct saa7134_dmaqueue *dmaq = vq->drv_priv;
	struct saa7134_dev *dev = dmaq->dev;

	saa7134_ts_stop(dev);
	saa7134_stop_streaming(dev, dmaq);
}
EXPORT_SYMBOL_GPL(saa7134_ts_stop_streaming);

struct vb2_ops saa7134_ts_qops = {
	.queue_setup	= saa7134_ts_queue_setup,
	.buf_init	= saa7134_ts_buffer_init,
	.buf_prepare	= saa7134_ts_buffer_prepare,
	.buf_queue	= saa7134_vb2_buffer_queue,
	.wait_prepare	= vb2_ops_wait_prepare,
	.wait_finish	= vb2_ops_wait_finish,
	.stop_streaming = saa7134_ts_stop_streaming,
};
EXPORT_SYMBOL_GPL(saa7134_ts_qops);

/* ----------------------------------------------------------- */
/* exported stuff                                              */

static unsigned int tsbufs = 8;
module_param(tsbufs, int, 0444);
MODULE_PARM_DESC(tsbufs, "number of ts buffers for read/write IO, range 2-32");

static unsigned int ts_nr_packets = 64;
module_param(ts_nr_packets, int, 0444);
MODULE_PARM_DESC(ts_nr_packets,"size of a ts buffers (in ts packets)");

int saa7134_ts_init_hw(struct saa7134_dev *dev)
{
	/* deactivate TS softreset */
	saa_writeb(SAA7134_TS_SERIAL1, 0x00);
	/* TSSOP high active, TSVAL high active, TSLOCK ignored */
	saa_writeb(SAA7134_TS_PARALLEL, 0x6c);
	saa_writeb(SAA7134_TS_PARALLEL_SERIAL, (TS_PACKET_SIZE-1));
	saa_writeb(SAA7134_TS_DMA0, ((dev->ts.nr_packets-1)&0xff));
	saa_writeb(SAA7134_TS_DMA1, (((dev->ts.nr_packets-1)>>8)&0xff));
	/* TSNOPIT=0, TSCOLAP=0 */
	saa_writeb(SAA7134_TS_DMA2,
		((((dev->ts.nr_packets-1)>>16)&0x3f) | 0x00));

	return 0;
}

int saa7134_ts_init1(struct saa7134_dev *dev)
{
	/* sanitycheck insmod options */
	if (tsbufs < 2)
		tsbufs = 2;
	if (tsbufs > VIDEO_MAX_FRAME)
		tsbufs = VIDEO_MAX_FRAME;
	if (ts_nr_packets < 4)
		ts_nr_packets = 4;
	if (ts_nr_packets > 312)
		ts_nr_packets = 312;
	dev->ts.nr_bufs    = tsbufs;
	dev->ts.nr_packets = ts_nr_packets;

	INIT_LIST_HEAD(&dev->ts_q.queue);
	init_timer(&dev->ts_q.timeout);
	dev->ts_q.timeout.function = saa7134_buffer_timeout;
	dev->ts_q.timeout.data     = (unsigned long)(&dev->ts_q);
	dev->ts_q.dev              = dev;
	dev->ts_q.need_two         = 1;
	dev->ts_started            = 0;
	saa7134_pgtable_alloc(dev->pci, &dev->ts_q.pt);

	/* init TS hw */
	saa7134_ts_init_hw(dev);

	return 0;
}

/* Function for stop TS */
int saa7134_ts_stop(struct saa7134_dev *dev)
{
	ts_dbg("TS stop\n");

	if (!dev->ts_started)
		return 0;

	/* Stop TS stream */
	switch (saa7134_boards[dev->board].ts_type) {
	case SAA7134_MPEG_TS_PARALLEL:
		saa_writeb(SAA7134_TS_PARALLEL, 0x6c);
		dev->ts_started = 0;
		break;
	case SAA7134_MPEG_TS_SERIAL:
		saa_writeb(SAA7134_TS_SERIAL0, 0x40);
		dev->ts_started = 0;
		break;
	}
	return 0;
}

/* Function for start TS */
int saa7134_ts_start(struct saa7134_dev *dev)
{
	ts_dbg("TS start\n");

	if (WARN_ON(dev->ts_started))
		return 0;

	/* dma: setup channel 5 (= TS) */
	saa_writeb(SAA7134_TS_DMA0, (dev->ts.nr_packets - 1) & 0xff);
	saa_writeb(SAA7134_TS_DMA1,
		((dev->ts.nr_packets - 1) >> 8) & 0xff);
	/* TSNOPIT=0, TSCOLAP=0 */
	saa_writeb(SAA7134_TS_DMA2,
		(((dev->ts.nr_packets - 1) >> 16) & 0x3f) | 0x00);
	saa_writel(SAA7134_RS_PITCH(5), TS_PACKET_SIZE);
	saa_writel(SAA7134_RS_CONTROL(5), SAA7134_RS_CONTROL_BURST_16 |
					  SAA7134_RS_CONTROL_ME |
					  (dev->ts_q.pt.dma >> 12));

	/* reset hardware TS buffers */
	saa_writeb(SAA7134_TS_SERIAL1, 0x00);
	saa_writeb(SAA7134_TS_SERIAL1, 0x03);
	saa_writeb(SAA7134_TS_SERIAL1, 0x00);
	saa_writeb(SAA7134_TS_SERIAL1, 0x01);

	/* TS clock non-inverted */
	saa_writeb(SAA7134_TS_SERIAL1, 0x00);

	/* Start TS stream */
	switch (saa7134_boards[dev->board].ts_type) {
	case SAA7134_MPEG_TS_PARALLEL:
		saa_writeb(SAA7134_TS_SERIAL0, 0x40);
		saa_writeb(SAA7134_TS_PARALLEL, 0xec |
			(saa7134_boards[dev->board].ts_force_val << 4));
		break;
	case SAA7134_MPEG_TS_SERIAL:
		saa_writeb(SAA7134_TS_SERIAL0, 0xd8);
		saa_writeb(SAA7134_TS_PARALLEL, 0x6c |
			(saa7134_boards[dev->board].ts_force_val << 4));
		saa_writeb(SAA7134_TS_PARALLEL_SERIAL, 0xbc);
		saa_writeb(SAA7134_TS_SERIAL1, 0x02);
		break;
	}

	dev->ts_started = 1;

	return 0;
}

int saa7134_ts_fini(struct saa7134_dev *dev)
{
	saa7134_pgtable_free(dev->pci, &dev->ts_q.pt);
	return 0;
}

void saa7134_irq_ts_done(struct saa7134_dev *dev, unsigned long status)
{
	enum v4l2_field field;

	spin_lock(&dev->slock);
	if (dev->ts_q.curr) {
		field = dev->ts_field;
		if (field != V4L2_FIELD_TOP) {
			if ((status & 0x100000) != 0x000000)
				goto done;
		} else {
			if ((status & 0x100000) != 0x100000)
				goto done;
		}
		saa7134_buffer_finish(dev, &dev->ts_q, VB2_BUF_STATE_DONE);
	}
	saa7134_buffer_next(dev,&dev->ts_q);

 done:
	spin_unlock(&dev->slock);
}
Commit	Line	Data
1da177e4	1	/*
1da177e4 LT	2	*
	3	* device driver for philips saa7134 based TV cards
	4	* video4linux video interface
	5	*
	6	* (c) 2001,02 Gerd Knorr <kraxel@bytesex.org> [SuSE Labs]
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License as published by
	10	* the Free Software Foundation; either version 2 of the License, or
	11	* (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
1da177e4 LT	17	*/
1da177e4 LT	18
9a12ccfc MCC	19	#include "saa7134.h"
	20	#include "saa7134-reg.h"
	21
1da177e4 LT	22	#include <linux/init.h>
	23	#include <linux/list.h>
	24	#include <linux/module.h>
1da177e4	25	#include <linux/kernel.h>
1da177e4 LT	26	#include <linux/delay.h>
1da177e4 LT	27
1da177e4 LT	28	/* ------------------------------------------------------------------ */
1da177e4 LT	29
ff699e6b	30	static unsigned int ts_debug;
1da177e4 LT	31	module_param(ts_debug, int, 0644);
	32	MODULE_PARM_DESC(ts_debug,"enable debug messages [ts]");
	33
45f38cb3 MCC	34	#define ts_dbg(fmt, arg...) do { \
	35	if (ts_debug) \
	36	printk(KERN_DEBUG pr_fmt("ts: " fmt), ## arg); \
	37	} while (0)
1da177e4 LT	38
1da177e4 LT	39	/* ------------------------------------------------------------------ */
1da177e4 LT	40	static int buffer_activate(struct saa7134_dev *dev,
	41	struct saa7134_buf *buf,
	42	struct saa7134_buf *next)
	43	{
1da177e4	44
6139ebc6	45	ts_dbg("buffer_activate [%p]", buf);
1da177e4 LT	46	buf->top_seen = 0;
1da177e4 LT	47
2ada815f HV	48	if (!dev->ts_started)
	49	dev->ts_field = V4L2_FIELD_TOP;
	50
1da177e4 LT	51	if (NULL == next)
1da177e4 LT	52	next = buf;
2ada815f	53	if (V4L2_FIELD_TOP == dev->ts_field) {
6139ebc6	54	ts_dbg("- [top] buf=%p next=%p\n", buf, next);
1da177e4 LT	55	saa_writel(SAA7134_RS_BA1(5),saa7134_buffer_base(buf));
1da177e4 LT	56	saa_writel(SAA7134_RS_BA2(5),saa7134_buffer_base(next));
2ada815f	57	dev->ts_field = V4L2_FIELD_BOTTOM;
1da177e4	58	} else {
6139ebc6	59	ts_dbg("- [bottom] buf=%p next=%p\n", buf, next);
1da177e4 LT	60	saa_writel(SAA7134_RS_BA1(5),saa7134_buffer_base(next));
1da177e4 LT	61	saa_writel(SAA7134_RS_BA2(5),saa7134_buffer_base(buf));
2ada815f	62	dev->ts_field = V4L2_FIELD_TOP;
1da177e4	63	}
1da177e4 LT	64
	65	/* start DMA */
	66	saa7134_set_dmabits(dev);
	67
82aa98fd	68	mod_timer(&dev->ts_q.timeout, jiffies+TS_BUFFER_TIMEOUT);
92c36147	69
6b6b7543 DB	70	if (!dev->ts_started)
6b6b7543 DB	71	saa7134_ts_start(dev);
92c36147	72
1da177e4 LT	73	return 0;
	74	}
	75
2ada815f HV	76	int saa7134_ts_buffer_init(struct vb2_buffer *vb2)
2ada815f HV	77	{
2d700715	78	struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb2);
2ada815f	79	struct saa7134_dmaqueue *dmaq = vb2->vb2_queue->drv_priv;
2d700715	80	struct saa7134_buf *buf = container_of(vbuf, struct saa7134_buf, vb2);
2ada815f HV	81
	82	dmaq->curr = NULL;
	83	buf->activate = buffer_activate;
	84
	85	return 0;
	86	}
	87	EXPORT_SYMBOL_GPL(saa7134_ts_buffer_init);
	88
	89	int saa7134_ts_buffer_prepare(struct vb2_buffer *vb2)
1da177e4	90	{
2d700715	91	struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb2);
2ada815f	92	struct saa7134_dmaqueue *dmaq = vb2->vb2_queue->drv_priv;
a00e6888	93	struct saa7134_dev *dev = dmaq->dev;
2d700715	94	struct saa7134_buf *buf = container_of(vbuf, struct saa7134_buf, vb2);
2ada815f	95	struct sg_table *dma = vb2_dma_sg_plane_desc(vb2, 0);
1da177e4	96	unsigned int lines, llength, size;
1da177e4	97
af5d20ce	98	ts_dbg("buffer_prepare [%p]\n", buf);
1da177e4 LT	99
	100	llength = TS_PACKET_SIZE;
	101	lines = dev->ts.nr_packets;
	102
	103	size = lines * llength;
2ada815f	104	if (vb2_plane_size(vb2, 0) < size)
1da177e4 LT	105	return -EINVAL;
1da177e4 LT	106
2ada815f	107	vb2_set_plane_payload(vb2, 0, size);
2d700715	108	vbuf->field = dev->field;
6b6b7543	109
2ada815f HV	110	return saa7134_pgtable_build(dev->pci, &dmaq->pt, dma->sgl, dma->nents,
2ada815f HV	111	saa7134_buffer_startpage(buf));
1da177e4	112	}
2ada815f	113	EXPORT_SYMBOL_GPL(saa7134_ts_buffer_prepare);
1da177e4	114
df9ecb0c	115	int saa7134_ts_queue_setup(struct vb2_queue *q,
2ada815f	116	unsigned int nbuffers, unsigned int nplanes,
36c0f8b3	117	unsigned int sizes[], struct device *alloc_devs[])
2ada815f HV	118	{
	119	struct saa7134_dmaqueue *dmaq = q->drv_priv;
	120	struct saa7134_dev *dev = dmaq->dev;
	121	int size = TS_PACKET_SIZE * dev->ts.nr_packets;
	122
	123	if (0 == *nbuffers)
	124	*nbuffers = dev->ts.nr_bufs;
	125	nbuffers = saa7134_buffer_count(size, nbuffers);
	126	if (*nbuffers < 3)
	127	*nbuffers = 3;
	128	*nplanes = 1;
	129	sizes[0] = size;
1da177e4 LT	130	return 0;
1da177e4 LT	131	}
2ada815f	132	EXPORT_SYMBOL_GPL(saa7134_ts_queue_setup);
1da177e4	133
2ada815f	134	int saa7134_ts_start_streaming(struct vb2_queue *vq, unsigned int count)
1da177e4	135	{
2ada815f	136	struct saa7134_dmaqueue *dmaq = vq->drv_priv;
a00e6888	137	struct saa7134_dev *dev = dmaq->dev;
1da177e4	138
2ada815f HV	139	/*
	140	* Planar video capture and TS share the same DMA channel,
	141	* so only one can be active at a time.
	142	*/
	143	if (vb2_is_busy(&dev->video_vbq) && dev->fmt->planar) {
	144	struct saa7134_buf buf, tmp;
	145
	146	list_for_each_entry_safe(buf, tmp, &dmaq->queue, entry) {
	147	list_del(&buf->entry);
2d700715 JS	148	vb2_buffer_done(&buf->vb2.vb2_buf,
2d700715 JS	149	VB2_BUF_STATE_QUEUED);
2ada815f HV	150	}
2ada815f HV	151	if (dmaq->curr) {
2d700715 JS	152	vb2_buffer_done(&dmaq->curr->vb2.vb2_buf,
2d700715 JS	153	VB2_BUF_STATE_QUEUED);
2ada815f HV	154	dmaq->curr = NULL;
	155	}
	156	return -EBUSY;
	157	}
	158	dmaq->seq_nr = 0;
	159	return 0;
1da177e4	160	}
2ada815f	161	EXPORT_SYMBOL_GPL(saa7134_ts_start_streaming);
1da177e4	162
2ada815f	163	void saa7134_ts_stop_streaming(struct vb2_queue *vq)
1da177e4	164	{
2ada815f	165	struct saa7134_dmaqueue *dmaq = vq->drv_priv;
a00e6888	166	struct saa7134_dev *dev = dmaq->dev;
1da177e4	167
2ada815f HV	168	saa7134_ts_stop(dev);
2ada815f HV	169	saa7134_stop_streaming(dev, dmaq);
1da177e4	170	}
2ada815f HV	171	EXPORT_SYMBOL_GPL(saa7134_ts_stop_streaming);
	172
	173	struct vb2_ops saa7134_ts_qops = {
	174	.queue_setup = saa7134_ts_queue_setup,
	175	.buf_init = saa7134_ts_buffer_init,
	176	.buf_prepare = saa7134_ts_buffer_prepare,
2ada815f HV	177	.buf_queue = saa7134_vb2_buffer_queue,
	178	.wait_prepare = vb2_ops_wait_prepare,
	179	.wait_finish = vb2_ops_wait_finish,
	180	.stop_streaming = saa7134_ts_stop_streaming,
1da177e4 LT	181	};
	182	EXPORT_SYMBOL_GPL(saa7134_ts_qops);
	183
	184	/* ----------------------------------------------------------- */
	185	/* exported stuff */
	186
3aa4f48a	187	static unsigned int tsbufs = 8;
1da177e4	188	module_param(tsbufs, int, 0444);
6b6b7543	189	MODULE_PARM_DESC(tsbufs, "number of ts buffers for read/write IO, range 2-32");
1da177e4	190
3aa4f48a	191	static unsigned int ts_nr_packets = 64;
1da177e4 LT	192	module_param(ts_nr_packets, int, 0444);
	193	MODULE_PARM_DESC(ts_nr_packets,"size of a ts buffers (in ts packets)");
	194
cb71201f ML	195	int saa7134_ts_init_hw(struct saa7134_dev *dev)
	196	{
	197	/* deactivate TS softreset */
	198	saa_writeb(SAA7134_TS_SERIAL1, 0x00);
	199	/* TSSOP high active, TSVAL high active, TSLOCK ignored */
92c36147	200	saa_writeb(SAA7134_TS_PARALLEL, 0x6c);
cb71201f ML	201	saa_writeb(SAA7134_TS_PARALLEL_SERIAL, (TS_PACKET_SIZE-1));
	202	saa_writeb(SAA7134_TS_DMA0, ((dev->ts.nr_packets-1)&0xff));
	203	saa_writeb(SAA7134_TS_DMA1, (((dev->ts.nr_packets-1)>>8)&0xff));
	204	/* TSNOPIT=0, TSCOLAP=0 */
	205	saa_writeb(SAA7134_TS_DMA2,
	206	((((dev->ts.nr_packets-1)>>16)&0x3f) \| 0x00));
	207
	208	return 0;
	209	}
	210
1da177e4 LT	211	int saa7134_ts_init1(struct saa7134_dev *dev)
	212	{
	213	/* sanitycheck insmod options */
	214	if (tsbufs < 2)
	215	tsbufs = 2;
	216	if (tsbufs > VIDEO_MAX_FRAME)
	217	tsbufs = VIDEO_MAX_FRAME;
	218	if (ts_nr_packets < 4)
	219	ts_nr_packets = 4;
	220	if (ts_nr_packets > 312)
	221	ts_nr_packets = 312;
	222	dev->ts.nr_bufs = tsbufs;
	223	dev->ts.nr_packets = ts_nr_packets;
	224
	225	INIT_LIST_HEAD(&dev->ts_q.queue);
	226	init_timer(&dev->ts_q.timeout);
	227	dev->ts_q.timeout.function = saa7134_buffer_timeout;
	228	dev->ts_q.timeout.data = (unsigned long)(&dev->ts_q);
	229	dev->ts_q.dev = dev;
	230	dev->ts_q.need_two = 1;
6b6b7543	231	dev->ts_started = 0;
a00e6888	232	saa7134_pgtable_alloc(dev->pci, &dev->ts_q.pt);
1da177e4 LT	233
1da177e4 LT	234	/* init TS hw */
cb71201f	235	saa7134_ts_init_hw(dev);
1da177e4 LT	236
	237	return 0;
	238	}
	239
6b6b7543 DB	240	/* Function for stop TS */
	241	int saa7134_ts_stop(struct saa7134_dev *dev)
	242	{
af5d20ce	243	ts_dbg("TS stop\n");
6b6b7543	244
2ada815f HV	245	if (!dev->ts_started)
2ada815f HV	246	return 0;
6b6b7543 DB	247
	248	/* Stop TS stream */
	249	switch (saa7134_boards[dev->board].ts_type) {
	250	case SAA7134_MPEG_TS_PARALLEL:
	251	saa_writeb(SAA7134_TS_PARALLEL, 0x6c);
	252	dev->ts_started = 0;
	253	break;
	254	case SAA7134_MPEG_TS_SERIAL:
	255	saa_writeb(SAA7134_TS_SERIAL0, 0x40);
	256	dev->ts_started = 0;
	257	break;
	258	}
	259	return 0;
	260	}
	261
	262	/* Function for start TS */
	263	int saa7134_ts_start(struct saa7134_dev *dev)
	264	{
af5d20ce	265	ts_dbg("TS start\n");
6b6b7543	266
2ada815f HV	267	if (WARN_ON(dev->ts_started))
2ada815f HV	268	return 0;
6b6b7543	269
08be64be DB	270	/* dma: setup channel 5 (= TS) */
	271	saa_writeb(SAA7134_TS_DMA0, (dev->ts.nr_packets - 1) & 0xff);
	272	saa_writeb(SAA7134_TS_DMA1,
	273	((dev->ts.nr_packets - 1) >> 8) & 0xff);
	274	/* TSNOPIT=0, TSCOLAP=0 */
	275	saa_writeb(SAA7134_TS_DMA2,
	276	(((dev->ts.nr_packets - 1) >> 16) & 0x3f) \| 0x00);
	277	saa_writel(SAA7134_RS_PITCH(5), TS_PACKET_SIZE);
	278	saa_writel(SAA7134_RS_CONTROL(5), SAA7134_RS_CONTROL_BURST_16 \|
	279	SAA7134_RS_CONTROL_ME \|
a00e6888	280	(dev->ts_q.pt.dma >> 12));
08be64be DB	281
08be64be DB	282	/* reset hardware TS buffers */
6b6b7543 DB	283	saa_writeb(SAA7134_TS_SERIAL1, 0x00);
	284	saa_writeb(SAA7134_TS_SERIAL1, 0x03);
	285	saa_writeb(SAA7134_TS_SERIAL1, 0x00);
	286	saa_writeb(SAA7134_TS_SERIAL1, 0x01);
	287
	288	/* TS clock non-inverted */
	289	saa_writeb(SAA7134_TS_SERIAL1, 0x00);
	290
	291	/* Start TS stream */
	292	switch (saa7134_boards[dev->board].ts_type) {
	293	case SAA7134_MPEG_TS_PARALLEL:
	294	saa_writeb(SAA7134_TS_SERIAL0, 0x40);
4007a672 MK	295	saa_writeb(SAA7134_TS_PARALLEL, 0xec \|
4007a672 MK	296	(saa7134_boards[dev->board].ts_force_val << 4));
6b6b7543 DB	297	break;
	298	case SAA7134_MPEG_TS_SERIAL:
	299	saa_writeb(SAA7134_TS_SERIAL0, 0xd8);
4007a672 MK	300	saa_writeb(SAA7134_TS_PARALLEL, 0x6c \|
4007a672 MK	301	(saa7134_boards[dev->board].ts_force_val << 4));
6b6b7543 DB	302	saa_writeb(SAA7134_TS_PARALLEL_SERIAL, 0xbc);
	303	saa_writeb(SAA7134_TS_SERIAL1, 0x02);
	304	break;
	305	}
	306
	307	dev->ts_started = 1;
	308
	309	return 0;
	310	}
	311
1da177e4 LT	312	int saa7134_ts_fini(struct saa7134_dev *dev)
1da177e4 LT	313	{
a00e6888	314	saa7134_pgtable_free(dev->pci, &dev->ts_q.pt);
1da177e4 LT	315	return 0;
	316	}
	317
1da177e4 LT	318	void saa7134_irq_ts_done(struct saa7134_dev *dev, unsigned long status)
	319	{
	320	enum v4l2_field field;
	321
	322	spin_lock(&dev->slock);
	323	if (dev->ts_q.curr) {
2ada815f HV	324	field = dev->ts_field;
2ada815f HV	325	if (field != V4L2_FIELD_TOP) {
3aa4f48a	326	if ((status & 0x100000) != 0x000000)
1da177e4 LT	327	goto done;
1da177e4 LT	328	} else {
3aa4f48a	329	if ((status & 0x100000) != 0x100000)
1da177e4 LT	330	goto done;
1da177e4 LT	331	}
2ada815f	332	saa7134_buffer_finish(dev, &dev->ts_q, VB2_BUF_STATE_DONE);
1da177e4 LT	333	}
	334	saa7134_buffer_next(dev,&dev->ts_q);
	335
	336	done:
	337	spin_unlock(&dev->slock);
	338	}