[mirror_ubuntu-artful-kernel.git] / drivers / media / pci / saa7134 / saa7134-ts.c

/*
 *
 * device driver for philips saa7134 based TV cards
 * video4linux video interface
 *
 * (c) 2001,02 Gerd Knorr <kraxel@bytesex.org> [SuSE Labs]
 *
 *  This program is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License as published by
 *  the Free Software Foundation; either version 2 of the License, or
 *  (at your option) any later version.
 *
 *  This program is distributed in the hope that it will be useful,
 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *  GNU General Public License for more details.
 *
 *  You should have received a copy of the GNU General Public License
 *  along with this program; if not, write to the Free Software
 *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 */

#include "saa7134.h"
#include "saa7134-reg.h"

#include <linux/init.h>
#include <linux/list.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/delay.h>

/* ------------------------------------------------------------------ */

static unsigned int ts_debug;
module_param(ts_debug, int, 0644);
MODULE_PARM_DESC(ts_debug,"enable debug messages [ts]");

#define ts_dbg(fmt, arg...)	if (ts_debug) \
	printk(KERN_DEBUG pr_fmt("ts: " fmt), ## arg)

/* ------------------------------------------------------------------ */
static int buffer_activate(struct saa7134_dev *dev,
			   struct saa7134_buf *buf,
			   struct saa7134_buf *next)
{

	ts_dbg("buffer_activate [%p]",buf);
	buf->top_seen = 0;

	if (!dev->ts_started)
		dev->ts_field = V4L2_FIELD_TOP;

	if (NULL == next)
		next = buf;
	if (V4L2_FIELD_TOP == dev->ts_field) {
		ts_dbg("- [top]     buf=%p next=%p\n",buf,next);
		saa_writel(SAA7134_RS_BA1(5),saa7134_buffer_base(buf));
		saa_writel(SAA7134_RS_BA2(5),saa7134_buffer_base(next));
		dev->ts_field = V4L2_FIELD_BOTTOM;
	} else {
		ts_dbg("- [bottom]  buf=%p next=%p\n",buf,next);
		saa_writel(SAA7134_RS_BA1(5),saa7134_buffer_base(next));
		saa_writel(SAA7134_RS_BA2(5),saa7134_buffer_base(buf));
		dev->ts_field = V4L2_FIELD_TOP;
	}

	/* start DMA */
	saa7134_set_dmabits(dev);

	mod_timer(&dev->ts_q.timeout, jiffies+TS_BUFFER_TIMEOUT);

	if (!dev->ts_started)
		saa7134_ts_start(dev);

	return 0;
}

int saa7134_ts_buffer_init(struct vb2_buffer *vb2)
{
	struct saa7134_dmaqueue *dmaq = vb2->vb2_queue->drv_priv;
	struct saa7134_buf *buf = container_of(vb2, struct saa7134_buf, vb2);

	dmaq->curr = NULL;
	buf->activate = buffer_activate;

	return 0;
}
EXPORT_SYMBOL_GPL(saa7134_ts_buffer_init);

int saa7134_ts_buffer_prepare(struct vb2_buffer *vb2)
{
	struct saa7134_dmaqueue *dmaq = vb2->vb2_queue->drv_priv;
	struct saa7134_dev *dev = dmaq->dev;
	struct saa7134_buf *buf = container_of(vb2, struct saa7134_buf, vb2);
	struct sg_table *dma = vb2_dma_sg_plane_desc(vb2, 0);
	unsigned int lines, llength, size;

	ts_dbg("buffer_prepare [%p]\n", buf);

	llength = TS_PACKET_SIZE;
	lines = dev->ts.nr_packets;

	size = lines * llength;
	if (vb2_plane_size(vb2, 0) < size)
		return -EINVAL;

	vb2_set_plane_payload(vb2, 0, size);
	vb2->v4l2_buf.field = dev->field;

	return saa7134_pgtable_build(dev->pci, &dmaq->pt, dma->sgl, dma->nents,
				    saa7134_buffer_startpage(buf));
}
EXPORT_SYMBOL_GPL(saa7134_ts_buffer_prepare);

int saa7134_ts_queue_setup(struct vb2_queue *q, const struct v4l2_format *fmt,
			   unsigned int *nbuffers, unsigned int *nplanes,
			   unsigned int sizes[], void *alloc_ctxs[])
{
	struct saa7134_dmaqueue *dmaq = q->drv_priv;
	struct saa7134_dev *dev = dmaq->dev;
	int size = TS_PACKET_SIZE * dev->ts.nr_packets;

	if (0 == *nbuffers)
		*nbuffers = dev->ts.nr_bufs;
	*nbuffers = saa7134_buffer_count(size, *nbuffers);
	if (*nbuffers < 3)
		*nbuffers = 3;
	*nplanes = 1;
	sizes[0] = size;
	alloc_ctxs[0] = dev->alloc_ctx;
	return 0;
}
EXPORT_SYMBOL_GPL(saa7134_ts_queue_setup);

int saa7134_ts_start_streaming(struct vb2_queue *vq, unsigned int count)
{
	struct saa7134_dmaqueue *dmaq = vq->drv_priv;
	struct saa7134_dev *dev = dmaq->dev;

	/*
	 * Planar video capture and TS share the same DMA channel,
	 * so only one can be active at a time.
	 */
	if (vb2_is_busy(&dev->video_vbq) && dev->fmt->planar) {
		struct saa7134_buf *buf, *tmp;

		list_for_each_entry_safe(buf, tmp, &dmaq->queue, entry) {
			list_del(&buf->entry);
			vb2_buffer_done(&buf->vb2, VB2_BUF_STATE_QUEUED);
		}
		if (dmaq->curr) {
			vb2_buffer_done(&dmaq->curr->vb2, VB2_BUF_STATE_QUEUED);
			dmaq->curr = NULL;
		}
		return -EBUSY;
	}
	dmaq->seq_nr = 0;
	return 0;
}
EXPORT_SYMBOL_GPL(saa7134_ts_start_streaming);

void saa7134_ts_stop_streaming(struct vb2_queue *vq)
{
	struct saa7134_dmaqueue *dmaq = vq->drv_priv;
	struct saa7134_dev *dev = dmaq->dev;

	saa7134_ts_stop(dev);
	saa7134_stop_streaming(dev, dmaq);
}
EXPORT_SYMBOL_GPL(saa7134_ts_stop_streaming);

struct vb2_ops saa7134_ts_qops = {
	.queue_setup	= saa7134_ts_queue_setup,
	.buf_init	= saa7134_ts_buffer_init,
	.buf_prepare	= saa7134_ts_buffer_prepare,
	.buf_queue	= saa7134_vb2_buffer_queue,
	.wait_prepare	= vb2_ops_wait_prepare,
	.wait_finish	= vb2_ops_wait_finish,
	.stop_streaming = saa7134_ts_stop_streaming,
};
EXPORT_SYMBOL_GPL(saa7134_ts_qops);

/* ----------------------------------------------------------- */
/* exported stuff                                              */

static unsigned int tsbufs = 8;
module_param(tsbufs, int, 0444);
MODULE_PARM_DESC(tsbufs, "number of ts buffers for read/write IO, range 2-32");

static unsigned int ts_nr_packets = 64;
module_param(ts_nr_packets, int, 0444);
MODULE_PARM_DESC(ts_nr_packets,"size of a ts buffers (in ts packets)");

int saa7134_ts_init_hw(struct saa7134_dev *dev)
{
	/* deactivate TS softreset */
	saa_writeb(SAA7134_TS_SERIAL1, 0x00);
	/* TSSOP high active, TSVAL high active, TSLOCK ignored */
	saa_writeb(SAA7134_TS_PARALLEL, 0x6c);
	saa_writeb(SAA7134_TS_PARALLEL_SERIAL, (TS_PACKET_SIZE-1));
	saa_writeb(SAA7134_TS_DMA0, ((dev->ts.nr_packets-1)&0xff));
	saa_writeb(SAA7134_TS_DMA1, (((dev->ts.nr_packets-1)>>8)&0xff));
	/* TSNOPIT=0, TSCOLAP=0 */
	saa_writeb(SAA7134_TS_DMA2,
		((((dev->ts.nr_packets-1)>>16)&0x3f) | 0x00));

	return 0;
}

int saa7134_ts_init1(struct saa7134_dev *dev)
{
	/* sanitycheck insmod options */
	if (tsbufs < 2)
		tsbufs = 2;
	if (tsbufs > VIDEO_MAX_FRAME)
		tsbufs = VIDEO_MAX_FRAME;
	if (ts_nr_packets < 4)
		ts_nr_packets = 4;
	if (ts_nr_packets > 312)
		ts_nr_packets = 312;
	dev->ts.nr_bufs    = tsbufs;
	dev->ts.nr_packets = ts_nr_packets;

	INIT_LIST_HEAD(&dev->ts_q.queue);
	init_timer(&dev->ts_q.timeout);
	dev->ts_q.timeout.function = saa7134_buffer_timeout;
	dev->ts_q.timeout.data     = (unsigned long)(&dev->ts_q);
	dev->ts_q.dev              = dev;
	dev->ts_q.need_two         = 1;
	dev->ts_started            = 0;
	saa7134_pgtable_alloc(dev->pci, &dev->ts_q.pt);

	/* init TS hw */
	saa7134_ts_init_hw(dev);

	return 0;
}

/* Function for stop TS */
int saa7134_ts_stop(struct saa7134_dev *dev)
{
	ts_dbg("TS stop\n");

	if (!dev->ts_started)
		return 0;

	/* Stop TS stream */
	switch (saa7134_boards[dev->board].ts_type) {
	case SAA7134_MPEG_TS_PARALLEL:
		saa_writeb(SAA7134_TS_PARALLEL, 0x6c);
		dev->ts_started = 0;
		break;
	case SAA7134_MPEG_TS_SERIAL:
		saa_writeb(SAA7134_TS_SERIAL0, 0x40);
		dev->ts_started = 0;
		break;
	}
	return 0;
}

/* Function for start TS */
int saa7134_ts_start(struct saa7134_dev *dev)
{
	ts_dbg("TS start\n");

	if (WARN_ON(dev->ts_started))
		return 0;

	/* dma: setup channel 5 (= TS) */
	saa_writeb(SAA7134_TS_DMA0, (dev->ts.nr_packets - 1) & 0xff);
	saa_writeb(SAA7134_TS_DMA1,
		((dev->ts.nr_packets - 1) >> 8) & 0xff);
	/* TSNOPIT=0, TSCOLAP=0 */
	saa_writeb(SAA7134_TS_DMA2,
		(((dev->ts.nr_packets - 1) >> 16) & 0x3f) | 0x00);
	saa_writel(SAA7134_RS_PITCH(5), TS_PACKET_SIZE);
	saa_writel(SAA7134_RS_CONTROL(5), SAA7134_RS_CONTROL_BURST_16 |
					  SAA7134_RS_CONTROL_ME |
					  (dev->ts_q.pt.dma >> 12));

	/* reset hardware TS buffers */
	saa_writeb(SAA7134_TS_SERIAL1, 0x00);
	saa_writeb(SAA7134_TS_SERIAL1, 0x03);
	saa_writeb(SAA7134_TS_SERIAL1, 0x00);
	saa_writeb(SAA7134_TS_SERIAL1, 0x01);

	/* TS clock non-inverted */
	saa_writeb(SAA7134_TS_SERIAL1, 0x00);

	/* Start TS stream */
	switch (saa7134_boards[dev->board].ts_type) {
	case SAA7134_MPEG_TS_PARALLEL:
		saa_writeb(SAA7134_TS_SERIAL0, 0x40);
		saa_writeb(SAA7134_TS_PARALLEL, 0xec |
			(saa7134_boards[dev->board].ts_force_val << 4));
		break;
	case SAA7134_MPEG_TS_SERIAL:
		saa_writeb(SAA7134_TS_SERIAL0, 0xd8);
		saa_writeb(SAA7134_TS_PARALLEL, 0x6c |
			(saa7134_boards[dev->board].ts_force_val << 4));
		saa_writeb(SAA7134_TS_PARALLEL_SERIAL, 0xbc);
		saa_writeb(SAA7134_TS_SERIAL1, 0x02);
		break;
	}

	dev->ts_started = 1;

	return 0;
}

int saa7134_ts_fini(struct saa7134_dev *dev)
{
	saa7134_pgtable_free(dev->pci, &dev->ts_q.pt);
	return 0;
}

void saa7134_irq_ts_done(struct saa7134_dev *dev, unsigned long status)
{
	enum v4l2_field field;

	spin_lock(&dev->slock);
	if (dev->ts_q.curr) {
		field = dev->ts_field;
		if (field != V4L2_FIELD_TOP) {
			if ((status & 0x100000) != 0x000000)
				goto done;
		} else {
			if ((status & 0x100000) != 0x100000)
				goto done;
		}
		saa7134_buffer_finish(dev, &dev->ts_q, VB2_BUF_STATE_DONE);
	}
	saa7134_buffer_next(dev,&dev->ts_q);

 done:
	spin_unlock(&dev->slock);
}
Commit	Line	Data
1da177e4	1	/*
1da177e4 LT	2	*
	3	* device driver for philips saa7134 based TV cards
	4	* video4linux video interface
	5	*
	6	* (c) 2001,02 Gerd Knorr <kraxel@bytesex.org> [SuSE Labs]
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License as published by
	10	* the Free Software Foundation; either version 2 of the License, or
	11	* (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
	21	*/
	22
9a12ccfc MCC	23	#include "saa7134.h"
	24	#include "saa7134-reg.h"
	25
1da177e4 LT	26	#include <linux/init.h>
	27	#include <linux/list.h>
	28	#include <linux/module.h>
1da177e4	29	#include <linux/kernel.h>
1da177e4 LT	30	#include <linux/delay.h>
1da177e4 LT	31
1da177e4 LT	32	/* ------------------------------------------------------------------ */
1da177e4 LT	33
ff699e6b	34	static unsigned int ts_debug;
1da177e4 LT	35	module_param(ts_debug, int, 0644);
	36	MODULE_PARM_DESC(ts_debug,"enable debug messages [ts]");
	37
af5d20ce MCC	38	#define ts_dbg(fmt, arg...) if (ts_debug) \
af5d20ce MCC	39	printk(KERN_DEBUG pr_fmt("ts: " fmt), ## arg)
1da177e4 LT	40
1da177e4 LT	41	/* ------------------------------------------------------------------ */
1da177e4 LT	42	static int buffer_activate(struct saa7134_dev *dev,
	43	struct saa7134_buf *buf,
	44	struct saa7134_buf *next)
	45	{
1da177e4	46
af5d20ce	47	ts_dbg("buffer_activate [%p]",buf);
1da177e4 LT	48	buf->top_seen = 0;
1da177e4 LT	49
2ada815f HV	50	if (!dev->ts_started)
	51	dev->ts_field = V4L2_FIELD_TOP;
	52
1da177e4 LT	53	if (NULL == next)
1da177e4 LT	54	next = buf;
2ada815f	55	if (V4L2_FIELD_TOP == dev->ts_field) {
af5d20ce	56	ts_dbg("- [top] buf=%p next=%p\n",buf,next);
1da177e4 LT	57	saa_writel(SAA7134_RS_BA1(5),saa7134_buffer_base(buf));
1da177e4 LT	58	saa_writel(SAA7134_RS_BA2(5),saa7134_buffer_base(next));
2ada815f	59	dev->ts_field = V4L2_FIELD_BOTTOM;
1da177e4	60	} else {
af5d20ce	61	ts_dbg("- [bottom] buf=%p next=%p\n",buf,next);
1da177e4 LT	62	saa_writel(SAA7134_RS_BA1(5),saa7134_buffer_base(next));
1da177e4 LT	63	saa_writel(SAA7134_RS_BA2(5),saa7134_buffer_base(buf));
2ada815f	64	dev->ts_field = V4L2_FIELD_TOP;
1da177e4	65	}
1da177e4 LT	66
	67	/* start DMA */
	68	saa7134_set_dmabits(dev);
	69
82aa98fd	70	mod_timer(&dev->ts_q.timeout, jiffies+TS_BUFFER_TIMEOUT);
92c36147	71
6b6b7543 DB	72	if (!dev->ts_started)
6b6b7543 DB	73	saa7134_ts_start(dev);
92c36147	74
1da177e4 LT	75	return 0;
	76	}
	77
2ada815f HV	78	int saa7134_ts_buffer_init(struct vb2_buffer *vb2)
	79	{
	80	struct saa7134_dmaqueue *dmaq = vb2->vb2_queue->drv_priv;
	81	struct saa7134_buf *buf = container_of(vb2, struct saa7134_buf, vb2);
	82
	83	dmaq->curr = NULL;
	84	buf->activate = buffer_activate;
	85
	86	return 0;
	87	}
	88	EXPORT_SYMBOL_GPL(saa7134_ts_buffer_init);
	89
	90	int saa7134_ts_buffer_prepare(struct vb2_buffer *vb2)
1da177e4	91	{
2ada815f	92	struct saa7134_dmaqueue *dmaq = vb2->vb2_queue->drv_priv;
a00e6888	93	struct saa7134_dev *dev = dmaq->dev;
2ada815f HV	94	struct saa7134_buf *buf = container_of(vb2, struct saa7134_buf, vb2);
2ada815f HV	95	struct sg_table *dma = vb2_dma_sg_plane_desc(vb2, 0);
1da177e4	96	unsigned int lines, llength, size;
1da177e4	97
af5d20ce	98	ts_dbg("buffer_prepare [%p]\n", buf);
1da177e4 LT	99
	100	llength = TS_PACKET_SIZE;
	101	lines = dev->ts.nr_packets;
	102
	103	size = lines * llength;
2ada815f	104	if (vb2_plane_size(vb2, 0) < size)
1da177e4 LT	105	return -EINVAL;
1da177e4 LT	106
2ada815f HV	107	vb2_set_plane_payload(vb2, 0, size);
2ada815f HV	108	vb2->v4l2_buf.field = dev->field;
6b6b7543	109
2ada815f HV	110	return saa7134_pgtable_build(dev->pci, &dmaq->pt, dma->sgl, dma->nents,
2ada815f HV	111	saa7134_buffer_startpage(buf));
1da177e4	112	}
2ada815f	113	EXPORT_SYMBOL_GPL(saa7134_ts_buffer_prepare);
1da177e4	114
2ada815f HV	115	int saa7134_ts_queue_setup(struct vb2_queue q, const struct v4l2_format fmt,
	116	unsigned int nbuffers, unsigned int nplanes,
	117	unsigned int sizes[], void *alloc_ctxs[])
	118	{
	119	struct saa7134_dmaqueue *dmaq = q->drv_priv;
	120	struct saa7134_dev *dev = dmaq->dev;
	121	int size = TS_PACKET_SIZE * dev->ts.nr_packets;
	122
	123	if (0 == *nbuffers)
	124	*nbuffers = dev->ts.nr_bufs;
	125	nbuffers = saa7134_buffer_count(size, nbuffers);
	126	if (*nbuffers < 3)
	127	*nbuffers = 3;
	128	*nplanes = 1;
	129	sizes[0] = size;
0c3a14c1	130	alloc_ctxs[0] = dev->alloc_ctx;
1da177e4 LT	131	return 0;
1da177e4 LT	132	}
2ada815f	133	EXPORT_SYMBOL_GPL(saa7134_ts_queue_setup);
1da177e4	134
2ada815f	135	int saa7134_ts_start_streaming(struct vb2_queue *vq, unsigned int count)
1da177e4	136	{
2ada815f	137	struct saa7134_dmaqueue *dmaq = vq->drv_priv;
a00e6888	138	struct saa7134_dev *dev = dmaq->dev;
1da177e4	139
2ada815f HV	140	/*
	141	* Planar video capture and TS share the same DMA channel,
	142	* so only one can be active at a time.
	143	*/
	144	if (vb2_is_busy(&dev->video_vbq) && dev->fmt->planar) {
	145	struct saa7134_buf buf, tmp;
	146
	147	list_for_each_entry_safe(buf, tmp, &dmaq->queue, entry) {
	148	list_del(&buf->entry);
	149	vb2_buffer_done(&buf->vb2, VB2_BUF_STATE_QUEUED);
	150	}
	151	if (dmaq->curr) {
	152	vb2_buffer_done(&dmaq->curr->vb2, VB2_BUF_STATE_QUEUED);
	153	dmaq->curr = NULL;
	154	}
	155	return -EBUSY;
	156	}
	157	dmaq->seq_nr = 0;
	158	return 0;
1da177e4	159	}
2ada815f	160	EXPORT_SYMBOL_GPL(saa7134_ts_start_streaming);
1da177e4	161
2ada815f	162	void saa7134_ts_stop_streaming(struct vb2_queue *vq)
1da177e4	163	{
2ada815f	164	struct saa7134_dmaqueue *dmaq = vq->drv_priv;
a00e6888	165	struct saa7134_dev *dev = dmaq->dev;
1da177e4	166
2ada815f HV	167	saa7134_ts_stop(dev);
2ada815f HV	168	saa7134_stop_streaming(dev, dmaq);
1da177e4	169	}
2ada815f HV	170	EXPORT_SYMBOL_GPL(saa7134_ts_stop_streaming);
	171
	172	struct vb2_ops saa7134_ts_qops = {
	173	.queue_setup = saa7134_ts_queue_setup,
	174	.buf_init = saa7134_ts_buffer_init,
	175	.buf_prepare = saa7134_ts_buffer_prepare,
2ada815f HV	176	.buf_queue = saa7134_vb2_buffer_queue,
	177	.wait_prepare = vb2_ops_wait_prepare,
	178	.wait_finish = vb2_ops_wait_finish,
	179	.stop_streaming = saa7134_ts_stop_streaming,
1da177e4 LT	180	};
	181	EXPORT_SYMBOL_GPL(saa7134_ts_qops);
	182
	183	/* ----------------------------------------------------------- */
	184	/* exported stuff */
	185
3aa4f48a	186	static unsigned int tsbufs = 8;
1da177e4	187	module_param(tsbufs, int, 0444);
6b6b7543	188	MODULE_PARM_DESC(tsbufs, "number of ts buffers for read/write IO, range 2-32");
1da177e4	189
3aa4f48a	190	static unsigned int ts_nr_packets = 64;
1da177e4 LT	191	module_param(ts_nr_packets, int, 0444);
	192	MODULE_PARM_DESC(ts_nr_packets,"size of a ts buffers (in ts packets)");
	193
cb71201f ML	194	int saa7134_ts_init_hw(struct saa7134_dev *dev)
	195	{
	196	/* deactivate TS softreset */
	197	saa_writeb(SAA7134_TS_SERIAL1, 0x00);
	198	/* TSSOP high active, TSVAL high active, TSLOCK ignored */
92c36147	199	saa_writeb(SAA7134_TS_PARALLEL, 0x6c);
cb71201f ML	200	saa_writeb(SAA7134_TS_PARALLEL_SERIAL, (TS_PACKET_SIZE-1));
	201	saa_writeb(SAA7134_TS_DMA0, ((dev->ts.nr_packets-1)&0xff));
	202	saa_writeb(SAA7134_TS_DMA1, (((dev->ts.nr_packets-1)>>8)&0xff));
	203	/* TSNOPIT=0, TSCOLAP=0 */
	204	saa_writeb(SAA7134_TS_DMA2,
	205	((((dev->ts.nr_packets-1)>>16)&0x3f) \| 0x00));
	206
	207	return 0;
	208	}
	209
1da177e4 LT	210	int saa7134_ts_init1(struct saa7134_dev *dev)
	211	{
	212	/* sanitycheck insmod options */
	213	if (tsbufs < 2)
	214	tsbufs = 2;
	215	if (tsbufs > VIDEO_MAX_FRAME)
	216	tsbufs = VIDEO_MAX_FRAME;
	217	if (ts_nr_packets < 4)
	218	ts_nr_packets = 4;
	219	if (ts_nr_packets > 312)
	220	ts_nr_packets = 312;
	221	dev->ts.nr_bufs = tsbufs;
	222	dev->ts.nr_packets = ts_nr_packets;
	223
	224	INIT_LIST_HEAD(&dev->ts_q.queue);
	225	init_timer(&dev->ts_q.timeout);
	226	dev->ts_q.timeout.function = saa7134_buffer_timeout;
	227	dev->ts_q.timeout.data = (unsigned long)(&dev->ts_q);
	228	dev->ts_q.dev = dev;
	229	dev->ts_q.need_two = 1;
6b6b7543	230	dev->ts_started = 0;
a00e6888	231	saa7134_pgtable_alloc(dev->pci, &dev->ts_q.pt);
1da177e4 LT	232
1da177e4 LT	233	/* init TS hw */
cb71201f	234	saa7134_ts_init_hw(dev);
1da177e4 LT	235
	236	return 0;
	237	}
	238
6b6b7543 DB	239	/* Function for stop TS */
	240	int saa7134_ts_stop(struct saa7134_dev *dev)
	241	{
af5d20ce	242	ts_dbg("TS stop\n");
6b6b7543	243
2ada815f HV	244	if (!dev->ts_started)
2ada815f HV	245	return 0;
6b6b7543 DB	246
	247	/* Stop TS stream */
	248	switch (saa7134_boards[dev->board].ts_type) {
	249	case SAA7134_MPEG_TS_PARALLEL:
	250	saa_writeb(SAA7134_TS_PARALLEL, 0x6c);
	251	dev->ts_started = 0;
	252	break;
	253	case SAA7134_MPEG_TS_SERIAL:
	254	saa_writeb(SAA7134_TS_SERIAL0, 0x40);
	255	dev->ts_started = 0;
	256	break;
	257	}
	258	return 0;
	259	}
	260
	261	/* Function for start TS */
	262	int saa7134_ts_start(struct saa7134_dev *dev)
	263	{
af5d20ce	264	ts_dbg("TS start\n");
6b6b7543	265
2ada815f HV	266	if (WARN_ON(dev->ts_started))
2ada815f HV	267	return 0;
6b6b7543	268
08be64be DB	269	/* dma: setup channel 5 (= TS) */
	270	saa_writeb(SAA7134_TS_DMA0, (dev->ts.nr_packets - 1) & 0xff);
	271	saa_writeb(SAA7134_TS_DMA1,
	272	((dev->ts.nr_packets - 1) >> 8) & 0xff);
	273	/* TSNOPIT=0, TSCOLAP=0 */
	274	saa_writeb(SAA7134_TS_DMA2,
	275	(((dev->ts.nr_packets - 1) >> 16) & 0x3f) \| 0x00);
	276	saa_writel(SAA7134_RS_PITCH(5), TS_PACKET_SIZE);
	277	saa_writel(SAA7134_RS_CONTROL(5), SAA7134_RS_CONTROL_BURST_16 \|
	278	SAA7134_RS_CONTROL_ME \|
a00e6888	279	(dev->ts_q.pt.dma >> 12));
08be64be DB	280
08be64be DB	281	/* reset hardware TS buffers */
6b6b7543 DB	282	saa_writeb(SAA7134_TS_SERIAL1, 0x00);
	283	saa_writeb(SAA7134_TS_SERIAL1, 0x03);
	284	saa_writeb(SAA7134_TS_SERIAL1, 0x00);
	285	saa_writeb(SAA7134_TS_SERIAL1, 0x01);
	286
	287	/* TS clock non-inverted */
	288	saa_writeb(SAA7134_TS_SERIAL1, 0x00);
	289
	290	/* Start TS stream */
	291	switch (saa7134_boards[dev->board].ts_type) {
	292	case SAA7134_MPEG_TS_PARALLEL:
	293	saa_writeb(SAA7134_TS_SERIAL0, 0x40);
4007a672 MK	294	saa_writeb(SAA7134_TS_PARALLEL, 0xec \|
4007a672 MK	295	(saa7134_boards[dev->board].ts_force_val << 4));
6b6b7543 DB	296	break;
	297	case SAA7134_MPEG_TS_SERIAL:
	298	saa_writeb(SAA7134_TS_SERIAL0, 0xd8);
4007a672 MK	299	saa_writeb(SAA7134_TS_PARALLEL, 0x6c \|
4007a672 MK	300	(saa7134_boards[dev->board].ts_force_val << 4));
6b6b7543 DB	301	saa_writeb(SAA7134_TS_PARALLEL_SERIAL, 0xbc);
	302	saa_writeb(SAA7134_TS_SERIAL1, 0x02);
	303	break;
	304	}
	305
	306	dev->ts_started = 1;
	307
	308	return 0;
	309	}
	310
1da177e4 LT	311	int saa7134_ts_fini(struct saa7134_dev *dev)
1da177e4 LT	312	{
a00e6888	313	saa7134_pgtable_free(dev->pci, &dev->ts_q.pt);
1da177e4 LT	314	return 0;
	315	}
	316
1da177e4 LT	317	void saa7134_irq_ts_done(struct saa7134_dev *dev, unsigned long status)
	318	{
	319	enum v4l2_field field;
	320
	321	spin_lock(&dev->slock);
	322	if (dev->ts_q.curr) {
2ada815f HV	323	field = dev->ts_field;
2ada815f HV	324	if (field != V4L2_FIELD_TOP) {
3aa4f48a	325	if ((status & 0x100000) != 0x000000)
1da177e4 LT	326	goto done;
1da177e4 LT	327	} else {
3aa4f48a	328	if ((status & 0x100000) != 0x100000)
1da177e4 LT	329	goto done;
1da177e4 LT	330	}
2ada815f	331	saa7134_buffer_finish(dev, &dev->ts_q, VB2_BUF_STATE_DONE);
1da177e4 LT	332	}
	333	saa7134_buffer_next(dev,&dev->ts_q);
	334
	335	done:
	336	spin_unlock(&dev->slock);
	337	}