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Commit | Line | Data |
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443c1228 ST |
1 | /* |
2 | * Driver for the NXP SAA7164 PCIe bridge | |
3 | * | |
63a412ec | 4 | * Copyright (c) 2010-2015 Steven Toth <stoth@kernellabs.com> |
443c1228 ST |
5 | * |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * | |
15 | * GNU General Public License for more details. | |
443c1228 ST |
16 | */ |
17 | ||
18 | #include <linux/init.h> | |
19 | #include <linux/list.h> | |
20 | #include <linux/module.h> | |
21 | #include <linux/moduleparam.h> | |
22 | #include <linux/kmod.h> | |
23 | #include <linux/kernel.h> | |
24 | #include <linux/slab.h> | |
25 | #include <linux/interrupt.h> | |
26 | #include <linux/delay.h> | |
27 | #include <asm/div64.h> | |
28 | ||
e48836b8 ST |
29 | #ifdef CONFIG_PROC_FS |
30 | #include <linux/proc_fs.h> | |
31 | #endif | |
443c1228 ST |
32 | #include "saa7164.h" |
33 | ||
34 | MODULE_DESCRIPTION("Driver for NXP SAA7164 based TV cards"); | |
9d119c33 | 35 | MODULE_AUTHOR("Steven Toth <stoth@kernellabs.com>"); |
443c1228 ST |
36 | MODULE_LICENSE("GPL"); |
37 | ||
38 | /* | |
bc250684 ST |
39 | * 1 Basic |
40 | * 2 | |
41 | * 4 i2c | |
42 | * 8 api | |
43 | * 16 cmd | |
44 | * 32 bus | |
443c1228 ST |
45 | */ |
46 | ||
b1912a85 IM |
47 | unsigned int saa_debug; |
48 | module_param_named(debug, saa_debug, int, 0644); | |
443c1228 ST |
49 | MODULE_PARM_DESC(debug, "enable debug messages"); |
50 | ||
5a9ff85d | 51 | static unsigned int fw_debug; |
e48836b8 | 52 | module_param(fw_debug, int, 0644); |
a895d57d | 53 | MODULE_PARM_DESC(fw_debug, "Firmware debug level def:2"); |
e48836b8 | 54 | |
66e1d378 ST |
55 | unsigned int encoder_buffers = SAA7164_MAX_ENCODER_BUFFERS; |
56 | module_param(encoder_buffers, int, 0644); | |
57 | MODULE_PARM_DESC(encoder_buffers, "Total buffers in read queue 16-512 def:64"); | |
58 | ||
e8ce2f21 ST |
59 | unsigned int vbi_buffers = SAA7164_MAX_VBI_BUFFERS; |
60 | module_param(vbi_buffers, int, 0644); | |
61 | MODULE_PARM_DESC(vbi_buffers, "Total buffers in read queue 16-512 def:64"); | |
62 | ||
bbf504c3 | 63 | unsigned int waitsecs = 10; |
dd1ee444 | 64 | module_param(waitsecs, int, 0644); |
66e1d378 | 65 | MODULE_PARM_DESC(waitsecs, "timeout on firmware messages"); |
dd1ee444 | 66 | |
443c1228 ST |
67 | static unsigned int card[] = {[0 ... (SAA7164_MAXBOARDS - 1)] = UNSET }; |
68 | module_param_array(card, int, NULL, 0444); | |
69 | MODULE_PARM_DESC(card, "card type"); | |
70 | ||
5a9ff85d | 71 | static unsigned int print_histogram = 64; |
91d80189 | 72 | module_param(print_histogram, int, 0644); |
66e1d378 | 73 | MODULE_PARM_DESC(print_histogram, "print histogram values once"); |
91d80189 | 74 | |
1b0e8e46 ST |
75 | unsigned int crc_checking = 1; |
76 | module_param(crc_checking, int, 0644); | |
77 | MODULE_PARM_DESC(crc_checking, "enable crc sanity checking on buffers"); | |
78 | ||
5a9ff85d | 79 | static unsigned int guard_checking = 1; |
1b0e8e46 | 80 | module_param(guard_checking, int, 0644); |
bc250684 ST |
81 | MODULE_PARM_DESC(guard_checking, |
82 | "enable dma sanity checking for buffer overruns"); | |
1b0e8e46 | 83 | |
77978089 BM |
84 | static bool enable_msi = true; |
85 | module_param(enable_msi, bool, 0444); | |
86 | MODULE_PARM_DESC(enable_msi, | |
87 | "enable the use of an msi interrupt if available"); | |
88 | ||
443c1228 ST |
89 | static unsigned int saa7164_devcount; |
90 | ||
91 | static DEFINE_MUTEX(devlist); | |
92 | LIST_HEAD(saa7164_devlist); | |
93 | ||
94 | #define INT_SIZE 16 | |
95 | ||
a97781ac ST |
96 | static void saa7164_pack_verifier(struct saa7164_buffer *buf) |
97 | { | |
98 | u8 *p = (u8 *)buf->cpu; | |
99 | int i; | |
100 | ||
101 | for (i = 0; i < buf->actual_size; i += 2048) { | |
102 | ||
c7e242ba MCC |
103 | if ((*(p + i + 0) != 0x00) || (*(p + i + 1) != 0x00) || |
104 | (*(p + i + 2) != 0x01) || (*(p + i + 3) != 0xBA)) { | |
a97781ac | 105 | printk(KERN_ERR "No pack at 0x%x\n", i); |
bc250684 | 106 | #if 0 |
518c267f AS |
107 | print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET, 16, 1, |
108 | p + 1, 32, false); | |
bc250684 | 109 | #endif |
1b0e8e46 | 110 | } |
a97781ac ST |
111 | } |
112 | } | |
113 | ||
1b0e8e46 ST |
114 | #define FIXED_VIDEO_PID 0xf1 |
115 | #define FIXED_AUDIO_PID 0xf2 | |
116 | ||
9230acaa ST |
117 | static void saa7164_ts_verifier(struct saa7164_buffer *buf) |
118 | { | |
119 | struct saa7164_port *port = buf->port; | |
9230acaa | 120 | u32 i; |
1b0e8e46 ST |
121 | u8 cc, a; |
122 | u16 pid; | |
065e1477 | 123 | u8 *bufcpu = (u8 *)buf->cpu; |
9230acaa ST |
124 | |
125 | port->sync_errors = 0; | |
126 | port->v_cc_errors = 0; | |
127 | port->a_cc_errors = 0; | |
128 | ||
129 | for (i = 0; i < buf->actual_size; i += 188) { | |
130 | if (*(bufcpu + i) != 0x47) | |
131 | port->sync_errors++; | |
132 | ||
1b0e8e46 ST |
133 | /* TODO: Query pid lower 8 bits, ignoring upper bits intensionally */ |
134 | pid = ((*(bufcpu + i + 1) & 0x1f) << 8) | *(bufcpu + i + 2); | |
9230acaa ST |
135 | cc = *(bufcpu + i + 3) & 0x0f; |
136 | ||
1b0e8e46 | 137 | if (pid == FIXED_VIDEO_PID) { |
9230acaa ST |
138 | a = ((port->last_v_cc + 1) & 0x0f); |
139 | if (a != cc) { | |
1b0e8e46 ST |
140 | printk(KERN_ERR "video cc last = %x current = %x i = %d\n", |
141 | port->last_v_cc, cc, i); | |
9230acaa ST |
142 | port->v_cc_errors++; |
143 | } | |
144 | ||
145 | port->last_v_cc = cc; | |
146 | } else | |
1b0e8e46 | 147 | if (pid == FIXED_AUDIO_PID) { |
9230acaa ST |
148 | a = ((port->last_a_cc + 1) & 0x0f); |
149 | if (a != cc) { | |
1b0e8e46 ST |
150 | printk(KERN_ERR "audio cc last = %x current = %x i = %d\n", |
151 | port->last_a_cc, cc, i); | |
9230acaa ST |
152 | port->a_cc_errors++; |
153 | } | |
154 | ||
155 | port->last_a_cc = cc; | |
156 | } | |
157 | ||
158 | } | |
159 | ||
32299a14 ST |
160 | /* Only report errors if we've been through this function atleast |
161 | * once already and the cached cc values are primed. First time through | |
162 | * always generates errors. | |
163 | */ | |
164 | if (port->v_cc_errors && (port->done_first_interrupt > 1)) | |
9230acaa ST |
165 | printk(KERN_ERR "video pid cc, %d errors\n", port->v_cc_errors); |
166 | ||
32299a14 | 167 | if (port->a_cc_errors && (port->done_first_interrupt > 1)) |
9230acaa ST |
168 | printk(KERN_ERR "audio pid cc, %d errors\n", port->a_cc_errors); |
169 | ||
32299a14 | 170 | if (port->sync_errors && (port->done_first_interrupt > 1)) |
9230acaa | 171 | printk(KERN_ERR "sync_errors = %d\n", port->sync_errors); |
32299a14 ST |
172 | |
173 | if (port->done_first_interrupt == 1) | |
174 | port->done_first_interrupt++; | |
9230acaa ST |
175 | } |
176 | ||
91d80189 | 177 | static void saa7164_histogram_reset(struct saa7164_histogram *hg, char *name) |
443c1228 | 178 | { |
91d80189 | 179 | int i; |
443c1228 | 180 | |
91d80189 ST |
181 | memset(hg, 0, sizeof(struct saa7164_histogram)); |
182 | strcpy(hg->name, name); | |
183 | ||
184 | /* First 30ms x 1ms */ | |
bc250684 | 185 | for (i = 0; i < 30; i++) |
91d80189 | 186 | hg->counter1[0 + i].val = i; |
91d80189 ST |
187 | |
188 | /* 30 - 200ms x 10ms */ | |
bc250684 | 189 | for (i = 0; i < 18; i++) |
91d80189 | 190 | hg->counter1[30 + i].val = 30 + (i * 10); |
91d80189 ST |
191 | |
192 | /* 200 - 2000ms x 100ms */ | |
bc250684 | 193 | for (i = 0; i < 15; i++) |
58acca10 | 194 | hg->counter1[48 + i].val = 200 + (i * 200); |
91d80189 | 195 | |
58acca10 ST |
196 | /* Catch all massive value (2secs) */ |
197 | hg->counter1[55].val = 2000; | |
198 | ||
199 | /* Catch all massive value (4secs) */ | |
200 | hg->counter1[56].val = 4000; | |
201 | ||
202 | /* Catch all massive value (8secs) */ | |
203 | hg->counter1[57].val = 8000; | |
204 | ||
205 | /* Catch all massive value (15secs) */ | |
206 | hg->counter1[58].val = 15000; | |
207 | ||
208 | /* Catch all massive value (30secs) */ | |
209 | hg->counter1[59].val = 30000; | |
210 | ||
211 | /* Catch all massive value (60secs) */ | |
212 | hg->counter1[60].val = 60000; | |
213 | ||
214 | /* Catch all massive value (5mins) */ | |
215 | hg->counter1[61].val = 300000; | |
216 | ||
217 | /* Catch all massive value (15mins) */ | |
218 | hg->counter1[62].val = 900000; | |
219 | ||
220 | /* Catch all massive values (1hr) */ | |
91d80189 | 221 | hg->counter1[63].val = 3600000; |
443c1228 ST |
222 | } |
223 | ||
58acca10 | 224 | void saa7164_histogram_update(struct saa7164_histogram *hg, u32 val) |
443c1228 | 225 | { |
91d80189 | 226 | int i; |
c7e242ba | 227 | for (i = 0; i < 64; i++) { |
91d80189 ST |
228 | if (val <= hg->counter1[i].val) { |
229 | hg->counter1[i].count++; | |
230 | hg->counter1[i].update_time = jiffies; | |
231 | break; | |
232 | } | |
233 | } | |
234 | } | |
443c1228 | 235 | |
91d80189 ST |
236 | static void saa7164_histogram_print(struct saa7164_port *port, |
237 | struct saa7164_histogram *hg) | |
238 | { | |
91d80189 ST |
239 | u32 entries = 0; |
240 | int i; | |
241 | ||
58acca10 | 242 | printk(KERN_ERR "Histogram named %s (ms, count, last_update_jiffy)\n", hg->name); |
c7e242ba | 243 | for (i = 0; i < 64; i++) { |
91d80189 ST |
244 | if (hg->counter1[i].count == 0) |
245 | continue; | |
443c1228 | 246 | |
91d80189 ST |
247 | printk(KERN_ERR " %4d %12d %Ld\n", |
248 | hg->counter1[i].val, | |
249 | hg->counter1[i].count, | |
250 | hg->counter1[i].update_time); | |
251 | ||
252 | entries++; | |
253 | } | |
254 | printk(KERN_ERR "Total: %d\n", entries); | |
443c1228 ST |
255 | } |
256 | ||
cfbaf337 | 257 | static void saa7164_work_enchandler_helper(struct saa7164_port *port, int bufnr) |
7615e434 ST |
258 | { |
259 | struct saa7164_dev *dev = port->dev; | |
61ca1500 PH |
260 | struct saa7164_buffer *buf = NULL; |
261 | struct saa7164_user_buffer *ubuf = NULL; | |
7615e434 | 262 | struct list_head *c, *n; |
cfbaf337 | 263 | int i = 0; |
065e1477 | 264 | u8 *p; |
91d80189 ST |
265 | |
266 | mutex_lock(&port->dmaqueue_lock); | |
7615e434 | 267 | list_for_each_safe(c, n, &port->dmaqueue.list) { |
91d80189 | 268 | |
7615e434 | 269 | buf = list_entry(c, struct saa7164_buffer, list); |
91d80189 ST |
270 | if (i++ > port->hwcfg.buffercount) { |
271 | printk(KERN_ERR "%s() illegal i count %d\n", | |
272 | __func__, i); | |
273 | break; | |
274 | } | |
7615e434 | 275 | |
cfbaf337 | 276 | if (buf->idx == bufnr) { |
12d3203e | 277 | |
7615e434 | 278 | /* Found the buffer, deal with it */ |
1b0e8e46 ST |
279 | dprintk(DBGLVL_IRQ, "%s() bufnr: %d\n", __func__, bufnr); |
280 | ||
281 | if (crc_checking) { | |
282 | /* Throw a new checksum on the dma buffer */ | |
283 | buf->crc = crc32(0, buf->cpu, buf->actual_size); | |
284 | } | |
285 | ||
286 | if (guard_checking) { | |
287 | p = (u8 *)buf->cpu; | |
c7e242ba | 288 | if ((*(p + buf->actual_size + 0) != 0xff) || |
1b0e8e46 ST |
289 | (*(p + buf->actual_size + 1) != 0xff) || |
290 | (*(p + buf->actual_size + 2) != 0xff) || | |
291 | (*(p + buf->actual_size + 3) != 0xff) || | |
292 | (*(p + buf->actual_size + 0x10) != 0xff) || | |
293 | (*(p + buf->actual_size + 0x11) != 0xff) || | |
294 | (*(p + buf->actual_size + 0x12) != 0xff) || | |
c7e242ba | 295 | (*(p + buf->actual_size + 0x13) != 0xff)) { |
1b0e8e46 ST |
296 | printk(KERN_ERR "%s() buf %p guard buffer breach\n", |
297 | __func__, buf); | |
bc250684 | 298 | #if 0 |
518c267f AS |
299 | print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET, 16, 1, |
300 | p + buf->actual_size - 32, 64, false); | |
bc250684 | 301 | #endif |
1b0e8e46 ST |
302 | } |
303 | } | |
7615e434 | 304 | |
1107237e ST |
305 | if ((port->nr != SAA7164_PORT_VBI1) && (port->nr != SAA7164_PORT_VBI2)) { |
306 | /* Validate the incoming buffer content */ | |
307 | if (port->encoder_params.stream_type == V4L2_MPEG_STREAM_TYPE_MPEG2_TS) | |
308 | saa7164_ts_verifier(buf); | |
309 | else if (port->encoder_params.stream_type == V4L2_MPEG_STREAM_TYPE_MPEG2_PS) | |
310 | saa7164_pack_verifier(buf); | |
311 | } | |
9230acaa | 312 | |
7615e434 ST |
313 | /* find a free user buffer and clone to it */ |
314 | if (!list_empty(&port->list_buf_free.list)) { | |
315 | ||
316 | /* Pull the first buffer from the used list */ | |
317 | ubuf = list_first_entry(&port->list_buf_free.list, | |
318 | struct saa7164_user_buffer, list); | |
319 | ||
a97781ac ST |
320 | if (buf->actual_size <= ubuf->actual_size) { |
321 | ||
065e1477 | 322 | memcpy(ubuf->data, buf->cpu, ubuf->actual_size); |
12d3203e | 323 | |
1b0e8e46 ST |
324 | if (crc_checking) { |
325 | /* Throw a new checksum on the read buffer */ | |
326 | ubuf->crc = crc32(0, ubuf->data, ubuf->actual_size); | |
327 | } | |
12d3203e | 328 | |
a97781ac ST |
329 | /* Requeue the buffer on the free list */ |
330 | ubuf->pos = 0; | |
7615e434 | 331 | |
a97781ac ST |
332 | list_move_tail(&ubuf->list, |
333 | &port->list_buf_used.list); | |
7615e434 | 334 | |
a97781ac ST |
335 | /* Flag any userland waiters */ |
336 | wake_up_interruptible(&port->wait_read); | |
7615e434 | 337 | |
a97781ac ST |
338 | } else { |
339 | printk(KERN_ERR "buf %p bufsize fails match\n", buf); | |
340 | } | |
7615e434 ST |
341 | |
342 | } else | |
66e1d378 | 343 | printk(KERN_ERR "encirq no free buffers, increase param encoder_buffers\n"); |
7615e434 | 344 | |
9230acaa | 345 | /* Ensure offset into buffer remains 0, fill buffer |
a97781ac ST |
346 | * with known bad data. We check for this data at a later point |
347 | * in time. */ | |
cfbaf337 | 348 | saa7164_buffer_zero_offsets(port, bufnr); |
065e1477 | 349 | memset(buf->cpu, 0xff, buf->pci_size); |
1b0e8e46 ST |
350 | if (crc_checking) { |
351 | /* Throw yet aanother new checksum on the dma buffer */ | |
352 | buf->crc = crc32(0, buf->cpu, buf->actual_size); | |
353 | } | |
12d3203e | 354 | |
a97781ac | 355 | break; |
cfbaf337 ST |
356 | } |
357 | } | |
358 | mutex_unlock(&port->dmaqueue_lock); | |
359 | } | |
360 | ||
361 | static void saa7164_work_enchandler(struct work_struct *w) | |
362 | { | |
363 | struct saa7164_port *port = | |
364 | container_of(w, struct saa7164_port, workenc); | |
365 | struct saa7164_dev *dev = port->dev; | |
366 | ||
367 | u32 wp, mcb, rp, cnt = 0; | |
368 | ||
369 | port->last_svc_msecs_diff = port->last_svc_msecs; | |
370 | port->last_svc_msecs = jiffies_to_msecs(jiffies); | |
371 | ||
372 | port->last_svc_msecs_diff = port->last_svc_msecs - | |
373 | port->last_svc_msecs_diff; | |
374 | ||
375 | saa7164_histogram_update(&port->svc_interval, | |
376 | port->last_svc_msecs_diff); | |
377 | ||
378 | port->last_irq_svc_msecs_diff = port->last_svc_msecs - | |
379 | port->last_irq_msecs; | |
380 | ||
381 | saa7164_histogram_update(&port->irq_svc_interval, | |
382 | port->last_irq_svc_msecs_diff); | |
9230acaa | 383 | |
cfbaf337 ST |
384 | dprintk(DBGLVL_IRQ, |
385 | "%s() %Ldms elapsed irq->deferred %Ldms wp: %d rp: %d\n", | |
386 | __func__, | |
387 | port->last_svc_msecs_diff, | |
388 | port->last_irq_svc_msecs_diff, | |
389 | port->last_svc_wp, | |
390 | port->last_svc_rp | |
391 | ); | |
392 | ||
393 | /* Current write position */ | |
394 | wp = saa7164_readl(port->bufcounter); | |
395 | if (wp > (port->hwcfg.buffercount - 1)) { | |
396 | printk(KERN_ERR "%s() illegal buf count %d\n", __func__, wp); | |
397 | return; | |
398 | } | |
399 | ||
400 | /* Most current complete buffer */ | |
401 | if (wp == 0) | |
1b0e8e46 | 402 | mcb = (port->hwcfg.buffercount - 1); |
cfbaf337 ST |
403 | else |
404 | mcb = wp - 1; | |
405 | ||
406 | while (1) { | |
1b0e8e46 ST |
407 | if (port->done_first_interrupt == 0) { |
408 | port->done_first_interrupt++; | |
409 | rp = mcb; | |
410 | } else | |
411 | rp = (port->last_svc_rp + 1) % 8; | |
cfbaf337 | 412 | |
3eeba4a7 | 413 | if (rp > (port->hwcfg.buffercount - 1)) { |
cfbaf337 ST |
414 | printk(KERN_ERR "%s() illegal rp count %d\n", __func__, rp); |
415 | break; | |
7615e434 | 416 | } |
1b0e8e46 | 417 | |
cfbaf337 ST |
418 | saa7164_work_enchandler_helper(port, rp); |
419 | port->last_svc_rp = rp; | |
420 | cnt++; | |
421 | ||
422 | if (rp == mcb) | |
423 | break; | |
7615e434 | 424 | } |
cfbaf337 | 425 | |
1b0e8e46 | 426 | /* TODO: Convert this into a /proc/saa7164 style readable file */ |
91d80189 ST |
427 | if (print_histogram == port->nr) { |
428 | saa7164_histogram_print(port, &port->irq_interval); | |
429 | saa7164_histogram_print(port, &port->svc_interval); | |
430 | saa7164_histogram_print(port, &port->irq_svc_interval); | |
58acca10 ST |
431 | saa7164_histogram_print(port, &port->read_interval); |
432 | saa7164_histogram_print(port, &port->poll_interval); | |
7c161822 | 433 | /* TODO: fix this to preserve any previous state */ |
91d80189 ST |
434 | print_histogram = 64 + port->nr; |
435 | } | |
436 | } | |
cfbaf337 | 437 | |
e8ce2f21 ST |
438 | static void saa7164_work_vbihandler(struct work_struct *w) |
439 | { | |
440 | struct saa7164_port *port = | |
441 | container_of(w, struct saa7164_port, workenc); | |
442 | struct saa7164_dev *dev = port->dev; | |
443 | ||
444 | u32 wp, mcb, rp, cnt = 0; | |
445 | ||
446 | port->last_svc_msecs_diff = port->last_svc_msecs; | |
447 | port->last_svc_msecs = jiffies_to_msecs(jiffies); | |
448 | port->last_svc_msecs_diff = port->last_svc_msecs - | |
449 | port->last_svc_msecs_diff; | |
450 | ||
451 | saa7164_histogram_update(&port->svc_interval, | |
452 | port->last_svc_msecs_diff); | |
453 | ||
454 | port->last_irq_svc_msecs_diff = port->last_svc_msecs - | |
455 | port->last_irq_msecs; | |
456 | ||
457 | saa7164_histogram_update(&port->irq_svc_interval, | |
458 | port->last_irq_svc_msecs_diff); | |
459 | ||
460 | dprintk(DBGLVL_IRQ, | |
461 | "%s() %Ldms elapsed irq->deferred %Ldms wp: %d rp: %d\n", | |
462 | __func__, | |
463 | port->last_svc_msecs_diff, | |
464 | port->last_irq_svc_msecs_diff, | |
465 | port->last_svc_wp, | |
466 | port->last_svc_rp | |
467 | ); | |
468 | ||
469 | /* Current write position */ | |
470 | wp = saa7164_readl(port->bufcounter); | |
471 | if (wp > (port->hwcfg.buffercount - 1)) { | |
472 | printk(KERN_ERR "%s() illegal buf count %d\n", __func__, wp); | |
473 | return; | |
474 | } | |
475 | ||
476 | /* Most current complete buffer */ | |
477 | if (wp == 0) | |
478 | mcb = (port->hwcfg.buffercount - 1); | |
479 | else | |
480 | mcb = wp - 1; | |
1107237e ST |
481 | |
482 | while (1) { | |
483 | if (port->done_first_interrupt == 0) { | |
484 | port->done_first_interrupt++; | |
485 | rp = mcb; | |
486 | } else | |
487 | rp = (port->last_svc_rp + 1) % 8; | |
488 | ||
3eeba4a7 | 489 | if (rp > (port->hwcfg.buffercount - 1)) { |
1107237e ST |
490 | printk(KERN_ERR "%s() illegal rp count %d\n", __func__, rp); |
491 | break; | |
492 | } | |
493 | ||
494 | saa7164_work_enchandler_helper(port, rp); | |
495 | port->last_svc_rp = rp; | |
496 | cnt++; | |
497 | ||
498 | if (rp == mcb) | |
499 | break; | |
500 | } | |
501 | ||
e8ce2f21 ST |
502 | /* TODO: Convert this into a /proc/saa7164 style readable file */ |
503 | if (print_histogram == port->nr) { | |
504 | saa7164_histogram_print(port, &port->irq_interval); | |
505 | saa7164_histogram_print(port, &port->svc_interval); | |
506 | saa7164_histogram_print(port, &port->irq_svc_interval); | |
507 | saa7164_histogram_print(port, &port->read_interval); | |
508 | saa7164_histogram_print(port, &port->poll_interval); | |
509 | /* TODO: fix this to preserve any previous state */ | |
510 | print_histogram = 64 + port->nr; | |
511 | } | |
512 | } | |
513 | ||
91d80189 ST |
514 | static void saa7164_work_cmdhandler(struct work_struct *w) |
515 | { | |
516 | struct saa7164_dev *dev = container_of(w, struct saa7164_dev, workcmd); | |
517 | ||
518 | /* Wake up any complete commands */ | |
519 | saa7164_irq_dequeue(dev); | |
520 | } | |
521 | ||
522 | static void saa7164_buffer_deliver(struct saa7164_buffer *buf) | |
523 | { | |
524 | struct saa7164_port *port = buf->port; | |
525 | ||
526 | /* Feed the transport payload into the kernel demux */ | |
527 | dvb_dmx_swfilter_packets(&port->dvb.demux, (u8 *)buf->cpu, | |
528 | SAA7164_TS_NUMBER_OF_LINES); | |
529 | ||
530 | } | |
531 | ||
e8ce2f21 ST |
532 | static irqreturn_t saa7164_irq_vbi(struct saa7164_port *port) |
533 | { | |
534 | struct saa7164_dev *dev = port->dev; | |
535 | ||
536 | /* Store old time */ | |
537 | port->last_irq_msecs_diff = port->last_irq_msecs; | |
538 | ||
539 | /* Collect new stats */ | |
540 | port->last_irq_msecs = jiffies_to_msecs(jiffies); | |
541 | ||
542 | /* Calculate stats */ | |
543 | port->last_irq_msecs_diff = port->last_irq_msecs - | |
544 | port->last_irq_msecs_diff; | |
545 | ||
546 | saa7164_histogram_update(&port->irq_interval, | |
547 | port->last_irq_msecs_diff); | |
548 | ||
549 | dprintk(DBGLVL_IRQ, "%s() %Ldms elapsed\n", __func__, | |
550 | port->last_irq_msecs_diff); | |
551 | ||
552 | /* Tis calls the vbi irq handler */ | |
553 | schedule_work(&port->workenc); | |
554 | return 0; | |
555 | } | |
556 | ||
91d80189 ST |
557 | static irqreturn_t saa7164_irq_encoder(struct saa7164_port *port) |
558 | { | |
559 | struct saa7164_dev *dev = port->dev; | |
07603131 ST |
560 | |
561 | /* Store old time */ | |
91d80189 ST |
562 | port->last_irq_msecs_diff = port->last_irq_msecs; |
563 | ||
564 | /* Collect new stats */ | |
565 | port->last_irq_msecs = jiffies_to_msecs(jiffies); | |
91d80189 ST |
566 | |
567 | /* Calculate stats */ | |
568 | port->last_irq_msecs_diff = port->last_irq_msecs - | |
569 | port->last_irq_msecs_diff; | |
570 | ||
571 | saa7164_histogram_update(&port->irq_interval, | |
572 | port->last_irq_msecs_diff); | |
573 | ||
cfbaf337 ST |
574 | dprintk(DBGLVL_IRQ, "%s() %Ldms elapsed\n", __func__, |
575 | port->last_irq_msecs_diff); | |
12d3203e | 576 | |
91d80189 | 577 | schedule_work(&port->workenc); |
7615e434 ST |
578 | return 0; |
579 | } | |
580 | ||
add3f580 | 581 | static irqreturn_t saa7164_irq_ts(struct saa7164_port *port) |
443c1228 ST |
582 | { |
583 | struct saa7164_dev *dev = port->dev; | |
584 | struct saa7164_buffer *buf; | |
585 | struct list_head *c, *n; | |
586 | int wp, i = 0, rp; | |
587 | ||
588 | /* Find the current write point from the hardware */ | |
589 | wp = saa7164_readl(port->bufcounter); | |
590 | if (wp > (port->hwcfg.buffercount - 1)) | |
591 | BUG(); | |
592 | ||
593 | /* Find the previous buffer to the current write point */ | |
594 | if (wp == 0) | |
1b0e8e46 | 595 | rp = (port->hwcfg.buffercount - 1); |
443c1228 ST |
596 | else |
597 | rp = wp - 1; | |
598 | ||
599 | /* Lookup the WP in the buffer list */ | |
600 | /* TODO: turn this into a worker thread */ | |
601 | list_for_each_safe(c, n, &port->dmaqueue.list) { | |
602 | buf = list_entry(c, struct saa7164_buffer, list); | |
603 | if (i++ > port->hwcfg.buffercount) | |
604 | BUG(); | |
605 | ||
add3f580 | 606 | if (buf->idx == rp) { |
443c1228 ST |
607 | /* Found the buffer, deal with it */ |
608 | dprintk(DBGLVL_IRQ, "%s() wp: %d processing: %d\n", | |
609 | __func__, wp, rp); | |
610 | saa7164_buffer_deliver(buf); | |
611 | break; | |
612 | } | |
613 | ||
614 | } | |
615 | return 0; | |
616 | } | |
617 | ||
618 | /* Primary IRQ handler and dispatch mechanism */ | |
619 | static irqreturn_t saa7164_irq(int irq, void *dev_id) | |
620 | { | |
621 | struct saa7164_dev *dev = dev_id; | |
3c71d978 | 622 | struct saa7164_port *porta, *portb, *portc, *portd, *porte, *portf; |
7615e434 | 623 | |
50bcb4ae | 624 | u32 intid, intstat[INT_SIZE/4]; |
443c1228 ST |
625 | int i, handled = 0, bit; |
626 | ||
61ca1500 | 627 | if (dev == NULL) { |
d888ea03 ST |
628 | printk(KERN_ERR "%s() No device specified\n", __func__); |
629 | handled = 0; | |
630 | goto out; | |
631 | } | |
632 | ||
3c71d978 MCC |
633 | porta = &dev->ports[SAA7164_PORT_TS1]; |
634 | portb = &dev->ports[SAA7164_PORT_TS2]; | |
635 | portc = &dev->ports[SAA7164_PORT_ENC1]; | |
636 | portd = &dev->ports[SAA7164_PORT_ENC2]; | |
637 | porte = &dev->ports[SAA7164_PORT_VBI1]; | |
638 | portf = &dev->ports[SAA7164_PORT_VBI2]; | |
639 | ||
b595076a UKK |
640 | /* Check that the hardware is accessible. If the status bytes are |
641 | * 0xFF then the device is not accessible, the the IRQ belongs | |
443c1228 | 642 | * to another driver. |
1a6450d4 | 643 | * 4 x u32 interrupt registers. |
443c1228 ST |
644 | */ |
645 | for (i = 0; i < INT_SIZE/4; i++) { | |
646 | ||
647 | /* TODO: Convert into saa7164_readl() */ | |
648 | /* Read the 4 hardware interrupt registers */ | |
1a6450d4 | 649 | intstat[i] = saa7164_readl(dev->int_status + (i * 4)); |
443c1228 | 650 | |
50bcb4ae ST |
651 | if (intstat[i]) |
652 | handled = 1; | |
443c1228 | 653 | } |
50bcb4ae | 654 | if (handled == 0) |
443c1228 | 655 | goto out; |
443c1228 ST |
656 | |
657 | /* For each of the HW interrupt registers */ | |
658 | for (i = 0; i < INT_SIZE/4; i++) { | |
659 | ||
660 | if (intstat[i]) { | |
661 | /* Each function of the board has it's own interruptid. | |
662 | * Find the function that triggered then call | |
663 | * it's handler. | |
664 | */ | |
665 | for (bit = 0; bit < 32; bit++) { | |
666 | ||
667 | if (((intstat[i] >> bit) & 0x00000001) == 0) | |
668 | continue; | |
669 | ||
670 | /* Calculate the interrupt id (0x00 to 0x7f) */ | |
671 | ||
50bcb4ae ST |
672 | intid = (i * 32) + bit; |
673 | if (intid == dev->intfdesc.bInterruptId) { | |
443c1228 ST |
674 | /* A response to an cmd/api call */ |
675 | schedule_work(&dev->workcmd); | |
7615e434 | 676 | } else if (intid == porta->hwcfg.interruptid) { |
443c1228 ST |
677 | |
678 | /* Transport path 1 */ | |
7615e434 | 679 | saa7164_irq_ts(porta); |
443c1228 | 680 | |
7615e434 | 681 | } else if (intid == portb->hwcfg.interruptid) { |
443c1228 ST |
682 | |
683 | /* Transport path 2 */ | |
7615e434 ST |
684 | saa7164_irq_ts(portb); |
685 | ||
686 | } else if (intid == portc->hwcfg.interruptid) { | |
687 | ||
688 | /* Encoder path 1 */ | |
689 | saa7164_irq_encoder(portc); | |
690 | ||
691 | } else if (intid == portd->hwcfg.interruptid) { | |
692 | ||
e8ce2f21 | 693 | /* Encoder path 2 */ |
7615e434 | 694 | saa7164_irq_encoder(portd); |
443c1228 | 695 | |
e8ce2f21 ST |
696 | } else if (intid == porte->hwcfg.interruptid) { |
697 | ||
698 | /* VBI path 1 */ | |
699 | saa7164_irq_vbi(porte); | |
700 | ||
701 | } else if (intid == portf->hwcfg.interruptid) { | |
702 | ||
703 | /* VBI path 2 */ | |
704 | saa7164_irq_vbi(portf); | |
705 | ||
443c1228 ST |
706 | } else { |
707 | /* Find the function */ | |
708 | dprintk(DBGLVL_IRQ, | |
24f711c1 | 709 | "%s() unhandled interrupt reg 0x%x bit 0x%x intid = 0x%x\n", |
50bcb4ae | 710 | __func__, i, bit, intid); |
443c1228 ST |
711 | } |
712 | } | |
713 | ||
443c1228 | 714 | /* Ack it */ |
1a6450d4 | 715 | saa7164_writel(dev->int_ack + (i * 4), intstat[i]); |
443c1228 ST |
716 | |
717 | } | |
718 | } | |
719 | out: | |
720 | return IRQ_RETVAL(handled); | |
721 | } | |
722 | ||
723 | void saa7164_getfirmwarestatus(struct saa7164_dev *dev) | |
724 | { | |
725 | struct saa7164_fw_status *s = &dev->fw_status; | |
726 | ||
727 | dev->fw_status.status = saa7164_readl(SAA_DEVICE_SYSINIT_STATUS); | |
728 | dev->fw_status.mode = saa7164_readl(SAA_DEVICE_SYSINIT_MODE); | |
729 | dev->fw_status.spec = saa7164_readl(SAA_DEVICE_SYSINIT_SPEC); | |
730 | dev->fw_status.inst = saa7164_readl(SAA_DEVICE_SYSINIT_INST); | |
731 | dev->fw_status.cpuload = saa7164_readl(SAA_DEVICE_SYSINIT_CPULOAD); | |
732 | dev->fw_status.remainheap = | |
733 | saa7164_readl(SAA_DEVICE_SYSINIT_REMAINHEAP); | |
734 | ||
735 | dprintk(1, "Firmware status:\n"); | |
736 | dprintk(1, " .status = 0x%08x\n", s->status); | |
737 | dprintk(1, " .mode = 0x%08x\n", s->mode); | |
738 | dprintk(1, " .spec = 0x%08x\n", s->spec); | |
739 | dprintk(1, " .inst = 0x%08x\n", s->inst); | |
740 | dprintk(1, " .cpuload = 0x%08x\n", s->cpuload); | |
741 | dprintk(1, " .remainheap = 0x%08x\n", s->remainheap); | |
742 | } | |
743 | ||
744 | u32 saa7164_getcurrentfirmwareversion(struct saa7164_dev *dev) | |
745 | { | |
746 | u32 reg; | |
747 | ||
748 | reg = saa7164_readl(SAA_DEVICE_VERSION); | |
749 | dprintk(1, "Device running firmware version %d.%d.%d.%d (0x%x)\n", | |
750 | (reg & 0x0000fc00) >> 10, | |
751 | (reg & 0x000003e0) >> 5, | |
752 | (reg & 0x0000001f), | |
753 | (reg & 0xffff0000) >> 16, | |
754 | reg); | |
755 | ||
756 | return reg; | |
757 | } | |
758 | ||
443c1228 ST |
759 | /* TODO: Debugging func, remove */ |
760 | void saa7164_dumpregs(struct saa7164_dev *dev, u32 addr) | |
761 | { | |
762 | int i; | |
763 | ||
24f711c1 | 764 | dprintk(1, "--------------------> 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f\n"); |
443c1228 ST |
765 | |
766 | for (i = 0; i < 0x100; i += 16) | |
24f711c1 MCC |
767 | dprintk(1, "region0[0x%08x] = %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n", |
768 | i, | |
443c1228 ST |
769 | (u8)saa7164_readb(addr + i + 0), |
770 | (u8)saa7164_readb(addr + i + 1), | |
771 | (u8)saa7164_readb(addr + i + 2), | |
772 | (u8)saa7164_readb(addr + i + 3), | |
773 | (u8)saa7164_readb(addr + i + 4), | |
774 | (u8)saa7164_readb(addr + i + 5), | |
775 | (u8)saa7164_readb(addr + i + 6), | |
776 | (u8)saa7164_readb(addr + i + 7), | |
777 | (u8)saa7164_readb(addr + i + 8), | |
778 | (u8)saa7164_readb(addr + i + 9), | |
779 | (u8)saa7164_readb(addr + i + 10), | |
780 | (u8)saa7164_readb(addr + i + 11), | |
781 | (u8)saa7164_readb(addr + i + 12), | |
782 | (u8)saa7164_readb(addr + i + 13), | |
783 | (u8)saa7164_readb(addr + i + 14), | |
784 | (u8)saa7164_readb(addr + i + 15) | |
785 | ); | |
786 | } | |
787 | ||
788 | static void saa7164_dump_hwdesc(struct saa7164_dev *dev) | |
789 | { | |
4d270cfb MCC |
790 | dprintk(1, "@0x%p hwdesc sizeof(struct tmComResHWDescr) = %d bytes\n", |
791 | &dev->hwdesc, (u32)sizeof(struct tmComResHWDescr)); | |
443c1228 ST |
792 | |
793 | dprintk(1, " .bLength = 0x%x\n", dev->hwdesc.bLength); | |
794 | dprintk(1, " .bDescriptorType = 0x%x\n", dev->hwdesc.bDescriptorType); | |
795 | dprintk(1, " .bDescriptorSubtype = 0x%x\n", | |
796 | dev->hwdesc.bDescriptorSubtype); | |
797 | ||
798 | dprintk(1, " .bcdSpecVersion = 0x%x\n", dev->hwdesc.bcdSpecVersion); | |
799 | dprintk(1, " .dwClockFrequency = 0x%x\n", dev->hwdesc.dwClockFrequency); | |
800 | dprintk(1, " .dwClockUpdateRes = 0x%x\n", dev->hwdesc.dwClockUpdateRes); | |
801 | dprintk(1, " .bCapabilities = 0x%x\n", dev->hwdesc.bCapabilities); | |
802 | dprintk(1, " .dwDeviceRegistersLocation = 0x%x\n", | |
803 | dev->hwdesc.dwDeviceRegistersLocation); | |
804 | ||
805 | dprintk(1, " .dwHostMemoryRegion = 0x%x\n", | |
806 | dev->hwdesc.dwHostMemoryRegion); | |
807 | ||
808 | dprintk(1, " .dwHostMemoryRegionSize = 0x%x\n", | |
809 | dev->hwdesc.dwHostMemoryRegionSize); | |
810 | ||
811 | dprintk(1, " .dwHostHibernatMemRegion = 0x%x\n", | |
812 | dev->hwdesc.dwHostHibernatMemRegion); | |
813 | ||
814 | dprintk(1, " .dwHostHibernatMemRegionSize = 0x%x\n", | |
815 | dev->hwdesc.dwHostHibernatMemRegionSize); | |
816 | } | |
817 | ||
818 | static void saa7164_dump_intfdesc(struct saa7164_dev *dev) | |
819 | { | |
24f711c1 | 820 | dprintk(1, "@0x%p intfdesc sizeof(struct tmComResInterfaceDescr) = %d bytes\n", |
4d270cfb | 821 | &dev->intfdesc, (u32)sizeof(struct tmComResInterfaceDescr)); |
443c1228 ST |
822 | |
823 | dprintk(1, " .bLength = 0x%x\n", dev->intfdesc.bLength); | |
824 | dprintk(1, " .bDescriptorType = 0x%x\n", dev->intfdesc.bDescriptorType); | |
825 | dprintk(1, " .bDescriptorSubtype = 0x%x\n", | |
826 | dev->intfdesc.bDescriptorSubtype); | |
827 | ||
828 | dprintk(1, " .bFlags = 0x%x\n", dev->intfdesc.bFlags); | |
829 | dprintk(1, " .bInterfaceType = 0x%x\n", dev->intfdesc.bInterfaceType); | |
830 | dprintk(1, " .bInterfaceId = 0x%x\n", dev->intfdesc.bInterfaceId); | |
831 | dprintk(1, " .bBaseInterface = 0x%x\n", dev->intfdesc.bBaseInterface); | |
832 | dprintk(1, " .bInterruptId = 0x%x\n", dev->intfdesc.bInterruptId); | |
833 | dprintk(1, " .bDebugInterruptId = 0x%x\n", | |
834 | dev->intfdesc.bDebugInterruptId); | |
835 | ||
836 | dprintk(1, " .BARLocation = 0x%x\n", dev->intfdesc.BARLocation); | |
837 | } | |
838 | ||
839 | static void saa7164_dump_busdesc(struct saa7164_dev *dev) | |
840 | { | |
4d270cfb MCC |
841 | dprintk(1, "@0x%p busdesc sizeof(struct tmComResBusDescr) = %d bytes\n", |
842 | &dev->busdesc, (u32)sizeof(struct tmComResBusDescr)); | |
443c1228 ST |
843 | |
844 | dprintk(1, " .CommandRing = 0x%016Lx\n", dev->busdesc.CommandRing); | |
845 | dprintk(1, " .ResponseRing = 0x%016Lx\n", dev->busdesc.ResponseRing); | |
846 | dprintk(1, " .CommandWrite = 0x%x\n", dev->busdesc.CommandWrite); | |
847 | dprintk(1, " .CommandRead = 0x%x\n", dev->busdesc.CommandRead); | |
848 | dprintk(1, " .ResponseWrite = 0x%x\n", dev->busdesc.ResponseWrite); | |
849 | dprintk(1, " .ResponseRead = 0x%x\n", dev->busdesc.ResponseRead); | |
850 | } | |
851 | ||
852 | /* Much of the hardware configuration and PCI registers are configured | |
853 | * dynamically depending on firmware. We have to cache some initial | |
854 | * structures then use these to locate other important structures | |
855 | * from PCI space. | |
856 | */ | |
857 | static void saa7164_get_descriptors(struct saa7164_dev *dev) | |
858 | { | |
4d270cfb MCC |
859 | memcpy_fromio(&dev->hwdesc, dev->bmmio, sizeof(struct tmComResHWDescr)); |
860 | memcpy_fromio(&dev->intfdesc, dev->bmmio + sizeof(struct tmComResHWDescr), | |
861 | sizeof(struct tmComResInterfaceDescr)); | |
12d3203e | 862 | memcpy_fromio(&dev->busdesc, dev->bmmio + dev->intfdesc.BARLocation, |
4d270cfb | 863 | sizeof(struct tmComResBusDescr)); |
443c1228 | 864 | |
4d270cfb MCC |
865 | if (dev->hwdesc.bLength != sizeof(struct tmComResHWDescr)) { |
866 | printk(KERN_ERR "Structure struct tmComResHWDescr is mangled\n"); | |
207b42c4 | 867 | printk(KERN_ERR "Need %x got %d\n", dev->hwdesc.bLength, |
4d270cfb | 868 | (u32)sizeof(struct tmComResHWDescr)); |
443c1228 ST |
869 | } else |
870 | saa7164_dump_hwdesc(dev); | |
871 | ||
4d270cfb MCC |
872 | if (dev->intfdesc.bLength != sizeof(struct tmComResInterfaceDescr)) { |
873 | printk(KERN_ERR "struct struct tmComResInterfaceDescr is mangled\n"); | |
207b42c4 | 874 | printk(KERN_ERR "Need %x got %d\n", dev->intfdesc.bLength, |
4d270cfb | 875 | (u32)sizeof(struct tmComResInterfaceDescr)); |
443c1228 ST |
876 | } else |
877 | saa7164_dump_intfdesc(dev); | |
878 | ||
879 | saa7164_dump_busdesc(dev); | |
880 | } | |
881 | ||
882 | static int saa7164_pci_quirks(struct saa7164_dev *dev) | |
883 | { | |
884 | return 0; | |
885 | } | |
886 | ||
887 | static int get_resources(struct saa7164_dev *dev) | |
888 | { | |
889 | if (request_mem_region(pci_resource_start(dev->pci, 0), | |
890 | pci_resource_len(dev->pci, 0), dev->name)) { | |
891 | ||
892 | if (request_mem_region(pci_resource_start(dev->pci, 2), | |
893 | pci_resource_len(dev->pci, 2), dev->name)) | |
894 | return 0; | |
895 | } | |
896 | ||
897 | printk(KERN_ERR "%s: can't get MMIO memory @ 0x%llx or 0x%llx\n", | |
898 | dev->name, | |
899 | (u64)pci_resource_start(dev->pci, 0), | |
900 | (u64)pci_resource_start(dev->pci, 2)); | |
901 | ||
902 | return -EBUSY; | |
903 | } | |
904 | ||
7615e434 ST |
905 | static int saa7164_port_init(struct saa7164_dev *dev, int portnr) |
906 | { | |
61ca1500 | 907 | struct saa7164_port *port = NULL; |
7615e434 ST |
908 | |
909 | if ((portnr < 0) || (portnr >= SAA7164_MAX_PORTS)) | |
910 | BUG(); | |
911 | ||
c7e242ba | 912 | port = &dev->ports[portnr]; |
7615e434 ST |
913 | |
914 | port->dev = dev; | |
915 | port->nr = portnr; | |
916 | ||
917 | if ((portnr == SAA7164_PORT_TS1) || (portnr == SAA7164_PORT_TS2)) | |
918 | port->type = SAA7164_MPEG_DVB; | |
919 | else | |
e8ce2f21 | 920 | if ((portnr == SAA7164_PORT_ENC1) || (portnr == SAA7164_PORT_ENC2)) { |
7615e434 | 921 | port->type = SAA7164_MPEG_ENCODER; |
e8ce2f21 ST |
922 | |
923 | /* We need a deferred interrupt handler for cmd handling */ | |
924 | INIT_WORK(&port->workenc, saa7164_work_enchandler); | |
bc250684 | 925 | } else if ((portnr == SAA7164_PORT_VBI1) || (portnr == SAA7164_PORT_VBI2)) { |
e8ce2f21 ST |
926 | port->type = SAA7164_MPEG_VBI; |
927 | ||
928 | /* We need a deferred interrupt handler for cmd handling */ | |
929 | INIT_WORK(&port->workenc, saa7164_work_vbihandler); | |
930 | } else | |
7615e434 ST |
931 | BUG(); |
932 | ||
933 | /* Init all the critical resources */ | |
934 | mutex_init(&port->dvb.lock); | |
935 | INIT_LIST_HEAD(&port->dmaqueue.list); | |
936 | mutex_init(&port->dmaqueue_lock); | |
937 | ||
938 | INIT_LIST_HEAD(&port->list_buf_used.list); | |
939 | INIT_LIST_HEAD(&port->list_buf_free.list); | |
940 | init_waitqueue_head(&port->wait_read); | |
91d80189 | 941 | |
91d80189 ST |
942 | |
943 | saa7164_histogram_reset(&port->irq_interval, "irq intervals"); | |
944 | saa7164_histogram_reset(&port->svc_interval, "deferred intervals"); | |
945 | saa7164_histogram_reset(&port->irq_svc_interval, | |
946 | "irq to deferred intervals"); | |
58acca10 | 947 | saa7164_histogram_reset(&port->read_interval, |
e8ce2f21 | 948 | "encoder/vbi read() intervals"); |
58acca10 | 949 | saa7164_histogram_reset(&port->poll_interval, |
e8ce2f21 | 950 | "encoder/vbi poll() intervals"); |
91d80189 | 951 | |
7615e434 ST |
952 | return 0; |
953 | } | |
954 | ||
443c1228 ST |
955 | static int saa7164_dev_setup(struct saa7164_dev *dev) |
956 | { | |
957 | int i; | |
958 | ||
959 | mutex_init(&dev->lock); | |
960 | atomic_inc(&dev->refcount); | |
961 | dev->nr = saa7164_devcount++; | |
962 | ||
0e72cc8b | 963 | snprintf(dev->name, sizeof(dev->name), "saa7164[%d]", dev->nr); |
443c1228 ST |
964 | |
965 | mutex_lock(&devlist); | |
966 | list_add_tail(&dev->devlist, &saa7164_devlist); | |
967 | mutex_unlock(&devlist); | |
968 | ||
969 | /* board config */ | |
970 | dev->board = UNSET; | |
971 | if (card[dev->nr] < saa7164_bcount) | |
972 | dev->board = card[dev->nr]; | |
973 | ||
974 | for (i = 0; UNSET == dev->board && i < saa7164_idcount; i++) | |
975 | if (dev->pci->subsystem_vendor == saa7164_subids[i].subvendor && | |
976 | dev->pci->subsystem_device == | |
977 | saa7164_subids[i].subdevice) | |
978 | dev->board = saa7164_subids[i].card; | |
979 | ||
980 | if (UNSET == dev->board) { | |
981 | dev->board = SAA7164_BOARD_UNKNOWN; | |
982 | saa7164_card_list(dev); | |
983 | } | |
984 | ||
985 | dev->pci_bus = dev->pci->bus->number; | |
986 | dev->pci_slot = PCI_SLOT(dev->pci->devfn); | |
987 | ||
988 | /* I2C Defaults / setup */ | |
989 | dev->i2c_bus[0].dev = dev; | |
990 | dev->i2c_bus[0].nr = 0; | |
991 | dev->i2c_bus[1].dev = dev; | |
992 | dev->i2c_bus[1].nr = 1; | |
993 | dev->i2c_bus[2].dev = dev; | |
994 | dev->i2c_bus[2].nr = 2; | |
995 | ||
7615e434 ST |
996 | /* Transport + Encoder ports 1, 2, 3, 4 - Defaults / setup */ |
997 | saa7164_port_init(dev, SAA7164_PORT_TS1); | |
998 | saa7164_port_init(dev, SAA7164_PORT_TS2); | |
999 | saa7164_port_init(dev, SAA7164_PORT_ENC1); | |
1000 | saa7164_port_init(dev, SAA7164_PORT_ENC2); | |
e8ce2f21 ST |
1001 | saa7164_port_init(dev, SAA7164_PORT_VBI1); |
1002 | saa7164_port_init(dev, SAA7164_PORT_VBI2); | |
443c1228 ST |
1003 | |
1004 | if (get_resources(dev) < 0) { | |
24f711c1 | 1005 | printk(KERN_ERR "CORE %s No more PCIe resources for subsystem: %04x:%04x\n", |
443c1228 ST |
1006 | dev->name, dev->pci->subsystem_vendor, |
1007 | dev->pci->subsystem_device); | |
1008 | ||
1009 | saa7164_devcount--; | |
1010 | return -ENODEV; | |
1011 | } | |
1012 | ||
1013 | /* PCI/e allocations */ | |
1014 | dev->lmmio = ioremap(pci_resource_start(dev->pci, 0), | |
1015 | pci_resource_len(dev->pci, 0)); | |
1016 | ||
1017 | dev->lmmio2 = ioremap(pci_resource_start(dev->pci, 2), | |
1018 | pci_resource_len(dev->pci, 2)); | |
1019 | ||
443c1228 ST |
1020 | dev->bmmio = (u8 __iomem *)dev->lmmio; |
1021 | dev->bmmio2 = (u8 __iomem *)dev->lmmio2; | |
443c1228 | 1022 | |
1a6450d4 ST |
1023 | /* Inerrupt and ack register locations offset of bmmio */ |
1024 | dev->int_status = 0x183000 + 0xf80; | |
1025 | dev->int_ack = 0x183000 + 0xf90; | |
443c1228 ST |
1026 | |
1027 | printk(KERN_INFO | |
1028 | "CORE %s: subsystem: %04x:%04x, board: %s [card=%d,%s]\n", | |
1029 | dev->name, dev->pci->subsystem_vendor, | |
1030 | dev->pci->subsystem_device, saa7164_boards[dev->board].name, | |
1031 | dev->board, card[dev->nr] == dev->board ? | |
1032 | "insmod option" : "autodetected"); | |
1033 | ||
1034 | saa7164_pci_quirks(dev); | |
1035 | ||
1036 | return 0; | |
1037 | } | |
1038 | ||
1039 | static void saa7164_dev_unregister(struct saa7164_dev *dev) | |
1040 | { | |
1041 | dprintk(1, "%s()\n", __func__); | |
1042 | ||
1043 | release_mem_region(pci_resource_start(dev->pci, 0), | |
1044 | pci_resource_len(dev->pci, 0)); | |
1045 | ||
1046 | release_mem_region(pci_resource_start(dev->pci, 2), | |
1047 | pci_resource_len(dev->pci, 2)); | |
1048 | ||
1049 | if (!atomic_dec_and_test(&dev->refcount)) | |
1050 | return; | |
1051 | ||
1052 | iounmap(dev->lmmio); | |
1053 | iounmap(dev->lmmio2); | |
1054 | ||
1055 | return; | |
1056 | } | |
1057 | ||
e48836b8 ST |
1058 | #ifdef CONFIG_PROC_FS |
1059 | static int saa7164_proc_show(struct seq_file *m, void *v) | |
1060 | { | |
1061 | struct saa7164_dev *dev; | |
4d270cfb | 1062 | struct tmComResBusInfo *b; |
e48836b8 ST |
1063 | struct list_head *list; |
1064 | int i, c; | |
1065 | ||
1066 | if (saa7164_devcount == 0) | |
1067 | return 0; | |
1068 | ||
1069 | list_for_each(list, &saa7164_devlist) { | |
1070 | dev = list_entry(list, struct saa7164_dev, devlist); | |
1071 | seq_printf(m, "%s = %p\n", dev->name, dev); | |
1072 | ||
e48836b8 ST |
1073 | /* Lock the bus from any other access */ |
1074 | b = &dev->bus; | |
1075 | mutex_lock(&b->lock); | |
0b62ceb0 ST |
1076 | |
1077 | seq_printf(m, " .m_pdwSetWritePos = 0x%x (0x%08x)\n", | |
1078 | b->m_dwSetReadPos, saa7164_readl(b->m_dwSetReadPos)); | |
1079 | ||
1080 | seq_printf(m, " .m_pdwSetReadPos = 0x%x (0x%08x)\n", | |
1081 | b->m_dwSetWritePos, saa7164_readl(b->m_dwSetWritePos)); | |
1082 | ||
1083 | seq_printf(m, " .m_pdwGetWritePos = 0x%x (0x%08x)\n", | |
1084 | b->m_dwGetReadPos, saa7164_readl(b->m_dwGetReadPos)); | |
1085 | ||
1086 | seq_printf(m, " .m_pdwGetReadPos = 0x%x (0x%08x)\n", | |
1087 | b->m_dwGetWritePos, saa7164_readl(b->m_dwGetWritePos)); | |
1088 | c = 0; | |
1089 | seq_printf(m, "\n Set Ring:\n"); | |
1090 | seq_printf(m, "\n addr 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f\n"); | |
1091 | for (i = 0; i < b->m_dwSizeSetRing; i++) { | |
1092 | if (c == 0) | |
1093 | seq_printf(m, " %04x:", i); | |
1094 | ||
065e1477 | 1095 | seq_printf(m, " %02x", readb(b->m_pdwSetRing + i)); |
0b62ceb0 ST |
1096 | |
1097 | if (++c == 16) { | |
1098 | seq_printf(m, "\n"); | |
1099 | c = 0; | |
1100 | } | |
1101 | } | |
1102 | ||
1103 | c = 0; | |
1104 | seq_printf(m, "\n Get Ring:\n"); | |
1105 | seq_printf(m, "\n addr 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f\n"); | |
1106 | for (i = 0; i < b->m_dwSizeGetRing; i++) { | |
1107 | if (c == 0) | |
1108 | seq_printf(m, " %04x:", i); | |
1109 | ||
065e1477 | 1110 | seq_printf(m, " %02x", readb(b->m_pdwGetRing + i)); |
0b62ceb0 ST |
1111 | |
1112 | if (++c == 16) { | |
1113 | seq_printf(m, "\n"); | |
1114 | c = 0; | |
1115 | } | |
1116 | } | |
1117 | ||
e48836b8 ST |
1118 | mutex_unlock(&b->lock); |
1119 | ||
1120 | } | |
1121 | ||
1122 | return 0; | |
1123 | } | |
1124 | ||
1125 | static int saa7164_proc_open(struct inode *inode, struct file *filp) | |
1126 | { | |
1127 | return single_open(filp, saa7164_proc_show, NULL); | |
1128 | } | |
1129 | ||
bc250684 | 1130 | static const struct file_operations saa7164_proc_fops = { |
e48836b8 ST |
1131 | .open = saa7164_proc_open, |
1132 | .read = seq_read, | |
1133 | .llseek = seq_lseek, | |
1134 | .release = single_release, | |
1135 | }; | |
1136 | ||
1137 | static int saa7164_proc_create(void) | |
1138 | { | |
1139 | struct proc_dir_entry *pe; | |
1140 | ||
1141 | pe = proc_create("saa7164", S_IRUGO, NULL, &saa7164_proc_fops); | |
1142 | if (!pe) | |
1143 | return -ENOMEM; | |
1144 | ||
1145 | return 0; | |
1146 | } | |
1147 | #endif | |
1148 | ||
0b62ceb0 ST |
1149 | static int saa7164_thread_function(void *data) |
1150 | { | |
1151 | struct saa7164_dev *dev = data; | |
4d270cfb | 1152 | struct tmFwInfoStruct fwinfo; |
1247ff5c | 1153 | u64 last_poll_time = 0; |
0b62ceb0 ST |
1154 | |
1155 | dprintk(DBGLVL_THR, "thread started\n"); | |
1156 | ||
1157 | set_freezable(); | |
1158 | ||
1159 | while (1) { | |
1160 | msleep_interruptible(100); | |
1161 | if (kthread_should_stop()) | |
1162 | break; | |
1163 | try_to_freeze(); | |
1164 | ||
1165 | dprintk(DBGLVL_THR, "thread running\n"); | |
1166 | ||
1167 | /* Dump the firmware debug message to console */ | |
1247ff5c ST |
1168 | /* Polling this costs us 1-2% of the arm CPU */ |
1169 | /* convert this into a respnde to interrupt 0x7a */ | |
0b62ceb0 ST |
1170 | saa7164_api_collect_debug(dev); |
1171 | ||
1247ff5c ST |
1172 | /* Monitor CPU load every 1 second */ |
1173 | if ((last_poll_time + 1000 /* ms */) < jiffies_to_msecs(jiffies)) { | |
1174 | saa7164_api_get_load_info(dev, &fwinfo); | |
1175 | last_poll_time = jiffies_to_msecs(jiffies); | |
1176 | } | |
1177 | ||
0b62ceb0 ST |
1178 | } |
1179 | ||
1180 | dprintk(DBGLVL_THR, "thread exiting\n"); | |
1181 | return 0; | |
1182 | } | |
1183 | ||
77978089 BM |
1184 | static bool saa7164_enable_msi(struct pci_dev *pci_dev, struct saa7164_dev *dev) |
1185 | { | |
1186 | int err; | |
1187 | ||
1188 | if (!enable_msi) { | |
1189 | printk(KERN_WARNING "%s() MSI disabled by module parameter 'enable_msi'" | |
1190 | , __func__); | |
1191 | return false; | |
1192 | } | |
1193 | ||
1194 | err = pci_enable_msi(pci_dev); | |
1195 | ||
1196 | if (err) { | |
24f711c1 MCC |
1197 | printk(KERN_ERR "%s() Failed to enable MSI interrupt. Falling back to a shared IRQ\n", |
1198 | __func__); | |
77978089 BM |
1199 | return false; |
1200 | } | |
1201 | ||
1202 | /* no error - so request an msi interrupt */ | |
1203 | err = request_irq(pci_dev->irq, saa7164_irq, 0, | |
1204 | dev->name, dev); | |
1205 | ||
1206 | if (err) { | |
1207 | /* fall back to legacy interrupt */ | |
24f711c1 MCC |
1208 | printk(KERN_ERR "%s() Failed to get an MSI interrupt. Falling back to a shared IRQ\n", |
1209 | __func__); | |
77978089 BM |
1210 | pci_disable_msi(pci_dev); |
1211 | return false; | |
1212 | } | |
1213 | ||
1214 | return true; | |
1215 | } | |
1216 | ||
4c62e976 GKH |
1217 | static int saa7164_initdev(struct pci_dev *pci_dev, |
1218 | const struct pci_device_id *pci_id) | |
443c1228 ST |
1219 | { |
1220 | struct saa7164_dev *dev; | |
1221 | int err, i; | |
1222 | u32 version; | |
1223 | ||
1224 | dev = kzalloc(sizeof(*dev), GFP_KERNEL); | |
1225 | if (NULL == dev) | |
1226 | return -ENOMEM; | |
1227 | ||
fd8d30bf HV |
1228 | err = v4l2_device_register(&pci_dev->dev, &dev->v4l2_dev); |
1229 | if (err < 0) { | |
d66de790 HV |
1230 | dev_err(&pci_dev->dev, "v4l2_device_register failed\n"); |
1231 | goto fail_free; | |
1232 | } | |
1233 | ||
443c1228 ST |
1234 | /* pci init */ |
1235 | dev->pci = pci_dev; | |
1236 | if (pci_enable_device(pci_dev)) { | |
1237 | err = -EIO; | |
1238 | goto fail_free; | |
1239 | } | |
1240 | ||
1241 | if (saa7164_dev_setup(dev) < 0) { | |
1242 | err = -EINVAL; | |
1243 | goto fail_free; | |
1244 | } | |
1245 | ||
1246 | /* print pci info */ | |
abd34d8d | 1247 | dev->pci_rev = pci_dev->revision; |
443c1228 | 1248 | pci_read_config_byte(pci_dev, PCI_LATENCY_TIMER, &dev->pci_lat); |
24f711c1 MCC |
1249 | printk(KERN_INFO "%s/0: found at %s, rev: %d, irq: %d, latency: %d, mmio: 0x%llx\n", |
1250 | dev->name, | |
443c1228 ST |
1251 | pci_name(pci_dev), dev->pci_rev, pci_dev->irq, |
1252 | dev->pci_lat, | |
1253 | (unsigned long long)pci_resource_start(pci_dev, 0)); | |
1254 | ||
1255 | pci_set_master(pci_dev); | |
1256 | /* TODO */ | |
1a47de6e CH |
1257 | err = pci_set_dma_mask(pci_dev, 0xffffffff); |
1258 | if (err) { | |
443c1228 | 1259 | printk("%s/0: Oops: no 32bit PCI DMA ???\n", dev->name); |
443c1228 ST |
1260 | goto fail_irq; |
1261 | } | |
1262 | ||
77978089 BM |
1263 | /* irq bit */ |
1264 | if (saa7164_enable_msi(pci_dev, dev)) { | |
1265 | dev->msi = true; | |
1266 | } else { | |
1267 | /* if we have an error (i.e. we don't have an interrupt) | |
1268 | or msi is not enabled - fallback to shared interrupt */ | |
1269 | ||
1270 | err = request_irq(pci_dev->irq, saa7164_irq, | |
1271 | IRQF_SHARED, dev->name, dev); | |
1272 | ||
1273 | if (err < 0) { | |
1274 | printk(KERN_ERR "%s: can't get IRQ %d\n", dev->name, | |
1275 | pci_dev->irq); | |
1276 | err = -EIO; | |
1277 | goto fail_irq; | |
1278 | } | |
443c1228 ST |
1279 | } |
1280 | ||
1281 | pci_set_drvdata(pci_dev, dev); | |
1282 | ||
443c1228 ST |
1283 | /* Init the internal command list */ |
1284 | for (i = 0; i < SAA_CMD_MAX_MSG_UNITS; i++) { | |
1285 | dev->cmds[i].seqno = i; | |
1286 | dev->cmds[i].inuse = 0; | |
1287 | mutex_init(&dev->cmds[i].lock); | |
1288 | init_waitqueue_head(&dev->cmds[i].wait); | |
1289 | } | |
1290 | ||
1291 | /* We need a deferred interrupt handler for cmd handling */ | |
1292 | INIT_WORK(&dev->workcmd, saa7164_work_cmdhandler); | |
1293 | ||
1294 | /* Only load the firmware if we know the board */ | |
1295 | if (dev->board != SAA7164_BOARD_UNKNOWN) { | |
1296 | ||
1297 | err = saa7164_downloadfirmware(dev); | |
1298 | if (err < 0) { | |
1299 | printk(KERN_ERR | |
24f711c1 | 1300 | "Failed to boot firmware, no features registered\n"); |
50bcb4ae | 1301 | goto fail_fw; |
443c1228 ST |
1302 | } |
1303 | ||
1304 | saa7164_get_descriptors(dev); | |
1305 | saa7164_dumpregs(dev, 0); | |
1306 | saa7164_getcurrentfirmwareversion(dev); | |
1307 | saa7164_getfirmwarestatus(dev); | |
1308 | err = saa7164_bus_setup(dev); | |
1309 | if (err < 0) | |
1310 | printk(KERN_ERR | |
1311 | "Failed to setup the bus, will continue\n"); | |
1312 | saa7164_bus_dump(dev); | |
1313 | ||
1314 | /* Ping the running firmware via the command bus and get the | |
1315 | * firmware version, this checks the bus is running OK. | |
1316 | */ | |
1317 | version = 0; | |
1318 | if (saa7164_api_get_fw_version(dev, &version) == SAA_OK) | |
24f711c1 | 1319 | dprintk(1, "Bus is operating correctly using version %d.%d.%d.%d (0x%x)\n", |
443c1228 ST |
1320 | (version & 0x0000fc00) >> 10, |
1321 | (version & 0x000003e0) >> 5, | |
1322 | (version & 0x0000001f), | |
1323 | (version & 0xffff0000) >> 16, | |
1324 | version); | |
1325 | else | |
1326 | printk(KERN_ERR | |
1327 | "Failed to communicate with the firmware\n"); | |
1328 | ||
1329 | /* Bring up the I2C buses */ | |
1330 | saa7164_i2c_register(&dev->i2c_bus[0]); | |
1331 | saa7164_i2c_register(&dev->i2c_bus[1]); | |
1332 | saa7164_i2c_register(&dev->i2c_bus[2]); | |
1333 | saa7164_gpio_setup(dev); | |
1334 | saa7164_card_setup(dev); | |
1335 | ||
443c1228 ST |
1336 | /* Parse the dynamic device configuration, find various |
1337 | * media endpoints (MPEG, WMV, PS, TS) and cache their | |
1338 | * configuration details into the driver, so we can | |
1339 | * reference them later during simething_register() func, | |
1340 | * interrupt handlers, deferred work handlers etc. | |
1341 | */ | |
1342 | saa7164_api_enum_subdevs(dev); | |
1343 | ||
443c1228 ST |
1344 | /* Begin to create the video sub-systems and register funcs */ |
1345 | if (saa7164_boards[dev->board].porta == SAA7164_MPEG_DVB) { | |
c7e242ba | 1346 | if (saa7164_dvb_register(&dev->ports[SAA7164_PORT_TS1]) < 0) { |
24f711c1 | 1347 | printk(KERN_ERR "%s() Failed to register dvb adapters on porta\n", |
443c1228 ST |
1348 | __func__); |
1349 | } | |
1350 | } | |
1351 | ||
1352 | if (saa7164_boards[dev->board].portb == SAA7164_MPEG_DVB) { | |
c7e242ba | 1353 | if (saa7164_dvb_register(&dev->ports[SAA7164_PORT_TS2]) < 0) { |
24f711c1 | 1354 | printk(KERN_ERR"%s() Failed to register dvb adapters on portb\n", |
443c1228 ST |
1355 | __func__); |
1356 | } | |
1357 | } | |
1358 | ||
7615e434 | 1359 | if (saa7164_boards[dev->board].portc == SAA7164_MPEG_ENCODER) { |
c7e242ba | 1360 | if (saa7164_encoder_register(&dev->ports[SAA7164_PORT_ENC1]) < 0) { |
24f711c1 MCC |
1361 | printk(KERN_ERR"%s() Failed to register mpeg encoder\n", |
1362 | __func__); | |
7615e434 ST |
1363 | } |
1364 | } | |
1365 | ||
1366 | if (saa7164_boards[dev->board].portd == SAA7164_MPEG_ENCODER) { | |
c7e242ba | 1367 | if (saa7164_encoder_register(&dev->ports[SAA7164_PORT_ENC2]) < 0) { |
24f711c1 MCC |
1368 | printk(KERN_ERR"%s() Failed to register mpeg encoder\n", |
1369 | __func__); | |
7615e434 ST |
1370 | } |
1371 | } | |
1372 | ||
e8ce2f21 | 1373 | if (saa7164_boards[dev->board].porte == SAA7164_MPEG_VBI) { |
c7e242ba | 1374 | if (saa7164_vbi_register(&dev->ports[SAA7164_PORT_VBI1]) < 0) { |
24f711c1 MCC |
1375 | printk(KERN_ERR"%s() Failed to register vbi device\n", |
1376 | __func__); | |
e8ce2f21 ST |
1377 | } |
1378 | } | |
1379 | ||
1380 | if (saa7164_boards[dev->board].portf == SAA7164_MPEG_VBI) { | |
c7e242ba | 1381 | if (saa7164_vbi_register(&dev->ports[SAA7164_PORT_VBI2]) < 0) { |
24f711c1 MCC |
1382 | printk(KERN_ERR"%s() Failed to register vbi device\n", |
1383 | __func__); | |
e8ce2f21 ST |
1384 | } |
1385 | } | |
e48836b8 | 1386 | saa7164_api_set_debug(dev, fw_debug); |
e8ce2f21 | 1387 | |
0b62ceb0 ST |
1388 | if (fw_debug) { |
1389 | dev->kthread = kthread_run(saa7164_thread_function, dev, | |
1390 | "saa7164 debug"); | |
89f4d45b WY |
1391 | if (IS_ERR(dev->kthread)) { |
1392 | dev->kthread = NULL; | |
24f711c1 MCC |
1393 | printk(KERN_ERR "%s() Failed to create debug kernel thread\n", |
1394 | __func__); | |
89f4d45b | 1395 | } |
0b62ceb0 ST |
1396 | } |
1397 | ||
443c1228 ST |
1398 | } /* != BOARD_UNKNOWN */ |
1399 | else | |
24f711c1 MCC |
1400 | printk(KERN_ERR "%s() Unsupported board detected, registering without firmware\n", |
1401 | __func__); | |
443c1228 | 1402 | |
b1912a85 | 1403 | dprintk(1, "%s() parameter debug = %d\n", __func__, saa_debug); |
2ceae8fd ST |
1404 | dprintk(1, "%s() parameter waitsecs = %d\n", __func__, waitsecs); |
1405 | ||
50bcb4ae | 1406 | fail_fw: |
443c1228 ST |
1407 | return 0; |
1408 | ||
1409 | fail_irq: | |
1410 | saa7164_dev_unregister(dev); | |
1411 | fail_free: | |
d66de790 | 1412 | v4l2_device_unregister(&dev->v4l2_dev); |
443c1228 ST |
1413 | kfree(dev); |
1414 | return err; | |
1415 | } | |
1416 | ||
1417 | static void saa7164_shutdown(struct saa7164_dev *dev) | |
1418 | { | |
1419 | dprintk(1, "%s()\n", __func__); | |
1420 | } | |
1421 | ||
4c62e976 | 1422 | static void saa7164_finidev(struct pci_dev *pci_dev) |
443c1228 ST |
1423 | { |
1424 | struct saa7164_dev *dev = pci_get_drvdata(pci_dev); | |
1425 | ||
0b62ceb0 ST |
1426 | if (dev->board != SAA7164_BOARD_UNKNOWN) { |
1427 | if (fw_debug && dev->kthread) { | |
1428 | kthread_stop(dev->kthread); | |
1429 | dev->kthread = NULL; | |
1430 | } | |
22760ed3 ST |
1431 | if (dev->firmwareloaded) |
1432 | saa7164_api_set_debug(dev, 0x00); | |
0b62ceb0 | 1433 | } |
e48836b8 | 1434 | |
c7e242ba MCC |
1435 | saa7164_histogram_print(&dev->ports[SAA7164_PORT_ENC1], |
1436 | &dev->ports[SAA7164_PORT_ENC1].irq_interval); | |
1437 | saa7164_histogram_print(&dev->ports[SAA7164_PORT_ENC1], | |
1438 | &dev->ports[SAA7164_PORT_ENC1].svc_interval); | |
1439 | saa7164_histogram_print(&dev->ports[SAA7164_PORT_ENC1], | |
1440 | &dev->ports[SAA7164_PORT_ENC1].irq_svc_interval); | |
1441 | saa7164_histogram_print(&dev->ports[SAA7164_PORT_ENC1], | |
1442 | &dev->ports[SAA7164_PORT_ENC1].read_interval); | |
1443 | saa7164_histogram_print(&dev->ports[SAA7164_PORT_ENC1], | |
1444 | &dev->ports[SAA7164_PORT_ENC1].poll_interval); | |
1445 | saa7164_histogram_print(&dev->ports[SAA7164_PORT_VBI1], | |
1446 | &dev->ports[SAA7164_PORT_VBI1].read_interval); | |
1447 | saa7164_histogram_print(&dev->ports[SAA7164_PORT_VBI2], | |
1448 | &dev->ports[SAA7164_PORT_VBI2].poll_interval); | |
91d80189 | 1449 | |
443c1228 ST |
1450 | saa7164_shutdown(dev); |
1451 | ||
1452 | if (saa7164_boards[dev->board].porta == SAA7164_MPEG_DVB) | |
c7e242ba | 1453 | saa7164_dvb_unregister(&dev->ports[SAA7164_PORT_TS1]); |
443c1228 ST |
1454 | |
1455 | if (saa7164_boards[dev->board].portb == SAA7164_MPEG_DVB) | |
c7e242ba | 1456 | saa7164_dvb_unregister(&dev->ports[SAA7164_PORT_TS2]); |
7615e434 ST |
1457 | |
1458 | if (saa7164_boards[dev->board].portc == SAA7164_MPEG_ENCODER) | |
c7e242ba | 1459 | saa7164_encoder_unregister(&dev->ports[SAA7164_PORT_ENC1]); |
7615e434 ST |
1460 | |
1461 | if (saa7164_boards[dev->board].portd == SAA7164_MPEG_ENCODER) | |
c7e242ba | 1462 | saa7164_encoder_unregister(&dev->ports[SAA7164_PORT_ENC2]); |
443c1228 | 1463 | |
e8ce2f21 | 1464 | if (saa7164_boards[dev->board].porte == SAA7164_MPEG_VBI) |
c7e242ba | 1465 | saa7164_vbi_unregister(&dev->ports[SAA7164_PORT_VBI1]); |
e8ce2f21 ST |
1466 | |
1467 | if (saa7164_boards[dev->board].portf == SAA7164_MPEG_VBI) | |
c7e242ba | 1468 | saa7164_vbi_unregister(&dev->ports[SAA7164_PORT_VBI2]); |
e8ce2f21 | 1469 | |
443c1228 ST |
1470 | saa7164_i2c_unregister(&dev->i2c_bus[0]); |
1471 | saa7164_i2c_unregister(&dev->i2c_bus[1]); | |
1472 | saa7164_i2c_unregister(&dev->i2c_bus[2]); | |
1473 | ||
443c1228 ST |
1474 | /* unregister stuff */ |
1475 | free_irq(pci_dev->irq, dev); | |
443c1228 | 1476 | |
77978089 BM |
1477 | if (dev->msi) { |
1478 | pci_disable_msi(pci_dev); | |
1479 | dev->msi = false; | |
1480 | } | |
1481 | ||
3f845f3c OS |
1482 | pci_disable_device(pci_dev); |
1483 | ||
443c1228 ST |
1484 | mutex_lock(&devlist); |
1485 | list_del(&dev->devlist); | |
1486 | mutex_unlock(&devlist); | |
1487 | ||
1488 | saa7164_dev_unregister(dev); | |
d66de790 | 1489 | v4l2_device_unregister(&dev->v4l2_dev); |
443c1228 ST |
1490 | kfree(dev); |
1491 | } | |
1492 | ||
1493 | static struct pci_device_id saa7164_pci_tbl[] = { | |
1494 | { | |
1495 | /* SAA7164 */ | |
1496 | .vendor = 0x1131, | |
1497 | .device = 0x7164, | |
1498 | .subvendor = PCI_ANY_ID, | |
1499 | .subdevice = PCI_ANY_ID, | |
1500 | }, { | |
1501 | /* --- end of list --- */ | |
1502 | } | |
1503 | }; | |
1504 | MODULE_DEVICE_TABLE(pci, saa7164_pci_tbl); | |
1505 | ||
1506 | static struct pci_driver saa7164_pci_driver = { | |
1507 | .name = "saa7164", | |
1508 | .id_table = saa7164_pci_tbl, | |
1509 | .probe = saa7164_initdev, | |
4c62e976 | 1510 | .remove = saa7164_finidev, |
443c1228 ST |
1511 | /* TODO */ |
1512 | .suspend = NULL, | |
1513 | .resume = NULL, | |
1514 | }; | |
1515 | ||
9d440a08 | 1516 | static int __init saa7164_init(void) |
443c1228 ST |
1517 | { |
1518 | printk(KERN_INFO "saa7164 driver loaded\n"); | |
e48836b8 ST |
1519 | |
1520 | #ifdef CONFIG_PROC_FS | |
1521 | saa7164_proc_create(); | |
1522 | #endif | |
443c1228 ST |
1523 | return pci_register_driver(&saa7164_pci_driver); |
1524 | } | |
1525 | ||
9d440a08 | 1526 | static void __exit saa7164_fini(void) |
443c1228 | 1527 | { |
e48836b8 ST |
1528 | #ifdef CONFIG_PROC_FS |
1529 | remove_proc_entry("saa7164", NULL); | |
1530 | #endif | |
443c1228 ST |
1531 | pci_unregister_driver(&saa7164_pci_driver); |
1532 | } | |
1533 | ||
1534 | module_init(saa7164_init); | |
1535 | module_exit(saa7164_fini); | |
1536 |