projects / mirror_ubuntu-artful-kernel.git / blame
| Commit | Line | Data |
|---|---|---|
| 443c1228 ST |
1 | /* |
| 2 | * Driver for the NXP SAA7164 PCIe bridge | |
| 3 | * | |
| 63a412ec | 4 | * Copyright (c) 2010-2015 Steven Toth <stoth@kernellabs.com> |
| 443c1228 ST |
5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify | |
| 7 | * it under the terms of the GNU General Public License as published by | |
| 8 | * the Free Software Foundation; either version 2 of the License, or | |
| 9 | * (at your option) any later version. | |
| 10 | * | |
| 11 | * This program is distributed in the hope that it will be useful, | |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 14 | * | |
| 15 | * GNU General Public License for more details. | |
| 443c1228 ST |
16 | */ |
| 17 | ||
| 18 | /* TODO: Retest the driver with errors expressed as negatives */ | |
| 19 | ||
| 20 | /* Result codes */ | |
| 21 | #define SAA_OK 0 | |
| 22 | #define SAA_ERR_BAD_PARAMETER 0x09 | |
| 23 | #define SAA_ERR_NO_RESOURCES 0x0c | |
| 24 | #define SAA_ERR_NOT_SUPPORTED 0x13 | |
| 25 | #define SAA_ERR_BUSY 0x15 | |
| 26 | #define SAA_ERR_READ 0x17 | |
| 27 | #define SAA_ERR_TIMEOUT 0x1f | |
| 28 | #define SAA_ERR_OVERFLOW 0x20 | |
| 29 | #define SAA_ERR_EMPTY 0x22 | |
| 30 | #define SAA_ERR_NOT_STARTED 0x23 | |
| 31 | #define SAA_ERR_ALREADY_STARTED 0x24 | |
| 32 | #define SAA_ERR_NOT_STOPPED 0x25 | |
| 33 | #define SAA_ERR_ALREADY_STOPPED 0x26 | |
| 34 | #define SAA_ERR_INVALID_COMMAND 0x3e | |
| 35 | #define SAA_ERR_NULL_PACKET 0x59 | |
| 36 | ||
| 37 | /* Errors and flags from the silicon */ | |
| 38 | #define PVC_ERRORCODE_UNKNOWN 0x00 | |
| 39 | #define PVC_ERRORCODE_INVALID_COMMAND 0x01 | |
| 40 | #define PVC_ERRORCODE_INVALID_CONTROL 0x02 | |
| 41 | #define PVC_ERRORCODE_INVALID_DATA 0x03 | |
| 42 | #define PVC_ERRORCODE_TIMEOUT 0x04 | |
| 43 | #define PVC_ERRORCODE_NAK 0x05 | |
| 44 | #define PVC_RESPONSEFLAG_ERROR 0x01 | |
| 45 | #define PVC_RESPONSEFLAG_OVERFLOW 0x02 | |
| 46 | #define PVC_RESPONSEFLAG_RESET 0x04 | |
| 47 | #define PVC_RESPONSEFLAG_INTERFACE 0x08 | |
| 48 | #define PVC_RESPONSEFLAG_CONTINUED 0x10 | |
| 49 | #define PVC_CMDFLAG_INTERRUPT 0x02 | |
| 50 | #define PVC_CMDFLAG_INTERFACE 0x04 | |
| 51 | #define PVC_CMDFLAG_SERIALIZE 0x08 | |
| 52 | #define PVC_CMDFLAG_CONTINUE 0x10 | |
| 53 | ||
| 54 | /* Silicon Commands */ | |
| 55 | #define GET_DESCRIPTORS_CONTROL 0x01 | |
| 56 | #define GET_STRING_CONTROL 0x03 | |
| 57 | #define GET_LANGUAGE_CONTROL 0x05 | |
| 58 | #define SET_POWER_CONTROL 0x07 | |
| 1247ff5c | 59 | #define GET_FW_STATUS_CONTROL 0x08 |
| 443c1228 ST |
60 | #define GET_FW_VERSION_CONTROL 0x09 |
| 61 | #define SET_DEBUG_LEVEL_CONTROL 0x0B | |
| 62 | #define GET_DEBUG_DATA_CONTROL 0x0C | |
| 63 | #define GET_PRODUCTION_INFO_CONTROL 0x0D | |
| 64 | ||
| 65 | /* cmd defines */ | |
| 66 | #define SAA_CMDFLAG_CONTINUE 0x10 | |
| 67 | #define SAA_CMD_MAX_MSG_UNITS 256 | |
| 68 | ||
| 69 | /* Some defines */ | |
| 70 | #define SAA_BUS_TIMEOUT 50 | |
| 71 | #define SAA_DEVICE_TIMEOUT 5000 | |
| 72 | #define SAA_DEVICE_MAXREQUESTSIZE 256 | |
| 73 | ||
| 74 | /* Register addresses */ | |
| 75 | #define SAA_DEVICE_VERSION 0x30 | |
| 76 | #define SAA_DOWNLOAD_FLAGS 0x34 | |
| 77 | #define SAA_DOWNLOAD_FLAG 0x34 | |
| 78 | #define SAA_DOWNLOAD_FLAG_ACK 0x38 | |
| 79 | #define SAA_DATAREADY_FLAG 0x3C | |
| 80 | #define SAA_DATAREADY_FLAG_ACK 0x40 | |
| 81 | ||
| 82 | /* Boot loader register and bit definitions */ | |
| 83 | #define SAA_BOOTLOADERERROR_FLAGS 0x44 | |
| 84 | #define SAA_DEVICE_IMAGE_SEARCHING 0x01 | |
| 85 | #define SAA_DEVICE_IMAGE_LOADING 0x02 | |
| 86 | #define SAA_DEVICE_IMAGE_BOOTING 0x03 | |
| 87 | #define SAA_DEVICE_IMAGE_CORRUPT 0x04 | |
| 88 | #define SAA_DEVICE_MEMORY_CORRUPT 0x08 | |
| 89 | #define SAA_DEVICE_NO_IMAGE 0x10 | |
| 90 | ||
| 91 | /* Register addresses */ | |
| 92 | #define SAA_DEVICE_2ND_VERSION 0x50 | |
| 93 | #define SAA_DEVICE_2ND_DOWNLOADFLAG_OFFSET 0x54 | |
| 94 | ||
| 95 | /* Register addresses */ | |
| 96 | #define SAA_SECONDSTAGEERROR_FLAGS 0x64 | |
| 97 | ||
| 98 | /* Bootloader regs and flags */ | |
| 99 | #define SAA_DEVICE_DEADLOCK_DETECTED_OFFSET 0x6C | |
| 100 | #define SAA_DEVICE_DEADLOCK_DETECTED 0xDEADDEAD | |
| 101 | ||
| 102 | /* Basic firmware status registers */ | |
| 103 | #define SAA_DEVICE_SYSINIT_STATUS_OFFSET 0x70 | |
| 104 | #define SAA_DEVICE_SYSINIT_STATUS 0x70 | |
| 105 | #define SAA_DEVICE_SYSINIT_MODE 0x74 | |
| 106 | #define SAA_DEVICE_SYSINIT_SPEC 0x78 | |
| 107 | #define SAA_DEVICE_SYSINIT_INST 0x7C | |
| 108 | #define SAA_DEVICE_SYSINIT_CPULOAD 0x80 | |
| 109 | #define SAA_DEVICE_SYSINIT_REMAINHEAP 0x84 | |
| 110 | ||
| 111 | #define SAA_DEVICE_DOWNLOAD_OFFSET 0x1000 | |
| 112 | #define SAA_DEVICE_BUFFERBLOCKSIZE 0x1000 | |
| 113 | ||
| 114 | #define SAA_DEVICE_2ND_BUFFERBLOCKSIZE 0x100000 | |
| 115 | #define SAA_DEVICE_2ND_DOWNLOAD_OFFSET 0x200000 | |
| 116 | ||
| 117 | /* Descriptors */ | |
| 118 | #define CS_INTERFACE 0x24 | |
| 119 | ||
| 120 | /* Descriptor subtypes */ | |
| 121 | #define VC_INPUT_TERMINAL 0x02 | |
| 122 | #define VC_OUTPUT_TERMINAL 0x03 | |
| 123 | #define VC_SELECTOR_UNIT 0x04 | |
| 124 | #define VC_PROCESSING_UNIT 0x05 | |
| 125 | #define FEATURE_UNIT 0x06 | |
| 126 | #define TUNER_UNIT 0x09 | |
| 127 | #define ENCODER_UNIT 0x0A | |
| 128 | #define EXTENSION_UNIT 0x0B | |
| 129 | #define VC_TUNER_PATH 0xF0 | |
| 130 | #define PVC_HARDWARE_DESCRIPTOR 0xF1 | |
| 131 | #define PVC_INTERFACE_DESCRIPTOR 0xF2 | |
| 132 | #define PVC_INFRARED_UNIT 0xF3 | |
| 133 | #define DRM_UNIT 0xF4 | |
| 134 | #define GENERAL_REQUEST 0xF5 | |
| 135 | ||
| 136 | /* Format Types */ | |
| 137 | #define VS_FORMAT_TYPE 0x02 | |
| 138 | #define VS_FORMAT_TYPE_I 0x01 | |
| 139 | #define VS_FORMAT_UNCOMPRESSED 0x04 | |
| 140 | #define VS_FRAME_UNCOMPRESSED 0x05 | |
| 141 | #define VS_FORMAT_MPEG2PS 0x09 | |
| 142 | #define VS_FORMAT_MPEG2TS 0x0A | |
| 143 | #define VS_FORMAT_MPEG4SL 0x0B | |
| 144 | #define VS_FORMAT_WM9 0x0C | |
| 145 | #define VS_FORMAT_DIVX 0x0D | |
| 146 | #define VS_FORMAT_VBI 0x0E | |
| 147 | #define VS_FORMAT_RDS 0x0F | |
| 148 | ||
| 149 | /* Device extension commands */ | |
| 150 | #define EXU_REGISTER_ACCESS_CONTROL 0x00 | |
| 151 | #define EXU_GPIO_CONTROL 0x01 | |
| 152 | #define EXU_GPIO_GROUP_CONTROL 0x02 | |
| 153 | #define EXU_INTERRUPT_CONTROL 0x03 | |
| 154 | ||
| 155 | /* State Transition and args */ | |
| e8ce2f21 ST |
156 | #define SAA_PROBE_CONTROL 0x01 |
| 157 | #define SAA_COMMIT_CONTROL 0x02 | |
| 443c1228 ST |
158 | #define SAA_STATE_CONTROL 0x03 |
| 159 | #define SAA_DMASTATE_STOP 0x00 | |
| 160 | #define SAA_DMASTATE_ACQUIRE 0x01 | |
| 161 | #define SAA_DMASTATE_PAUSE 0x02 | |
| 162 | #define SAA_DMASTATE_RUN 0x03 | |
| 163 | ||
| 335961ca ST |
164 | /* A/V Mux Input Selector */ |
| 165 | #define SU_INPUT_SELECT_CONTROL 0x01 | |
| 166 | ||
| 167 | /* Encoder Profiles */ | |
| 168 | #define EU_PROFILE_PS_DVD 0x06 | |
| 169 | #define EU_PROFILE_TS_HQ 0x09 | |
| 170 | #define EU_VIDEO_FORMAT_MPEG_2 0x02 | |
| 171 | ||
| 172 | /* Tuner */ | |
| 173 | #define TU_AUDIO_MODE_CONTROL 0x17 | |
| 174 | ||
| 175 | /* Video Formats */ | |
| 176 | #define TU_STANDARD_CONTROL 0x00 | |
| 177 | #define TU_STANDARD_AUTO_CONTROL 0x01 | |
| 178 | #define TU_STANDARD_NONE 0x00 | |
| 179 | #define TU_STANDARD_NTSC_M 0x01 | |
| 180 | #define TU_STANDARD_PAL_I 0x08 | |
| 181 | #define TU_STANDARD_MANUAL 0x00 | |
| 182 | #define TU_STANDARD_AUTO 0x01 | |
| 183 | ||
| 184 | /* Video Controls */ | |
| 185 | #define PU_BRIGHTNESS_CONTROL 0x02 | |
| 186 | #define PU_CONTRAST_CONTROL 0x03 | |
| 187 | #define PU_HUE_CONTROL 0x06 | |
| 188 | #define PU_SATURATION_CONTROL 0x07 | |
| 189 | #define PU_SHARPNESS_CONTROL 0x08 | |
| 190 | ||
| 191 | /* Audio Controls */ | |
| 192 | #define MUTE_CONTROL 0x01 | |
| 193 | #define VOLUME_CONTROL 0x02 | |
| 194 | #define AUDIO_DEFAULT_CONTROL 0x0D | |
| 195 | ||
| 196 | /* Default Volume Levels */ | |
| 197 | #define TMHW_LEV_ADJ_DECLEV_DEFAULT 0x00 | |
| 198 | #define TMHW_LEV_ADJ_MONOLEV_DEFAULT 0x00 | |
| 199 | #define TMHW_LEV_ADJ_NICLEV_DEFAULT 0x00 | |
| 200 | #define TMHW_LEV_ADJ_SAPLEV_DEFAULT 0x00 | |
| 201 | #define TMHW_LEV_ADJ_ADCLEV_DEFAULT 0x00 | |
| 202 | ||
| 203 | /* Encoder Related Commands */ | |
| 204 | #define EU_PROFILE_CONTROL 0x00 | |
| 205 | #define EU_VIDEO_FORMAT_CONTROL 0x01 | |
| 206 | #define EU_VIDEO_BIT_RATE_CONTROL 0x02 | |
| f6eeece8 | 207 | #define EU_VIDEO_RESOLUTION_CONTROL 0x03 |
| eafea210 | 208 | #define EU_VIDEO_GOP_STRUCTURE_CONTROL 0x04 |
| 335961ca ST |
209 | #define EU_VIDEO_INPUT_ASPECT_CONTROL 0x0A |
| 210 | #define EU_AUDIO_FORMAT_CONTROL 0x0C | |
| 211 | #define EU_AUDIO_BIT_RATE_CONTROL 0x0D | |
| 443c1228 | 212 | |
| e48836b8 ST |
213 | /* Firmware Debugging */ |
| 214 | #define SET_DEBUG_LEVEL_CONTROL 0x0B | |
| 215 | #define GET_DEBUG_DATA_CONTROL 0x0C |