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c942fddf | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
faa4fd2a | 2 | /* |
dcae5dac HV |
3 | * Copyright (C) 2010-2013 Bluecherry, LLC <http://www.bluecherrydvr.com> |
4 | * | |
5 | * Original author: | |
6 | * Ben Collins <bcollins@ubuntu.com> | |
7 | * | |
8 | * Additional work by: | |
9 | * John Brooks <john.brooks@bluecherry.net> | |
faa4fd2a BC |
10 | */ |
11 | ||
decebabf KH |
12 | #ifndef __SOLO6X10_REGISTERS_H |
13 | #define __SOLO6X10_REGISTERS_H | |
faa4fd2a | 14 | |
dad7fab9 | 15 | #include "solo6x10-offsets.h" |
faa4fd2a | 16 | |
dcae5dac | 17 | /* Global 6010 system configuration */ |
faa4fd2a | 18 | #define SOLO_SYS_CFG 0x0000 |
dcae5dac HV |
19 | #define SOLO_SYS_CFG_FOUT_EN 0x00000001 |
20 | #define SOLO_SYS_CFG_PLL_BYPASS 0x00000002 | |
21 | #define SOLO_SYS_CFG_PLL_PWDN 0x00000004 | |
22 | #define SOLO_SYS_CFG_OUTDIV(__n) (((__n) & 0x003) << 3) | |
23 | #define SOLO_SYS_CFG_FEEDBACKDIV(__n) (((__n) & 0x1ff) << 5) | |
24 | #define SOLO_SYS_CFG_INPUTDIV(__n) (((__n) & 0x01f) << 14) | |
faa4fd2a BC |
25 | #define SOLO_SYS_CFG_CLOCK_DIV 0x00080000 |
26 | #define SOLO_SYS_CFG_NCLK_DELAY(__n) (((__n) & 0x003) << 24) | |
27 | #define SOLO_SYS_CFG_PCLK_DELAY(__n) (((__n) & 0x00f) << 26) | |
dcae5dac | 28 | #define SOLO_SYS_CFG_SDRAM64BIT 0x40000000 |
faa4fd2a BC |
29 | #define SOLO_SYS_CFG_RESET 0x80000000 |
30 | ||
31 | #define SOLO_DMA_CTRL 0x0004 | |
32 | #define SOLO_DMA_CTRL_REFRESH_CYCLE(n) ((n)<<8) | |
33 | /* 0=16/32MB, 1=32/64MB, 2=64/128MB, 3=128/256MB */ | |
34 | #define SOLO_DMA_CTRL_SDRAM_SIZE(n) ((n)<<6) | |
35 | #define SOLO_DMA_CTRL_SDRAM_CLK_INVERT (1<<5) | |
36 | #define SOLO_DMA_CTRL_STROBE_SELECT (1<<4) | |
37 | #define SOLO_DMA_CTRL_READ_DATA_SELECT (1<<3) | |
38 | #define SOLO_DMA_CTRL_READ_CLK_SELECT (1<<2) | |
39 | #define SOLO_DMA_CTRL_LATENCY(n) ((n)<<0) | |
dcae5dac HV |
40 | |
41 | /* Some things we set in this are undocumented. Why Softlogic?!?! */ | |
42 | #define SOLO_DMA_CTRL1 0x0008 | |
faa4fd2a BC |
43 | |
44 | #define SOLO_SYS_VCLK 0x000C | |
45 | #define SOLO_VCLK_INVERT (1<<22) | |
46 | /* 0=sys_clk/4, 1=sys_clk/2, 2=clk_in/2 of system input */ | |
47 | #define SOLO_VCLK_SELECT(n) ((n)<<20) | |
48 | #define SOLO_VCLK_VIN1415_DELAY(n) ((n)<<14) | |
49 | #define SOLO_VCLK_VIN1213_DELAY(n) ((n)<<12) | |
50 | #define SOLO_VCLK_VIN1011_DELAY(n) ((n)<<10) | |
51 | #define SOLO_VCLK_VIN0809_DELAY(n) ((n)<<8) | |
52 | #define SOLO_VCLK_VIN0607_DELAY(n) ((n)<<6) | |
53 | #define SOLO_VCLK_VIN0405_DELAY(n) ((n)<<4) | |
54 | #define SOLO_VCLK_VIN0203_DELAY(n) ((n)<<2) | |
55 | #define SOLO_VCLK_VIN0001_DELAY(n) ((n)<<0) | |
56 | ||
57 | #define SOLO_IRQ_STAT 0x0010 | |
dcae5dac | 58 | #define SOLO_IRQ_MASK 0x0014 |
faa4fd2a BC |
59 | #define SOLO_IRQ_P2M(n) (1<<((n)+17)) |
60 | #define SOLO_IRQ_GPIO (1<<16) | |
61 | #define SOLO_IRQ_VIDEO_LOSS (1<<15) | |
62 | #define SOLO_IRQ_VIDEO_IN (1<<14) | |
63 | #define SOLO_IRQ_MOTION (1<<13) | |
64 | #define SOLO_IRQ_ATA_CMD (1<<12) | |
65 | #define SOLO_IRQ_ATA_DIR (1<<11) | |
66 | #define SOLO_IRQ_PCI_ERR (1<<10) | |
67 | #define SOLO_IRQ_PS2_1 (1<<9) | |
68 | #define SOLO_IRQ_PS2_0 (1<<8) | |
69 | #define SOLO_IRQ_SPI (1<<7) | |
70 | #define SOLO_IRQ_IIC (1<<6) | |
71 | #define SOLO_IRQ_UART(n) (1<<((n) + 4)) | |
72 | #define SOLO_IRQ_G723 (1<<3) | |
73 | #define SOLO_IRQ_DECODER (1<<1) | |
74 | #define SOLO_IRQ_ENCODER (1<<0) | |
75 | ||
76 | #define SOLO_CHIP_OPTION 0x001C | |
77 | #define SOLO_CHIP_ID_MASK 0x00000007 | |
78 | ||
dcae5dac | 79 | #define SOLO_PLL_CONFIG 0x0020 /* 6110 Only */ |
908113d8 | 80 | |
faa4fd2a BC |
81 | #define SOLO_EEPROM_CTRL 0x0060 |
82 | #define SOLO_EEPROM_ACCESS_EN (1<<7) | |
83 | #define SOLO_EEPROM_CS (1<<3) | |
84 | #define SOLO_EEPROM_CLK (1<<2) | |
85 | #define SOLO_EEPROM_DO (1<<1) | |
86 | #define SOLO_EEPROM_DI (1<<0) | |
dcae5dac | 87 | #define SOLO_EEPROM_ENABLE (SOLO_EEPROM_ACCESS_EN | SOLO_EEPROM_CS) |
faa4fd2a BC |
88 | |
89 | #define SOLO_PCI_ERR 0x0070 | |
90 | #define SOLO_PCI_ERR_FATAL 0x00000001 | |
91 | #define SOLO_PCI_ERR_PARITY 0x00000002 | |
92 | #define SOLO_PCI_ERR_TARGET 0x00000004 | |
93 | #define SOLO_PCI_ERR_TIMEOUT 0x00000008 | |
94 | #define SOLO_PCI_ERR_P2M 0x00000010 | |
95 | #define SOLO_PCI_ERR_ATA 0x00000020 | |
96 | #define SOLO_PCI_ERR_P2M_DESC 0x00000040 | |
97 | #define SOLO_PCI_ERR_FSM0(__s) (((__s) >> 16) & 0x0f) | |
98 | #define SOLO_PCI_ERR_FSM1(__s) (((__s) >> 20) & 0x0f) | |
99 | #define SOLO_PCI_ERR_FSM2(__s) (((__s) >> 24) & 0x1f) | |
100 | ||
101 | #define SOLO_P2M_BASE 0x0080 | |
102 | ||
103 | #define SOLO_P2M_CONFIG(n) (0x0080 + ((n)*0x20)) | |
104 | #define SOLO_P2M_DMA_INTERVAL(n) ((n)<<6)/* N*32 clocks */ | |
105 | #define SOLO_P2M_CSC_BYTE_REORDER (1<<5) /* BGR -> RGB */ | |
106 | /* 0:r=[14:10] g=[9:5] b=[4:0], 1:r=[15:11] g=[10:5] b=[4:0] */ | |
107 | #define SOLO_P2M_CSC_16BIT_565 (1<<4) | |
108 | #define SOLO_P2M_UV_SWAP (1<<3) | |
109 | #define SOLO_P2M_PCI_MASTER_MODE (1<<2) | |
110 | #define SOLO_P2M_DESC_INTR_OPT (1<<1) /* 1:Empty, 0:Each */ | |
111 | #define SOLO_P2M_DESC_MODE (1<<0) | |
112 | ||
113 | #define SOLO_P2M_DES_ADR(n) (0x0084 + ((n)*0x20)) | |
114 | ||
115 | #define SOLO_P2M_DESC_ID(n) (0x0088 + ((n)*0x20)) | |
116 | #define SOLO_P2M_UPDATE_ID(n) ((n)<<0) | |
117 | ||
118 | #define SOLO_P2M_STATUS(n) (0x008C + ((n)*0x20)) | |
119 | #define SOLO_P2M_COMMAND_DONE (1<<8) | |
120 | #define SOLO_P2M_CURRENT_ID(stat) (0xff & (stat)) | |
121 | ||
122 | #define SOLO_P2M_CONTROL(n) (0x0090 + ((n)*0x20)) | |
123 | #define SOLO_P2M_PCI_INC(n) ((n)<<20) | |
124 | #define SOLO_P2M_REPEAT(n) ((n)<<10) | |
125 | /* 0:512, 1:256, 2:128, 3:64, 4:32, 5:128(2page) */ | |
126 | #define SOLO_P2M_BURST_SIZE(n) ((n)<<7) | |
127 | #define SOLO_P2M_BURST_512 0 | |
128 | #define SOLO_P2M_BURST_256 1 | |
129 | #define SOLO_P2M_BURST_128 2 | |
130 | #define SOLO_P2M_BURST_64 3 | |
131 | #define SOLO_P2M_BURST_32 4 | |
132 | #define SOLO_P2M_CSC_16BIT (1<<6) /* 0:24bit, 1:16bit */ | |
133 | /* 0:Y[0]<-0(OFF), 1:Y[0]<-1(ON), 2:Y[0]<-G[0], 3:Y[0]<-Bit[15] */ | |
134 | #define SOLO_P2M_ALPHA_MODE(n) ((n)<<4) | |
135 | #define SOLO_P2M_CSC_ON (1<<3) | |
136 | #define SOLO_P2M_INTERRUPT_REQ (1<<2) | |
137 | #define SOLO_P2M_WRITE (1<<1) | |
138 | #define SOLO_P2M_TRANS_ON (1<<0) | |
139 | ||
140 | #define SOLO_P2M_EXT_CFG(n) (0x0094 + ((n)*0x20)) | |
141 | #define SOLO_P2M_EXT_INC(n) ((n)<<20) | |
142 | #define SOLO_P2M_COPY_SIZE(n) ((n)<<0) | |
143 | ||
144 | #define SOLO_P2M_TAR_ADR(n) (0x0098 + ((n)*0x20)) | |
145 | ||
146 | #define SOLO_P2M_EXT_ADR(n) (0x009C + ((n)*0x20)) | |
147 | ||
148 | #define SOLO_P2M_BUFFER(i) (0x2000 + ((i)*4)) | |
149 | ||
150 | #define SOLO_VI_CH_SWITCH_0 0x0100 | |
151 | #define SOLO_VI_CH_SWITCH_1 0x0104 | |
152 | #define SOLO_VI_CH_SWITCH_2 0x0108 | |
153 | ||
154 | #define SOLO_VI_CH_ENA 0x010C | |
155 | #define SOLO_VI_CH_FORMAT 0x0110 | |
156 | #define SOLO_VI_FD_SEL_MASK(n) ((n)<<16) | |
157 | #define SOLO_VI_PROG_MASK(n) ((n)<<0) | |
158 | ||
159 | #define SOLO_VI_FMT_CFG 0x0114 | |
160 | #define SOLO_VI_FMT_CHECK_VCOUNT (1<<31) | |
161 | #define SOLO_VI_FMT_CHECK_HCOUNT (1<<30) | |
162 | #define SOLO_VI_FMT_TEST_SIGNAL (1<<28) | |
163 | ||
164 | #define SOLO_VI_PAGE_SW 0x0118 | |
165 | #define SOLO_FI_INV_DISP_LIVE(n) ((n)<<8) | |
166 | #define SOLO_FI_INV_DISP_OUT(n) ((n)<<7) | |
167 | #define SOLO_DISP_SYNC_FI(n) ((n)<<6) | |
168 | #define SOLO_PIP_PAGE_ADD(n) ((n)<<3) | |
169 | #define SOLO_NORMAL_PAGE_ADD(n) ((n)<<0) | |
170 | ||
171 | #define SOLO_VI_ACT_I_P 0x011C | |
172 | #define SOLO_VI_ACT_I_S 0x0120 | |
173 | #define SOLO_VI_ACT_P 0x0124 | |
174 | #define SOLO_VI_FI_INVERT (1<<31) | |
175 | #define SOLO_VI_H_START(n) ((n)<<21) | |
176 | #define SOLO_VI_V_START(n) ((n)<<11) | |
177 | #define SOLO_VI_V_STOP(n) ((n)<<0) | |
178 | ||
179 | #define SOLO_VI_STATUS0 0x0128 | |
180 | #define SOLO_VI_STATUS0_PAGE(__n) ((__n) & 0x07) | |
181 | #define SOLO_VI_STATUS1 0x012C | |
182 | ||
183 | /* XXX: Might be better off in kernel level disp.h */ | |
184 | #define DISP_PAGE(stat) ((stat) & 0x07) | |
185 | ||
186 | #define SOLO_VI_PB_CONFIG 0x0130 | |
187 | #define SOLO_VI_PB_USER_MODE (1<<1) | |
188 | #define SOLO_VI_PB_PAL (1<<0) | |
189 | #define SOLO_VI_PB_RANGE_HV 0x0134 | |
190 | #define SOLO_VI_PB_HSIZE(h) ((h)<<12) | |
191 | #define SOLO_VI_PB_VSIZE(v) ((v)<<0) | |
192 | #define SOLO_VI_PB_ACT_H 0x0138 | |
193 | #define SOLO_VI_PB_HSTART(n) ((n)<<12) | |
194 | #define SOLO_VI_PB_HSTOP(n) ((n)<<0) | |
195 | #define SOLO_VI_PB_ACT_V 0x013C | |
196 | #define SOLO_VI_PB_VSTART(n) ((n)<<12) | |
197 | #define SOLO_VI_PB_VSTOP(n) ((n)<<0) | |
198 | ||
199 | #define SOLO_VI_MOSAIC(ch) (0x0140 + ((ch)*4)) | |
200 | #define SOLO_VI_MOSAIC_SX(x) ((x)<<24) | |
201 | #define SOLO_VI_MOSAIC_EX(x) ((x)<<16) | |
202 | #define SOLO_VI_MOSAIC_SY(x) ((x)<<8) | |
203 | #define SOLO_VI_MOSAIC_EY(x) ((x)<<0) | |
204 | ||
205 | #define SOLO_VI_WIN_CTRL0(ch) (0x0180 + ((ch)*4)) | |
206 | #define SOLO_VI_WIN_CTRL1(ch) (0x01C0 + ((ch)*4)) | |
207 | ||
208 | #define SOLO_VI_WIN_CHANNEL(n) ((n)<<28) | |
209 | ||
210 | #define SOLO_VI_WIN_PIP(n) ((n)<<27) | |
211 | #define SOLO_VI_WIN_SCALE(n) ((n)<<24) | |
212 | ||
213 | #define SOLO_VI_WIN_SX(x) ((x)<<12) | |
214 | #define SOLO_VI_WIN_EX(x) ((x)<<0) | |
215 | ||
216 | #define SOLO_VI_WIN_SY(x) ((x)<<12) | |
217 | #define SOLO_VI_WIN_EY(x) ((x)<<0) | |
218 | ||
219 | #define SOLO_VI_WIN_ON(ch) (0x0200 + ((ch)*4)) | |
220 | ||
221 | #define SOLO_VI_WIN_SW 0x0240 | |
222 | #define SOLO_VI_WIN_LIVE_AUTO_MUTE 0x0244 | |
223 | ||
224 | #define SOLO_VI_MOT_ADR 0x0260 | |
225 | #define SOLO_VI_MOTION_EN(mask) ((mask)<<16) | |
226 | #define SOLO_VI_MOT_CTRL 0x0264 | |
227 | #define SOLO_VI_MOTION_FRAME_COUNT(n) ((n)<<24) | |
228 | #define SOLO_VI_MOTION_SAMPLE_LENGTH(n) ((n)<<16) | |
229 | #define SOLO_VI_MOTION_INTR_START_STOP (1<<15) | |
230 | #define SOLO_VI_MOTION_FREEZE_DATA (1<<14) | |
231 | #define SOLO_VI_MOTION_SAMPLE_COUNT(n) ((n)<<0) | |
232 | #define SOLO_VI_MOT_CLEAR 0x0268 | |
233 | #define SOLO_VI_MOT_STATUS 0x026C | |
234 | #define SOLO_VI_MOTION_CNT(n) ((n)<<0) | |
235 | #define SOLO_VI_MOTION_BORDER 0x0270 | |
236 | #define SOLO_VI_MOTION_BAR 0x0274 | |
237 | #define SOLO_VI_MOTION_Y_SET (1<<29) | |
238 | #define SOLO_VI_MOTION_Y_ADD (1<<28) | |
239 | #define SOLO_VI_MOTION_CB_SET (1<<27) | |
240 | #define SOLO_VI_MOTION_CB_ADD (1<<26) | |
241 | #define SOLO_VI_MOTION_CR_SET (1<<25) | |
242 | #define SOLO_VI_MOTION_CR_ADD (1<<24) | |
243 | #define SOLO_VI_MOTION_Y_VALUE(v) ((v)<<16) | |
244 | #define SOLO_VI_MOTION_CB_VALUE(v) ((v)<<8) | |
245 | #define SOLO_VI_MOTION_CR_VALUE(v) ((v)<<0) | |
246 | ||
247 | #define SOLO_VO_FMT_ENC 0x0300 | |
248 | #define SOLO_VO_SCAN_MODE_PROGRESSIVE (1<<31) | |
249 | #define SOLO_VO_FMT_TYPE_PAL (1<<30) | |
250 | #define SOLO_VO_FMT_TYPE_NTSC 0 | |
251 | #define SOLO_VO_USER_SET (1<<29) | |
252 | ||
253 | #define SOLO_VO_FI_CHANGE (1<<20) | |
254 | #define SOLO_VO_USER_COLOR_SET_VSYNC (1<<19) | |
255 | #define SOLO_VO_USER_COLOR_SET_HSYNC (1<<18) | |
dcae5dac HV |
256 | #define SOLO_VO_USER_COLOR_SET_NAH (1<<17) |
257 | #define SOLO_VO_USER_COLOR_SET_NAV (1<<16) | |
faa4fd2a BC |
258 | #define SOLO_VO_NA_COLOR_Y(Y) ((Y)<<8) |
259 | #define SOLO_VO_NA_COLOR_CB(CB) (((CB)/16)<<4) | |
260 | #define SOLO_VO_NA_COLOR_CR(CR) (((CR)/16)<<0) | |
261 | ||
262 | #define SOLO_VO_ACT_H 0x0304 | |
263 | #define SOLO_VO_H_BLANK(n) ((n)<<22) | |
264 | #define SOLO_VO_H_START(n) ((n)<<11) | |
265 | #define SOLO_VO_H_STOP(n) ((n)<<0) | |
266 | ||
267 | #define SOLO_VO_ACT_V 0x0308 | |
268 | #define SOLO_VO_V_BLANK(n) ((n)<<22) | |
269 | #define SOLO_VO_V_START(n) ((n)<<11) | |
270 | #define SOLO_VO_V_STOP(n) ((n)<<0) | |
271 | ||
272 | #define SOLO_VO_RANGE_HV 0x030C | |
273 | #define SOLO_VO_SYNC_INVERT (1<<24) | |
274 | #define SOLO_VO_HSYNC_INVERT (1<<23) | |
275 | #define SOLO_VO_VSYNC_INVERT (1<<22) | |
276 | #define SOLO_VO_H_LEN(n) ((n)<<11) | |
277 | #define SOLO_VO_V_LEN(n) ((n)<<0) | |
278 | ||
279 | #define SOLO_VO_DISP_CTRL 0x0310 | |
280 | #define SOLO_VO_DISP_ON (1<<31) | |
281 | #define SOLO_VO_DISP_ERASE_COUNT(n) ((n&0xf)<<24) | |
282 | #define SOLO_VO_DISP_DOUBLE_SCAN (1<<22) | |
283 | #define SOLO_VO_DISP_SINGLE_PAGE (1<<21) | |
284 | #define SOLO_VO_DISP_BASE(n) (((n)>>16) & 0xffff) | |
285 | ||
286 | #define SOLO_VO_DISP_ERASE 0x0314 | |
287 | #define SOLO_VO_DISP_ERASE_ON (1<<0) | |
288 | ||
289 | #define SOLO_VO_ZOOM_CTRL 0x0318 | |
290 | #define SOLO_VO_ZOOM_VER_ON (1<<24) | |
291 | #define SOLO_VO_ZOOM_HOR_ON (1<<23) | |
292 | #define SOLO_VO_ZOOM_V_COMP (1<<22) | |
293 | #define SOLO_VO_ZOOM_SX(h) (((h)/2)<<11) | |
294 | #define SOLO_VO_ZOOM_SY(v) (((v)/2)<<0) | |
295 | ||
296 | #define SOLO_VO_FREEZE_CTRL 0x031C | |
297 | #define SOLO_VO_FREEZE_ON (1<<1) | |
298 | #define SOLO_VO_FREEZE_INTERPOLATION (1<<0) | |
299 | ||
300 | #define SOLO_VO_BKG_COLOR 0x0320 | |
301 | #define SOLO_BG_Y(y) ((y)<<16) | |
302 | #define SOLO_BG_U(u) ((u)<<8) | |
303 | #define SOLO_BG_V(v) ((v)<<0) | |
304 | ||
305 | #define SOLO_VO_DEINTERLACE 0x0324 | |
306 | #define SOLO_VO_DEINTERLACE_THRESHOLD(n) ((n)<<8) | |
307 | #define SOLO_VO_DEINTERLACE_EDGE_VALUE(n) ((n)<<0) | |
308 | ||
309 | #define SOLO_VO_BORDER_LINE_COLOR 0x0330 | |
310 | #define SOLO_VO_BORDER_FILL_COLOR 0x0334 | |
311 | #define SOLO_VO_BORDER_LINE_MASK 0x0338 | |
312 | #define SOLO_VO_BORDER_FILL_MASK 0x033c | |
313 | ||
314 | #define SOLO_VO_BORDER_X(n) (0x0340+((n)*4)) | |
315 | #define SOLO_VO_BORDER_Y(n) (0x0354+((n)*4)) | |
316 | ||
317 | #define SOLO_VO_CELL_EXT_SET 0x0368 | |
318 | #define SOLO_VO_CELL_EXT_START 0x036c | |
319 | #define SOLO_VO_CELL_EXT_STOP 0x0370 | |
320 | ||
321 | #define SOLO_VO_CELL_EXT_SET2 0x0374 | |
322 | #define SOLO_VO_CELL_EXT_START2 0x0378 | |
323 | #define SOLO_VO_CELL_EXT_STOP2 0x037c | |
324 | ||
325 | #define SOLO_VO_RECTANGLE_CTRL(n) (0x0368+((n)*12)) | |
326 | #define SOLO_VO_RECTANGLE_START(n) (0x036c+((n)*12)) | |
327 | #define SOLO_VO_RECTANGLE_STOP(n) (0x0370+((n)*12)) | |
328 | ||
329 | #define SOLO_VO_CURSOR_POS (0x0380) | |
330 | #define SOLO_VO_CURSOR_CLR (0x0384) | |
331 | #define SOLO_VO_CURSOR_CLR2 (0x0388) | |
332 | #define SOLO_VO_CURSOR_MASK(id) (0x0390+((id)*4)) | |
333 | ||
334 | #define SOLO_VO_EXPANSION(id) (0x0250+((id)*4)) | |
335 | ||
336 | #define SOLO_OSG_CONFIG 0x03E0 | |
337 | #define SOLO_VO_OSG_ON (1<<31) | |
338 | #define SOLO_VO_OSG_COLOR_MUTE (1<<28) | |
339 | #define SOLO_VO_OSG_ALPHA_RATE(n) ((n)<<22) | |
340 | #define SOLO_VO_OSG_ALPHA_BG_RATE(n) ((n)<<16) | |
341 | #define SOLO_VO_OSG_BASE(offset) (((offset)>>16)&0xffff) | |
342 | ||
343 | #define SOLO_OSG_ERASE 0x03E4 | |
344 | #define SOLO_OSG_ERASE_ON (0x80) | |
345 | #define SOLO_OSG_ERASE_OFF (0x00) | |
346 | ||
347 | #define SOLO_VO_OSG_BLINK 0x03E8 | |
348 | #define SOLO_VO_OSG_BLINK_ON (1<<1) | |
349 | #define SOLO_VO_OSG_BLINK_INTREVAL18 (1<<0) | |
350 | ||
351 | #define SOLO_CAP_BASE 0x0400 | |
352 | #define SOLO_CAP_MAX_PAGE(n) ((n)<<16) | |
353 | #define SOLO_CAP_BASE_ADDR(n) ((n)<<0) | |
354 | #define SOLO_CAP_BTW 0x0404 | |
355 | #define SOLO_CAP_PROG_BANDWIDTH(n) ((n)<<8) | |
356 | #define SOLO_CAP_MAX_BANDWIDTH(n) ((n)<<0) | |
357 | ||
358 | #define SOLO_DIM_SCALE1 0x0408 | |
359 | #define SOLO_DIM_SCALE2 0x040C | |
360 | #define SOLO_DIM_SCALE3 0x0410 | |
361 | #define SOLO_DIM_SCALE4 0x0414 | |
362 | #define SOLO_DIM_SCALE5 0x0418 | |
363 | #define SOLO_DIM_V_MB_NUM_FRAME(n) ((n)<<16) | |
364 | #define SOLO_DIM_V_MB_NUM_FIELD(n) ((n)<<8) | |
365 | #define SOLO_DIM_H_MB_NUM(n) ((n)<<0) | |
366 | ||
367 | #define SOLO_DIM_PROG 0x041C | |
368 | #define SOLO_CAP_STATUS 0x0420 | |
369 | ||
370 | #define SOLO_CAP_CH_SCALE(ch) (0x0440+((ch)*4)) | |
371 | #define SOLO_CAP_CH_COMP_ENA_E(ch) (0x0480+((ch)*4)) | |
372 | #define SOLO_CAP_CH_INTV(ch) (0x04C0+((ch)*4)) | |
373 | #define SOLO_CAP_CH_INTV_E(ch) (0x0500+((ch)*4)) | |
374 | ||
375 | ||
376 | #define SOLO_VE_CFG0 0x0610 | |
377 | #define SOLO_VE_TWO_PAGE_MODE (1<<31) | |
378 | #define SOLO_VE_INTR_CTRL(n) ((n)<<24) | |
379 | #define SOLO_VE_BLOCK_SIZE(n) ((n)<<16) | |
380 | #define SOLO_VE_BLOCK_BASE(n) ((n)<<0) | |
381 | ||
382 | #define SOLO_VE_CFG1 0x0614 | |
dcae5dac | 383 | #define SOLO_VE_BYTE_ALIGN(n) ((n)<<24) |
faa4fd2a BC |
384 | #define SOLO_VE_INSERT_INDEX (1<<18) |
385 | #define SOLO_VE_MOTION_MODE(n) ((n)<<16) | |
386 | #define SOLO_VE_MOTION_BASE(n) ((n)<<0) | |
dcae5dac HV |
387 | #define SOLO_VE_MPEG_SIZE_H(n) ((n)<<28) /* 6110 Only */ |
388 | #define SOLO_VE_JPEG_SIZE_H(n) ((n)<<20) /* 6110 Only */ | |
389 | #define SOLO_VE_INSERT_INDEX_JPEG (1<<19) /* 6110 Only */ | |
faa4fd2a BC |
390 | |
391 | #define SOLO_VE_WMRK_POLY 0x061C | |
392 | #define SOLO_VE_VMRK_INIT_KEY 0x0620 | |
393 | #define SOLO_VE_WMRK_STRL 0x0624 | |
394 | #define SOLO_VE_ENCRYP_POLY 0x0628 | |
395 | #define SOLO_VE_ENCRYP_INIT 0x062C | |
396 | #define SOLO_VE_ATTR 0x0630 | |
397 | #define SOLO_VE_LITTLE_ENDIAN (1<<31) | |
398 | #define SOLO_COMP_ATTR_RN (1<<30) | |
399 | #define SOLO_COMP_ATTR_FCODE(n) ((n)<<27) | |
400 | #define SOLO_COMP_TIME_INC(n) ((n)<<25) | |
401 | #define SOLO_COMP_TIME_WIDTH(n) ((n)<<21) | |
402 | #define SOLO_DCT_INTERVAL(n) ((n)<<16) | |
dcae5dac | 403 | #define SOLO_VE_COMPT_MOT 0x0634 /* 6110 Only */ |
faa4fd2a BC |
404 | |
405 | #define SOLO_VE_STATE(n) (0x0640+((n)*4)) | |
faa4fd2a BC |
406 | |
407 | #define SOLO_VE_JPEG_QP_TBL 0x0670 | |
408 | #define SOLO_VE_JPEG_QP_CH_L 0x0674 | |
409 | #define SOLO_VE_JPEG_QP_CH_H 0x0678 | |
410 | #define SOLO_VE_JPEG_CFG 0x067C | |
411 | #define SOLO_VE_JPEG_CTRL 0x0680 | |
dcae5dac HV |
412 | #define SOLO_VE_CODE_ENCRYPT 0x0684 /* 6110 Only */ |
413 | #define SOLO_VE_JPEG_CFG1 0x0688 /* 6110 Only */ | |
414 | #define SOLO_VE_WMRK_ENABLE 0x068C /* 6110 Only */ | |
faa4fd2a BC |
415 | #define SOLO_VE_OSD_CH 0x0690 |
416 | #define SOLO_VE_OSD_BASE 0x0694 | |
417 | #define SOLO_VE_OSD_CLR 0x0698 | |
418 | #define SOLO_VE_OSD_OPT 0x069C | |
dcae5dac HV |
419 | #define SOLO_VE_OSD_V_DOUBLE (1<<16) /* 6110 Only */ |
420 | #define SOLO_VE_OSD_H_SHADOW (1<<15) | |
421 | #define SOLO_VE_OSD_V_SHADOW (1<<14) | |
422 | #define SOLO_VE_OSD_H_OFFSET(n) ((n & 0x7f)<<7) | |
423 | #define SOLO_VE_OSD_V_OFFSET(n) (n & 0x7f) | |
faa4fd2a BC |
424 | |
425 | #define SOLO_VE_CH_INTL(ch) (0x0700+((ch)*4)) | |
dcae5dac | 426 | #define SOLO_VE_CH_MOT(ch) (0x0740+((ch)*4)) |
faa4fd2a BC |
427 | #define SOLO_VE_CH_QP(ch) (0x0780+((ch)*4)) |
428 | #define SOLO_VE_CH_QP_E(ch) (0x07C0+((ch)*4)) | |
429 | #define SOLO_VE_CH_GOP(ch) (0x0800+((ch)*4)) | |
430 | #define SOLO_VE_CH_GOP_E(ch) (0x0840+((ch)*4)) | |
431 | #define SOLO_VE_CH_REF_BASE(ch) (0x0880+((ch)*4)) | |
432 | #define SOLO_VE_CH_REF_BASE_E(ch) (0x08C0+((ch)*4)) | |
433 | ||
434 | #define SOLO_VE_MPEG4_QUE(n) (0x0A00+((n)*8)) | |
435 | #define SOLO_VE_JPEG_QUE(n) (0x0A04+((n)*8)) | |
436 | ||
437 | #define SOLO_VD_CFG0 0x0900 | |
dcae5dac | 438 | #define SOLO_VD_CFG_NO_WRITE_NO_WINDOW (1<<24) |
faa4fd2a BC |
439 | #define SOLO_VD_CFG_BUSY_WIAT_CODE (1<<23) |
440 | #define SOLO_VD_CFG_BUSY_WIAT_REF (1<<22) | |
441 | #define SOLO_VD_CFG_BUSY_WIAT_RES (1<<21) | |
442 | #define SOLO_VD_CFG_BUSY_WIAT_MS (1<<20) | |
443 | #define SOLO_VD_CFG_SINGLE_MODE (1<<18) | |
444 | #define SOLO_VD_CFG_SCAL_MANUAL (1<<17) | |
445 | #define SOLO_VD_CFG_USER_PAGE_CTRL (1<<16) | |
446 | #define SOLO_VD_CFG_LITTLE_ENDIAN (1<<15) | |
447 | #define SOLO_VD_CFG_START_FI (1<<14) | |
448 | #define SOLO_VD_CFG_ERR_LOCK (1<<13) | |
449 | #define SOLO_VD_CFG_ERR_INT_ENA (1<<12) | |
450 | #define SOLO_VD_CFG_TIME_WIDTH(n) ((n)<<8) | |
451 | #define SOLO_VD_CFG_DCT_INTERVAL(n) ((n)<<0) | |
452 | ||
453 | #define SOLO_VD_CFG1 0x0904 | |
454 | ||
455 | #define SOLO_VD_DEINTERLACE 0x0908 | |
456 | #define SOLO_VD_DEINTERLACE_THRESHOLD(n) ((n)<<8) | |
457 | #define SOLO_VD_DEINTERLACE_EDGE_VALUE(n) ((n)<<0) | |
458 | ||
459 | #define SOLO_VD_CODE_ADR 0x090C | |
460 | ||
461 | #define SOLO_VD_CTRL 0x0910 | |
462 | #define SOLO_VD_OPER_ON (1<<31) | |
463 | #define SOLO_VD_MAX_ITEM(n) ((n)<<0) | |
464 | ||
465 | #define SOLO_VD_STATUS0 0x0920 | |
466 | #define SOLO_VD_STATUS0_INTR_ACK (1<<22) | |
467 | #define SOLO_VD_STATUS0_INTR_EMPTY (1<<21) | |
468 | #define SOLO_VD_STATUS0_INTR_ERR (1<<20) | |
469 | ||
470 | #define SOLO_VD_STATUS1 0x0924 | |
471 | ||
472 | #define SOLO_VD_IDX0 0x0930 | |
473 | #define SOLO_VD_IDX_INTERLACE (1<<30) | |
474 | #define SOLO_VD_IDX_CHANNEL(n) ((n)<<24) | |
475 | #define SOLO_VD_IDX_SIZE(n) ((n)<<0) | |
476 | ||
477 | #define SOLO_VD_IDX1 0x0934 | |
478 | #define SOLO_VD_IDX_SRC_SCALE(n) ((n)<<28) | |
479 | #define SOLO_VD_IDX_WINDOW(n) ((n)<<24) | |
480 | #define SOLO_VD_IDX_DEINTERLACE (1<<16) | |
481 | #define SOLO_VD_IDX_H_BLOCK(n) ((n)<<8) | |
482 | #define SOLO_VD_IDX_V_BLOCK(n) ((n)<<0) | |
483 | ||
484 | #define SOLO_VD_IDX2 0x0938 | |
485 | #define SOLO_VD_IDX_REF_BASE_SIDE (1<<31) | |
486 | #define SOLO_VD_IDX_REF_BASE(n) (((n)>>16)&0xffff) | |
487 | ||
488 | #define SOLO_VD_IDX3 0x093C | |
489 | #define SOLO_VD_IDX_DISP_SCALE(n) ((n)<<28) | |
490 | #define SOLO_VD_IDX_INTERLACE_WR (1<<27) | |
491 | #define SOLO_VD_IDX_INTERPOL (1<<26) | |
492 | #define SOLO_VD_IDX_HOR2X (1<<25) | |
493 | #define SOLO_VD_IDX_OFFSET_X(n) ((n)<<12) | |
494 | #define SOLO_VD_IDX_OFFSET_Y(n) ((n)<<0) | |
495 | ||
496 | #define SOLO_VD_IDX4 0x0940 | |
497 | #define SOLO_VD_IDX_DEC_WR_PAGE(n) ((n)<<8) | |
498 | #define SOLO_VD_IDX_DISP_RD_PAGE(n) ((n)<<0) | |
499 | ||
500 | #define SOLO_VD_WR_PAGE(n) (0x03F0 + ((n) * 4)) | |
501 | ||
502 | ||
503 | #define SOLO_GPIO_CONFIG_0 0x0B00 | |
504 | #define SOLO_GPIO_CONFIG_1 0x0B04 | |
505 | #define SOLO_GPIO_DATA_OUT 0x0B08 | |
506 | #define SOLO_GPIO_DATA_IN 0x0B0C | |
507 | #define SOLO_GPIO_INT_ACK_STA 0x0B10 | |
508 | #define SOLO_GPIO_INT_ENA 0x0B14 | |
509 | #define SOLO_GPIO_INT_CFG_0 0x0B18 | |
510 | #define SOLO_GPIO_INT_CFG_1 0x0B1C | |
511 | ||
512 | ||
513 | #define SOLO_IIC_CFG 0x0B20 | |
514 | #define SOLO_IIC_ENABLE (1<<8) | |
515 | #define SOLO_IIC_PRESCALE(n) ((n)<<0) | |
516 | ||
517 | #define SOLO_IIC_CTRL 0x0B24 | |
518 | #define SOLO_IIC_AUTO_CLEAR (1<<20) | |
519 | #define SOLO_IIC_STATE_RX_ACK (1<<19) | |
520 | #define SOLO_IIC_STATE_BUSY (1<<18) | |
521 | #define SOLO_IIC_STATE_SIG_ERR (1<<17) | |
522 | #define SOLO_IIC_STATE_TRNS (1<<16) | |
523 | #define SOLO_IIC_CH_SET(n) ((n)<<5) | |
524 | #define SOLO_IIC_ACK_EN (1<<4) | |
525 | #define SOLO_IIC_START (1<<3) | |
526 | #define SOLO_IIC_STOP (1<<2) | |
527 | #define SOLO_IIC_READ (1<<1) | |
528 | #define SOLO_IIC_WRITE (1<<0) | |
529 | ||
530 | #define SOLO_IIC_TXD 0x0B28 | |
531 | #define SOLO_IIC_RXD 0x0B2C | |
532 | ||
533 | /* | |
534 | * UART REGISTER | |
535 | */ | |
536 | #define SOLO_UART_CONTROL(n) (0x0BA0 + ((n)*0x20)) | |
537 | #define SOLO_UART_CLK_DIV(n) ((n)<<24) | |
538 | #define SOLO_MODEM_CTRL_EN (1<<20) | |
539 | #define SOLO_PARITY_ERROR_DROP (1<<18) | |
540 | #define SOLO_IRQ_ERR_EN (1<<17) | |
541 | #define SOLO_IRQ_RX_EN (1<<16) | |
542 | #define SOLO_IRQ_TX_EN (1<<15) | |
543 | #define SOLO_RX_EN (1<<14) | |
544 | #define SOLO_TX_EN (1<<13) | |
545 | #define SOLO_UART_HALF_DUPLEX (1<<12) | |
546 | #define SOLO_UART_LOOPBACK (1<<11) | |
547 | ||
548 | #define SOLO_BAUDRATE_230400 ((0<<9)|(0<<6)) | |
549 | #define SOLO_BAUDRATE_115200 ((0<<9)|(1<<6)) | |
550 | #define SOLO_BAUDRATE_57600 ((0<<9)|(2<<6)) | |
551 | #define SOLO_BAUDRATE_38400 ((0<<9)|(3<<6)) | |
552 | #define SOLO_BAUDRATE_19200 ((0<<9)|(4<<6)) | |
553 | #define SOLO_BAUDRATE_9600 ((0<<9)|(5<<6)) | |
554 | #define SOLO_BAUDRATE_4800 ((0<<9)|(6<<6)) | |
555 | #define SOLO_BAUDRATE_2400 ((1<<9)|(6<<6)) | |
556 | #define SOLO_BAUDRATE_1200 ((2<<9)|(6<<6)) | |
557 | #define SOLO_BAUDRATE_300 ((3<<9)|(6<<6)) | |
558 | ||
559 | #define SOLO_UART_DATA_BIT_8 (3<<4) | |
560 | #define SOLO_UART_DATA_BIT_7 (2<<4) | |
561 | #define SOLO_UART_DATA_BIT_6 (1<<4) | |
562 | #define SOLO_UART_DATA_BIT_5 (0<<4) | |
563 | ||
564 | #define SOLO_UART_STOP_BIT_1 (0<<2) | |
565 | #define SOLO_UART_STOP_BIT_2 (1<<2) | |
566 | ||
567 | #define SOLO_UART_PARITY_NONE (0<<0) | |
568 | #define SOLO_UART_PARITY_EVEN (2<<0) | |
569 | #define SOLO_UART_PARITY_ODD (3<<0) | |
570 | ||
571 | #define SOLO_UART_STATUS(n) (0x0BA4 + ((n)*0x20)) | |
572 | #define SOLO_UART_CTS (1<<15) | |
573 | #define SOLO_UART_RX_BUSY (1<<14) | |
574 | #define SOLO_UART_OVERRUN (1<<13) | |
575 | #define SOLO_UART_FRAME_ERR (1<<12) | |
576 | #define SOLO_UART_PARITY_ERR (1<<11) | |
577 | #define SOLO_UART_TX_BUSY (1<<5) | |
578 | ||
579 | #define SOLO_UART_RX_BUFF_CNT(stat) (((stat)>>6) & 0x1f) | |
580 | #define SOLO_UART_RX_BUFF_SIZE 8 | |
581 | #define SOLO_UART_TX_BUFF_CNT(stat) (((stat)>>0) & 0x1f) | |
582 | #define SOLO_UART_TX_BUFF_SIZE 8 | |
583 | ||
584 | #define SOLO_UART_TX_DATA(n) (0x0BA8 + ((n)*0x20)) | |
585 | #define SOLO_UART_TX_DATA_PUSH (1<<8) | |
586 | #define SOLO_UART_RX_DATA(n) (0x0BAC + ((n)*0x20)) | |
587 | #define SOLO_UART_RX_DATA_POP (1<<8) | |
588 | ||
589 | #define SOLO_TIMER_CLOCK_NUM 0x0be0 | |
faa4fd2a BC |
590 | #define SOLO_TIMER_USEC 0x0be8 |
591 | #define SOLO_TIMER_SEC 0x0bec | |
dcae5dac | 592 | #define SOLO_TIMER_USEC_LSB 0x0d20 /* 6110 Only */ |
faa4fd2a BC |
593 | |
594 | #define SOLO_AUDIO_CONTROL 0x0D00 | |
595 | #define SOLO_AUDIO_ENABLE (1<<31) | |
596 | #define SOLO_AUDIO_MASTER_MODE (1<<30) | |
597 | #define SOLO_AUDIO_I2S_MODE (1<<29) | |
598 | #define SOLO_AUDIO_I2S_LR_SWAP (1<<27) | |
599 | #define SOLO_AUDIO_I2S_8BIT (1<<26) | |
600 | #define SOLO_AUDIO_I2S_MULTI(n) ((n)<<24) | |
601 | #define SOLO_AUDIO_MIX_9TO0 (1<<23) | |
602 | #define SOLO_AUDIO_DEC_9TO0_VOL(n) ((n)<<20) | |
603 | #define SOLO_AUDIO_MIX_19TO10 (1<<19) | |
604 | #define SOLO_AUDIO_DEC_19TO10_VOL(n) ((n)<<16) | |
605 | #define SOLO_AUDIO_MODE(n) ((n)<<0) | |
606 | #define SOLO_AUDIO_SAMPLE 0x0D04 | |
607 | #define SOLO_AUDIO_EE_MODE_ON (1<<30) | |
608 | #define SOLO_AUDIO_EE_ENC_CH(ch) ((ch)<<25) | |
609 | #define SOLO_AUDIO_BITRATE(n) ((n)<<16) | |
610 | #define SOLO_AUDIO_CLK_DIV(n) ((n)<<0) | |
611 | #define SOLO_AUDIO_FDMA_INTR 0x0D08 | |
612 | #define SOLO_AUDIO_FDMA_INTERVAL(n) ((n)<<19) | |
613 | #define SOLO_AUDIO_INTR_ORDER(n) ((n)<<16) | |
614 | #define SOLO_AUDIO_FDMA_BASE(n) ((n)<<0) | |
615 | #define SOLO_AUDIO_EVOL_0 0x0D0C | |
616 | #define SOLO_AUDIO_EVOL_1 0x0D10 | |
617 | #define SOLO_AUDIO_EVOL(ch, value) ((value)<<((ch)%10)) | |
618 | #define SOLO_AUDIO_STA 0x0D14 | |
619 | ||
dcae5dac HV |
620 | /* |
621 | * Watchdog configuration | |
622 | */ | |
623 | #define SOLO_WATCHDOG 0x0be4 | |
624 | #define SOLO_WATCHDOG_SET(status, sec) (status << 8 | (sec & 0xff)) | |
faa4fd2a | 625 | |
decebabf | 626 | #endif /* __SOLO6X10_REGISTERS_H */ |