[mirror_ubuntu-focal-kernel.git] / drivers / media / pci / solo6x10 / solo6x10.h

/*
 * Copyright (C) 2010-2013 Bluecherry, LLC <http://www.bluecherrydvr.com>
 *
 * Original author:
 * Ben Collins <bcollins@ubuntu.com>
 *
 * Additional work by:
 * John Brooks <john.brooks@bluecherry.net>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#ifndef __SOLO6X10_H
#define __SOLO6X10_H

#include <linux/pci.h>
#include <linux/i2c.h>
#include <linux/mutex.h>
#include <linux/list.h>
#include <linux/wait.h>
#include <linux/stringify.h>
#include <linux/io.h>
#include <linux/atomic.h>
#include <linux/slab.h>
#include <linux/videodev2.h>

#include <media/v4l2-dev.h>
#include <media/v4l2-device.h>
#include <media/v4l2-ctrls.h>
#include <media/videobuf2-v4l2.h>

#include "solo6x10-regs.h"

#ifndef PCI_VENDOR_ID_SOFTLOGIC
#define PCI_VENDOR_ID_SOFTLOGIC		0x9413
#define PCI_DEVICE_ID_SOLO6010		0x6010
#define PCI_DEVICE_ID_SOLO6110		0x6110
#endif

#ifndef PCI_VENDOR_ID_BLUECHERRY
#define PCI_VENDOR_ID_BLUECHERRY	0x1BB3
/* Neugent Softlogic 6010 based cards */
#define PCI_DEVICE_ID_NEUSOLO_4		0x4304
#define PCI_DEVICE_ID_NEUSOLO_9		0x4309
#define PCI_DEVICE_ID_NEUSOLO_16	0x4310
/* Bluecherry Softlogic 6010 based cards */
#define PCI_DEVICE_ID_BC_SOLO_4		0x4E04
#define PCI_DEVICE_ID_BC_SOLO_9		0x4E09
#define PCI_DEVICE_ID_BC_SOLO_16	0x4E10
/* Bluecherry Softlogic 6110 based cards */
#define PCI_DEVICE_ID_BC_6110_4		0x5304
#define PCI_DEVICE_ID_BC_6110_8		0x5308
#define PCI_DEVICE_ID_BC_6110_16	0x5310
#endif /* Bluecherry */

/* Used in pci_device_id, and solo_dev->type */
#define SOLO_DEV_6010			0
#define SOLO_DEV_6110			1

#define SOLO6X10_NAME			"solo6x10"

#define SOLO_MAX_CHANNELS		16

#define SOLO6X10_VERSION		"3.0.0"

/*
 * The SOLO6x10 actually has 8 i2c channels, but we only use 2.
 * 0 - Techwell chip(s)
 * 1 - SAA7128
 */
#define SOLO_I2C_ADAPTERS		2
#define SOLO_I2C_TW			0
#define SOLO_I2C_SAA			1

/* DMA Engine setup */
#define SOLO_NR_P2M			4
#define SOLO_NR_P2M_DESC		256
#define SOLO_P2M_DESC_SIZE		(SOLO_NR_P2M_DESC * 16)

/* Encoder standard modes */
#define SOLO_ENC_MODE_CIF		2
#define SOLO_ENC_MODE_HD1		1
#define SOLO_ENC_MODE_D1		9

#define SOLO_DEFAULT_QP			3

#define SOLO_CID_CUSTOM_BASE		(V4L2_CID_USER_BASE | 0xf000)
#define V4L2_CID_MOTION_TRACE		(SOLO_CID_CUSTOM_BASE+2)
#define V4L2_CID_OSD_TEXT		(SOLO_CID_CUSTOM_BASE+3)

/*
 * Motion thresholds are in a table of 64x64 samples, with
 * each sample representing 16x16 pixels of the source. In
 * effect, 44x30 samples are used for NTSC, and 44x36 for PAL.
 * The 5th sample on the 10th row is (10*64)+5 = 645.
 *
 * Internally it is stored as a 45x45 array (45*16 = 720, which is the
 * maximum PAL/NTSC width).
 */
#define SOLO_MOTION_SZ (45)

enum SOLO_I2C_STATE {
	IIC_STATE_IDLE,
	IIC_STATE_START,
	IIC_STATE_READ,
	IIC_STATE_WRITE,
	IIC_STATE_STOP
};

/* Defined in Table 4-16, Page 68-69 of the 6010 Datasheet */
struct solo_p2m_desc {
	u32	ctrl;
	u32	cfg;
	u32	dma_addr;
	u32	ext_addr;
};

struct solo_p2m_dev {
	struct mutex		mutex;
	struct completion	completion;
	int			desc_count;
	int			desc_idx;
	struct solo_p2m_desc	*descs;
	int			error;
};

#define OSD_TEXT_MAX		44

struct solo_vb2_buf {
	struct vb2_v4l2_buffer vb;
	struct list_head list;
};

enum solo_enc_types {
	SOLO_ENC_TYPE_STD,
	SOLO_ENC_TYPE_EXT,
};

struct solo_enc_dev {
	struct solo_dev	*solo_dev;
	/* V4L2 Items */
	struct v4l2_ctrl_handler hdl;
	struct v4l2_ctrl *md_thresholds;
	struct video_device	*vfd;
	/* General accounting */
	struct mutex		lock;
	spinlock_t		motion_lock;
	u8			ch;
	u8			mode, gop, qp, interlaced, interval;
	u8			bw_weight;
	u16			motion_thresh;
	bool			motion_global;
	bool			motion_enabled;
	u16			width;
	u16			height;

	/* OSD buffers */
	char			osd_text[OSD_TEXT_MAX + 1];
	u8			osd_buf[SOLO_EOSD_EXT_SIZE_MAX]
					__aligned(4);

	/* VOP stuff */
	u8			vop[64];
	int			vop_len;
	u8			jpeg_header[1024];
	int			jpeg_len;

	u32			fmt;
	enum solo_enc_types	type;
	u32			sequence;
	struct vb2_queue	vidq;
	struct list_head	vidq_active;
	void			*alloc_ctx;
	int			desc_count;
	int			desc_nelts;
	struct solo_p2m_desc	*desc_items;
	dma_addr_t		desc_dma;
	spinlock_t		av_lock;
};

/* The SOLO6x10 PCI Device */
struct solo_dev {
	/* General stuff */
	struct pci_dev		*pdev;
	int			type;
	unsigned int		time_sync;
	unsigned int		usec_lsb;
	unsigned int		clock_mhz;
	u8 __iomem		*reg_base;
	int			nr_chans;
	int			nr_ext;
	u32			irq_mask;
	u32			motion_mask;
	struct v4l2_device	v4l2_dev;

	/* tw28xx accounting */
	u8			tw2865, tw2864, tw2815;
	u8			tw28_cnt;

	/* i2c related items */
	struct i2c_adapter	i2c_adap[SOLO_I2C_ADAPTERS];
	enum SOLO_I2C_STATE	i2c_state;
	struct mutex		i2c_mutex;
	int			i2c_id;
	wait_queue_head_t	i2c_wait;
	struct i2c_msg		*i2c_msg;
	unsigned int		i2c_msg_num;
	unsigned int		i2c_msg_ptr;

	/* P2M DMA Engine */
	struct solo_p2m_dev	p2m_dev[SOLO_NR_P2M];
	atomic_t		p2m_count;
	int			p2m_jiffies;
	unsigned int		p2m_timeouts;

	/* V4L2 Display items */
	struct video_device	*vfd;
	unsigned int		erasing;
	unsigned int		frame_blank;
	u8			cur_disp_ch;
	wait_queue_head_t	disp_thread_wait;
	struct v4l2_ctrl_handler disp_hdl;

	/* V4L2 Encoder items */
	struct solo_enc_dev	*v4l2_enc[SOLO_MAX_CHANNELS];
	u16			enc_bw_remain;
	/* IDX into hw mp4 encoder */
	u8			enc_idx;

	/* Current video settings */
	u32			video_type;
	u16			video_hsize, video_vsize;
	u16			vout_hstart, vout_vstart;
	u16			vin_hstart, vin_vstart;
	u8			fps;

	/* JPEG Qp setting */
	spinlock_t      jpeg_qp_lock;
	u32		jpeg_qp[2];

	/* Audio components */
	struct snd_card		*snd_card;
	struct snd_pcm		*snd_pcm;
	atomic_t		snd_users;
	int			g723_hw_idx;

	/* sysfs stuffs */
	struct device		dev;
	int			sdram_size;
	struct bin_attribute	sdram_attr;
	unsigned int		sys_config;

	/* Ring thread */
	struct task_struct	*ring_thread;
	wait_queue_head_t	ring_thread_wait;

	/* VOP_HEADER handling */
	void                    *vh_buf;
	dma_addr_t		vh_dma;
	int			vh_size;

	/* Buffer handling */
	struct vb2_queue	vidq;
	struct vb2_alloc_ctx	*alloc_ctx;
	u32			sequence;
	struct task_struct      *kthread;
	struct mutex		lock;
	spinlock_t		slock;
	int			old_write;
	struct list_head	vidq_active;
};

static inline u32 solo_reg_read(struct solo_dev *solo_dev, int reg)
{
	return readl(solo_dev->reg_base + reg);
}

static inline void solo_reg_write(struct solo_dev *solo_dev, int reg,
				  u32 data)
{
	writel(data, solo_dev->reg_base + reg);
}

static inline void solo_irq_on(struct solo_dev *dev, u32 mask)
{
	dev->irq_mask |= mask;
	solo_reg_write(dev, SOLO_IRQ_MASK, dev->irq_mask);
}

static inline void solo_irq_off(struct solo_dev *dev, u32 mask)
{
	dev->irq_mask &= ~mask;
	solo_reg_write(dev, SOLO_IRQ_MASK, dev->irq_mask);
}

/* Init/exit routines for subsystems */
int solo_disp_init(struct solo_dev *solo_dev);
void solo_disp_exit(struct solo_dev *solo_dev);

int solo_gpio_init(struct solo_dev *solo_dev);
void solo_gpio_exit(struct solo_dev *solo_dev);

int solo_i2c_init(struct solo_dev *solo_dev);
void solo_i2c_exit(struct solo_dev *solo_dev);

int solo_p2m_init(struct solo_dev *solo_dev);
void solo_p2m_exit(struct solo_dev *solo_dev);

int solo_v4l2_init(struct solo_dev *solo_dev, unsigned nr);
void solo_v4l2_exit(struct solo_dev *solo_dev);

int solo_enc_init(struct solo_dev *solo_dev);
void solo_enc_exit(struct solo_dev *solo_dev);

int solo_enc_v4l2_init(struct solo_dev *solo_dev, unsigned nr);
void solo_enc_v4l2_exit(struct solo_dev *solo_dev);

int solo_g723_init(struct solo_dev *solo_dev);
void solo_g723_exit(struct solo_dev *solo_dev);

/* ISR's */
int solo_i2c_isr(struct solo_dev *solo_dev);
void solo_p2m_isr(struct solo_dev *solo_dev, int id);
void solo_p2m_error_isr(struct solo_dev *solo_dev);
void solo_enc_v4l2_isr(struct solo_dev *solo_dev);
void solo_g723_isr(struct solo_dev *solo_dev);
void solo_motion_isr(struct solo_dev *solo_dev);
void solo_video_in_isr(struct solo_dev *solo_dev);

/* i2c read/write */
u8 solo_i2c_readbyte(struct solo_dev *solo_dev, int id, u8 addr, u8 off);
void solo_i2c_writebyte(struct solo_dev *solo_dev, int id, u8 addr, u8 off,
			u8 data);

/* P2M DMA */
int solo_p2m_dma_t(struct solo_dev *solo_dev, int wr,
		   dma_addr_t dma_addr, u32 ext_addr, u32 size,
		   int repeat, u32 ext_size);
int solo_p2m_dma(struct solo_dev *solo_dev, int wr,
		 void *sys_addr, u32 ext_addr, u32 size,
		 int repeat, u32 ext_size);
void solo_p2m_fill_desc(struct solo_p2m_desc *desc, int wr,
			dma_addr_t dma_addr, u32 ext_addr, u32 size,
			int repeat, u32 ext_size);
int solo_p2m_dma_desc(struct solo_dev *solo_dev,
		      struct solo_p2m_desc *desc, dma_addr_t desc_dma,
		      int desc_cnt);

/* Global s_std ioctl */
int solo_set_video_type(struct solo_dev *solo_dev, bool is_50hz);
void solo_update_mode(struct solo_enc_dev *solo_enc);

/* Set the threshold for motion detection */
int solo_set_motion_threshold(struct solo_dev *solo_dev, u8 ch, u16 val);
int solo_set_motion_block(struct solo_dev *solo_dev, u8 ch,
		const u16 *thresholds);
#define SOLO_DEF_MOT_THRESH		0x0300

/* Write text on OSD */
int solo_osd_print(struct solo_enc_dev *solo_enc);

/* EEPROM commands */
unsigned int solo_eeprom_ewen(struct solo_dev *solo_dev, int w_en);
__be16 solo_eeprom_read(struct solo_dev *solo_dev, int loc);
int solo_eeprom_write(struct solo_dev *solo_dev, int loc,
		      __be16 data);

/* JPEG Qp functions */
void solo_s_jpeg_qp(struct solo_dev *solo_dev, unsigned int ch,
		    unsigned int qp);
int solo_g_jpeg_qp(struct solo_dev *solo_dev, unsigned int ch);

#define CHK_FLAGS(v, flags) (((v) & (flags)) == (flags))

#endif /* __SOLO6X10_H */
Commit	Line	Data
faa4fd2a	1	/*
dcae5dac HV	2	* Copyright (C) 2010-2013 Bluecherry, LLC <http://www.bluecherrydvr.com>
	3	*
	4	* Original author:
	5	* Ben Collins <bcollins@ubuntu.com>
	6	*
	7	* Additional work by:
	8	* John Brooks <john.brooks@bluecherry.net>
faa4fd2a BC	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License as published by
	12	* the Free Software Foundation; either version 2 of the License, or
	13	* (at your option) any later version.
	14	*
	15	* This program is distributed in the hope that it will be useful,
	16	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	18	* GNU General Public License for more details.
faa4fd2a BC	19	*/
faa4fd2a BC	20
decebabf KH	21	#ifndef __SOLO6X10_H
decebabf KH	22	#define __SOLO6X10_H
faa4fd2a	23
faa4fd2a BC	24	#include <linux/pci.h>
faa4fd2a BC	25	#include <linux/i2c.h>
faa4fd2a BC	26	#include <linux/mutex.h>
	27	#include <linux/list.h>
	28	#include <linux/wait.h>
dcae5dac HV	29	#include <linux/stringify.h>
dcae5dac HV	30	#include <linux/io.h>
60063497	31	#include <linux/atomic.h>
dcae5dac	32	#include <linux/slab.h>
faa4fd2a	33	#include <linux/videodev2.h>
dcae5dac	34
faa4fd2a	35	#include <media/v4l2-dev.h>
d9ebd623	36	#include <media/v4l2-device.h>
c813bd3c	37	#include <media/v4l2-ctrls.h>
c139990e	38	#include <media/videobuf2-v4l2.h>
dcae5dac	39
dad7fab9	40	#include "solo6x10-regs.h"
faa4fd2a BC	41
	42	#ifndef PCI_VENDOR_ID_SOFTLOGIC
	43	#define PCI_VENDOR_ID_SOFTLOGIC 0x9413
	44	#define PCI_DEVICE_ID_SOLO6010 0x6010
908113d8	45	#define PCI_DEVICE_ID_SOLO6110 0x6110
faa4fd2a BC	46	#endif
	47
	48	#ifndef PCI_VENDOR_ID_BLUECHERRY
	49	#define PCI_VENDOR_ID_BLUECHERRY 0x1BB3
	50	/* Neugent Softlogic 6010 based cards */
	51	#define PCI_DEVICE_ID_NEUSOLO_4 0x4304
	52	#define PCI_DEVICE_ID_NEUSOLO_9 0x4309
	53	#define PCI_DEVICE_ID_NEUSOLO_16 0x4310
f62de9be BC	54	/* Bluecherry Softlogic 6010 based cards */
	55	#define PCI_DEVICE_ID_BC_SOLO_4 0x4E04
	56	#define PCI_DEVICE_ID_BC_SOLO_9 0x4E09
	57	#define PCI_DEVICE_ID_BC_SOLO_16 0x4E10
	58	/* Bluecherry Softlogic 6110 based cards */
	59	#define PCI_DEVICE_ID_BC_6110_4 0x5304
	60	#define PCI_DEVICE_ID_BC_6110_8 0x5308
	61	#define PCI_DEVICE_ID_BC_6110_16 0x5310
faa4fd2a BC	62	#endif /* Bluecherry */
faa4fd2a BC	63
dcae5dac HV	64	/* Used in pci_device_id, and solo_dev->type */
	65	#define SOLO_DEV_6010 0
	66	#define SOLO_DEV_6110 1
	67
decebabf	68	#define SOLO6X10_NAME "solo6x10"
faa4fd2a BC	69
	70	#define SOLO_MAX_CHANNELS 16
	71
20c5f492	72	#define SOLO6X10_VERSION "3.0.0"
908113d8	73
faa4fd2a	74	/*
decebabf	75	* The SOLO6x10 actually has 8 i2c channels, but we only use 2.
faa4fd2a BC	76	* 0 - Techwell chip(s)
	77	* 1 - SAA7128
	78	*/
	79	#define SOLO_I2C_ADAPTERS 2
	80	#define SOLO_I2C_TW 0
	81	#define SOLO_I2C_SAA 1
	82
	83	/* DMA Engine setup */
	84	#define SOLO_NR_P2M 4
	85	#define SOLO_NR_P2M_DESC 256
dcae5dac	86	#define SOLO_P2M_DESC_SIZE (SOLO_NR_P2M_DESC * 16)
faa4fd2a BC	87
	88	/* Encoder standard modes */
	89	#define SOLO_ENC_MODE_CIF 2
	90	#define SOLO_ENC_MODE_HD1 1
	91	#define SOLO_ENC_MODE_D1 9
	92
faa4fd2a BC	93	#define SOLO_DEFAULT_QP 3
faa4fd2a BC	94
c813bd3c	95	#define SOLO_CID_CUSTOM_BASE (V4L2_CID_USER_BASE \| 0xf000)
c813bd3c HV	96	#define V4L2_CID_MOTION_TRACE (SOLO_CID_CUSTOM_BASE+2)
c813bd3c HV	97	#define V4L2_CID_OSD_TEXT (SOLO_CID_CUSTOM_BASE+3)
faa4fd2a	98
f5df0b7f HV	99	/*
	100	* Motion thresholds are in a table of 64x64 samples, with
	101	* each sample representing 16x16 pixels of the source. In
	102	* effect, 44x30 samples are used for NTSC, and 44x36 for PAL.
	103	* The 5th sample on the 10th row is (10*64)+5 = 645.
9e7664e0	104	*
4063a3c7 HV	105	* Internally it is stored as a 45x45 array (45*16 = 720, which is the
4063a3c7 HV	106	* maximum PAL/NTSC width).
f5df0b7f	107	*/
9e7664e0	108	#define SOLO_MOTION_SZ (45)
f5df0b7f	109
faa4fd2a BC	110	enum SOLO_I2C_STATE {
	111	IIC_STATE_IDLE,
	112	IIC_STATE_START,
	113	IIC_STATE_READ,
	114	IIC_STATE_WRITE,
	115	IIC_STATE_STOP
	116	};
	117
dcae5dac HV	118	/* Defined in Table 4-16, Page 68-69 of the 6010 Datasheet */
	119	struct solo_p2m_desc {
	120	u32 ctrl;
	121	u32 cfg;
	122	u32 dma_addr;
	123	u32 ext_addr;
f62de9be BC	124	};
f62de9be BC	125
faa4fd2a	126	struct solo_p2m_dev {
f62de9be	127	struct mutex mutex;
faa4fd2a	128	struct completion completion;
dcae5dac HV	129	int desc_count;
	130	int desc_idx;
	131	struct solo_p2m_desc *descs;
faa4fd2a	132	int error;
faa4fd2a BC	133	};
faa4fd2a BC	134
dcae5dac	135	#define OSD_TEXT_MAX 44
faa4fd2a	136
382c31a9	137	struct solo_vb2_buf {
2d700715	138	struct vb2_v4l2_buffer vb;
382c31a9 HV	139	struct list_head list;
	140	};
	141
a7eb931d HV	142	enum solo_enc_types {
	143	SOLO_ENC_TYPE_STD,
	144	SOLO_ENC_TYPE_EXT,
	145	};
	146
faa4fd2a	147	struct solo_enc_dev {
dcae5dac	148	struct solo_dev *solo_dev;
faa4fd2a	149	/* V4L2 Items */
c813bd3c	150	struct v4l2_ctrl_handler hdl;
4063a3c7	151	struct v4l2_ctrl *md_thresholds;
faa4fd2a BC	152	struct video_device *vfd;
faa4fd2a BC	153	/* General accounting */
382c31a9	154	struct mutex lock;
dcae5dac	155	spinlock_t motion_lock;
faa4fd2a BC	156	u8 ch;
faa4fd2a BC	157	u8 mode, gop, qp, interlaced, interval;
faa4fd2a	158	u8 bw_weight;
faa4fd2a	159	u16 motion_thresh;
f5df0b7f HV	160	bool motion_global;
f5df0b7f HV	161	bool motion_enabled;
faa4fd2a BC	162	u16 width;
faa4fd2a BC	163	u16 height;
dcae5dac HV	164
dcae5dac HV	165	/* OSD buffers */
faa4fd2a	166	char osd_text[OSD_TEXT_MAX + 1];
dcae5dac HV	167	u8 osd_buf[SOLO_EOSD_EXT_SIZE_MAX]
dcae5dac HV	168	__aligned(4);
faa4fd2a	169
dcae5dac	170	/* VOP stuff */
8a4d9a9c	171	u8 vop[64];
dcae5dac	172	int vop_len;
8a4d9a9c	173	u8 jpeg_header[1024];
dcae5dac HV	174	int jpeg_len;
dcae5dac HV	175
a7eb931d	176	u32 fmt;
a7eb931d	177	enum solo_enc_types type;
15513c12	178	u32 sequence;
382c31a9	179	struct vb2_queue vidq;
a7eb931d	180	struct list_head vidq_active;
0c3a14c1	181	void *alloc_ctx;
a7eb931d HV	182	int desc_count;
	183	int desc_nelts;
	184	struct solo_p2m_desc *desc_items;
	185	dma_addr_t desc_dma;
	186	spinlock_t av_lock;
faa4fd2a BC	187	};
faa4fd2a BC	188
decebabf KH	189	/* The SOLO6x10 PCI Device */
decebabf KH	190	struct solo_dev {
faa4fd2a BC	191	/* General stuff */
faa4fd2a BC	192	struct pci_dev *pdev;
dcae5dac HV	193	int type;
	194	unsigned int time_sync;
	195	unsigned int usec_lsb;
	196	unsigned int clock_mhz;
faa4fd2a BC	197	u8 __iomem *reg_base;
	198	int nr_chans;
	199	int nr_ext;
	200	u32 irq_mask;
	201	u32 motion_mask;
d9ebd623	202	struct v4l2_device v4l2_dev;
faa4fd2a BC	203
faa4fd2a BC	204	/* tw28xx accounting */
ee6351f5	205	u8 tw2865, tw2864, tw2815;
faa4fd2a BC	206	u8 tw28_cnt;
	207
	208	/* i2c related items */
	209	struct i2c_adapter i2c_adap[SOLO_I2C_ADAPTERS];
	210	enum SOLO_I2C_STATE i2c_state;
f62de9be	211	struct mutex i2c_mutex;
faa4fd2a BC	212	int i2c_id;
	213	wait_queue_head_t i2c_wait;
	214	struct i2c_msg *i2c_msg;
	215	unsigned int i2c_msg_num;
	216	unsigned int i2c_msg_ptr;
	217
	218	/* P2M DMA Engine */
	219	struct solo_p2m_dev p2m_dev[SOLO_NR_P2M];
dcae5dac HV	220	atomic_t p2m_count;
	221	int p2m_jiffies;
	222	unsigned int p2m_timeouts;
faa4fd2a BC	223
	224	/* V4L2 Display items */
	225	struct video_device *vfd;
	226	unsigned int erasing;
	227	unsigned int frame_blank;
	228	u8 cur_disp_ch;
	229	wait_queue_head_t disp_thread_wait;
c813bd3c	230	struct v4l2_ctrl_handler disp_hdl;
faa4fd2a BC	231
	232	/* V4L2 Encoder items */
	233	struct solo_enc_dev *v4l2_enc[SOLO_MAX_CHANNELS];
	234	u16 enc_bw_remain;
	235	/* IDX into hw mp4 encoder */
	236	u8 enc_idx;
faa4fd2a BC	237
faa4fd2a BC	238	/* Current video settings */
afabbe6d	239	u32 video_type;
faa4fd2a BC	240	u16 video_hsize, video_vsize;
	241	u16 vout_hstart, vout_vstart;
	242	u16 vin_hstart, vin_vstart;
	243	u8 fps;
	244
dcae5dac HV	245	/* JPEG Qp setting */
	246	spinlock_t jpeg_qp_lock;
	247	u32 jpeg_qp[2];
	248
faa4fd2a BC	249	/* Audio components */
	250	struct snd_card *snd_card;
	251	struct snd_pcm *snd_pcm;
	252	atomic_t snd_users;
	253	int g723_hw_idx;
dcae5dac HV	254
	255	/* sysfs stuffs */
	256	struct device dev;
	257	int sdram_size;
	258	struct bin_attribute sdram_attr;
	259	unsigned int sys_config;
	260
	261	/* Ring thread */
	262	struct task_struct *ring_thread;
	263	wait_queue_head_t ring_thread_wait;
dcae5dac HV	264
	265	/* VOP_HEADER handling */
	266	void *vh_buf;
	267	dma_addr_t vh_dma;
	268	int vh_size;
6a2e65d5 HV	269
6a2e65d5 HV	270	/* Buffer handling */
a4056c2f HV	271	struct vb2_queue vidq;
a4056c2f HV	272	struct vb2_alloc_ctx *alloc_ctx;
15513c12	273	u32 sequence;
6a2e65d5	274	struct task_struct *kthread;
a4056c2f	275	struct mutex lock;
6a2e65d5 HV	276	spinlock_t slock;
	277	int old_write;
	278	struct list_head vidq_active;
faa4fd2a BC	279	};
faa4fd2a BC	280
decebabf	281	static inline u32 solo_reg_read(struct solo_dev *solo_dev, int reg)
faa4fd2a	282	{
e1ceb25a	283	return readl(solo_dev->reg_base + reg);
faa4fd2a BC	284	}
faa4fd2a BC	285
dcae5dac HV	286	static inline void solo_reg_write(struct solo_dev *solo_dev, int reg,
dcae5dac HV	287	u32 data)
faa4fd2a	288	{
faa4fd2a	289	writel(data, solo_dev->reg_base + reg);
faa4fd2a BC	290	}
faa4fd2a BC	291
dcae5dac HV	292	static inline void solo_irq_on(struct solo_dev *dev, u32 mask)
	293	{
	294	dev->irq_mask \|= mask;
	295	solo_reg_write(dev, SOLO_IRQ_MASK, dev->irq_mask);
	296	}
	297
	298	static inline void solo_irq_off(struct solo_dev *dev, u32 mask)
	299	{
	300	dev->irq_mask &= ~mask;
	301	solo_reg_write(dev, SOLO_IRQ_MASK, dev->irq_mask);
	302	}
faa4fd2a	303
4c211ed7	304	/* Init/exit routines for subsystems */
decebabf KH	305	int solo_disp_init(struct solo_dev *solo_dev);
decebabf KH	306	void solo_disp_exit(struct solo_dev *solo_dev);
faa4fd2a	307
decebabf KH	308	int solo_gpio_init(struct solo_dev *solo_dev);
decebabf KH	309	void solo_gpio_exit(struct solo_dev *solo_dev);
faa4fd2a	310
decebabf KH	311	int solo_i2c_init(struct solo_dev *solo_dev);
decebabf KH	312	void solo_i2c_exit(struct solo_dev *solo_dev);
faa4fd2a	313
decebabf KH	314	int solo_p2m_init(struct solo_dev *solo_dev);
decebabf KH	315	void solo_p2m_exit(struct solo_dev *solo_dev);
faa4fd2a	316
dcae5dac	317	int solo_v4l2_init(struct solo_dev *solo_dev, unsigned nr);
decebabf	318	void solo_v4l2_exit(struct solo_dev *solo_dev);
faa4fd2a	319
decebabf KH	320	int solo_enc_init(struct solo_dev *solo_dev);
decebabf KH	321	void solo_enc_exit(struct solo_dev *solo_dev);
faa4fd2a	322
dcae5dac	323	int solo_enc_v4l2_init(struct solo_dev *solo_dev, unsigned nr);
decebabf	324	void solo_enc_v4l2_exit(struct solo_dev *solo_dev);
faa4fd2a	325
decebabf KH	326	int solo_g723_init(struct solo_dev *solo_dev);
decebabf KH	327	void solo_g723_exit(struct solo_dev *solo_dev);
faa4fd2a BC	328
faa4fd2a BC	329	/* ISR's */
decebabf KH	330	int solo_i2c_isr(struct solo_dev *solo_dev);
decebabf KH	331	void solo_p2m_isr(struct solo_dev *solo_dev, int id);
dcae5dac	332	void solo_p2m_error_isr(struct solo_dev *solo_dev);
decebabf KH	333	void solo_enc_v4l2_isr(struct solo_dev *solo_dev);
	334	void solo_g723_isr(struct solo_dev *solo_dev);
	335	void solo_motion_isr(struct solo_dev *solo_dev);
	336	void solo_video_in_isr(struct solo_dev *solo_dev);
faa4fd2a BC	337
faa4fd2a BC	338	/* i2c read/write */
decebabf KH	339	u8 solo_i2c_readbyte(struct solo_dev *solo_dev, int id, u8 addr, u8 off);
decebabf KH	340	void solo_i2c_writebyte(struct solo_dev *solo_dev, int id, u8 addr, u8 off,
faa4fd2a BC	341	u8 data);
	342
	343	/* P2M DMA */
dcae5dac HV	344	int solo_p2m_dma_t(struct solo_dev *solo_dev, int wr,
	345	dma_addr_t dma_addr, u32 ext_addr, u32 size,
	346	int repeat, u32 ext_size);
	347	int solo_p2m_dma(struct solo_dev *solo_dev, int wr,
	348	void *sys_addr, u32 ext_addr, u32 size,
	349	int repeat, u32 ext_size);
	350	void solo_p2m_fill_desc(struct solo_p2m_desc *desc, int wr,
	351	dma_addr_t dma_addr, u32 ext_addr, u32 size,
	352	int repeat, u32 ext_size);
	353	int solo_p2m_dma_desc(struct solo_dev *solo_dev,
	354	struct solo_p2m_desc *desc, dma_addr_t desc_dma,
	355	int desc_cnt);
faa4fd2a	356
4c211ed7	357	/* Global s_std ioctl */
429df502	358	int solo_set_video_type(struct solo_dev *solo_dev, bool is_50hz);
4c211ed7 HV	359	void solo_update_mode(struct solo_enc_dev *solo_enc);
4c211ed7 HV	360
faa4fd2a	361	/* Set the threshold for motion detection */
dcae5dac	362	int solo_set_motion_threshold(struct solo_dev *solo_dev, u8 ch, u16 val);
f5df0b7f	363	int solo_set_motion_block(struct solo_dev *solo_dev, u8 ch,
4063a3c7	364	const u16 *thresholds);
faa4fd2a BC	365	#define SOLO_DEF_MOT_THRESH 0x0300
	366
	367	/* Write text on OSD */
	368	int solo_osd_print(struct solo_enc_dev *solo_enc);
	369
dcae5dac HV	370	/* EEPROM commands */
dcae5dac HV	371	unsigned int solo_eeprom_ewen(struct solo_dev *solo_dev, int w_en);
c44b6484	372	__be16 solo_eeprom_read(struct solo_dev *solo_dev, int loc);
dcae5dac	373	int solo_eeprom_write(struct solo_dev *solo_dev, int loc,
c44b6484	374	__be16 data);
dcae5dac HV	375
	376	/* JPEG Qp functions */
	377	void solo_s_jpeg_qp(struct solo_dev *solo_dev, unsigned int ch,
	378	unsigned int qp);
	379	int solo_g_jpeg_qp(struct solo_dev *solo_dev, unsigned int ch);
	380
	381	#define CHK_FLAGS(v, flags) (((v) & (flags)) == (flags))
	382
decebabf	383	#endif /* __SOLO6X10_H */