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5740f4e7 HV |
1 | /* |
2 | * tw68_risc.c | |
3 | * Part of the device driver for Techwell 68xx based cards | |
4 | * | |
5 | * Much of this code is derived from the cx88 and sa7134 drivers, which | |
6 | * were in turn derived from the bt87x driver. The original work was by | |
7 | * Gerd Knorr; more recently the code was enhanced by Mauro Carvalho Chehab, | |
8 | * Hans Verkuil, Andy Walls and many others. Their work is gratefully | |
9 | * acknowledged. Full credit goes to them - any problems within this code | |
10 | * are mine. | |
11 | * | |
e15d1c12 HV |
12 | * Copyright (C) 2009 William M. Brack |
13 | * | |
14 | * Refactored and updated to the latest v4l core frameworks: | |
15 | * | |
16 | * Copyright (C) 2014 Hans Verkuil <hverkuil@xs4all.nl> | |
5740f4e7 HV |
17 | * |
18 | * This program is free software; you can redistribute it and/or modify | |
19 | * it under the terms of the GNU General Public License as published by | |
20 | * the Free Software Foundation; either version 2 of the License, or | |
21 | * (at your option) any later version. | |
22 | * | |
23 | * This program is distributed in the hope that it will be useful, | |
24 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
25 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
26 | * GNU General Public License for more details. | |
5740f4e7 HV |
27 | */ |
28 | ||
29 | #include "tw68.h" | |
30 | ||
5740f4e7 | 31 | /** |
ef69f8d2 MCC |
32 | * tw68_risc_field |
33 | * @rp: pointer to current risc program position | |
34 | * @sglist: pointer to "scatter-gather list" of buffer pointers | |
35 | * @offset: offset to target memory buffer | |
36 | * @sync_line: 0 -> no sync, 1 -> odd sync, 2 -> even sync | |
37 | * @bpl: number of bytes per scan line | |
38 | * @padding: number of bytes of padding to add | |
39 | * @lines: number of lines in field | |
40 | * @jump: insert a jump at the start | |
5740f4e7 HV |
41 | */ |
42 | static __le32 *tw68_risc_field(__le32 *rp, struct scatterlist *sglist, | |
43 | unsigned int offset, u32 sync_line, | |
44 | unsigned int bpl, unsigned int padding, | |
e15d1c12 | 45 | unsigned int lines, bool jump) |
5740f4e7 HV |
46 | { |
47 | struct scatterlist *sg; | |
48 | unsigned int line, todo, done; | |
49 | ||
e15d1c12 HV |
50 | if (jump) { |
51 | *(rp++) = cpu_to_le32(RISC_JUMP); | |
5740f4e7 HV |
52 | *(rp++) = 0; |
53 | } | |
e15d1c12 HV |
54 | |
55 | /* sync instruction */ | |
56 | if (sync_line == 1) | |
57 | *(rp++) = cpu_to_le32(RISC_SYNCO); | |
58 | else | |
59 | *(rp++) = cpu_to_le32(RISC_SYNCE); | |
60 | *(rp++) = 0; | |
61 | ||
5740f4e7 HV |
62 | /* scan lines */ |
63 | sg = sglist; | |
64 | for (line = 0; line < lines; line++) { | |
65 | /* calculate next starting position */ | |
66 | while (offset && offset >= sg_dma_len(sg)) { | |
67 | offset -= sg_dma_len(sg); | |
e15d1c12 | 68 | sg = sg_next(sg); |
5740f4e7 HV |
69 | } |
70 | if (bpl <= sg_dma_len(sg) - offset) { | |
71 | /* fits into current chunk */ | |
72 | *(rp++) = cpu_to_le32(RISC_LINESTART | | |
73 | /* (offset<<12) |*/ bpl); | |
74 | *(rp++) = cpu_to_le32(sg_dma_address(sg) + offset); | |
75 | offset += bpl; | |
76 | } else { | |
77 | /* | |
78 | * scanline needs to be split. Put the start in | |
79 | * whatever memory remains using RISC_LINESTART, | |
80 | * then the remainder into following addresses | |
81 | * given by the scatter-gather list. | |
82 | */ | |
83 | todo = bpl; /* one full line to be done */ | |
84 | /* first fragment */ | |
85 | done = (sg_dma_len(sg) - offset); | |
86 | *(rp++) = cpu_to_le32(RISC_LINESTART | | |
87 | (7 << 24) | | |
88 | done); | |
89 | *(rp++) = cpu_to_le32(sg_dma_address(sg) + offset); | |
90 | todo -= done; | |
e15d1c12 | 91 | sg = sg_next(sg); |
5740f4e7 HV |
92 | /* succeeding fragments have no offset */ |
93 | while (todo > sg_dma_len(sg)) { | |
94 | *(rp++) = cpu_to_le32(RISC_INLINE | | |
95 | (done << 12) | | |
96 | sg_dma_len(sg)); | |
97 | *(rp++) = cpu_to_le32(sg_dma_address(sg)); | |
98 | todo -= sg_dma_len(sg); | |
e15d1c12 | 99 | sg = sg_next(sg); |
5740f4e7 HV |
100 | done += sg_dma_len(sg); |
101 | } | |
102 | if (todo) { | |
103 | /* final chunk - offset 0, count 'todo' */ | |
104 | *(rp++) = cpu_to_le32(RISC_INLINE | | |
105 | (done << 12) | | |
106 | todo); | |
107 | *(rp++) = cpu_to_le32(sg_dma_address(sg)); | |
108 | } | |
109 | offset = todo; | |
110 | } | |
111 | offset += padding; | |
5740f4e7 HV |
112 | } |
113 | ||
114 | return rp; | |
115 | } | |
116 | ||
117 | /** | |
118 | * tw68_risc_buffer | |
119 | * | |
e15d1c12 HV |
120 | * This routine is called by tw68-video. It allocates |
121 | * memory for the dma controller "program" and then fills in that | |
122 | * memory with the appropriate "instructions". | |
5740f4e7 | 123 | * |
ef69f8d2 | 124 | * @pci: structure with info about the pci |
e15d1c12 | 125 | * slot which our device is in. |
ef69f8d2 | 126 | * @buf: structure with info about the memory |
e15d1c12 | 127 | * used for our controller program. |
ef69f8d2 MCC |
128 | * @sglist: scatter-gather list entry |
129 | * @top_offset: offset within the risc program area for the | |
e15d1c12 | 130 | * first odd frame line |
ef69f8d2 | 131 | * @bottom_offset: offset within the risc program area for the |
e15d1c12 | 132 | * first even frame line |
ef69f8d2 MCC |
133 | * @bpl: number of data bytes per scan line |
134 | * @padding: number of extra bytes to add at end of line | |
135 | * @lines: number of scan lines | |
5740f4e7 HV |
136 | */ |
137 | int tw68_risc_buffer(struct pci_dev *pci, | |
e15d1c12 | 138 | struct tw68_buf *buf, |
5740f4e7 HV |
139 | struct scatterlist *sglist, |
140 | unsigned int top_offset, | |
141 | unsigned int bottom_offset, | |
142 | unsigned int bpl, | |
143 | unsigned int padding, | |
144 | unsigned int lines) | |
145 | { | |
146 | u32 instructions, fields; | |
147 | __le32 *rp; | |
5740f4e7 HV |
148 | |
149 | fields = 0; | |
150 | if (UNSET != top_offset) | |
151 | fields++; | |
152 | if (UNSET != bottom_offset) | |
153 | fields++; | |
154 | /* | |
155 | * estimate risc mem: worst case is one write per page border + | |
e15d1c12 | 156 | * one write per scan line + syncs + 2 jumps (all 2 dwords). |
5740f4e7 HV |
157 | * Padding can cause next bpl to start close to a page border. |
158 | * First DMA region may be smaller than PAGE_SIZE | |
159 | */ | |
160 | instructions = fields * (1 + (((bpl + padding) * lines) / | |
e15d1c12 HV |
161 | PAGE_SIZE) + lines) + 4; |
162 | buf->size = instructions * 8; | |
163 | buf->cpu = pci_alloc_consistent(pci, buf->size, &buf->dma); | |
164 | if (buf->cpu == NULL) | |
165 | return -ENOMEM; | |
5740f4e7 HV |
166 | |
167 | /* write risc instructions */ | |
e15d1c12 | 168 | rp = buf->cpu; |
5740f4e7 HV |
169 | if (UNSET != top_offset) /* generates SYNCO */ |
170 | rp = tw68_risc_field(rp, sglist, top_offset, 1, | |
e15d1c12 | 171 | bpl, padding, lines, true); |
5740f4e7 HV |
172 | if (UNSET != bottom_offset) /* generates SYNCE */ |
173 | rp = tw68_risc_field(rp, sglist, bottom_offset, 2, | |
e15d1c12 | 174 | bpl, padding, lines, top_offset == UNSET); |
5740f4e7 HV |
175 | |
176 | /* save pointer to jmp instruction address */ | |
e15d1c12 HV |
177 | buf->jmp = rp; |
178 | buf->cpu[1] = cpu_to_le32(buf->dma + 8); | |
5740f4e7 | 179 | /* assure risc buffer hasn't overflowed */ |
e15d1c12 | 180 | BUG_ON((buf->jmp - buf->cpu + 2) * sizeof(buf->cpu[0]) > buf->size); |
5740f4e7 HV |
181 | return 0; |
182 | } | |
183 | ||
184 | #if 0 | |
185 | /* ------------------------------------------------------------------ */ | |
186 | /* debug helper code */ | |
187 | ||
188 | static void tw68_risc_decode(u32 risc, u32 addr) | |
189 | { | |
190 | #define RISC_OP(reg) (((reg) >> 28) & 7) | |
191 | static struct instr_details { | |
192 | char *name; | |
193 | u8 has_data_type; | |
194 | u8 has_byte_info; | |
195 | u8 has_addr; | |
196 | } instr[8] = { | |
197 | [RISC_OP(RISC_SYNCO)] = {"syncOdd", 0, 0, 0}, | |
198 | [RISC_OP(RISC_SYNCE)] = {"syncEven", 0, 0, 0}, | |
199 | [RISC_OP(RISC_JUMP)] = {"jump", 0, 0, 1}, | |
200 | [RISC_OP(RISC_LINESTART)] = {"lineStart", 1, 1, 1}, | |
201 | [RISC_OP(RISC_INLINE)] = {"inline", 1, 1, 1}, | |
202 | }; | |
203 | u32 p; | |
204 | ||
205 | p = RISC_OP(risc); | |
206 | if (!(risc & 0x80000000) || !instr[p].name) { | |
e15d1c12 | 207 | pr_debug("0x%08x [ INVALID ]\n", risc); |
5740f4e7 HV |
208 | return; |
209 | } | |
e15d1c12 | 210 | pr_debug("0x%08x %-9s IRQ=%d", |
5740f4e7 HV |
211 | risc, instr[p].name, (risc >> 27) & 1); |
212 | if (instr[p].has_data_type) | |
e15d1c12 | 213 | pr_debug(" Type=%d", (risc >> 24) & 7); |
5740f4e7 | 214 | if (instr[p].has_byte_info) |
e15d1c12 | 215 | pr_debug(" Start=0x%03x Count=%03u", |
5740f4e7 HV |
216 | (risc >> 12) & 0xfff, risc & 0xfff); |
217 | if (instr[p].has_addr) | |
e15d1c12 HV |
218 | pr_debug(" StartAddr=0x%08x", addr); |
219 | pr_debug("\n"); | |
5740f4e7 HV |
220 | } |
221 | ||
e15d1c12 | 222 | void tw68_risc_program_dump(struct tw68_core *core, struct tw68_buf *buf) |
5740f4e7 | 223 | { |
e15d1c12 | 224 | const __le32 *addr; |
5740f4e7 | 225 | |
e15d1c12 HV |
226 | pr_debug("%s: risc_program_dump: risc=%p, buf->cpu=0x%p, buf->jmp=0x%p\n", |
227 | core->name, buf, buf->cpu, buf->jmp); | |
228 | for (addr = buf->cpu; addr <= buf->jmp; addr += 2) | |
5740f4e7 HV |
229 | tw68_risc_decode(*addr, *(addr+1)); |
230 | } | |
5740f4e7 | 231 | #endif |