projects / mirror_ubuntu-artful-kernel.git / blame
| Commit | Line | Data |
|---|---|---|
| 1da177e4 LT |
1 | /* |
| 2 | * Zoran ZR36050 basic configuration functions - header file | |
| 3 | * | |
| 4 | * Copyright (C) 2001 Wolfgang Scherr <scherr@net4you.at> | |
| 5 | * | |
| 6 | * $Id: zr36050.h,v 1.1.2.2 2003/01/14 21:18:22 rbultje Exp $ | |
| 7 | * | |
| 8 | * ------------------------------------------------------------------------ | |
| 9 | * | |
| 10 | * This program is free software; you can redistribute it and/or modify | |
| 11 | * it under the terms of the GNU General Public License as published by | |
| 12 | * the Free Software Foundation; either version 2 of the License, or | |
| 13 | * (at your option) any later version. | |
| 14 | * | |
| 15 | * This program is distributed in the hope that it will be useful, | |
| 16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 18 | * GNU General Public License for more details. | |
| 19 | * | |
| 1da177e4 LT |
20 | * ------------------------------------------------------------------------ |
| 21 | */ | |
| 22 | ||
| 23 | #ifndef ZR36050_H | |
| 24 | #define ZR36050_H | |
| 25 | ||
| 26 | #include "videocodec.h" | |
| 27 | ||
| 28 | /* data stored for each zoran jpeg codec chip */ | |
| 29 | struct zr36050 { | |
| 30 | char name[32]; | |
| 31 | int num; | |
| 32 | /* io datastructure */ | |
| 33 | struct videocodec *codec; | |
| 34 | // last coder status | |
| 35 | __u8 status1; | |
| 36 | // actual coder setup | |
| 37 | int mode; | |
| 38 | ||
| 39 | __u16 width; | |
| 40 | __u16 height; | |
| 41 | ||
| 42 | __u16 bitrate_ctrl; | |
| 43 | ||
| 44 | __u32 total_code_vol; | |
| 45 | __u32 real_code_vol; | |
| 46 | __u16 max_block_vol; | |
| 47 | ||
| 48 | __u8 h_samp_ratio[8]; | |
| 49 | __u8 v_samp_ratio[8]; | |
| 50 | __u16 scalefact; | |
| 51 | __u16 dri; | |
| 52 | ||
| 53 | /* com/app marker */ | |
| 54 | struct jpeg_com_marker com; | |
| 55 | struct jpeg_app_marker app; | |
| 56 | }; | |
| 57 | ||
| 58 | /* zr36050 register addresses */ | |
| 59 | #define ZR050_GO 0x000 | |
| 60 | #define ZR050_HARDWARE 0x002 | |
| 61 | #define ZR050_MODE 0x003 | |
| 62 | #define ZR050_OPTIONS 0x004 | |
| 63 | #define ZR050_MBCV 0x005 | |
| 64 | #define ZR050_MARKERS_EN 0x006 | |
| 65 | #define ZR050_INT_REQ_0 0x007 | |
| 66 | #define ZR050_INT_REQ_1 0x008 | |
| 67 | #define ZR050_TCV_NET_HI 0x009 | |
| 68 | #define ZR050_TCV_NET_MH 0x00a | |
| 69 | #define ZR050_TCV_NET_ML 0x00b | |
| 70 | #define ZR050_TCV_NET_LO 0x00c | |
| 71 | #define ZR050_TCV_DATA_HI 0x00d | |
| 72 | #define ZR050_TCV_DATA_MH 0x00e | |
| 73 | #define ZR050_TCV_DATA_ML 0x00f | |
| 74 | #define ZR050_TCV_DATA_LO 0x010 | |
| 75 | #define ZR050_SF_HI 0x011 | |
| 76 | #define ZR050_SF_LO 0x012 | |
| 77 | #define ZR050_AF_HI 0x013 | |
| 78 | #define ZR050_AF_M 0x014 | |
| 79 | #define ZR050_AF_LO 0x015 | |
| 80 | #define ZR050_ACV_HI 0x016 | |
| 81 | #define ZR050_ACV_MH 0x017 | |
| 82 | #define ZR050_ACV_ML 0x018 | |
| 83 | #define ZR050_ACV_LO 0x019 | |
| 84 | #define ZR050_ACT_HI 0x01a | |
| 85 | #define ZR050_ACT_MH 0x01b | |
| 86 | #define ZR050_ACT_ML 0x01c | |
| 87 | #define ZR050_ACT_LO 0x01d | |
| 88 | #define ZR050_ACV_TRUN_HI 0x01e | |
| 89 | #define ZR050_ACV_TRUN_MH 0x01f | |
| 90 | #define ZR050_ACV_TRUN_ML 0x020 | |
| 91 | #define ZR050_ACV_TRUN_LO 0x021 | |
| 92 | #define ZR050_STATUS_0 0x02e | |
| 93 | #define ZR050_STATUS_1 0x02f | |
| 94 | ||
| 95 | #define ZR050_SOF_IDX 0x040 | |
| 96 | #define ZR050_SOS1_IDX 0x07a | |
| 97 | #define ZR050_SOS2_IDX 0x08a | |
| 98 | #define ZR050_SOS3_IDX 0x09a | |
| 99 | #define ZR050_SOS4_IDX 0x0aa | |
| 100 | #define ZR050_DRI_IDX 0x0c0 | |
| 101 | #define ZR050_DNL_IDX 0x0c6 | |
| 102 | #define ZR050_DQT_IDX 0x0cc | |
| 103 | #define ZR050_DHT_IDX 0x1d4 | |
| 104 | #define ZR050_APP_IDX 0x380 | |
| 105 | #define ZR050_COM_IDX 0x3c0 | |
| 106 | ||
| 107 | /* zr36050 hardware register bits */ | |
| 108 | ||
| 109 | #define ZR050_HW_BSWD 0x80 | |
| 110 | #define ZR050_HW_MSTR 0x40 | |
| 111 | #define ZR050_HW_DMA 0x20 | |
| 112 | #define ZR050_HW_CFIS_1_CLK 0x00 | |
| 113 | #define ZR050_HW_CFIS_2_CLK 0x04 | |
| 114 | #define ZR050_HW_CFIS_3_CLK 0x08 | |
| 115 | #define ZR050_HW_CFIS_4_CLK 0x0C | |
| 116 | #define ZR050_HW_CFIS_5_CLK 0x10 | |
| 117 | #define ZR050_HW_CFIS_6_CLK 0x14 | |
| 118 | #define ZR050_HW_CFIS_7_CLK 0x18 | |
| 119 | #define ZR050_HW_CFIS_8_CLK 0x1C | |
| 120 | #define ZR050_HW_BELE 0x01 | |
| 121 | ||
| 122 | /* zr36050 mode register bits */ | |
| 123 | ||
| 1da177e4 LT |
124 | #define ZR050_MO_COMP 0x80 |
| 125 | #define ZR050_MO_ATP 0x40 | |
| 126 | #define ZR050_MO_PASS2 0x20 | |
| 127 | #define ZR050_MO_TLM 0x10 | |
| 128 | #define ZR050_MO_DCONLY 0x08 | |
| 129 | #define ZR050_MO_BRC 0x04 | |
| 130 | ||
| 131 | #define ZR050_MO_ATP 0x40 | |
| 132 | #define ZR050_MO_PASS2 0x20 | |
| 133 | #define ZR050_MO_TLM 0x10 | |
| 134 | #define ZR050_MO_DCONLY 0x08 | |
| 135 | ||
| 136 | /* zr36050 option register bits */ | |
| 137 | ||
| 138 | #define ZR050_OP_NSCN_1 0x00 | |
| 139 | #define ZR050_OP_NSCN_2 0x20 | |
| 140 | #define ZR050_OP_NSCN_3 0x40 | |
| 141 | #define ZR050_OP_NSCN_4 0x60 | |
| 142 | #define ZR050_OP_NSCN_5 0x80 | |
| 143 | #define ZR050_OP_NSCN_6 0xA0 | |
| 144 | #define ZR050_OP_NSCN_7 0xC0 | |
| 145 | #define ZR050_OP_NSCN_8 0xE0 | |
| 146 | #define ZR050_OP_OVF 0x10 | |
| 147 | ||
| 148 | ||
| 149 | /* zr36050 markers-enable register bits */ | |
| 150 | ||
| 151 | #define ZR050_ME_APP 0x80 | |
| 152 | #define ZR050_ME_COM 0x40 | |
| 153 | #define ZR050_ME_DRI 0x20 | |
| 154 | #define ZR050_ME_DQT 0x10 | |
| 155 | #define ZR050_ME_DHT 0x08 | |
| 156 | #define ZR050_ME_DNL 0x04 | |
| 157 | #define ZR050_ME_DQTI 0x02 | |
| 158 | #define ZR050_ME_DHTI 0x01 | |
| 159 | ||
| 160 | /* zr36050 status0/1 register bit masks */ | |
| 161 | ||
| 162 | #define ZR050_ST_RST_MASK 0x20 | |
| 163 | #define ZR050_ST_SOF_MASK 0x02 | |
| 164 | #define ZR050_ST_SOS_MASK 0x02 | |
| 165 | #define ZR050_ST_DATRDY_MASK 0x80 | |
| 166 | #define ZR050_ST_MRKDET_MASK 0x40 | |
| 167 | #define ZR050_ST_RFM_MASK 0x10 | |
| 168 | #define ZR050_ST_RFD_MASK 0x08 | |
| 169 | #define ZR050_ST_END_MASK 0x04 | |
| 170 | #define ZR050_ST_TCVOVF_MASK 0x02 | |
| 171 | #define ZR050_ST_DATOVF_MASK 0x01 | |
| 172 | ||
| 173 | /* pixel component idx */ | |
| 174 | ||
| 175 | #define ZR050_Y_COMPONENT 0 | |
| 176 | #define ZR050_U_COMPONENT 1 | |
| 177 | #define ZR050_V_COMPONENT 2 | |
| 178 | ||
| 179 | #endif /*fndef ZR36050_H */ |