[mirror_ubuntu-artful-kernel.git] / drivers / media / platform / atmel / atmel-isc-regs.h

#ifndef __ATMEL_ISC_REGS_H
#define __ATMEL_ISC_REGS_H

#include <linux/bitops.h>

/* ISC Control Enable Register 0 */
#define ISC_CTRLEN      0x00000000

/* ISC Control Disable Register 0 */
#define ISC_CTRLDIS     0x00000004

/* ISC Control Status Register 0 */
#define ISC_CTRLSR      0x00000008

#define ISC_CTRL_CAPTURE	BIT(0)
#define ISC_CTRL_UPPRO		BIT(1)
#define ISC_CTRL_HISREQ		BIT(2)
#define ISC_CTRL_HISCLR		BIT(3)

/* ISC Parallel Front End Configuration 0 Register */
#define ISC_PFE_CFG0    0x0000000c

#define ISC_PFE_CFG0_HPOL_LOW   BIT(0)
#define ISC_PFE_CFG0_VPOL_LOW   BIT(1)
#define ISC_PFE_CFG0_PPOL_LOW   BIT(2)

#define ISC_PFE_CFG0_MODE_PROGRESSIVE   (0x0 << 4)
#define ISC_PFE_CFG0_MODE_MASK          GENMASK(6, 4)

#define ISC_PFE_CFG0_BPS_EIGHT  (0x4 << 28)
#define ISC_PFG_CFG0_BPS_NINE   (0x3 << 28)
#define ISC_PFG_CFG0_BPS_TEN    (0x2 << 28)
#define ISC_PFG_CFG0_BPS_ELEVEN (0x1 << 28)
#define ISC_PFG_CFG0_BPS_TWELVE (0x0 << 28)
#define ISC_PFE_CFG0_BPS_MASK   GENMASK(30, 28)

/* ISC Clock Enable Register */
#define ISC_CLKEN               0x00000018

/* ISC Clock Disable Register */
#define ISC_CLKDIS              0x0000001c

/* ISC Clock Status Register */
#define ISC_CLKSR               0x00000020

#define ISC_CLK(n)		BIT(n)

/* ISC Clock Configuration Register */
#define ISC_CLKCFG              0x00000024
#define ISC_CLKCFG_DIV_SHIFT(n) ((n)*16)
#define ISC_CLKCFG_DIV_MASK(n)  GENMASK(((n)*16 + 7), (n)*16)
#define ISC_CLKCFG_SEL_SHIFT(n) ((n)*16 + 8)
#define ISC_CLKCFG_SEL_MASK(n)  GENMASK(((n)*17 + 8), ((n)*16 + 8))

/* ISC Interrupt Enable Register */
#define ISC_INTEN       0x00000028

/* ISC Interrupt Disable Register */
#define ISC_INTDIS      0x0000002c

/* ISC Interrupt Mask Register */
#define ISC_INTMASK     0x00000030

/* ISC Interrupt Status Register */
#define ISC_INTSR       0x00000034

#define ISC_INT_DDONE		BIT(8)
#define ISC_INT_HISDONE		BIT(12)

/* ISC White Balance Control Register */
#define ISC_WB_CTRL     0x00000058

/* ISC White Balance Configuration Register */
#define ISC_WB_CFG      0x0000005c

/* ISC White Balance Offset for R, GR Register */
#define ISC_WB_O_RGR	0x00000060

/* ISC White Balance Offset for B, GB Register */
#define ISC_WB_O_BGR	0x00000064

/* ISC White Balance Gain for R, GR Register */
#define ISC_WB_G_RGR	0x00000068

/* ISC White Balance Gain for B, GB Register */
#define ISC_WB_G_BGR	0x0000006c

/* ISC Color Filter Array Control Register */
#define ISC_CFA_CTRL    0x00000070

/* ISC Color Filter Array Configuration Register */
#define ISC_CFA_CFG     0x00000074
#define ISC_CFA_CFG_EITPOL	BIT(4)

#define ISC_BAY_CFG_GRGR	0x0
#define ISC_BAY_CFG_RGRG	0x1
#define ISC_BAY_CFG_GBGB	0x2
#define ISC_BAY_CFG_BGBG	0x3

/* ISC Color Correction Control Register */
#define ISC_CC_CTRL     0x00000078

/* ISC Color Correction RR RG Register */
#define ISC_CC_RR_RG	0x0000007c

/* ISC Color Correction RB OR Register */
#define ISC_CC_RB_OR	0x00000080

/* ISC Color Correction GR GG Register */
#define ISC_CC_GR_GG	0x00000084

/* ISC Color Correction GB OG Register */
#define ISC_CC_GB_OG	0x00000088

/* ISC Color Correction BR BG Register */
#define ISC_CC_BR_BG	0x0000008c

/* ISC Color Correction BB OB Register */
#define ISC_CC_BB_OB	0x00000090

/* ISC Gamma Correction Control Register */
#define ISC_GAM_CTRL    0x00000094

/* ISC_Gamma Correction Blue Entry Register */
#define ISC_GAM_BENTRY	0x00000098

/* ISC_Gamma Correction Green Entry Register */
#define ISC_GAM_GENTRY	0x00000198

/* ISC_Gamma Correction Green Entry Register */
#define ISC_GAM_RENTRY	0x00000298

/* Color Space Conversion Control Register */
#define ISC_CSC_CTRL    0x00000398

/* Color Space Conversion YR YG Register */
#define ISC_CSC_YR_YG	0x0000039c

/* Color Space Conversion YB OY Register */
#define ISC_CSC_YB_OY	0x000003a0

/* Color Space Conversion CBR CBG Register */
#define ISC_CSC_CBR_CBG	0x000003a4

/* Color Space Conversion CBB OCB Register */
#define ISC_CSC_CBB_OCB	0x000003a8

/* Color Space Conversion CRR CRG Register */
#define ISC_CSC_CRR_CRG	0x000003ac

/* Color Space Conversion CRB OCR Register */
#define ISC_CSC_CRB_OCR	0x000003b0

/* Contrast And Brightness Control Register */
#define ISC_CBC_CTRL    0x000003b4

/* Contrast And Brightness Configuration Register */
#define ISC_CBC_CFG	0x000003b8

/* Brightness Register */
#define ISC_CBC_BRIGHT	0x000003bc
#define ISC_CBC_BRIGHT_MASK	GENMASK(10, 0)

/* Contrast Register */
#define ISC_CBC_CONTRAST	0x000003c0
#define ISC_CBC_CONTRAST_MASK	GENMASK(11, 0)

/* Subsampling 4:4:4 to 4:2:2 Control Register */
#define ISC_SUB422_CTRL 0x000003c4

/* Subsampling 4:2:2 to 4:2:0 Control Register */
#define ISC_SUB420_CTRL 0x000003cc

/* Rounding, Limiting and Packing Configuration Register */
#define ISC_RLP_CFG     0x000003d0

#define ISC_RLP_CFG_MODE_DAT8           0x0
#define ISC_RLP_CFG_MODE_DAT9           0x1
#define ISC_RLP_CFG_MODE_DAT10          0x2
#define ISC_RLP_CFG_MODE_DAT11          0x3
#define ISC_RLP_CFG_MODE_DAT12          0x4
#define ISC_RLP_CFG_MODE_DATY8          0x5
#define ISC_RLP_CFG_MODE_DATY10         0x6
#define ISC_RLP_CFG_MODE_ARGB444        0x7
#define ISC_RLP_CFG_MODE_ARGB555        0x8
#define ISC_RLP_CFG_MODE_RGB565         0x9
#define ISC_RLP_CFG_MODE_ARGB32         0xa
#define ISC_RLP_CFG_MODE_YYCC           0xb
#define ISC_RLP_CFG_MODE_YYCC_LIMITED   0xc
#define ISC_RLP_CFG_MODE_MASK           GENMASK(3, 0)

/* Histogram Control Register */
#define ISC_HIS_CTRL	0x000003d4

#define ISC_HIS_CTRL_EN			BIT(0)
#define ISC_HIS_CTRL_DIS		0x0

/* Histogram Configuration Register */
#define ISC_HIS_CFG	0x000003d8

#define ISC_HIS_CFG_MODE_GR		0x0
#define ISC_HIS_CFG_MODE_R		0x1
#define ISC_HIS_CFG_MODE_GB		0x2
#define ISC_HIS_CFG_MODE_B		0x3
#define ISC_HIS_CFG_MODE_Y		0x4
#define ISC_HIS_CFG_MODE_RAW		0x5
#define ISC_HIS_CFG_MODE_YCCIR656	0x6

#define ISC_HIS_CFG_BAYSEL_SHIFT	4

#define ISC_HIS_CFG_RAR			BIT(8)

/* DMA Configuration Register */
#define ISC_DCFG        0x000003e0
#define ISC_DCFG_IMODE_PACKED8          0x0
#define ISC_DCFG_IMODE_PACKED16         0x1
#define ISC_DCFG_IMODE_PACKED32         0x2
#define ISC_DCFG_IMODE_YC422SP          0x3
#define ISC_DCFG_IMODE_YC422P           0x4
#define ISC_DCFG_IMODE_YC420SP          0x5
#define ISC_DCFG_IMODE_YC420P           0x6
#define ISC_DCFG_IMODE_MASK             GENMASK(2, 0)

#define ISC_DCFG_YMBSIZE_SINGLE         (0x0 << 4)
#define ISC_DCFG_YMBSIZE_BEATS4         (0x1 << 4)
#define ISC_DCFG_YMBSIZE_BEATS8         (0x2 << 4)
#define ISC_DCFG_YMBSIZE_BEATS16        (0x3 << 4)
#define ISC_DCFG_YMBSIZE_MASK           GENMASK(5, 4)

#define ISC_DCFG_CMBSIZE_SINGLE         (0x0 << 8)
#define ISC_DCFG_CMBSIZE_BEATS4         (0x1 << 8)
#define ISC_DCFG_CMBSIZE_BEATS8         (0x2 << 8)
#define ISC_DCFG_CMBSIZE_BEATS16        (0x3 << 8)
#define ISC_DCFG_CMBSIZE_MASK           GENMASK(9, 8)

/* DMA Control Register */
#define ISC_DCTRL       0x000003e4

#define ISC_DCTRL_DVIEW_PACKED          (0x0 << 1)
#define ISC_DCTRL_DVIEW_SEMIPLANAR      (0x1 << 1)
#define ISC_DCTRL_DVIEW_PLANAR          (0x2 << 1)
#define ISC_DCTRL_DVIEW_MASK            GENMASK(2, 1)

#define ISC_DCTRL_IE_IS			(0x0 << 4)

/* DMA Descriptor Address Register */
#define ISC_DNDA        0x000003e8

/* DMA Address 0 Register */
#define ISC_DAD0        0x000003ec

/* DMA Address 1 Register */
#define ISC_DAD1        0x000003f4

/* DMA Address 2 Register */
#define ISC_DAD2        0x000003fc

/* Histogram Entry */
#define ISC_HIS_ENTRY	0x00000410

#endif
Commit	Line	Data
10626744 SW	1	#ifndef __ATMEL_ISC_REGS_H
	2	#define __ATMEL_ISC_REGS_H
	3
	4	#include <linux/bitops.h>
	5
	6	/* ISC Control Enable Register 0 */
	7	#define ISC_CTRLEN 0x00000000
	8
	9	/* ISC Control Disable Register 0 */
	10	#define ISC_CTRLDIS 0x00000004
	11
	12	/* ISC Control Status Register 0 */
	13	#define ISC_CTRLSR 0x00000008
	14
	15	#define ISC_CTRL_CAPTURE BIT(0)
	16	#define ISC_CTRL_UPPRO BIT(1)
	17	#define ISC_CTRL_HISREQ BIT(2)
	18	#define ISC_CTRL_HISCLR BIT(3)
	19
	20	/* ISC Parallel Front End Configuration 0 Register */
	21	#define ISC_PFE_CFG0 0x0000000c
	22
	23	#define ISC_PFE_CFG0_HPOL_LOW BIT(0)
	24	#define ISC_PFE_CFG0_VPOL_LOW BIT(1)
	25	#define ISC_PFE_CFG0_PPOL_LOW BIT(2)
	26
	27	#define ISC_PFE_CFG0_MODE_PROGRESSIVE (0x0 << 4)
	28	#define ISC_PFE_CFG0_MODE_MASK GENMASK(6, 4)
	29
	30	#define ISC_PFE_CFG0_BPS_EIGHT (0x4 << 28)
	31	#define ISC_PFG_CFG0_BPS_NINE (0x3 << 28)
	32	#define ISC_PFG_CFG0_BPS_TEN (0x2 << 28)
	33	#define ISC_PFG_CFG0_BPS_ELEVEN (0x1 << 28)
	34	#define ISC_PFG_CFG0_BPS_TWELVE (0x0 << 28)
	35	#define ISC_PFE_CFG0_BPS_MASK GENMASK(30, 28)
	36
	37	/* ISC Clock Enable Register */
	38	#define ISC_CLKEN 0x00000018
	39
	40	/* ISC Clock Disable Register */
	41	#define ISC_CLKDIS 0x0000001c
	42
	43	/* ISC Clock Status Register */
	44	#define ISC_CLKSR 0x00000020
	45
	46	#define ISC_CLK(n) BIT(n)
	47
	48	/* ISC Clock Configuration Register */
	49	#define ISC_CLKCFG 0x00000024
	50	#define ISC_CLKCFG_DIV_SHIFT(n) ((n)*16)
	51	#define ISC_CLKCFG_DIV_MASK(n) GENMASK(((n)16 + 7), (n)16)
	52	#define ISC_CLKCFG_SEL_SHIFT(n) ((n)*16 + 8)
	53	#define ISC_CLKCFG_SEL_MASK(n) GENMASK(((n)17 + 8), ((n)16 + 8))
	54
	55	/* ISC Interrupt Enable Register */
	56	#define ISC_INTEN 0x00000028
	57
	58	/* ISC Interrupt Disable Register */
	59	#define ISC_INTDIS 0x0000002c
	60
	61	/* ISC Interrupt Mask Register */
	62	#define ISC_INTMASK 0x00000030
	63
	64	/* ISC Interrupt Status Register */
65	#define ISC_INTSR 0x00000034
66
67	#define ISC_INT_DDONE BIT(8)
93d4a26c	68	#define ISC_INT_HISDONE BIT(12)
10626744 SW	69
	70	/* ISC White Balance Control Register */
	71	#define ISC_WB_CTRL 0x00000058
	72
	73	/* ISC White Balance Configuration Register */
	74	#define ISC_WB_CFG 0x0000005c
	75
93d4a26c SW	76	/* ISC White Balance Offset for R, GR Register */
	77	#define ISC_WB_O_RGR 0x00000060
	78
	79	/* ISC White Balance Offset for B, GB Register */
	80	#define ISC_WB_O_BGR 0x00000064
	81
	82	/* ISC White Balance Gain for R, GR Register */
	83	#define ISC_WB_G_RGR 0x00000068
	84
	85	/* ISC White Balance Gain for B, GB Register */
	86	#define ISC_WB_G_BGR 0x0000006c
	87
10626744 SW	88	/* ISC Color Filter Array Control Register */
	89	#define ISC_CFA_CTRL 0x00000070
	90
	91	/* ISC Color Filter Array Configuration Register */
	92	#define ISC_CFA_CFG 0x00000074
93d4a26c	93	#define ISC_CFA_CFG_EITPOL BIT(4)
10626744 SW	94
	95	#define ISC_BAY_CFG_GRGR 0x0
	96	#define ISC_BAY_CFG_RGRG 0x1
	97	#define ISC_BAY_CFG_GBGB 0x2
	98	#define ISC_BAY_CFG_BGBG 0x3
10626744 SW	99
	100	/* ISC Color Correction Control Register */
	101	#define ISC_CC_CTRL 0x00000078
	102
93d4a26c SW	103	/* ISC Color Correction RR RG Register */
	104	#define ISC_CC_RR_RG 0x0000007c
	105
	106	/* ISC Color Correction RB OR Register */
	107	#define ISC_CC_RB_OR 0x00000080
	108
	109	/* ISC Color Correction GR GG Register */
	110	#define ISC_CC_GR_GG 0x00000084
	111
	112	/* ISC Color Correction GB OG Register */
	113	#define ISC_CC_GB_OG 0x00000088
	114
	115	/* ISC Color Correction BR BG Register */
	116	#define ISC_CC_BR_BG 0x0000008c
	117
	118	/* ISC Color Correction BB OB Register */
	119	#define ISC_CC_BB_OB 0x00000090
	120
10626744 SW	121	/* ISC Gamma Correction Control Register */
	122	#define ISC_GAM_CTRL 0x00000094
	123
93d4a26c SW	124	/* ISC_Gamma Correction Blue Entry Register */
	125	#define ISC_GAM_BENTRY 0x00000098
	126
	127	/* ISC_Gamma Correction Green Entry Register */
	128	#define ISC_GAM_GENTRY 0x00000198
	129
	130	/* ISC_Gamma Correction Green Entry Register */
	131	#define ISC_GAM_RENTRY 0x00000298
	132
10626744 SW	133	/* Color Space Conversion Control Register */
	134	#define ISC_CSC_CTRL 0x00000398
	135
93d4a26c SW	136	/* Color Space Conversion YR YG Register */
	137	#define ISC_CSC_YR_YG 0x0000039c
	138
	139	/* Color Space Conversion YB OY Register */
	140	#define ISC_CSC_YB_OY 0x000003a0
	141
	142	/* Color Space Conversion CBR CBG Register */
	143	#define ISC_CSC_CBR_CBG 0x000003a4
	144
	145	/* Color Space Conversion CBB OCB Register */
	146	#define ISC_CSC_CBB_OCB 0x000003a8
	147
	148	/* Color Space Conversion CRR CRG Register */
	149	#define ISC_CSC_CRR_CRG 0x000003ac
	150
	151	/* Color Space Conversion CRB OCR Register */
	152	#define ISC_CSC_CRB_OCR 0x000003b0
	153
10626744 SW	154	/* Contrast And Brightness Control Register */
	155	#define ISC_CBC_CTRL 0x000003b4
	156
93d4a26c SW	157	/* Contrast And Brightness Configuration Register */
	158	#define ISC_CBC_CFG 0x000003b8
	159
	160	/* Brightness Register */
	161	#define ISC_CBC_BRIGHT 0x000003bc
	162	#define ISC_CBC_BRIGHT_MASK GENMASK(10, 0)
	163
	164	/* Contrast Register */
	165	#define ISC_CBC_CONTRAST 0x000003c0
	166	#define ISC_CBC_CONTRAST_MASK GENMASK(11, 0)
	167
10626744 SW	168	/* Subsampling 4:4:4 to 4:2:2 Control Register */
	169	#define ISC_SUB422_CTRL 0x000003c4
	170
	171	/* Subsampling 4:2:2 to 4:2:0 Control Register */
	172	#define ISC_SUB420_CTRL 0x000003cc
	173
	174	/* Rounding, Limiting and Packing Configuration Register */
	175	#define ISC_RLP_CFG 0x000003d0
	176
	177	#define ISC_RLP_CFG_MODE_DAT8 0x0
	178	#define ISC_RLP_CFG_MODE_DAT9 0x1
	179	#define ISC_RLP_CFG_MODE_DAT10 0x2
	180	#define ISC_RLP_CFG_MODE_DAT11 0x3
	181	#define ISC_RLP_CFG_MODE_DAT12 0x4
	182	#define ISC_RLP_CFG_MODE_DATY8 0x5
	183	#define ISC_RLP_CFG_MODE_DATY10 0x6
	184	#define ISC_RLP_CFG_MODE_ARGB444 0x7
	185	#define ISC_RLP_CFG_MODE_ARGB555 0x8
	186	#define ISC_RLP_CFG_MODE_RGB565 0x9
	187	#define ISC_RLP_CFG_MODE_ARGB32 0xa
	188	#define ISC_RLP_CFG_MODE_YYCC 0xb
	189	#define ISC_RLP_CFG_MODE_YYCC_LIMITED 0xc
	190	#define ISC_RLP_CFG_MODE_MASK GENMASK(3, 0)
	191
93d4a26c SW	192	/* Histogram Control Register */
	193	#define ISC_HIS_CTRL 0x000003d4
	194
	195	#define ISC_HIS_CTRL_EN BIT(0)
	196	#define ISC_HIS_CTRL_DIS 0x0
	197
	198	/* Histogram Configuration Register */
	199	#define ISC_HIS_CFG 0x000003d8
	200
	201	#define ISC_HIS_CFG_MODE_GR 0x0
	202	#define ISC_HIS_CFG_MODE_R 0x1
	203	#define ISC_HIS_CFG_MODE_GB 0x2
	204	#define ISC_HIS_CFG_MODE_B 0x3
	205	#define ISC_HIS_CFG_MODE_Y 0x4
	206	#define ISC_HIS_CFG_MODE_RAW 0x5
	207	#define ISC_HIS_CFG_MODE_YCCIR656 0x6
	208
	209	#define ISC_HIS_CFG_BAYSEL_SHIFT 4
	210
	211	#define ISC_HIS_CFG_RAR BIT(8)
	212
10626744 SW	213	/* DMA Configuration Register */
	214	#define ISC_DCFG 0x000003e0
	215	#define ISC_DCFG_IMODE_PACKED8 0x0
	216	#define ISC_DCFG_IMODE_PACKED16 0x1
	217	#define ISC_DCFG_IMODE_PACKED32 0x2
	218	#define ISC_DCFG_IMODE_YC422SP 0x3
	219	#define ISC_DCFG_IMODE_YC422P 0x4
	220	#define ISC_DCFG_IMODE_YC420SP 0x5
	221	#define ISC_DCFG_IMODE_YC420P 0x6
	222	#define ISC_DCFG_IMODE_MASK GENMASK(2, 0)
	223
	224	#define ISC_DCFG_YMBSIZE_SINGLE (0x0 << 4)
	225	#define ISC_DCFG_YMBSIZE_BEATS4 (0x1 << 4)
	226	#define ISC_DCFG_YMBSIZE_BEATS8 (0x2 << 4)
	227	#define ISC_DCFG_YMBSIZE_BEATS16 (0x3 << 4)
	228	#define ISC_DCFG_YMBSIZE_MASK GENMASK(5, 4)
	229
	230	#define ISC_DCFG_CMBSIZE_SINGLE (0x0 << 8)
	231	#define ISC_DCFG_CMBSIZE_BEATS4 (0x1 << 8)
	232	#define ISC_DCFG_CMBSIZE_BEATS8 (0x2 << 8)
	233	#define ISC_DCFG_CMBSIZE_BEATS16 (0x3 << 8)
	234	#define ISC_DCFG_CMBSIZE_MASK GENMASK(9, 8)
	235
	236	/* DMA Control Register */
	237	#define ISC_DCTRL 0x000003e4
	238
	239	#define ISC_DCTRL_DVIEW_PACKED (0x0 << 1)
	240	#define ISC_DCTRL_DVIEW_SEMIPLANAR (0x1 << 1)
	241	#define ISC_DCTRL_DVIEW_PLANAR (0x2 << 1)
	242	#define ISC_DCTRL_DVIEW_MASK GENMASK(2, 1)
	243
	244	#define ISC_DCTRL_IE_IS (0x0 << 4)
	245
	246	/* DMA Descriptor Address Register */
	247	#define ISC_DNDA 0x000003e8
	248
	249	/* DMA Address 0 Register */
	250	#define ISC_DAD0 0x000003ec
	251
93d4a26c SW	252	/* DMA Address 1 Register */
	253	#define ISC_DAD1 0x000003f4
	254
	255	/* DMA Address 2 Register */
	256	#define ISC_DAD2 0x000003fc
	257
	258	/* Histogram Entry */
	259	#define ISC_HIS_ENTRY 0x00000410
10626744 SW	260
10626744 SW	261	#endif