[mirror_ubuntu-artful-kernel.git] / drivers / media / platform / blackfin / ppi.c

/*
 * ppi.c Analog Devices Parallel Peripheral Interface driver
 *
 * Copyright (c) 2011 Analog Devices Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 */

#include <linux/module.h>
#include <linux/slab.h>

#include <asm/bfin_ppi.h>
#include <asm/blackfin.h>
#include <asm/cacheflush.h>
#include <asm/dma.h>
#include <asm/portmux.h>

#include <media/blackfin/ppi.h>

static int ppi_attach_irq(struct ppi_if *ppi, irq_handler_t handler);
static void ppi_detach_irq(struct ppi_if *ppi);
static int ppi_start(struct ppi_if *ppi);
static int ppi_stop(struct ppi_if *ppi);
static int ppi_set_params(struct ppi_if *ppi, struct ppi_params *params);
static void ppi_update_addr(struct ppi_if *ppi, unsigned long addr);

static const struct ppi_ops ppi_ops = {
	.attach_irq = ppi_attach_irq,
	.detach_irq = ppi_detach_irq,
	.start = ppi_start,
	.stop = ppi_stop,
	.set_params = ppi_set_params,
	.update_addr = ppi_update_addr,
};

static irqreturn_t ppi_irq_err(int irq, void *dev_id)
{
	struct ppi_if *ppi = dev_id;
	const struct ppi_info *info = ppi->info;

	switch (info->type) {
	case PPI_TYPE_PPI:
	{
		struct bfin_ppi_regs *reg = info->base;
		unsigned short status;

		/* register on bf561 is cleared when read 
		 * others are W1C
		 */
		status = bfin_read16(&reg->status);
		if (status & 0x3000)
			ppi->err = true;
		bfin_write16(&reg->status, 0xff00);
		break;
	}
	case PPI_TYPE_EPPI:
	{
		struct bfin_eppi_regs *reg = info->base;
		unsigned short status;

		status = bfin_read16(&reg->status);
		if (status & 0x2)
			ppi->err = true;
		bfin_write16(&reg->status, 0xffff);
		break;
	}
	case PPI_TYPE_EPPI3:
	{
		struct bfin_eppi3_regs *reg = info->base;
		unsigned long stat;

		stat = bfin_read32(&reg->stat);
		if (stat & 0x2)
			ppi->err = true;
		bfin_write32(&reg->stat, 0xc0ff);
		break;
	}
	default:
		break;
	}

	return IRQ_HANDLED;
}

static int ppi_attach_irq(struct ppi_if *ppi, irq_handler_t handler)
{
	const struct ppi_info *info = ppi->info;
	int ret;

	ret = request_dma(info->dma_ch, "PPI_DMA");

	if (ret) {
		pr_err("Unable to allocate DMA channel for PPI\n");
		return ret;
	}
	set_dma_callback(info->dma_ch, handler, ppi);

	if (ppi->err_int) {
		ret = request_irq(info->irq_err, ppi_irq_err, 0, "PPI ERROR", ppi);
		if (ret) {
			pr_err("Unable to allocate IRQ for PPI\n");
			free_dma(info->dma_ch);
		}
	}
	return ret;
}

static void ppi_detach_irq(struct ppi_if *ppi)
{
	const struct ppi_info *info = ppi->info;

	if (ppi->err_int)
		free_irq(info->irq_err, ppi);
	free_dma(info->dma_ch);
}

static int ppi_start(struct ppi_if *ppi)
{
	const struct ppi_info *info = ppi->info;

	/* enable DMA */
	enable_dma(info->dma_ch);

	/* enable PPI */
	ppi->ppi_control |= PORT_EN;
	switch (info->type) {
	case PPI_TYPE_PPI:
	{
		struct bfin_ppi_regs *reg = info->base;
		bfin_write16(&reg->control, ppi->ppi_control);
		break;
	}
	case PPI_TYPE_EPPI:
	{
		struct bfin_eppi_regs *reg = info->base;
		bfin_write32(&reg->control, ppi->ppi_control);
		break;
	}
	case PPI_TYPE_EPPI3:
	{
		struct bfin_eppi3_regs *reg = info->base;
		bfin_write32(&reg->ctl, ppi->ppi_control);
		break;
	}
	default:
		return -EINVAL;
	}

	SSYNC();
	return 0;
}

static int ppi_stop(struct ppi_if *ppi)
{
	const struct ppi_info *info = ppi->info;

	/* disable PPI */
	ppi->ppi_control &= ~PORT_EN;
	switch (info->type) {
	case PPI_TYPE_PPI:
	{
		struct bfin_ppi_regs *reg = info->base;
		bfin_write16(&reg->control, ppi->ppi_control);
		break;
	}
	case PPI_TYPE_EPPI:
	{
		struct bfin_eppi_regs *reg = info->base;
		bfin_write32(&reg->control, ppi->ppi_control);
		break;
	}
	case PPI_TYPE_EPPI3:
	{
		struct bfin_eppi3_regs *reg = info->base;
		bfin_write32(&reg->ctl, ppi->ppi_control);
		break;
	}
	default:
		return -EINVAL;
	}

	/* disable DMA */
	clear_dma_irqstat(info->dma_ch);
	disable_dma(info->dma_ch);

	SSYNC();
	return 0;
}

static int ppi_set_params(struct ppi_if *ppi, struct ppi_params *params)
{
	const struct ppi_info *info = ppi->info;
	int dma32 = 0;
	int dma_config, bytes_per_line;
	int hcount, hdelay, samples_per_line;

	bytes_per_line = params->width * params->bpp / 8;
	/* convert parameters unit from pixels to samples */
	hcount = params->width * params->bpp / params->dlen;
	hdelay = params->hdelay * params->bpp / params->dlen;
	samples_per_line = params->line * params->bpp / params->dlen;
	if (params->int_mask == 0xFFFFFFFF)
		ppi->err_int = false;
	else
		ppi->err_int = true;

	dma_config = (DMA_FLOW_STOP | RESTART | DMA2D | DI_EN_Y);
	ppi->ppi_control = params->ppi_control & ~PORT_EN;
	if (!(ppi->ppi_control & PORT_DIR))
		dma_config |= WNR;
	switch (info->type) {
	case PPI_TYPE_PPI:
	{
		struct bfin_ppi_regs *reg = info->base;

		if (params->ppi_control & DMA32)
			dma32 = 1;

		bfin_write16(&reg->control, ppi->ppi_control);
		bfin_write16(&reg->count, samples_per_line - 1);
		bfin_write16(&reg->frame, params->frame);
		break;
	}
	case PPI_TYPE_EPPI:
	{
		struct bfin_eppi_regs *reg = info->base;

		if ((params->ppi_control & PACK_EN)
			|| (params->ppi_control & 0x38000) > DLEN_16)
			dma32 = 1;

		bfin_write32(&reg->control, ppi->ppi_control);
		bfin_write16(&reg->line, samples_per_line);
		bfin_write16(&reg->frame, params->frame);
		bfin_write16(&reg->hdelay, hdelay);
		bfin_write16(&reg->vdelay, params->vdelay);
		bfin_write16(&reg->hcount, hcount);
		bfin_write16(&reg->vcount, params->height);
		break;
	}
	case PPI_TYPE_EPPI3:
	{
		struct bfin_eppi3_regs *reg = info->base;

		if ((params->ppi_control & PACK_EN)
			|| (params->ppi_control & 0x70000) > DLEN_16)
			dma32 = 1;

		bfin_write32(&reg->ctl, ppi->ppi_control);
		bfin_write32(&reg->line, samples_per_line);
		bfin_write32(&reg->frame, params->frame);
		bfin_write32(&reg->hdly, hdelay);
		bfin_write32(&reg->vdly, params->vdelay);
		bfin_write32(&reg->hcnt, hcount);
		bfin_write32(&reg->vcnt, params->height);
		if (params->int_mask)
			bfin_write32(&reg->imsk, params->int_mask & 0xFF);
		break;
	}
	default:
		return -EINVAL;
	}

	if (dma32) {
		dma_config |= WDSIZE_32 | PSIZE_32;
		set_dma_x_count(info->dma_ch, bytes_per_line >> 2);
		set_dma_x_modify(info->dma_ch, 4);
		set_dma_y_modify(info->dma_ch, 4);
	} else {
		dma_config |= WDSIZE_16 | PSIZE_16;
		set_dma_x_count(info->dma_ch, bytes_per_line >> 1);
		set_dma_x_modify(info->dma_ch, 2);
		set_dma_y_modify(info->dma_ch, 2);
	}
	set_dma_y_count(info->dma_ch, params->height);
	set_dma_config(info->dma_ch, dma_config);

	SSYNC();
	return 0;
}

static void ppi_update_addr(struct ppi_if *ppi, unsigned long addr)
{
	set_dma_start_addr(ppi->info->dma_ch, addr);
}

struct ppi_if *ppi_create_instance(const struct ppi_info *info)
{
	struct ppi_if *ppi;

	if (!info || !info->pin_req)
		return NULL;

	if (peripheral_request_list(info->pin_req, KBUILD_MODNAME)) {
		pr_err("request peripheral failed\n");
		return NULL;
	}

	ppi = kzalloc(sizeof(*ppi), GFP_KERNEL);
	if (!ppi) {
		peripheral_free_list(info->pin_req);
		pr_err("unable to allocate memory for ppi handle\n");
		return NULL;
	}
	ppi->ops = &ppi_ops;
	ppi->info = info;

	pr_info("ppi probe success\n");
	return ppi;
}
EXPORT_SYMBOL(ppi_create_instance);

void ppi_delete_instance(struct ppi_if *ppi)
{
	peripheral_free_list(ppi->info->pin_req);
	kfree(ppi);
}
EXPORT_SYMBOL(ppi_delete_instance);

MODULE_DESCRIPTION("Analog Devices PPI driver");
MODULE_AUTHOR("Scott Jiang <Scott.Jiang.Linux@gmail.com>");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
63b1a90d SJ	1	/*
	2	* ppi.c Analog Devices Parallel Peripheral Interface driver
	3	*
	4	* Copyright (c) 2011 Analog Devices Inc.
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
	9	*
	10	* This program is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
	14	*
	15	* You should have received a copy of the GNU General Public License
	16	* along with this program; if not, write to the Free Software
	17	* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
	18	*/
	19
fab0e8fa	20	#include <linux/module.h>
63b1a90d SJ	21	#include <linux/slab.h>
	22
	23	#include <asm/bfin_ppi.h>
	24	#include <asm/blackfin.h>
	25	#include <asm/cacheflush.h>
	26	#include <asm/dma.h>
	27	#include <asm/portmux.h>
	28
	29	#include <media/blackfin/ppi.h>
	30
	31	static int ppi_attach_irq(struct ppi_if *ppi, irq_handler_t handler);
	32	static void ppi_detach_irq(struct ppi_if *ppi);
	33	static int ppi_start(struct ppi_if *ppi);
	34	static int ppi_stop(struct ppi_if *ppi);
	35	static int ppi_set_params(struct ppi_if ppi, struct ppi_params params);
	36	static void ppi_update_addr(struct ppi_if *ppi, unsigned long addr);
	37
	38	static const struct ppi_ops ppi_ops = {
	39	.attach_irq = ppi_attach_irq,
	40	.detach_irq = ppi_detach_irq,
	41	.start = ppi_start,
	42	.stop = ppi_stop,
	43	.set_params = ppi_set_params,
	44	.update_addr = ppi_update_addr,
	45	};
	46
	47	static irqreturn_t ppi_irq_err(int irq, void *dev_id)
	48	{
	49	struct ppi_if *ppi = dev_id;
	50	const struct ppi_info *info = ppi->info;
	51
	52	switch (info->type) {
	53	case PPI_TYPE_PPI:
	54	{
	55	struct bfin_ppi_regs *reg = info->base;
	56	unsigned short status;
	57
	58	/* register on bf561 is cleared when read
	59	* others are W1C
	60	*/
	61	status = bfin_read16(&reg->status);
d78a4882 SJ	62	if (status & 0x3000)
d78a4882 SJ	63	ppi->err = true;
63b1a90d SJ	64	bfin_write16(&reg->status, 0xff00);
	65	break;
	66	}
	67	case PPI_TYPE_EPPI:
	68	{
	69	struct bfin_eppi_regs *reg = info->base;
d78a4882 SJ	70	unsigned short status;
	71
	72	status = bfin_read16(&reg->status);
	73	if (status & 0x2)
	74	ppi->err = true;
63b1a90d SJ	75	bfin_write16(&reg->status, 0xffff);
	76	break;
	77	}
45b82596 SJ	78	case PPI_TYPE_EPPI3:
	79	{
	80	struct bfin_eppi3_regs *reg = info->base;
d78a4882	81	unsigned long stat;
45b82596	82
d78a4882 SJ	83	stat = bfin_read32(&reg->stat);
	84	if (stat & 0x2)
	85	ppi->err = true;
45b82596 SJ	86	bfin_write32(&reg->stat, 0xc0ff);
	87	break;
	88	}
63b1a90d SJ	89	default:
	90	break;
	91	}
	92
	93	return IRQ_HANDLED;
	94	}
	95
	96	static int ppi_attach_irq(struct ppi_if *ppi, irq_handler_t handler)
	97	{
	98	const struct ppi_info *info = ppi->info;
	99	int ret;
	100
	101	ret = request_dma(info->dma_ch, "PPI_DMA");
	102
	103	if (ret) {
	104	pr_err("Unable to allocate DMA channel for PPI\n");
	105	return ret;
	106	}
	107	set_dma_callback(info->dma_ch, handler, ppi);
	108
	109	if (ppi->err_int) {
	110	ret = request_irq(info->irq_err, ppi_irq_err, 0, "PPI ERROR", ppi);
	111	if (ret) {
	112	pr_err("Unable to allocate IRQ for PPI\n");
	113	free_dma(info->dma_ch);
	114	}
	115	}
	116	return ret;
	117	}
	118
	119	static void ppi_detach_irq(struct ppi_if *ppi)
	120	{
	121	const struct ppi_info *info = ppi->info;
	122
	123	if (ppi->err_int)
	124	free_irq(info->irq_err, ppi);
	125	free_dma(info->dma_ch);
	126	}
	127
	128	static int ppi_start(struct ppi_if *ppi)
	129	{
	130	const struct ppi_info *info = ppi->info;
	131
	132	/* enable DMA */
	133	enable_dma(info->dma_ch);
	134
	135	/* enable PPI */
	136	ppi->ppi_control \|= PORT_EN;
	137	switch (info->type) {
	138	case PPI_TYPE_PPI:
	139	{
	140	struct bfin_ppi_regs *reg = info->base;
	141	bfin_write16(&reg->control, ppi->ppi_control);
	142	break;
	143	}
	144	case PPI_TYPE_EPPI:
	145	{
	146	struct bfin_eppi_regs *reg = info->base;
	147	bfin_write32(&reg->control, ppi->ppi_control);
	148	break;
	149	}
45b82596 SJ	150	case PPI_TYPE_EPPI3:
	151	{
	152	struct bfin_eppi3_regs *reg = info->base;
	153	bfin_write32(&reg->ctl, ppi->ppi_control);
	154	break;
	155	}
63b1a90d SJ	156	default:
	157	return -EINVAL;
	158	}
	159
	160	SSYNC();
	161	return 0;
	162	}
	163
	164	static int ppi_stop(struct ppi_if *ppi)
	165	{
	166	const struct ppi_info *info = ppi->info;
	167
	168	/* disable PPI */
	169	ppi->ppi_control &= ~PORT_EN;
	170	switch (info->type) {
	171	case PPI_TYPE_PPI:
	172	{
	173	struct bfin_ppi_regs *reg = info->base;
	174	bfin_write16(&reg->control, ppi->ppi_control);
	175	break;
	176	}
	177	case PPI_TYPE_EPPI:
	178	{
	179	struct bfin_eppi_regs *reg = info->base;
	180	bfin_write32(&reg->control, ppi->ppi_control);
	181	break;
	182	}
45b82596 SJ	183	case PPI_TYPE_EPPI3:
	184	{
	185	struct bfin_eppi3_regs *reg = info->base;
	186	bfin_write32(&reg->ctl, ppi->ppi_control);
	187	break;
	188	}
63b1a90d SJ	189	default:
	190	return -EINVAL;
	191	}
	192
	193	/* disable DMA */
	194	clear_dma_irqstat(info->dma_ch);
	195	disable_dma(info->dma_ch);
	196
	197	SSYNC();
	198	return 0;
	199	}
	200
	201	static int ppi_set_params(struct ppi_if ppi, struct ppi_params params)
	202	{
	203	const struct ppi_info *info = ppi->info;
	204	int dma32 = 0;
45b82596 SJ	205	int dma_config, bytes_per_line;
45b82596 SJ	206	int hcount, hdelay, samples_per_line;
63b1a90d SJ	207
63b1a90d SJ	208	bytes_per_line = params->width * params->bpp / 8;
45b82596 SJ	209	/* convert parameters unit from pixels to samples */
	210	hcount = params->width * params->bpp / params->dlen;
	211	hdelay = params->hdelay * params->bpp / params->dlen;
	212	samples_per_line = params->line * params->bpp / params->dlen;
63b1a90d SJ	213	if (params->int_mask == 0xFFFFFFFF)
	214	ppi->err_int = false;
	215	else
	216	ppi->err_int = true;
	217
45b82596	218	dma_config = (DMA_FLOW_STOP \| RESTART \| DMA2D \| DI_EN_Y);
63b1a90d	219	ppi->ppi_control = params->ppi_control & ~PORT_EN;
45b82596 SJ	220	if (!(ppi->ppi_control & PORT_DIR))
45b82596 SJ	221	dma_config \|= WNR;
63b1a90d SJ	222	switch (info->type) {
	223	case PPI_TYPE_PPI:
	224	{
	225	struct bfin_ppi_regs *reg = info->base;
	226
	227	if (params->ppi_control & DMA32)
	228	dma32 = 1;
	229
	230	bfin_write16(&reg->control, ppi->ppi_control);
45b82596 SJ	231	bfin_write16(&reg->count, samples_per_line - 1);
45b82596 SJ	232	bfin_write16(&reg->frame, params->frame);
63b1a90d SJ	233	break;
	234	}
	235	case PPI_TYPE_EPPI:
	236	{
	237	struct bfin_eppi_regs *reg = info->base;
	238
	239	if ((params->ppi_control & PACK_EN)
	240	\|\| (params->ppi_control & 0x38000) > DLEN_16)
	241	dma32 = 1;
	242
	243	bfin_write32(&reg->control, ppi->ppi_control);
45b82596 SJ	244	bfin_write16(&reg->line, samples_per_line);
	245	bfin_write16(&reg->frame, params->frame);
	246	bfin_write16(&reg->hdelay, hdelay);
	247	bfin_write16(&reg->vdelay, params->vdelay);
	248	bfin_write16(&reg->hcount, hcount);
	249	bfin_write16(&reg->vcount, params->height);
	250	break;
	251	}
	252	case PPI_TYPE_EPPI3:
	253	{
	254	struct bfin_eppi3_regs *reg = info->base;
	255
	256	if ((params->ppi_control & PACK_EN)
	257	\|\| (params->ppi_control & 0x70000) > DLEN_16)
	258	dma32 = 1;
	259
	260	bfin_write32(&reg->ctl, ppi->ppi_control);
	261	bfin_write32(&reg->line, samples_per_line);
	262	bfin_write32(&reg->frame, params->frame);
	263	bfin_write32(&reg->hdly, hdelay);
	264	bfin_write32(&reg->vdly, params->vdelay);
	265	bfin_write32(&reg->hcnt, hcount);
	266	bfin_write32(&reg->vcnt, params->height);
	267	if (params->int_mask)
	268	bfin_write32(&reg->imsk, params->int_mask & 0xFF);
63b1a90d SJ	269	break;
	270	}
	271	default:
	272	return -EINVAL;
	273	}
	274
	275	if (dma32) {
45b82596	276	dma_config \|= WDSIZE_32 \| PSIZE_32;
63b1a90d SJ	277	set_dma_x_count(info->dma_ch, bytes_per_line >> 2);
	278	set_dma_x_modify(info->dma_ch, 4);
	279	set_dma_y_modify(info->dma_ch, 4);
	280	} else {
45b82596	281	dma_config \|= WDSIZE_16 \| PSIZE_16;
63b1a90d SJ	282	set_dma_x_count(info->dma_ch, bytes_per_line >> 1);
	283	set_dma_x_modify(info->dma_ch, 2);
	284	set_dma_y_modify(info->dma_ch, 2);
	285	}
45b82596	286	set_dma_y_count(info->dma_ch, params->height);
63b1a90d SJ	287	set_dma_config(info->dma_ch, dma_config);
	288
	289	SSYNC();
	290	return 0;
	291	}
	292
	293	static void ppi_update_addr(struct ppi_if *ppi, unsigned long addr)
	294	{
	295	set_dma_start_addr(ppi->info->dma_ch, addr);
	296	}
	297
	298	struct ppi_if ppi_create_instance(const struct ppi_info info)
	299	{
	300	struct ppi_if *ppi;
	301
	302	if (!info \|\| !info->pin_req)
	303	return NULL;
	304
	305	if (peripheral_request_list(info->pin_req, KBUILD_MODNAME)) {
	306	pr_err("request peripheral failed\n");
	307	return NULL;
	308	}
	309
	310	ppi = kzalloc(sizeof(*ppi), GFP_KERNEL);
	311	if (!ppi) {
	312	peripheral_free_list(info->pin_req);
	313	pr_err("unable to allocate memory for ppi handle\n");
	314	return NULL;
	315	}
	316	ppi->ops = &ppi_ops;
	317	ppi->info = info;
	318
	319	pr_info("ppi probe success\n");
	320	return ppi;
	321	}
fab0e8fa	322	EXPORT_SYMBOL(ppi_create_instance);
63b1a90d SJ	323
	324	void ppi_delete_instance(struct ppi_if *ppi)
	325	{
	326	peripheral_free_list(ppi->info->pin_req);
	327	kfree(ppi);
	328	}
fab0e8fa SJ	329	EXPORT_SYMBOL(ppi_delete_instance);
	330
	331	MODULE_DESCRIPTION("Analog Devices PPI driver");
	332	MODULE_AUTHOR("Scott Jiang <Scott.Jiang.Linux@gmail.com>");
	333	MODULE_LICENSE("GPL v2");