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dd2ceb1a MK |
1 | /* |
2 | * Copyright (C) 2005-2009 Texas Instruments Inc | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License as published by | |
6 | * the Free Software Foundation; either version 2 of the License, or | |
7 | * (at your option) any later version. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
dd2ceb1a MK |
14 | * CCDC hardware module for DM355 |
15 | * ------------------------------ | |
16 | * | |
17 | * This module is for configuring DM355 CCD controller of VPFE to capture | |
18 | * Raw yuv or Bayer RGB data from a decoder. CCDC has several modules | |
19 | * such as Defect Pixel Correction, Color Space Conversion etc to | |
20 | * pre-process the Bayer RGB data, before writing it to SDRAM. This | |
21 | * module also allows application to configure individual | |
22 | * module parameters through VPFE_CMD_S_CCDC_RAW_PARAMS IOCTL. | |
23 | * To do so, application include dm355_ccdc.h and vpfe_capture.h header | |
24 | * files. The setparams() API is called by vpfe_capture driver | |
25 | * to configure module parameters | |
26 | * | |
27 | * TODO: 1) Raw bayer parameter settings and bayer capture | |
28 | * 2) Split module parameter structure to module specific ioctl structs | |
29 | * 3) add support for lense shading correction | |
30 | * 4) investigate if enum used for user space type definition | |
31 | * to be replaced by #defines or integer | |
32 | */ | |
33 | #include <linux/platform_device.h> | |
34 | #include <linux/uaccess.h> | |
35 | #include <linux/videodev2.h> | |
c70fc2d2 | 36 | #include <linux/err.h> |
7a707b89 | 37 | #include <linux/module.h> |
c70fc2d2 | 38 | |
dd2ceb1a MK |
39 | #include <media/davinci/dm355_ccdc.h> |
40 | #include <media/davinci/vpss.h> | |
c70fc2d2 | 41 | |
dd2ceb1a MK |
42 | #include "dm355_ccdc_regs.h" |
43 | #include "ccdc_hw_device.h" | |
44 | ||
45 | MODULE_LICENSE("GPL"); | |
46 | MODULE_DESCRIPTION("CCDC Driver for DM355"); | |
47 | MODULE_AUTHOR("Texas Instruments"); | |
48 | ||
c70fc2d2 MK |
49 | static struct ccdc_oper_config { |
50 | struct device *dev; | |
51 | /* CCDC interface type */ | |
52 | enum vpfe_hw_if_type if_type; | |
53 | /* Raw Bayer configuration */ | |
54 | struct ccdc_params_raw bayer; | |
55 | /* YCbCr configuration */ | |
56 | struct ccdc_params_ycbcr ycbcr; | |
c70fc2d2 MK |
57 | /* ccdc base address */ |
58 | void __iomem *base_addr; | |
59 | } ccdc_cfg = { | |
60 | /* Raw configurations */ | |
61 | .bayer = { | |
62 | .pix_fmt = CCDC_PIXFMT_RAW, | |
63 | .frm_fmt = CCDC_FRMFMT_PROGRESSIVE, | |
64 | .win = CCDC_WIN_VGA, | |
65 | .fid_pol = VPFE_PINPOL_POSITIVE, | |
66 | .vd_pol = VPFE_PINPOL_POSITIVE, | |
67 | .hd_pol = VPFE_PINPOL_POSITIVE, | |
68 | .gain = { | |
69 | .r_ye = 256, | |
70 | .gb_g = 256, | |
71 | .gr_cy = 256, | |
72 | .b_mg = 256 | |
dd2ceb1a | 73 | }, |
c70fc2d2 MK |
74 | .config_params = { |
75 | .datasft = 2, | |
76 | .mfilt1 = CCDC_NO_MEDIAN_FILTER1, | |
77 | .mfilt2 = CCDC_NO_MEDIAN_FILTER2, | |
78 | .alaw = { | |
db242f62 | 79 | .gamma_wd = 2, |
c70fc2d2 MK |
80 | }, |
81 | .blk_clamp = { | |
82 | .sample_pixel = 1, | |
83 | .dc_sub = 25 | |
84 | }, | |
85 | .col_pat_field0 = { | |
86 | .olop = CCDC_GREEN_BLUE, | |
87 | .olep = CCDC_BLUE, | |
88 | .elop = CCDC_RED, | |
89 | .elep = CCDC_GREEN_RED | |
90 | }, | |
91 | .col_pat_field1 = { | |
92 | .olop = CCDC_GREEN_BLUE, | |
93 | .olep = CCDC_BLUE, | |
94 | .elop = CCDC_RED, | |
95 | .elep = CCDC_GREEN_RED | |
96 | }, | |
dd2ceb1a MK |
97 | }, |
98 | }, | |
c70fc2d2 MK |
99 | /* YCbCr configuration */ |
100 | .ycbcr = { | |
101 | .win = CCDC_WIN_PAL, | |
102 | .pix_fmt = CCDC_PIXFMT_YCBCR_8BIT, | |
103 | .frm_fmt = CCDC_FRMFMT_INTERLACED, | |
104 | .fid_pol = VPFE_PINPOL_POSITIVE, | |
105 | .vd_pol = VPFE_PINPOL_POSITIVE, | |
106 | .hd_pol = VPFE_PINPOL_POSITIVE, | |
107 | .bt656_enable = 1, | |
108 | .pix_order = CCDC_PIXORDER_CBYCRY, | |
109 | .buf_type = CCDC_BUFTYPE_FLD_INTERLEAVED | |
110 | }, | |
dd2ceb1a MK |
111 | }; |
112 | ||
113 | ||
dd2ceb1a MK |
114 | /* Raw Bayer formats */ |
115 | static u32 ccdc_raw_bayer_pix_formats[] = | |
116 | {V4L2_PIX_FMT_SBGGR8, V4L2_PIX_FMT_SBGGR16}; | |
117 | ||
118 | /* Raw YUV formats */ | |
119 | static u32 ccdc_raw_yuv_pix_formats[] = | |
120 | {V4L2_PIX_FMT_UYVY, V4L2_PIX_FMT_YUYV}; | |
121 | ||
122 | /* register access routines */ | |
123 | static inline u32 regr(u32 offset) | |
124 | { | |
c70fc2d2 | 125 | return __raw_readl(ccdc_cfg.base_addr + offset); |
dd2ceb1a MK |
126 | } |
127 | ||
128 | static inline void regw(u32 val, u32 offset) | |
129 | { | |
c70fc2d2 | 130 | __raw_writel(val, ccdc_cfg.base_addr + offset); |
dd2ceb1a MK |
131 | } |
132 | ||
133 | static void ccdc_enable(int en) | |
134 | { | |
135 | unsigned int temp; | |
136 | temp = regr(SYNCEN); | |
137 | temp &= (~CCDC_SYNCEN_VDHDEN_MASK); | |
138 | temp |= (en & CCDC_SYNCEN_VDHDEN_MASK); | |
139 | regw(temp, SYNCEN); | |
140 | } | |
141 | ||
142 | static void ccdc_enable_output_to_sdram(int en) | |
143 | { | |
144 | unsigned int temp; | |
145 | temp = regr(SYNCEN); | |
146 | temp &= (~(CCDC_SYNCEN_WEN_MASK)); | |
147 | temp |= ((en << CCDC_SYNCEN_WEN_SHIFT) & CCDC_SYNCEN_WEN_MASK); | |
148 | regw(temp, SYNCEN); | |
149 | } | |
150 | ||
151 | static void ccdc_config_gain_offset(void) | |
152 | { | |
153 | /* configure gain */ | |
c70fc2d2 MK |
154 | regw(ccdc_cfg.bayer.gain.r_ye, RYEGAIN); |
155 | regw(ccdc_cfg.bayer.gain.gr_cy, GRCYGAIN); | |
156 | regw(ccdc_cfg.bayer.gain.gb_g, GBGGAIN); | |
157 | regw(ccdc_cfg.bayer.gain.b_mg, BMGGAIN); | |
dd2ceb1a | 158 | /* configure offset */ |
c70fc2d2 | 159 | regw(ccdc_cfg.bayer.ccdc_offset, OFFSET); |
dd2ceb1a MK |
160 | } |
161 | ||
162 | /* | |
163 | * ccdc_restore_defaults() | |
164 | * This function restore power on defaults in the ccdc registers | |
165 | */ | |
166 | static int ccdc_restore_defaults(void) | |
167 | { | |
168 | int i; | |
169 | ||
c70fc2d2 | 170 | dev_dbg(ccdc_cfg.dev, "\nstarting ccdc_restore_defaults..."); |
dd2ceb1a MK |
171 | /* set all registers to zero */ |
172 | for (i = 0; i <= CCDC_REG_LAST; i += 4) | |
173 | regw(0, i); | |
174 | ||
175 | /* now override the values with power on defaults in registers */ | |
176 | regw(MODESET_DEFAULT, MODESET); | |
177 | /* no culling support */ | |
178 | regw(CULH_DEFAULT, CULH); | |
179 | regw(CULV_DEFAULT, CULV); | |
180 | /* Set default Gain and Offset */ | |
c70fc2d2 MK |
181 | ccdc_cfg.bayer.gain.r_ye = GAIN_DEFAULT; |
182 | ccdc_cfg.bayer.gain.gb_g = GAIN_DEFAULT; | |
183 | ccdc_cfg.bayer.gain.gr_cy = GAIN_DEFAULT; | |
184 | ccdc_cfg.bayer.gain.b_mg = GAIN_DEFAULT; | |
dd2ceb1a MK |
185 | ccdc_config_gain_offset(); |
186 | regw(OUTCLIP_DEFAULT, OUTCLIP); | |
187 | regw(LSCCFG2_DEFAULT, LSCCFG2); | |
188 | /* select ccdc input */ | |
189 | if (vpss_select_ccdc_source(VPSS_CCDCIN)) { | |
c70fc2d2 | 190 | dev_dbg(ccdc_cfg.dev, "\ncouldn't select ccdc input source"); |
dd2ceb1a MK |
191 | return -EFAULT; |
192 | } | |
193 | /* select ccdc clock */ | |
194 | if (vpss_enable_clock(VPSS_CCDC_CLOCK, 1) < 0) { | |
c70fc2d2 | 195 | dev_dbg(ccdc_cfg.dev, "\ncouldn't enable ccdc clock"); |
dd2ceb1a MK |
196 | return -EFAULT; |
197 | } | |
c70fc2d2 | 198 | dev_dbg(ccdc_cfg.dev, "\nEnd of ccdc_restore_defaults..."); |
dd2ceb1a MK |
199 | return 0; |
200 | } | |
201 | ||
202 | static int ccdc_open(struct device *device) | |
203 | { | |
dd2ceb1a MK |
204 | return ccdc_restore_defaults(); |
205 | } | |
206 | ||
207 | static int ccdc_close(struct device *device) | |
208 | { | |
209 | /* disable clock */ | |
210 | vpss_enable_clock(VPSS_CCDC_CLOCK, 0); | |
211 | /* do nothing for now */ | |
212 | return 0; | |
213 | } | |
214 | /* | |
215 | * ccdc_setwin() | |
216 | * This function will configure the window size to | |
217 | * be capture in CCDC reg. | |
218 | */ | |
219 | static void ccdc_setwin(struct v4l2_rect *image_win, | |
220 | enum ccdc_frmfmt frm_fmt, int ppc) | |
221 | { | |
222 | int horz_start, horz_nr_pixels; | |
223 | int vert_start, vert_nr_lines; | |
224 | int mid_img = 0; | |
225 | ||
c70fc2d2 | 226 | dev_dbg(ccdc_cfg.dev, "\nStarting ccdc_setwin..."); |
dd2ceb1a MK |
227 | |
228 | /* | |
229 | * ppc - per pixel count. indicates how many pixels per cell | |
230 | * output to SDRAM. example, for ycbcr, it is one y and one c, so 2. | |
231 | * raw capture this is 1 | |
232 | */ | |
233 | horz_start = image_win->left << (ppc - 1); | |
234 | horz_nr_pixels = ((image_win->width) << (ppc - 1)) - 1; | |
235 | ||
236 | /* Writing the horizontal info into the registers */ | |
237 | regw(horz_start, SPH); | |
238 | regw(horz_nr_pixels, NPH); | |
239 | vert_start = image_win->top; | |
240 | ||
241 | if (frm_fmt == CCDC_FRMFMT_INTERLACED) { | |
242 | vert_nr_lines = (image_win->height >> 1) - 1; | |
243 | vert_start >>= 1; | |
244 | /* Since first line doesn't have any data */ | |
245 | vert_start += 1; | |
246 | /* configure VDINT0 and VDINT1 */ | |
247 | regw(vert_start, VDINT0); | |
248 | } else { | |
249 | /* Since first line doesn't have any data */ | |
250 | vert_start += 1; | |
251 | vert_nr_lines = image_win->height - 1; | |
252 | /* configure VDINT0 and VDINT1 */ | |
253 | mid_img = vert_start + (image_win->height / 2); | |
254 | regw(vert_start, VDINT0); | |
255 | regw(mid_img, VDINT1); | |
256 | } | |
257 | regw(vert_start & CCDC_START_VER_ONE_MASK, SLV0); | |
258 | regw(vert_start & CCDC_START_VER_TWO_MASK, SLV1); | |
259 | regw(vert_nr_lines & CCDC_NUM_LINES_VER, NLV); | |
c70fc2d2 | 260 | dev_dbg(ccdc_cfg.dev, "\nEnd of ccdc_setwin..."); |
dd2ceb1a MK |
261 | } |
262 | ||
263 | static int validate_ccdc_param(struct ccdc_config_params_raw *ccdcparam) | |
264 | { | |
265 | if (ccdcparam->datasft < CCDC_DATA_NO_SHIFT || | |
266 | ccdcparam->datasft > CCDC_DATA_SHIFT_6BIT) { | |
c70fc2d2 | 267 | dev_dbg(ccdc_cfg.dev, "Invalid value of data shift\n"); |
dd2ceb1a MK |
268 | return -EINVAL; |
269 | } | |
270 | ||
271 | if (ccdcparam->mfilt1 < CCDC_NO_MEDIAN_FILTER1 || | |
272 | ccdcparam->mfilt1 > CCDC_MEDIAN_FILTER1) { | |
c70fc2d2 | 273 | dev_dbg(ccdc_cfg.dev, "Invalid value of median filter1\n"); |
dd2ceb1a MK |
274 | return -EINVAL; |
275 | } | |
276 | ||
277 | if (ccdcparam->mfilt2 < CCDC_NO_MEDIAN_FILTER2 || | |
278 | ccdcparam->mfilt2 > CCDC_MEDIAN_FILTER2) { | |
c70fc2d2 | 279 | dev_dbg(ccdc_cfg.dev, "Invalid value of median filter2\n"); |
dd2ceb1a MK |
280 | return -EINVAL; |
281 | } | |
282 | ||
283 | if ((ccdcparam->med_filt_thres < 0) || | |
284 | (ccdcparam->med_filt_thres > CCDC_MED_FILT_THRESH)) { | |
c70fc2d2 | 285 | dev_dbg(ccdc_cfg.dev, |
c5f79f6a | 286 | "Invalid value of median filter threshold\n"); |
dd2ceb1a MK |
287 | return -EINVAL; |
288 | } | |
289 | ||
290 | if (ccdcparam->data_sz < CCDC_DATA_16BITS || | |
291 | ccdcparam->data_sz > CCDC_DATA_8BITS) { | |
c70fc2d2 | 292 | dev_dbg(ccdc_cfg.dev, "Invalid value of data size\n"); |
dd2ceb1a MK |
293 | return -EINVAL; |
294 | } | |
295 | ||
296 | if (ccdcparam->alaw.enable) { | |
db242f62 HV |
297 | if (ccdcparam->alaw.gamma_wd < CCDC_GAMMA_BITS_13_4 || |
298 | ccdcparam->alaw.gamma_wd > CCDC_GAMMA_BITS_09_0) { | |
c70fc2d2 | 299 | dev_dbg(ccdc_cfg.dev, "Invalid value of ALAW\n"); |
dd2ceb1a MK |
300 | return -EINVAL; |
301 | } | |
302 | } | |
303 | ||
304 | if (ccdcparam->blk_clamp.b_clamp_enable) { | |
305 | if (ccdcparam->blk_clamp.sample_pixel < CCDC_SAMPLE_1PIXELS || | |
306 | ccdcparam->blk_clamp.sample_pixel > CCDC_SAMPLE_16PIXELS) { | |
c70fc2d2 MK |
307 | dev_dbg(ccdc_cfg.dev, |
308 | "Invalid value of sample pixel\n"); | |
dd2ceb1a MK |
309 | return -EINVAL; |
310 | } | |
311 | if (ccdcparam->blk_clamp.sample_ln < CCDC_SAMPLE_1LINES || | |
312 | ccdcparam->blk_clamp.sample_ln > CCDC_SAMPLE_16LINES) { | |
c70fc2d2 MK |
313 | dev_dbg(ccdc_cfg.dev, |
314 | "Invalid value of sample lines\n"); | |
dd2ceb1a MK |
315 | return -EINVAL; |
316 | } | |
317 | } | |
318 | return 0; | |
319 | } | |
320 | ||
321 | /* Parameter operations */ | |
322 | static int ccdc_set_params(void __user *params) | |
323 | { | |
324 | struct ccdc_config_params_raw ccdc_raw_params; | |
325 | int x; | |
326 | ||
327 | /* only raw module parameters can be set through the IOCTL */ | |
c70fc2d2 | 328 | if (ccdc_cfg.if_type != VPFE_RAW_BAYER) |
dd2ceb1a MK |
329 | return -EINVAL; |
330 | ||
331 | x = copy_from_user(&ccdc_raw_params, params, sizeof(ccdc_raw_params)); | |
332 | if (x) { | |
ded026e0 MCC |
333 | dev_dbg(ccdc_cfg.dev, "ccdc_set_params: error in copying ccdcparams, %d\n", |
334 | x); | |
dd2ceb1a MK |
335 | return -EFAULT; |
336 | } | |
337 | ||
338 | if (!validate_ccdc_param(&ccdc_raw_params)) { | |
c70fc2d2 | 339 | memcpy(&ccdc_cfg.bayer.config_params, |
dd2ceb1a MK |
340 | &ccdc_raw_params, |
341 | sizeof(ccdc_raw_params)); | |
342 | return 0; | |
343 | } | |
344 | return -EINVAL; | |
345 | } | |
346 | ||
347 | /* This function will configure CCDC for YCbCr video capture */ | |
348 | static void ccdc_config_ycbcr(void) | |
349 | { | |
c70fc2d2 | 350 | struct ccdc_params_ycbcr *params = &ccdc_cfg.ycbcr; |
dd2ceb1a MK |
351 | u32 temp; |
352 | ||
353 | /* first set the CCDC power on defaults values in all registers */ | |
c70fc2d2 | 354 | dev_dbg(ccdc_cfg.dev, "\nStarting ccdc_config_ycbcr..."); |
dd2ceb1a MK |
355 | ccdc_restore_defaults(); |
356 | ||
357 | /* configure pixel format & video frame format */ | |
358 | temp = (((params->pix_fmt & CCDC_INPUT_MODE_MASK) << | |
359 | CCDC_INPUT_MODE_SHIFT) | | |
360 | ((params->frm_fmt & CCDC_FRM_FMT_MASK) << | |
361 | CCDC_FRM_FMT_SHIFT)); | |
362 | ||
363 | /* setup BT.656 sync mode */ | |
364 | if (params->bt656_enable) { | |
365 | regw(CCDC_REC656IF_BT656_EN, REC656IF); | |
366 | /* | |
367 | * configure the FID, VD, HD pin polarity fld,hd pol positive, | |
368 | * vd negative, 8-bit pack mode | |
369 | */ | |
370 | temp |= CCDC_VD_POL_NEGATIVE; | |
371 | } else { /* y/c external sync mode */ | |
372 | temp |= (((params->fid_pol & CCDC_FID_POL_MASK) << | |
373 | CCDC_FID_POL_SHIFT) | | |
374 | ((params->hd_pol & CCDC_HD_POL_MASK) << | |
375 | CCDC_HD_POL_SHIFT) | | |
376 | ((params->vd_pol & CCDC_VD_POL_MASK) << | |
377 | CCDC_VD_POL_SHIFT)); | |
378 | } | |
379 | ||
380 | /* pack the data to 8-bit */ | |
381 | temp |= CCDC_DATA_PACK_ENABLE; | |
382 | ||
383 | regw(temp, MODESET); | |
384 | ||
385 | /* configure video window */ | |
386 | ccdc_setwin(¶ms->win, params->frm_fmt, 2); | |
387 | ||
388 | /* configure the order of y cb cr in SD-RAM */ | |
389 | temp = (params->pix_order << CCDC_Y8POS_SHIFT); | |
390 | temp |= CCDC_LATCH_ON_VSYNC_DISABLE | CCDC_CCDCFG_FIDMD_NO_LATCH_VSYNC; | |
391 | regw(temp, CCDCFG); | |
392 | ||
393 | /* | |
394 | * configure the horizontal line offset. This is done by rounding up | |
395 | * width to a multiple of 16 pixels and multiply by two to account for | |
396 | * y:cb:cr 4:2:2 data | |
397 | */ | |
398 | regw(((params->win.width * 2 + 31) >> 5), HSIZE); | |
399 | ||
400 | /* configure the memory line offset */ | |
401 | if (params->buf_type == CCDC_BUFTYPE_FLD_INTERLEAVED) { | |
402 | /* two fields are interleaved in memory */ | |
403 | regw(CCDC_SDOFST_FIELD_INTERLEAVED, SDOFST); | |
404 | } | |
405 | ||
c70fc2d2 | 406 | dev_dbg(ccdc_cfg.dev, "\nEnd of ccdc_config_ycbcr...\n"); |
dd2ceb1a MK |
407 | } |
408 | ||
409 | /* | |
410 | * ccdc_config_black_clamp() | |
411 | * configure parameters for Optical Black Clamp | |
412 | */ | |
413 | static void ccdc_config_black_clamp(struct ccdc_black_clamp *bclamp) | |
414 | { | |
415 | u32 val; | |
416 | ||
417 | if (!bclamp->b_clamp_enable) { | |
418 | /* configure DCSub */ | |
419 | regw(bclamp->dc_sub & CCDC_BLK_DC_SUB_MASK, DCSUB); | |
420 | regw(0x0000, CLAMP); | |
421 | return; | |
422 | } | |
423 | /* Enable the Black clamping, set sample lines and pixels */ | |
424 | val = (bclamp->start_pixel & CCDC_BLK_ST_PXL_MASK) | | |
425 | ((bclamp->sample_pixel & CCDC_BLK_SAMPLE_LN_MASK) << | |
426 | CCDC_BLK_SAMPLE_LN_SHIFT) | CCDC_BLK_CLAMP_ENABLE; | |
427 | regw(val, CLAMP); | |
428 | ||
429 | /* If Black clamping is enable then make dcsub 0 */ | |
430 | val = (bclamp->sample_ln & CCDC_NUM_LINE_CALC_MASK) | |
431 | << CCDC_NUM_LINE_CALC_SHIFT; | |
432 | regw(val, DCSUB); | |
433 | } | |
434 | ||
435 | /* | |
436 | * ccdc_config_black_compense() | |
437 | * configure parameters for Black Compensation | |
438 | */ | |
439 | static void ccdc_config_black_compense(struct ccdc_black_compensation *bcomp) | |
440 | { | |
441 | u32 val; | |
442 | ||
443 | val = (bcomp->b & CCDC_BLK_COMP_MASK) | | |
444 | ((bcomp->gb & CCDC_BLK_COMP_MASK) << | |
445 | CCDC_BLK_COMP_GB_COMP_SHIFT); | |
446 | regw(val, BLKCMP1); | |
447 | ||
448 | val = ((bcomp->gr & CCDC_BLK_COMP_MASK) << | |
449 | CCDC_BLK_COMP_GR_COMP_SHIFT) | | |
450 | ((bcomp->r & CCDC_BLK_COMP_MASK) << | |
451 | CCDC_BLK_COMP_R_COMP_SHIFT); | |
452 | regw(val, BLKCMP0); | |
453 | } | |
454 | ||
455 | /* | |
456 | * ccdc_write_dfc_entry() | |
457 | * write an entry in the dfc table. | |
458 | */ | |
0448056c | 459 | static int ccdc_write_dfc_entry(int index, struct ccdc_vertical_dft *dfc) |
dd2ceb1a MK |
460 | { |
461 | /* TODO This is to be re-visited and adjusted */ | |
462 | #define DFC_WRITE_WAIT_COUNT 1000 | |
463 | u32 val, count = DFC_WRITE_WAIT_COUNT; | |
464 | ||
465 | regw(dfc->dft_corr_vert[index], DFCMEM0); | |
466 | regw(dfc->dft_corr_horz[index], DFCMEM1); | |
467 | regw(dfc->dft_corr_sub1[index], DFCMEM2); | |
468 | regw(dfc->dft_corr_sub2[index], DFCMEM3); | |
469 | regw(dfc->dft_corr_sub3[index], DFCMEM4); | |
470 | /* set WR bit to write */ | |
471 | val = regr(DFCMEMCTL) | CCDC_DFCMEMCTL_DFCMWR_MASK; | |
472 | regw(val, DFCMEMCTL); | |
473 | ||
474 | /* | |
475 | * Assume, it is very short. If we get an error, we need to | |
476 | * adjust this value | |
477 | */ | |
478 | while (regr(DFCMEMCTL) & CCDC_DFCMEMCTL_DFCMWR_MASK) | |
479 | count--; | |
480 | /* | |
481 | * TODO We expect the count to be non-zero to be successful. Adjust | |
482 | * the count if write requires more time | |
483 | */ | |
484 | ||
485 | if (count) { | |
c70fc2d2 | 486 | dev_err(ccdc_cfg.dev, "defect table write timeout !!!\n"); |
dd2ceb1a MK |
487 | return -1; |
488 | } | |
489 | return 0; | |
490 | } | |
491 | ||
492 | /* | |
493 | * ccdc_config_vdfc() | |
494 | * configure parameters for Vertical Defect Correction | |
495 | */ | |
496 | static int ccdc_config_vdfc(struct ccdc_vertical_dft *dfc) | |
497 | { | |
498 | u32 val; | |
499 | int i; | |
500 | ||
501 | /* Configure General Defect Correction. The table used is from IPIPE */ | |
502 | val = dfc->gen_dft_en & CCDC_DFCCTL_GDFCEN_MASK; | |
503 | ||
504 | /* Configure Vertical Defect Correction if needed */ | |
505 | if (!dfc->ver_dft_en) { | |
506 | /* Enable only General Defect Correction */ | |
507 | regw(val, DFCCTL); | |
508 | return 0; | |
509 | } | |
510 | ||
511 | if (dfc->table_size > CCDC_DFT_TABLE_SIZE) | |
512 | return -EINVAL; | |
513 | ||
514 | val |= CCDC_DFCCTL_VDFC_DISABLE; | |
515 | val |= (dfc->dft_corr_ctl.vdfcsl & CCDC_DFCCTL_VDFCSL_MASK) << | |
516 | CCDC_DFCCTL_VDFCSL_SHIFT; | |
517 | val |= (dfc->dft_corr_ctl.vdfcuda & CCDC_DFCCTL_VDFCUDA_MASK) << | |
518 | CCDC_DFCCTL_VDFCUDA_SHIFT; | |
519 | val |= (dfc->dft_corr_ctl.vdflsft & CCDC_DFCCTL_VDFLSFT_MASK) << | |
520 | CCDC_DFCCTL_VDFLSFT_SHIFT; | |
521 | regw(val , DFCCTL); | |
522 | ||
523 | /* clear address ptr to offset 0 */ | |
524 | val = CCDC_DFCMEMCTL_DFCMARST_MASK << CCDC_DFCMEMCTL_DFCMARST_SHIFT; | |
525 | ||
526 | /* write defect table entries */ | |
527 | for (i = 0; i < dfc->table_size; i++) { | |
528 | /* increment address for non zero index */ | |
529 | if (i != 0) | |
530 | val = CCDC_DFCMEMCTL_INC_ADDR; | |
531 | regw(val, DFCMEMCTL); | |
532 | if (ccdc_write_dfc_entry(i, dfc) < 0) | |
533 | return -EFAULT; | |
534 | } | |
535 | ||
536 | /* update saturation level and enable dfc */ | |
537 | regw(dfc->saturation_ctl & CCDC_VDC_DFCVSAT_MASK, DFCVSAT); | |
538 | val = regr(DFCCTL) | (CCDC_DFCCTL_VDFCEN_MASK << | |
539 | CCDC_DFCCTL_VDFCEN_SHIFT); | |
540 | regw(val, DFCCTL); | |
541 | return 0; | |
542 | } | |
543 | ||
544 | /* | |
545 | * ccdc_config_csc() | |
546 | * configure parameters for color space conversion | |
547 | * Each register CSCM0-7 has two values in S8Q5 format. | |
548 | */ | |
549 | static void ccdc_config_csc(struct ccdc_csc *csc) | |
550 | { | |
b9f1fbcd | 551 | u32 val1 = 0, val2; |
dd2ceb1a MK |
552 | int i; |
553 | ||
554 | if (!csc->enable) | |
555 | return; | |
556 | ||
557 | /* Enable the CSC sub-module */ | |
558 | regw(CCDC_CSC_ENABLE, CSCCTL); | |
559 | ||
560 | /* Converting the co-eff as per the format of the register */ | |
561 | for (i = 0; i < CCDC_CSC_COEFF_TABLE_SIZE; i++) { | |
562 | if ((i % 2) == 0) { | |
563 | /* CSCM - LSB */ | |
564 | val1 = (csc->coeff[i].integer & | |
565 | CCDC_CSC_COEF_INTEG_MASK) | |
566 | << CCDC_CSC_COEF_INTEG_SHIFT; | |
567 | /* | |
568 | * convert decimal part to binary. Use 2 decimal | |
569 | * precision, user values range from .00 - 0.99 | |
570 | */ | |
571 | val1 |= (((csc->coeff[i].decimal & | |
572 | CCDC_CSC_COEF_DECIMAL_MASK) * | |
573 | CCDC_CSC_DEC_MAX) / 100); | |
574 | } else { | |
575 | ||
576 | /* CSCM - MSB */ | |
577 | val2 = (csc->coeff[i].integer & | |
578 | CCDC_CSC_COEF_INTEG_MASK) | |
579 | << CCDC_CSC_COEF_INTEG_SHIFT; | |
580 | val2 |= (((csc->coeff[i].decimal & | |
581 | CCDC_CSC_COEF_DECIMAL_MASK) * | |
582 | CCDC_CSC_DEC_MAX) / 100); | |
583 | val2 <<= CCDC_CSCM_MSB_SHIFT; | |
584 | val2 |= val1; | |
585 | regw(val2, (CSCM0 + ((i - 1) << 1))); | |
586 | } | |
587 | } | |
588 | } | |
589 | ||
590 | /* | |
591 | * ccdc_config_color_patterns() | |
592 | * configure parameters for color patterns | |
593 | */ | |
594 | static void ccdc_config_color_patterns(struct ccdc_col_pat *pat0, | |
595 | struct ccdc_col_pat *pat1) | |
596 | { | |
597 | u32 val; | |
598 | ||
599 | val = (pat0->olop | (pat0->olep << 2) | (pat0->elop << 4) | | |
600 | (pat0->elep << 6) | (pat1->olop << 8) | (pat1->olep << 10) | | |
601 | (pat1->elop << 12) | (pat1->elep << 14)); | |
602 | regw(val, COLPTN); | |
603 | } | |
604 | ||
605 | /* This function will configure CCDC for Raw mode image capture */ | |
606 | static int ccdc_config_raw(void) | |
607 | { | |
c70fc2d2 | 608 | struct ccdc_params_raw *params = &ccdc_cfg.bayer; |
dd2ceb1a | 609 | struct ccdc_config_params_raw *config_params = |
c70fc2d2 | 610 | &ccdc_cfg.bayer.config_params; |
dd2ceb1a MK |
611 | unsigned int val; |
612 | ||
c70fc2d2 | 613 | dev_dbg(ccdc_cfg.dev, "\nStarting ccdc_config_raw..."); |
dd2ceb1a MK |
614 | |
615 | /* restore power on defaults to register */ | |
616 | ccdc_restore_defaults(); | |
617 | ||
618 | /* CCDCFG register: | |
619 | * set CCD Not to swap input since input is RAW data | |
620 | * set FID detection function to Latch at V-Sync | |
621 | * set WENLOG - ccdc valid area to AND | |
622 | * set TRGSEL to WENBIT | |
623 | * set EXTRG to DISABLE | |
624 | * disable latching function on VSYNC - shadowed registers | |
625 | */ | |
626 | regw(CCDC_YCINSWP_RAW | CCDC_CCDCFG_FIDMD_LATCH_VSYNC | | |
627 | CCDC_CCDCFG_WENLOG_AND | CCDC_CCDCFG_TRGSEL_WEN | | |
628 | CCDC_CCDCFG_EXTRG_DISABLE | CCDC_LATCH_ON_VSYNC_DISABLE, CCDCFG); | |
629 | ||
630 | /* | |
631 | * Set VDHD direction to input, input type to raw input | |
632 | * normal data polarity, do not use external WEN | |
633 | */ | |
634 | val = (CCDC_VDHDOUT_INPUT | CCDC_RAW_IP_MODE | CCDC_DATAPOL_NORMAL | | |
635 | CCDC_EXWEN_DISABLE); | |
636 | ||
637 | /* | |
638 | * Configure the vertical sync polarity (MODESET.VDPOL), horizontal | |
639 | * sync polarity (MODESET.HDPOL), field id polarity (MODESET.FLDPOL), | |
640 | * frame format(progressive or interlace), & pixel format (Input mode) | |
641 | */ | |
642 | val |= (((params->vd_pol & CCDC_VD_POL_MASK) << CCDC_VD_POL_SHIFT) | | |
643 | ((params->hd_pol & CCDC_HD_POL_MASK) << CCDC_HD_POL_SHIFT) | | |
644 | ((params->fid_pol & CCDC_FID_POL_MASK) << CCDC_FID_POL_SHIFT) | | |
645 | ((params->frm_fmt & CCDC_FRM_FMT_MASK) << CCDC_FRM_FMT_SHIFT) | | |
646 | ((params->pix_fmt & CCDC_PIX_FMT_MASK) << CCDC_PIX_FMT_SHIFT)); | |
647 | ||
648 | /* set pack for alaw compression */ | |
649 | if ((config_params->data_sz == CCDC_DATA_8BITS) || | |
650 | config_params->alaw.enable) | |
651 | val |= CCDC_DATA_PACK_ENABLE; | |
652 | ||
653 | /* Configure for LPF */ | |
654 | if (config_params->lpf_enable) | |
655 | val |= (config_params->lpf_enable & CCDC_LPF_MASK) << | |
656 | CCDC_LPF_SHIFT; | |
657 | ||
658 | /* Configure the data shift */ | |
659 | val |= (config_params->datasft & CCDC_DATASFT_MASK) << | |
660 | CCDC_DATASFT_SHIFT; | |
661 | regw(val , MODESET); | |
c70fc2d2 | 662 | dev_dbg(ccdc_cfg.dev, "\nWriting 0x%x to MODESET...\n", val); |
dd2ceb1a MK |
663 | |
664 | /* Configure the Median Filter threshold */ | |
665 | regw((config_params->med_filt_thres) & CCDC_MED_FILT_THRESH, MEDFILT); | |
666 | ||
667 | /* Configure GAMMAWD register. defaur 11-2, and Mosaic cfa pattern */ | |
668 | val = CCDC_GAMMA_BITS_11_2 << CCDC_GAMMAWD_INPUT_SHIFT | | |
669 | CCDC_CFA_MOSAIC; | |
670 | ||
671 | /* Enable and configure aLaw register if needed */ | |
672 | if (config_params->alaw.enable) { | |
673 | val |= (CCDC_ALAW_ENABLE | | |
db242f62 HV |
674 | ((config_params->alaw.gamma_wd & |
675 | CCDC_ALAW_GAMMA_WD_MASK) << | |
dd2ceb1a MK |
676 | CCDC_GAMMAWD_INPUT_SHIFT)); |
677 | } | |
678 | ||
679 | /* Configure Median filter1 & filter2 */ | |
680 | val |= ((config_params->mfilt1 << CCDC_MFILT1_SHIFT) | | |
681 | (config_params->mfilt2 << CCDC_MFILT2_SHIFT)); | |
682 | ||
683 | regw(val, GAMMAWD); | |
c70fc2d2 | 684 | dev_dbg(ccdc_cfg.dev, "\nWriting 0x%x to GAMMAWD...\n", val); |
dd2ceb1a MK |
685 | |
686 | /* configure video window */ | |
687 | ccdc_setwin(¶ms->win, params->frm_fmt, 1); | |
688 | ||
689 | /* Optical Clamp Averaging */ | |
690 | ccdc_config_black_clamp(&config_params->blk_clamp); | |
691 | ||
692 | /* Black level compensation */ | |
693 | ccdc_config_black_compense(&config_params->blk_comp); | |
694 | ||
695 | /* Vertical Defect Correction if needed */ | |
696 | if (ccdc_config_vdfc(&config_params->vertical_dft) < 0) | |
697 | return -EFAULT; | |
698 | ||
699 | /* color space conversion */ | |
700 | ccdc_config_csc(&config_params->csc); | |
701 | ||
702 | /* color pattern */ | |
703 | ccdc_config_color_patterns(&config_params->col_pat_field0, | |
704 | &config_params->col_pat_field1); | |
705 | ||
706 | /* Configure the Gain & offset control */ | |
707 | ccdc_config_gain_offset(); | |
708 | ||
c70fc2d2 | 709 | dev_dbg(ccdc_cfg.dev, "\nWriting %x to COLPTN...\n", val); |
dd2ceb1a MK |
710 | |
711 | /* Configure DATAOFST register */ | |
712 | val = (config_params->data_offset.horz_offset & CCDC_DATAOFST_MASK) << | |
713 | CCDC_DATAOFST_H_SHIFT; | |
714 | val |= (config_params->data_offset.vert_offset & CCDC_DATAOFST_MASK) << | |
715 | CCDC_DATAOFST_V_SHIFT; | |
716 | regw(val, DATAOFST); | |
717 | ||
718 | /* configuring HSIZE register */ | |
719 | val = (params->horz_flip_enable & CCDC_HSIZE_FLIP_MASK) << | |
720 | CCDC_HSIZE_FLIP_SHIFT; | |
721 | ||
722 | /* If pack 8 is enable then 1 pixel will take 1 byte */ | |
723 | if ((config_params->data_sz == CCDC_DATA_8BITS) || | |
724 | config_params->alaw.enable) { | |
725 | val |= (((params->win.width) + 31) >> 5) & | |
726 | CCDC_HSIZE_VAL_MASK; | |
727 | ||
728 | /* adjust to multiple of 32 */ | |
c70fc2d2 | 729 | dev_dbg(ccdc_cfg.dev, "\nWriting 0x%x to HSIZE...\n", |
dd2ceb1a MK |
730 | (((params->win.width) + 31) >> 5) & |
731 | CCDC_HSIZE_VAL_MASK); | |
732 | } else { | |
733 | /* else one pixel will take 2 byte */ | |
734 | val |= (((params->win.width * 2) + 31) >> 5) & | |
735 | CCDC_HSIZE_VAL_MASK; | |
736 | ||
c70fc2d2 | 737 | dev_dbg(ccdc_cfg.dev, "\nWriting 0x%x to HSIZE...\n", |
dd2ceb1a MK |
738 | (((params->win.width * 2) + 31) >> 5) & |
739 | CCDC_HSIZE_VAL_MASK); | |
740 | } | |
741 | regw(val, HSIZE); | |
742 | ||
743 | /* Configure SDOFST register */ | |
744 | if (params->frm_fmt == CCDC_FRMFMT_INTERLACED) { | |
745 | if (params->image_invert_enable) { | |
746 | /* For interlace inverse mode */ | |
747 | regw(CCDC_SDOFST_INTERLACE_INVERSE, SDOFST); | |
c70fc2d2 | 748 | dev_dbg(ccdc_cfg.dev, "\nWriting %x to SDOFST...\n", |
dd2ceb1a MK |
749 | CCDC_SDOFST_INTERLACE_INVERSE); |
750 | } else { | |
751 | /* For interlace non inverse mode */ | |
752 | regw(CCDC_SDOFST_INTERLACE_NORMAL, SDOFST); | |
c70fc2d2 | 753 | dev_dbg(ccdc_cfg.dev, "\nWriting %x to SDOFST...\n", |
dd2ceb1a MK |
754 | CCDC_SDOFST_INTERLACE_NORMAL); |
755 | } | |
756 | } else if (params->frm_fmt == CCDC_FRMFMT_PROGRESSIVE) { | |
757 | if (params->image_invert_enable) { | |
758 | /* For progessive inverse mode */ | |
759 | regw(CCDC_SDOFST_PROGRESSIVE_INVERSE, SDOFST); | |
c70fc2d2 | 760 | dev_dbg(ccdc_cfg.dev, "\nWriting %x to SDOFST...\n", |
dd2ceb1a MK |
761 | CCDC_SDOFST_PROGRESSIVE_INVERSE); |
762 | } else { | |
763 | /* For progessive non inverse mode */ | |
764 | regw(CCDC_SDOFST_PROGRESSIVE_NORMAL, SDOFST); | |
c70fc2d2 | 765 | dev_dbg(ccdc_cfg.dev, "\nWriting %x to SDOFST...\n", |
dd2ceb1a MK |
766 | CCDC_SDOFST_PROGRESSIVE_NORMAL); |
767 | } | |
768 | } | |
c70fc2d2 | 769 | dev_dbg(ccdc_cfg.dev, "\nend of ccdc_config_raw..."); |
dd2ceb1a MK |
770 | return 0; |
771 | } | |
772 | ||
773 | static int ccdc_configure(void) | |
774 | { | |
c70fc2d2 | 775 | if (ccdc_cfg.if_type == VPFE_RAW_BAYER) |
dd2ceb1a MK |
776 | return ccdc_config_raw(); |
777 | else | |
778 | ccdc_config_ycbcr(); | |
779 | return 0; | |
780 | } | |
781 | ||
782 | static int ccdc_set_buftype(enum ccdc_buftype buf_type) | |
783 | { | |
c70fc2d2 MK |
784 | if (ccdc_cfg.if_type == VPFE_RAW_BAYER) |
785 | ccdc_cfg.bayer.buf_type = buf_type; | |
dd2ceb1a | 786 | else |
c70fc2d2 | 787 | ccdc_cfg.ycbcr.buf_type = buf_type; |
dd2ceb1a MK |
788 | return 0; |
789 | } | |
790 | static enum ccdc_buftype ccdc_get_buftype(void) | |
791 | { | |
c70fc2d2 MK |
792 | if (ccdc_cfg.if_type == VPFE_RAW_BAYER) |
793 | return ccdc_cfg.bayer.buf_type; | |
794 | return ccdc_cfg.ycbcr.buf_type; | |
dd2ceb1a MK |
795 | } |
796 | ||
797 | static int ccdc_enum_pix(u32 *pix, int i) | |
798 | { | |
799 | int ret = -EINVAL; | |
c70fc2d2 | 800 | if (ccdc_cfg.if_type == VPFE_RAW_BAYER) { |
dd2ceb1a MK |
801 | if (i < ARRAY_SIZE(ccdc_raw_bayer_pix_formats)) { |
802 | *pix = ccdc_raw_bayer_pix_formats[i]; | |
803 | ret = 0; | |
804 | } | |
805 | } else { | |
806 | if (i < ARRAY_SIZE(ccdc_raw_yuv_pix_formats)) { | |
807 | *pix = ccdc_raw_yuv_pix_formats[i]; | |
808 | ret = 0; | |
809 | } | |
810 | } | |
811 | return ret; | |
812 | } | |
813 | ||
814 | static int ccdc_set_pixel_format(u32 pixfmt) | |
815 | { | |
c70fc2d2 | 816 | struct ccdc_a_law *alaw = &ccdc_cfg.bayer.config_params.alaw; |
dd2ceb1a | 817 | |
c70fc2d2 MK |
818 | if (ccdc_cfg.if_type == VPFE_RAW_BAYER) { |
819 | ccdc_cfg.bayer.pix_fmt = CCDC_PIXFMT_RAW; | |
dd2ceb1a MK |
820 | if (pixfmt == V4L2_PIX_FMT_SBGGR8) |
821 | alaw->enable = 1; | |
822 | else if (pixfmt != V4L2_PIX_FMT_SBGGR16) | |
823 | return -EINVAL; | |
824 | } else { | |
825 | if (pixfmt == V4L2_PIX_FMT_YUYV) | |
c70fc2d2 | 826 | ccdc_cfg.ycbcr.pix_order = CCDC_PIXORDER_YCBYCR; |
dd2ceb1a | 827 | else if (pixfmt == V4L2_PIX_FMT_UYVY) |
c70fc2d2 | 828 | ccdc_cfg.ycbcr.pix_order = CCDC_PIXORDER_CBYCRY; |
dd2ceb1a MK |
829 | else |
830 | return -EINVAL; | |
831 | } | |
832 | return 0; | |
833 | } | |
834 | static u32 ccdc_get_pixel_format(void) | |
835 | { | |
c70fc2d2 | 836 | struct ccdc_a_law *alaw = &ccdc_cfg.bayer.config_params.alaw; |
dd2ceb1a MK |
837 | u32 pixfmt; |
838 | ||
c70fc2d2 | 839 | if (ccdc_cfg.if_type == VPFE_RAW_BAYER) |
dd2ceb1a MK |
840 | if (alaw->enable) |
841 | pixfmt = V4L2_PIX_FMT_SBGGR8; | |
842 | else | |
843 | pixfmt = V4L2_PIX_FMT_SBGGR16; | |
844 | else { | |
c70fc2d2 | 845 | if (ccdc_cfg.ycbcr.pix_order == CCDC_PIXORDER_YCBYCR) |
dd2ceb1a MK |
846 | pixfmt = V4L2_PIX_FMT_YUYV; |
847 | else | |
848 | pixfmt = V4L2_PIX_FMT_UYVY; | |
849 | } | |
850 | return pixfmt; | |
851 | } | |
852 | static int ccdc_set_image_window(struct v4l2_rect *win) | |
853 | { | |
c70fc2d2 MK |
854 | if (ccdc_cfg.if_type == VPFE_RAW_BAYER) |
855 | ccdc_cfg.bayer.win = *win; | |
dd2ceb1a | 856 | else |
c70fc2d2 | 857 | ccdc_cfg.ycbcr.win = *win; |
dd2ceb1a MK |
858 | return 0; |
859 | } | |
860 | ||
861 | static void ccdc_get_image_window(struct v4l2_rect *win) | |
862 | { | |
c70fc2d2 MK |
863 | if (ccdc_cfg.if_type == VPFE_RAW_BAYER) |
864 | *win = ccdc_cfg.bayer.win; | |
dd2ceb1a | 865 | else |
c70fc2d2 | 866 | *win = ccdc_cfg.ycbcr.win; |
dd2ceb1a MK |
867 | } |
868 | ||
869 | static unsigned int ccdc_get_line_length(void) | |
870 | { | |
871 | struct ccdc_config_params_raw *config_params = | |
c70fc2d2 | 872 | &ccdc_cfg.bayer.config_params; |
dd2ceb1a MK |
873 | unsigned int len; |
874 | ||
c70fc2d2 | 875 | if (ccdc_cfg.if_type == VPFE_RAW_BAYER) { |
dd2ceb1a MK |
876 | if ((config_params->alaw.enable) || |
877 | (config_params->data_sz == CCDC_DATA_8BITS)) | |
c70fc2d2 | 878 | len = ccdc_cfg.bayer.win.width; |
dd2ceb1a | 879 | else |
c70fc2d2 | 880 | len = ccdc_cfg.bayer.win.width * 2; |
dd2ceb1a | 881 | } else |
c70fc2d2 | 882 | len = ccdc_cfg.ycbcr.win.width * 2; |
dd2ceb1a MK |
883 | return ALIGN(len, 32); |
884 | } | |
885 | ||
886 | static int ccdc_set_frame_format(enum ccdc_frmfmt frm_fmt) | |
887 | { | |
c70fc2d2 MK |
888 | if (ccdc_cfg.if_type == VPFE_RAW_BAYER) |
889 | ccdc_cfg.bayer.frm_fmt = frm_fmt; | |
dd2ceb1a | 890 | else |
c70fc2d2 | 891 | ccdc_cfg.ycbcr.frm_fmt = frm_fmt; |
dd2ceb1a MK |
892 | return 0; |
893 | } | |
894 | ||
895 | static enum ccdc_frmfmt ccdc_get_frame_format(void) | |
896 | { | |
c70fc2d2 MK |
897 | if (ccdc_cfg.if_type == VPFE_RAW_BAYER) |
898 | return ccdc_cfg.bayer.frm_fmt; | |
dd2ceb1a | 899 | else |
c70fc2d2 | 900 | return ccdc_cfg.ycbcr.frm_fmt; |
dd2ceb1a MK |
901 | } |
902 | ||
903 | static int ccdc_getfid(void) | |
904 | { | |
905 | return (regr(MODESET) >> 15) & 1; | |
906 | } | |
907 | ||
908 | /* misc operations */ | |
909 | static inline void ccdc_setfbaddr(unsigned long addr) | |
910 | { | |
911 | regw((addr >> 21) & 0x007f, STADRH); | |
912 | regw((addr >> 5) & 0x0ffff, STADRL); | |
913 | } | |
914 | ||
915 | static int ccdc_set_hw_if_params(struct vpfe_hw_if_param *params) | |
916 | { | |
c70fc2d2 | 917 | ccdc_cfg.if_type = params->if_type; |
dd2ceb1a MK |
918 | |
919 | switch (params->if_type) { | |
920 | case VPFE_BT656: | |
921 | case VPFE_YCBCR_SYNC_16: | |
922 | case VPFE_YCBCR_SYNC_8: | |
c70fc2d2 MK |
923 | ccdc_cfg.ycbcr.vd_pol = params->vdpol; |
924 | ccdc_cfg.ycbcr.hd_pol = params->hdpol; | |
dd2ceb1a MK |
925 | break; |
926 | default: | |
927 | /* TODO add support for raw bayer here */ | |
928 | return -EINVAL; | |
929 | } | |
930 | return 0; | |
931 | } | |
932 | ||
933 | static struct ccdc_hw_device ccdc_hw_dev = { | |
934 | .name = "DM355 CCDC", | |
935 | .owner = THIS_MODULE, | |
936 | .hw_ops = { | |
937 | .open = ccdc_open, | |
938 | .close = ccdc_close, | |
dd2ceb1a MK |
939 | .enable = ccdc_enable, |
940 | .enable_out_to_sdram = ccdc_enable_output_to_sdram, | |
941 | .set_hw_if_params = ccdc_set_hw_if_params, | |
942 | .set_params = ccdc_set_params, | |
943 | .configure = ccdc_configure, | |
944 | .set_buftype = ccdc_set_buftype, | |
945 | .get_buftype = ccdc_get_buftype, | |
946 | .enum_pix = ccdc_enum_pix, | |
947 | .set_pixel_format = ccdc_set_pixel_format, | |
948 | .get_pixel_format = ccdc_get_pixel_format, | |
949 | .set_frame_format = ccdc_set_frame_format, | |
950 | .get_frame_format = ccdc_get_frame_format, | |
951 | .set_image_window = ccdc_set_image_window, | |
952 | .get_image_window = ccdc_get_image_window, | |
953 | .get_line_length = ccdc_get_line_length, | |
954 | .setfbaddr = ccdc_setfbaddr, | |
955 | .getfid = ccdc_getfid, | |
956 | }, | |
957 | }; | |
958 | ||
4c62e976 | 959 | static int dm355_ccdc_probe(struct platform_device *pdev) |
dd2ceb1a | 960 | { |
c70fc2d2 MK |
961 | void (*setup_pinmux)(void); |
962 | struct resource *res; | |
963 | int status = 0; | |
964 | ||
965 | /* | |
966 | * first try to register with vpfe. If not correct platform, then we | |
967 | * don't have to iomap | |
968 | */ | |
969 | status = vpfe_register_ccdc_device(&ccdc_hw_dev); | |
970 | if (status < 0) | |
971 | return status; | |
972 | ||
973 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
974 | if (!res) { | |
975 | status = -ENODEV; | |
976 | goto fail_nores; | |
977 | } | |
978 | ||
979 | res = request_mem_region(res->start, resource_size(res), res->name); | |
980 | if (!res) { | |
981 | status = -EBUSY; | |
982 | goto fail_nores; | |
983 | } | |
984 | ||
985 | ccdc_cfg.base_addr = ioremap_nocache(res->start, resource_size(res)); | |
986 | if (!ccdc_cfg.base_addr) { | |
987 | status = -ENOMEM; | |
988 | goto fail_nomem; | |
989 | } | |
990 | ||
c70fc2d2 MK |
991 | /* Platform data holds setup_pinmux function ptr */ |
992 | if (NULL == pdev->dev.platform_data) { | |
993 | status = -ENODEV; | |
9a3e89b1 | 994 | goto fail_nomap; |
c70fc2d2 MK |
995 | } |
996 | setup_pinmux = pdev->dev.platform_data; | |
997 | /* | |
998 | * setup Mux configuration for ccdc which may be different for | |
999 | * different SoCs using this CCDC | |
1000 | */ | |
1001 | setup_pinmux(); | |
1002 | ccdc_cfg.dev = &pdev->dev; | |
1003 | printk(KERN_NOTICE "%s is registered with vpfe.\n", ccdc_hw_dev.name); | |
dd2ceb1a | 1004 | return 0; |
c70fc2d2 MK |
1005 | fail_nomap: |
1006 | iounmap(ccdc_cfg.base_addr); | |
1007 | fail_nomem: | |
1008 | release_mem_region(res->start, resource_size(res)); | |
1009 | fail_nores: | |
1010 | vpfe_unregister_ccdc_device(&ccdc_hw_dev); | |
1011 | return status; | |
dd2ceb1a MK |
1012 | } |
1013 | ||
c70fc2d2 | 1014 | static int dm355_ccdc_remove(struct platform_device *pdev) |
dd2ceb1a | 1015 | { |
c70fc2d2 MK |
1016 | struct resource *res; |
1017 | ||
c70fc2d2 MK |
1018 | iounmap(ccdc_cfg.base_addr); |
1019 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1020 | if (res) | |
1021 | release_mem_region(res->start, resource_size(res)); | |
dd2ceb1a | 1022 | vpfe_unregister_ccdc_device(&ccdc_hw_dev); |
c70fc2d2 MK |
1023 | return 0; |
1024 | } | |
1025 | ||
a1b3a6ce | 1026 | static struct platform_driver dm355_ccdc_driver = { |
c70fc2d2 MK |
1027 | .driver = { |
1028 | .name = "dm355_ccdc", | |
c70fc2d2 | 1029 | }, |
4c62e976 | 1030 | .remove = dm355_ccdc_remove, |
c70fc2d2 MK |
1031 | .probe = dm355_ccdc_probe, |
1032 | }; | |
1033 | ||
1d6629b1 | 1034 | module_platform_driver(dm355_ccdc_driver); |