[mirror_ubuntu-hirsute-kernel.git] / drivers / media / platform / davinci / vpss.c

/*
 * Copyright (C) 2009 Texas Instruments.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * common vpss system module platform driver for all video drivers.
 */
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/pm_runtime.h>
#include <linux/err.h>

#include <media/davinci/vpss.h>

MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("VPSS Driver");
MODULE_AUTHOR("Texas Instruments");

/* DM644x defines */
#define DM644X_SBL_PCR_VPSS		(4)

#define DM355_VPSSBL_INTSEL		0x10
#define DM355_VPSSBL_EVTSEL		0x14
/* vpss BL register offsets */
#define DM355_VPSSBL_CCDCMUX		0x1c
/* vpss CLK register offsets */
#define DM355_VPSSCLK_CLKCTRL		0x04
/* masks and shifts */
#define VPSS_HSSISEL_SHIFT		4
/*
 * VDINT0 - vpss_int0, VDINT1 - vpss_int1, H3A - vpss_int4,
 * IPIPE_INT1_SDR - vpss_int5
 */
#define DM355_VPSSBL_INTSEL_DEFAULT	0xff83ff10
/* VENCINT - vpss_int8 */
#define DM355_VPSSBL_EVTSEL_DEFAULT	0x4

#define DM365_ISP5_PCCR				0x04
#define DM365_ISP5_PCCR_BL_CLK_ENABLE		BIT(0)
#define DM365_ISP5_PCCR_ISIF_CLK_ENABLE		BIT(1)
#define DM365_ISP5_PCCR_H3A_CLK_ENABLE		BIT(2)
#define DM365_ISP5_PCCR_RSZ_CLK_ENABLE		BIT(3)
#define DM365_ISP5_PCCR_IPIPE_CLK_ENABLE	BIT(4)
#define DM365_ISP5_PCCR_IPIPEIF_CLK_ENABLE	BIT(5)
#define DM365_ISP5_PCCR_RSV			BIT(6)

#define DM365_ISP5_BCR			0x08
#define DM365_ISP5_BCR_ISIF_OUT_ENABLE	BIT(1)

#define DM365_ISP5_INTSEL1		0x10
#define DM365_ISP5_INTSEL2		0x14
#define DM365_ISP5_INTSEL3		0x18
#define DM365_ISP5_CCDCMUX 		0x20
#define DM365_ISP5_PG_FRAME_SIZE 	0x28
#define DM365_VPBE_CLK_CTRL 		0x00

#define VPSS_CLK_CTRL			0x01c40044
#define VPSS_CLK_CTRL_VENCCLKEN		BIT(3)
#define VPSS_CLK_CTRL_DACCLKEN		BIT(4)

/*
 * vpss interrupts. VDINT0 - vpss_int0, VDINT1 - vpss_int1,
 * AF - vpss_int3
 */
#define DM365_ISP5_INTSEL1_DEFAULT	0x0b1f0100
/* AEW - vpss_int6, RSZ_INT_DMA - vpss_int5 */
#define DM365_ISP5_INTSEL2_DEFAULT	0x1f0a0f1f
/* VENC - vpss_int8 */
#define DM365_ISP5_INTSEL3_DEFAULT	0x00000015

/* masks and shifts for DM365*/
#define DM365_CCDC_PG_VD_POL_SHIFT 	0
#define DM365_CCDC_PG_HD_POL_SHIFT 	1

#define CCD_SRC_SEL_MASK		(BIT_MASK(5) | BIT_MASK(4))
#define CCD_SRC_SEL_SHIFT		4

/* Different SoC platforms supported by this driver */
enum vpss_platform_type {
	DM644X,
	DM355,
	DM365,
};

/*
 * vpss operations. Depends on platform. Not all functions are available
 * on all platforms. The api, first check if a function is available before
 * invoking it. In the probe, the function ptrs are initialized based on
 * vpss name. vpss name can be "dm355_vpss", "dm644x_vpss" etc.
 */
struct vpss_hw_ops {
	/* enable clock */
	int (*enable_clock)(enum vpss_clock_sel clock_sel, int en);
	/* select input to ccdc */
	void (*select_ccdc_source)(enum vpss_ccdc_source_sel src_sel);
	/* clear wbl overflow bit */
	int (*clear_wbl_overflow)(enum vpss_wbl_sel wbl_sel);
	/* set sync polarity */
	void (*set_sync_pol)(struct vpss_sync_pol);
	/* set the PG_FRAME_SIZE register*/
	void (*set_pg_frame_size)(struct vpss_pg_frame_size);
	/* check and clear interrupt if occurred */
	int (*dma_complete_interrupt)(void);
};

/* vpss configuration */
struct vpss_oper_config {
	__iomem void *vpss_regs_base0;
	__iomem void *vpss_regs_base1;
	resource_size_t *vpss_regs_base2;
	enum vpss_platform_type platform;
	spinlock_t vpss_lock;
	struct vpss_hw_ops hw_ops;
};

static struct vpss_oper_config oper_cfg;

/* register access routines */
static inline u32 bl_regr(u32 offset)
{
	return __raw_readl(oper_cfg.vpss_regs_base0 + offset);
}

static inline void bl_regw(u32 val, u32 offset)
{
	__raw_writel(val, oper_cfg.vpss_regs_base0 + offset);
}

static inline u32 vpss_regr(u32 offset)
{
	return __raw_readl(oper_cfg.vpss_regs_base1 + offset);
}

static inline void vpss_regw(u32 val, u32 offset)
{
	__raw_writel(val, oper_cfg.vpss_regs_base1 + offset);
}

/* For DM365 only */
static inline u32 isp5_read(u32 offset)
{
	return __raw_readl(oper_cfg.vpss_regs_base0 + offset);
}

/* For DM365 only */
static inline void isp5_write(u32 val, u32 offset)
{
	__raw_writel(val, oper_cfg.vpss_regs_base0 + offset);
}

static void dm365_select_ccdc_source(enum vpss_ccdc_source_sel src_sel)
{
	u32 temp = isp5_read(DM365_ISP5_CCDCMUX) & ~CCD_SRC_SEL_MASK;

	/* if we are using pattern generator, enable it */
	if (src_sel == VPSS_PGLPBK || src_sel == VPSS_CCDCPG)
		temp |= 0x08;

	temp |= (src_sel << CCD_SRC_SEL_SHIFT);
	isp5_write(temp, DM365_ISP5_CCDCMUX);
}

static void dm355_select_ccdc_source(enum vpss_ccdc_source_sel src_sel)
{
	bl_regw(src_sel << VPSS_HSSISEL_SHIFT, DM355_VPSSBL_CCDCMUX);
}

int vpss_dma_complete_interrupt(void)
{
	if (!oper_cfg.hw_ops.dma_complete_interrupt)
		return 2;
	return oper_cfg.hw_ops.dma_complete_interrupt();
}
EXPORT_SYMBOL(vpss_dma_complete_interrupt);

int vpss_select_ccdc_source(enum vpss_ccdc_source_sel src_sel)
{
	if (!oper_cfg.hw_ops.select_ccdc_source)
		return -EINVAL;

	oper_cfg.hw_ops.select_ccdc_source(src_sel);
	return 0;
}
EXPORT_SYMBOL(vpss_select_ccdc_source);

static int dm644x_clear_wbl_overflow(enum vpss_wbl_sel wbl_sel)
{
	u32 mask = 1, val;

	if (wbl_sel < VPSS_PCR_AEW_WBL_0 ||
	    wbl_sel > VPSS_PCR_CCDC_WBL_O)
		return -EINVAL;

	/* writing a 0 clear the overflow */
	mask = ~(mask << wbl_sel);
	val = bl_regr(DM644X_SBL_PCR_VPSS) & mask;
	bl_regw(val, DM644X_SBL_PCR_VPSS);
	return 0;
}

void vpss_set_sync_pol(struct vpss_sync_pol sync)
{
	if (!oper_cfg.hw_ops.set_sync_pol)
		return;

	oper_cfg.hw_ops.set_sync_pol(sync);
}
EXPORT_SYMBOL(vpss_set_sync_pol);

int vpss_clear_wbl_overflow(enum vpss_wbl_sel wbl_sel)
{
	if (!oper_cfg.hw_ops.clear_wbl_overflow)
		return -EINVAL;

	return oper_cfg.hw_ops.clear_wbl_overflow(wbl_sel);
}
EXPORT_SYMBOL(vpss_clear_wbl_overflow);

/*
 *  dm355_enable_clock - Enable VPSS Clock
 *  @clock_sel: Clock to be enabled/disabled
 *  @en: enable/disable flag
 *
 *  This is called to enable or disable a vpss clock
 */
static int dm355_enable_clock(enum vpss_clock_sel clock_sel, int en)
{
	unsigned long flags;
	u32 utemp, mask = 0x1, shift = 0;

	switch (clock_sel) {
	case VPSS_VPBE_CLOCK:
		/* nothing since lsb */
		break;
	case VPSS_VENC_CLOCK_SEL:
		shift = 2;
		break;
	case VPSS_CFALD_CLOCK:
		shift = 3;
		break;
	case VPSS_H3A_CLOCK:
		shift = 4;
		break;
	case VPSS_IPIPE_CLOCK:
		shift = 5;
		break;
	case VPSS_CCDC_CLOCK:
		shift = 6;
		break;
	default:
		printk(KERN_ERR "dm355_enable_clock: Invalid selector: %d\n",
		       clock_sel);
		return -EINVAL;
	}

	spin_lock_irqsave(&oper_cfg.vpss_lock, flags);
	utemp = vpss_regr(DM355_VPSSCLK_CLKCTRL);
	if (!en)
		utemp &= ~(mask << shift);
	else
		utemp |= (mask << shift);

	vpss_regw(utemp, DM355_VPSSCLK_CLKCTRL);
	spin_unlock_irqrestore(&oper_cfg.vpss_lock, flags);
	return 0;
}

static int dm365_enable_clock(enum vpss_clock_sel clock_sel, int en)
{
	unsigned long flags;
	u32 utemp, mask = 0x1, shift = 0, offset = DM365_ISP5_PCCR;
	u32 (*read)(u32 offset) = isp5_read;
	void(*write)(u32 val, u32 offset) = isp5_write;

	switch (clock_sel) {
	case VPSS_BL_CLOCK:
		break;
	case VPSS_CCDC_CLOCK:
		shift = 1;
		break;
	case VPSS_H3A_CLOCK:
		shift = 2;
		break;
	case VPSS_RSZ_CLOCK:
		shift = 3;
		break;
	case VPSS_IPIPE_CLOCK:
		shift = 4;
		break;
	case VPSS_IPIPEIF_CLOCK:
		shift = 5;
		break;
	case VPSS_PCLK_INTERNAL:
		shift = 6;
		break;
	case VPSS_PSYNC_CLOCK_SEL:
		shift = 7;
		break;
	case VPSS_VPBE_CLOCK:
		read = vpss_regr;
		write = vpss_regw;
		offset = DM365_VPBE_CLK_CTRL;
		break;
	case VPSS_VENC_CLOCK_SEL:
		shift = 2;
		read = vpss_regr;
		write = vpss_regw;
		offset = DM365_VPBE_CLK_CTRL;
		break;
	case VPSS_LDC_CLOCK:
		shift = 3;
		read = vpss_regr;
		write = vpss_regw;
		offset = DM365_VPBE_CLK_CTRL;
		break;
	case VPSS_FDIF_CLOCK:
		shift = 4;
		read = vpss_regr;
		write = vpss_regw;
		offset = DM365_VPBE_CLK_CTRL;
		break;
	case VPSS_OSD_CLOCK_SEL:
		shift = 6;
		read = vpss_regr;
		write = vpss_regw;
		offset = DM365_VPBE_CLK_CTRL;
		break;
	case VPSS_LDC_CLOCK_SEL:
		shift = 7;
		read = vpss_regr;
		write = vpss_regw;
		offset = DM365_VPBE_CLK_CTRL;
		break;
	default:
		printk(KERN_ERR "dm365_enable_clock: Invalid selector: %d\n",
		       clock_sel);
		return -1;
	}

	spin_lock_irqsave(&oper_cfg.vpss_lock, flags);
	utemp = read(offset);
	if (!en) {
		mask = ~mask;
		utemp &= (mask << shift);
	} else
		utemp |= (mask << shift);

	write(utemp, offset);
	spin_unlock_irqrestore(&oper_cfg.vpss_lock, flags);

	return 0;
}

int vpss_enable_clock(enum vpss_clock_sel clock_sel, int en)
{
	if (!oper_cfg.hw_ops.enable_clock)
		return -EINVAL;

	return oper_cfg.hw_ops.enable_clock(clock_sel, en);
}
EXPORT_SYMBOL(vpss_enable_clock);

void dm365_vpss_set_sync_pol(struct vpss_sync_pol sync)
{
	int val = 0;
	val = isp5_read(DM365_ISP5_CCDCMUX);

	val |= (sync.ccdpg_hdpol << DM365_CCDC_PG_HD_POL_SHIFT);
	val |= (sync.ccdpg_vdpol << DM365_CCDC_PG_VD_POL_SHIFT);

	isp5_write(val, DM365_ISP5_CCDCMUX);
}
EXPORT_SYMBOL(dm365_vpss_set_sync_pol);

void vpss_set_pg_frame_size(struct vpss_pg_frame_size frame_size)
{
	if (!oper_cfg.hw_ops.set_pg_frame_size)
		return;

	oper_cfg.hw_ops.set_pg_frame_size(frame_size);
}
EXPORT_SYMBOL(vpss_set_pg_frame_size);

void dm365_vpss_set_pg_frame_size(struct vpss_pg_frame_size frame_size)
{
	int current_reg = ((frame_size.hlpfr >> 1) - 1) << 16;

	current_reg |= (frame_size.pplen - 1);
	isp5_write(current_reg, DM365_ISP5_PG_FRAME_SIZE);
}
EXPORT_SYMBOL(dm365_vpss_set_pg_frame_size);

static int vpss_probe(struct platform_device *pdev)
{
	struct resource *res;
	char *platform_name;

	if (!pdev->dev.platform_data) {
		dev_err(&pdev->dev, "no platform data\n");
		return -ENOENT;
	}

	platform_name = pdev->dev.platform_data;
	if (!strcmp(platform_name, "dm355_vpss"))
		oper_cfg.platform = DM355;
	else if (!strcmp(platform_name, "dm365_vpss"))
		oper_cfg.platform = DM365;
	else if (!strcmp(platform_name, "dm644x_vpss"))
		oper_cfg.platform = DM644X;
	else {
		dev_err(&pdev->dev, "vpss driver not supported on this platform\n");
		return -ENODEV;
	}

	dev_info(&pdev->dev, "%s vpss probed\n", platform_name);
	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);

	oper_cfg.vpss_regs_base0 = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(oper_cfg.vpss_regs_base0))
		return PTR_ERR(oper_cfg.vpss_regs_base0);

	if (oper_cfg.platform == DM355 || oper_cfg.platform == DM365) {
		res = platform_get_resource(pdev, IORESOURCE_MEM, 1);

		oper_cfg.vpss_regs_base1 = devm_ioremap_resource(&pdev->dev,
								 res);
		if (IS_ERR(oper_cfg.vpss_regs_base1))
			return PTR_ERR(oper_cfg.vpss_regs_base1);
	}

	if (oper_cfg.platform == DM355) {
		oper_cfg.hw_ops.enable_clock = dm355_enable_clock;
		oper_cfg.hw_ops.select_ccdc_source = dm355_select_ccdc_source;
		/* Setup vpss interrupts */
		bl_regw(DM355_VPSSBL_INTSEL_DEFAULT, DM355_VPSSBL_INTSEL);
		bl_regw(DM355_VPSSBL_EVTSEL_DEFAULT, DM355_VPSSBL_EVTSEL);
	} else if (oper_cfg.platform == DM365) {
		oper_cfg.hw_ops.enable_clock = dm365_enable_clock;
		oper_cfg.hw_ops.select_ccdc_source = dm365_select_ccdc_source;
		/* Setup vpss interrupts */
		isp5_write((isp5_read(DM365_ISP5_PCCR) |
				      DM365_ISP5_PCCR_BL_CLK_ENABLE |
				      DM365_ISP5_PCCR_ISIF_CLK_ENABLE |
				      DM365_ISP5_PCCR_H3A_CLK_ENABLE |
				      DM365_ISP5_PCCR_RSZ_CLK_ENABLE |
				      DM365_ISP5_PCCR_IPIPE_CLK_ENABLE |
				      DM365_ISP5_PCCR_IPIPEIF_CLK_ENABLE |
				      DM365_ISP5_PCCR_RSV), DM365_ISP5_PCCR);
		isp5_write((isp5_read(DM365_ISP5_BCR) |
			    DM365_ISP5_BCR_ISIF_OUT_ENABLE), DM365_ISP5_BCR);
		isp5_write(DM365_ISP5_INTSEL1_DEFAULT, DM365_ISP5_INTSEL1);
		isp5_write(DM365_ISP5_INTSEL2_DEFAULT, DM365_ISP5_INTSEL2);
		isp5_write(DM365_ISP5_INTSEL3_DEFAULT, DM365_ISP5_INTSEL3);
	} else
		oper_cfg.hw_ops.clear_wbl_overflow = dm644x_clear_wbl_overflow;

	pm_runtime_enable(&pdev->dev);

	pm_runtime_get(&pdev->dev);

	spin_lock_init(&oper_cfg.vpss_lock);
	dev_info(&pdev->dev, "%s vpss probe success\n", platform_name);

	return 0;
}

static int vpss_remove(struct platform_device *pdev)
{
	pm_runtime_disable(&pdev->dev);
	return 0;
}

static int vpss_suspend(struct device *dev)
{
	pm_runtime_put(dev);
	return 0;
}

static int vpss_resume(struct device *dev)
{
	pm_runtime_get(dev);
	return 0;
}

static const struct dev_pm_ops vpss_pm_ops = {
	.suspend = vpss_suspend,
	.resume = vpss_resume,
};

static struct platform_driver vpss_driver = {
	.driver = {
		.name	= "vpss",
		.pm = &vpss_pm_ops,
	},
	.remove = vpss_remove,
	.probe = vpss_probe,
};

static void vpss_exit(void)
{
	iounmap(oper_cfg.vpss_regs_base2);
	release_mem_region(VPSS_CLK_CTRL, 4);
	platform_driver_unregister(&vpss_driver);
}

static int __init vpss_init(void)
{
	if (!request_mem_region(VPSS_CLK_CTRL, 4, "vpss_clock_control"))
		return -EBUSY;

	oper_cfg.vpss_regs_base2 = ioremap(VPSS_CLK_CTRL, 4);
	writel(VPSS_CLK_CTRL_VENCCLKEN |
		     VPSS_CLK_CTRL_DACCLKEN, oper_cfg.vpss_regs_base2);

	return platform_driver_register(&vpss_driver);
}
subsys_initcall(vpss_init);
module_exit(vpss_exit);
Commit	Line	Data
7b140b89 MK	1	/*
	2	* Copyright (C) 2009 Texas Instruments.
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License as published by
	6	* the Free Software Foundation; either version 2 of the License, or
	7	* (at your option) any later version.
	8	*
	9	* This program is distributed in the hope that it will be useful,
	10	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	12	* GNU General Public License for more details.
	13	*
85b848ca	14	* common vpss system module platform driver for all video drivers.
7b140b89	15	*/
7b140b89 MK	16	#include <linux/module.h>
7b140b89 MK	17	#include <linux/platform_device.h>
7b140b89	18	#include <linux/io.h>
9a3e89b1	19	#include <linux/pm_runtime.h>
6ef83359	20	#include <linux/err.h>
9a3e89b1	21
7b140b89 MK	22	#include <media/davinci/vpss.h>
	23
	24	MODULE_LICENSE("GPL");
	25	MODULE_DESCRIPTION("VPSS Driver");
	26	MODULE_AUTHOR("Texas Instruments");
	27
	28	/* DM644x defines */
	29	#define DM644X_SBL_PCR_VPSS (4)
	30
85b848ca MK	31	#define DM355_VPSSBL_INTSEL 0x10
85b848ca MK	32	#define DM355_VPSSBL_EVTSEL 0x14
7b140b89 MK	33	/* vpss BL register offsets */
	34	#define DM355_VPSSBL_CCDCMUX 0x1c
	35	/* vpss CLK register offsets */
	36	#define DM355_VPSSCLK_CLKCTRL 0x04
	37	/* masks and shifts */
	38	#define VPSS_HSSISEL_SHIFT 4
85b848ca MK	39	/*
	40	* VDINT0 - vpss_int0, VDINT1 - vpss_int1, H3A - vpss_int4,
	41	* IPIPE_INT1_SDR - vpss_int5
	42	*/
	43	#define DM355_VPSSBL_INTSEL_DEFAULT 0xff83ff10
	44	/* VENCINT - vpss_int8 */
	45	#define DM355_VPSSBL_EVTSEL_DEFAULT 0x4
	46
c1819fc5 MH	47	#define DM365_ISP5_PCCR 0x04
	48	#define DM365_ISP5_PCCR_BL_CLK_ENABLE BIT(0)
	49	#define DM365_ISP5_PCCR_ISIF_CLK_ENABLE BIT(1)
	50	#define DM365_ISP5_PCCR_H3A_CLK_ENABLE BIT(2)
	51	#define DM365_ISP5_PCCR_RSZ_CLK_ENABLE BIT(3)
	52	#define DM365_ISP5_PCCR_IPIPE_CLK_ENABLE BIT(4)
	53	#define DM365_ISP5_PCCR_IPIPEIF_CLK_ENABLE BIT(5)
	54	#define DM365_ISP5_PCCR_RSV BIT(6)
	55
	56	#define DM365_ISP5_BCR 0x08
	57	#define DM365_ISP5_BCR_ISIF_OUT_ENABLE BIT(1)
	58
85b848ca MK	59	#define DM365_ISP5_INTSEL1 0x10
	60	#define DM365_ISP5_INTSEL2 0x14
	61	#define DM365_ISP5_INTSEL3 0x18
	62	#define DM365_ISP5_CCDCMUX 0x20
	63	#define DM365_ISP5_PG_FRAME_SIZE 0x28
	64	#define DM365_VPBE_CLK_CTRL 0x00
3de93941 MH	65
	66	#define VPSS_CLK_CTRL 0x01c40044
	67	#define VPSS_CLK_CTRL_VENCCLKEN BIT(3)
	68	#define VPSS_CLK_CTRL_DACCLKEN BIT(4)
	69
85b848ca MK	70	/*
	71	* vpss interrupts. VDINT0 - vpss_int0, VDINT1 - vpss_int1,
	72	* AF - vpss_int3
	73	*/
	74	#define DM365_ISP5_INTSEL1_DEFAULT 0x0b1f0100
	75	/* AEW - vpss_int6, RSZ_INT_DMA - vpss_int5 */
	76	#define DM365_ISP5_INTSEL2_DEFAULT 0x1f0a0f1f
	77	/* VENC - vpss_int8 */
	78	#define DM365_ISP5_INTSEL3_DEFAULT 0x00000015
	79
	80	/* masks and shifts for DM365*/
	81	#define DM365_CCDC_PG_VD_POL_SHIFT 0
	82	#define DM365_CCDC_PG_HD_POL_SHIFT 1
	83
	84	#define CCD_SRC_SEL_MASK (BIT_MASK(5) \| BIT_MASK(4))
	85	#define CCD_SRC_SEL_SHIFT 4
	86
	87	/* Different SoC platforms supported by this driver */
	88	enum vpss_platform_type {
	89	DM644X,
	90	DM355,
	91	DM365,
	92	};
7b140b89 MK	93
	94	/*
	95	* vpss operations. Depends on platform. Not all functions are available
54d5e4be	96	* on all platforms. The api, first check if a function is available before
b595076a	97	* invoking it. In the probe, the function ptrs are initialized based on
7b140b89 MK	98	* vpss name. vpss name can be "dm355_vpss", "dm644x_vpss" etc.
	99	*/
	100	struct vpss_hw_ops {
	101	/* enable clock */
	102	int (*enable_clock)(enum vpss_clock_sel clock_sel, int en);
	103	/* select input to ccdc */
	104	void (*select_ccdc_source)(enum vpss_ccdc_source_sel src_sel);
af901ca1	105	/* clear wbl overflow bit */
7b140b89	106	int (*clear_wbl_overflow)(enum vpss_wbl_sel wbl_sel);
d31c1002 MH	107	/* set sync polarity */
	108	void (*set_sync_pol)(struct vpss_sync_pol);
	109	/* set the PG_FRAME_SIZE register*/
	110	void (*set_pg_frame_size)(struct vpss_pg_frame_size);
54d5e4be	111	/* check and clear interrupt if occurred */
d31c1002	112	int (*dma_complete_interrupt)(void);
7b140b89 MK	113	};
	114
	115	/* vpss configuration */
	116	struct vpss_oper_config {
85b848ca MK	117	__iomem void *vpss_regs_base0;
85b848ca MK	118	__iomem void *vpss_regs_base1;
3de93941	119	resource_size_t *vpss_regs_base2;
85b848ca	120	enum vpss_platform_type platform;
7b140b89 MK	121	spinlock_t vpss_lock;
	122	struct vpss_hw_ops hw_ops;
	123	};
	124
	125	static struct vpss_oper_config oper_cfg;
	126
	127	/* register access routines */
	128	static inline u32 bl_regr(u32 offset)
	129	{
85b848ca	130	return __raw_readl(oper_cfg.vpss_regs_base0 + offset);
7b140b89 MK	131	}
	132
	133	static inline void bl_regw(u32 val, u32 offset)
	134	{
85b848ca	135	__raw_writel(val, oper_cfg.vpss_regs_base0 + offset);
7b140b89 MK	136	}
	137
	138	static inline u32 vpss_regr(u32 offset)
	139	{
85b848ca	140	return __raw_readl(oper_cfg.vpss_regs_base1 + offset);
7b140b89 MK	141	}
	142
	143	static inline void vpss_regw(u32 val, u32 offset)
	144	{
85b848ca MK	145	__raw_writel(val, oper_cfg.vpss_regs_base1 + offset);
	146	}
	147
	148	/* For DM365 only */
	149	static inline u32 isp5_read(u32 offset)
	150	{
	151	return __raw_readl(oper_cfg.vpss_regs_base0 + offset);
	152	}
	153
	154	/* For DM365 only */
	155	static inline void isp5_write(u32 val, u32 offset)
	156	{
	157	__raw_writel(val, oper_cfg.vpss_regs_base0 + offset);
	158	}
	159
	160	static void dm365_select_ccdc_source(enum vpss_ccdc_source_sel src_sel)
	161	{
	162	u32 temp = isp5_read(DM365_ISP5_CCDCMUX) & ~CCD_SRC_SEL_MASK;
	163
	164	/* if we are using pattern generator, enable it */
	165	if (src_sel == VPSS_PGLPBK \|\| src_sel == VPSS_CCDCPG)
	166	temp \|= 0x08;
	167
	168	temp \|= (src_sel << CCD_SRC_SEL_SHIFT);
	169	isp5_write(temp, DM365_ISP5_CCDCMUX);
7b140b89 MK	170	}
	171
	172	static void dm355_select_ccdc_source(enum vpss_ccdc_source_sel src_sel)
	173	{
	174	bl_regw(src_sel << VPSS_HSSISEL_SHIFT, DM355_VPSSBL_CCDCMUX);
	175	}
	176
d31c1002 MH	177	int vpss_dma_complete_interrupt(void)
	178	{
	179	if (!oper_cfg.hw_ops.dma_complete_interrupt)
	180	return 2;
	181	return oper_cfg.hw_ops.dma_complete_interrupt();
	182	}
	183	EXPORT_SYMBOL(vpss_dma_complete_interrupt);
	184
7b140b89 MK	185	int vpss_select_ccdc_source(enum vpss_ccdc_source_sel src_sel)
	186	{
	187	if (!oper_cfg.hw_ops.select_ccdc_source)
85b848ca	188	return -EINVAL;
7b140b89	189
85b848ca	190	oper_cfg.hw_ops.select_ccdc_source(src_sel);
7b140b89 MK	191	return 0;
	192	}
	193	EXPORT_SYMBOL(vpss_select_ccdc_source);
	194
	195	static int dm644x_clear_wbl_overflow(enum vpss_wbl_sel wbl_sel)
	196	{
	197	u32 mask = 1, val;
	198
	199	if (wbl_sel < VPSS_PCR_AEW_WBL_0 \|\|
	200	wbl_sel > VPSS_PCR_CCDC_WBL_O)
85b848ca	201	return -EINVAL;
7b140b89 MK	202
	203	/* writing a 0 clear the overflow */
	204	mask = ~(mask << wbl_sel);
	205	val = bl_regr(DM644X_SBL_PCR_VPSS) & mask;
	206	bl_regw(val, DM644X_SBL_PCR_VPSS);
	207	return 0;
	208	}
	209
d31c1002 MH	210	void vpss_set_sync_pol(struct vpss_sync_pol sync)
	211	{
	212	if (!oper_cfg.hw_ops.set_sync_pol)
	213	return;
	214
	215	oper_cfg.hw_ops.set_sync_pol(sync);
	216	}
	217	EXPORT_SYMBOL(vpss_set_sync_pol);
	218
7b140b89 MK	219	int vpss_clear_wbl_overflow(enum vpss_wbl_sel wbl_sel)
	220	{
	221	if (!oper_cfg.hw_ops.clear_wbl_overflow)
85b848ca	222	return -EINVAL;
7b140b89 MK	223
	224	return oper_cfg.hw_ops.clear_wbl_overflow(wbl_sel);
	225	}
	226	EXPORT_SYMBOL(vpss_clear_wbl_overflow);
	227
	228	/*
	229	* dm355_enable_clock - Enable VPSS Clock
54d5e4be	230	* @clock_sel: Clock to be enabled/disabled
7b140b89 MK	231	* @en: enable/disable flag
	232	*
	233	* This is called to enable or disable a vpss clock
	234	*/
	235	static int dm355_enable_clock(enum vpss_clock_sel clock_sel, int en)
	236	{
	237	unsigned long flags;
	238	u32 utemp, mask = 0x1, shift = 0;
	239
	240	switch (clock_sel) {
	241	case VPSS_VPBE_CLOCK:
	242	/* nothing since lsb */
	243	break;
	244	case VPSS_VENC_CLOCK_SEL:
	245	shift = 2;
	246	break;
	247	case VPSS_CFALD_CLOCK:
	248	shift = 3;
	249	break;
	250	case VPSS_H3A_CLOCK:
	251	shift = 4;
	252	break;
	253	case VPSS_IPIPE_CLOCK:
	254	shift = 5;
	255	break;
	256	case VPSS_CCDC_CLOCK:
	257	shift = 6;
	258	break;
	259	default:
ded026e0 MCC	260	printk(KERN_ERR "dm355_enable_clock: Invalid selector: %d\n",
ded026e0 MCC	261	clock_sel);
85b848ca	262	return -EINVAL;
7b140b89 MK	263	}
	264
	265	spin_lock_irqsave(&oper_cfg.vpss_lock, flags);
	266	utemp = vpss_regr(DM355_VPSSCLK_CLKCTRL);
	267	if (!en)
	268	utemp &= ~(mask << shift);
	269	else
	270	utemp \|= (mask << shift);
	271
	272	vpss_regw(utemp, DM355_VPSSCLK_CLKCTRL);
	273	spin_unlock_irqrestore(&oper_cfg.vpss_lock, flags);
	274	return 0;
	275	}
	276
85b848ca MK	277	static int dm365_enable_clock(enum vpss_clock_sel clock_sel, int en)
	278	{
	279	unsigned long flags;
	280	u32 utemp, mask = 0x1, shift = 0, offset = DM365_ISP5_PCCR;
	281	u32 (*read)(u32 offset) = isp5_read;
	282	void(*write)(u32 val, u32 offset) = isp5_write;
	283
	284	switch (clock_sel) {
	285	case VPSS_BL_CLOCK:
	286	break;
	287	case VPSS_CCDC_CLOCK:
	288	shift = 1;
	289	break;
	290	case VPSS_H3A_CLOCK:
	291	shift = 2;
	292	break;
	293	case VPSS_RSZ_CLOCK:
	294	shift = 3;
	295	break;
	296	case VPSS_IPIPE_CLOCK:
	297	shift = 4;
	298	break;
	299	case VPSS_IPIPEIF_CLOCK:
	300	shift = 5;
	301	break;
	302	case VPSS_PCLK_INTERNAL:
	303	shift = 6;
	304	break;
	305	case VPSS_PSYNC_CLOCK_SEL:
	306	shift = 7;
	307	break;
	308	case VPSS_VPBE_CLOCK:
	309	read = vpss_regr;
	310	write = vpss_regw;
	311	offset = DM365_VPBE_CLK_CTRL;
	312	break;
	313	case VPSS_VENC_CLOCK_SEL:
	314	shift = 2;
	315	read = vpss_regr;
	316	write = vpss_regw;
	317	offset = DM365_VPBE_CLK_CTRL;
	318	break;
	319	case VPSS_LDC_CLOCK:
	320	shift = 3;
	321	read = vpss_regr;
	322	write = vpss_regw;
	323	offset = DM365_VPBE_CLK_CTRL;
	324	break;
	325	case VPSS_FDIF_CLOCK:
	326	shift = 4;
	327	read = vpss_regr;
	328	write = vpss_regw;
	329	offset = DM365_VPBE_CLK_CTRL;
	330	break;
	331	case VPSS_OSD_CLOCK_SEL:
	332	shift = 6;
	333	read = vpss_regr;
	334	write = vpss_regw;
	335	offset = DM365_VPBE_CLK_CTRL;
	336	break;
	337	case VPSS_LDC_CLOCK_SEL:
	338	shift = 7;
	339	read = vpss_regr;
	340	write = vpss_regw;
341	offset = DM365_VPBE_CLK_CTRL;
342	break;
343	default:
344	printk(KERN_ERR "dm365_enable_clock: Invalid selector: %d\n",
345	clock_sel);
346	return -1;
347	}
348
349	spin_lock_irqsave(&oper_cfg.vpss_lock, flags);
350	utemp = read(offset);
351	if (!en) {
352	mask = ~mask;
353	utemp &= (mask << shift);
354	} else
355	utemp \|= (mask << shift);
356
357	write(utemp, offset);
358	spin_unlock_irqrestore(&oper_cfg.vpss_lock, flags);
359
360	return 0;
361	}
362
7b140b89 MK	363	int vpss_enable_clock(enum vpss_clock_sel clock_sel, int en)
	364	{
	365	if (!oper_cfg.hw_ops.enable_clock)
85b848ca	366	return -EINVAL;
7b140b89 MK	367
	368	return oper_cfg.hw_ops.enable_clock(clock_sel, en);
	369	}
	370	EXPORT_SYMBOL(vpss_enable_clock);
	371
85b848ca MK	372	void dm365_vpss_set_sync_pol(struct vpss_sync_pol sync)
	373	{
	374	int val = 0;
	375	val = isp5_read(DM365_ISP5_CCDCMUX);
	376
	377	val \|= (sync.ccdpg_hdpol << DM365_CCDC_PG_HD_POL_SHIFT);
	378	val \|= (sync.ccdpg_vdpol << DM365_CCDC_PG_VD_POL_SHIFT);
	379
	380	isp5_write(val, DM365_ISP5_CCDCMUX);
	381	}
	382	EXPORT_SYMBOL(dm365_vpss_set_sync_pol);
	383
d31c1002 MH	384	void vpss_set_pg_frame_size(struct vpss_pg_frame_size frame_size)
	385	{
	386	if (!oper_cfg.hw_ops.set_pg_frame_size)
	387	return;
	388
	389	oper_cfg.hw_ops.set_pg_frame_size(frame_size);
	390	}
	391	EXPORT_SYMBOL(vpss_set_pg_frame_size);
	392
85b848ca MK	393	void dm365_vpss_set_pg_frame_size(struct vpss_pg_frame_size frame_size)
	394	{
	395	int current_reg = ((frame_size.hlpfr >> 1) - 1) << 16;
	396
	397	current_reg \|= (frame_size.pplen - 1);
	398	isp5_write(current_reg, DM365_ISP5_PG_FRAME_SIZE);
	399	}
	400	EXPORT_SYMBOL(dm365_vpss_set_pg_frame_size);
	401
4c62e976	402	static int vpss_probe(struct platform_device *pdev)
7b140b89	403	{
6ef83359	404	struct resource *res;
85b848ca	405	char *platform_name;
7b140b89 MK	406
	407	if (!pdev->dev.platform_data) {
	408	dev_err(&pdev->dev, "no platform data\n");
	409	return -ENOENT;
	410	}
7b140b89	411
85b848ca MK	412	platform_name = pdev->dev.platform_data;
	413	if (!strcmp(platform_name, "dm355_vpss"))
	414	oper_cfg.platform = DM355;
	415	else if (!strcmp(platform_name, "dm365_vpss"))
	416	oper_cfg.platform = DM365;
	417	else if (!strcmp(platform_name, "dm644x_vpss"))
	418	oper_cfg.platform = DM644X;
	419	else {
ded026e0	420	dev_err(&pdev->dev, "vpss driver not supported on this platform\n");
7b140b89 MK	421	return -ENODEV;
	422	}
	423
85b848ca	424	dev_info(&pdev->dev, "%s vpss probed\n", platform_name);
6ef83359	425	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
7b140b89	426
6ef83359 LP	427	oper_cfg.vpss_regs_base0 = devm_ioremap_resource(&pdev->dev, res);
	428	if (IS_ERR(oper_cfg.vpss_regs_base0))
	429	return PTR_ERR(oper_cfg.vpss_regs_base0);
7b140b89	430
85b848ca	431	if (oper_cfg.platform == DM355 \|\| oper_cfg.platform == DM365) {
6ef83359 LP	432	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
	433
	434	oper_cfg.vpss_regs_base1 = devm_ioremap_resource(&pdev->dev,
	435	res);
	436	if (IS_ERR(oper_cfg.vpss_regs_base1))
	437	return PTR_ERR(oper_cfg.vpss_regs_base1);
7b140b89 MK	438	}
7b140b89 MK	439
85b848ca	440	if (oper_cfg.platform == DM355) {
7b140b89 MK	441	oper_cfg.hw_ops.enable_clock = dm355_enable_clock;
7b140b89 MK	442	oper_cfg.hw_ops.select_ccdc_source = dm355_select_ccdc_source;
85b848ca MK	443	/* Setup vpss interrupts */
	444	bl_regw(DM355_VPSSBL_INTSEL_DEFAULT, DM355_VPSSBL_INTSEL);
	445	bl_regw(DM355_VPSSBL_EVTSEL_DEFAULT, DM355_VPSSBL_EVTSEL);
	446	} else if (oper_cfg.platform == DM365) {
	447	oper_cfg.hw_ops.enable_clock = dm365_enable_clock;
	448	oper_cfg.hw_ops.select_ccdc_source = dm365_select_ccdc_source;
	449	/* Setup vpss interrupts */
c1819fc5 MH	450	isp5_write((isp5_read(DM365_ISP5_PCCR) \|
	451	DM365_ISP5_PCCR_BL_CLK_ENABLE \|
	452	DM365_ISP5_PCCR_ISIF_CLK_ENABLE \|
	453	DM365_ISP5_PCCR_H3A_CLK_ENABLE \|
	454	DM365_ISP5_PCCR_RSZ_CLK_ENABLE \|
	455	DM365_ISP5_PCCR_IPIPE_CLK_ENABLE \|
	456	DM365_ISP5_PCCR_IPIPEIF_CLK_ENABLE \|
	457	DM365_ISP5_PCCR_RSV), DM365_ISP5_PCCR);
	458	isp5_write((isp5_read(DM365_ISP5_BCR) \|
	459	DM365_ISP5_BCR_ISIF_OUT_ENABLE), DM365_ISP5_BCR);
85b848ca MK	460	isp5_write(DM365_ISP5_INTSEL1_DEFAULT, DM365_ISP5_INTSEL1);
	461	isp5_write(DM365_ISP5_INTSEL2_DEFAULT, DM365_ISP5_INTSEL2);
	462	isp5_write(DM365_ISP5_INTSEL3_DEFAULT, DM365_ISP5_INTSEL3);
7b140b89 MK	463	} else
	464	oper_cfg.hw_ops.clear_wbl_overflow = dm644x_clear_wbl_overflow;
	465
9a3e89b1 LP	466	pm_runtime_enable(&pdev->dev);
	467
	468	pm_runtime_get(&pdev->dev);
	469
7b140b89	470	spin_lock_init(&oper_cfg.vpss_lock);
85b848ca	471	dev_info(&pdev->dev, "%s vpss probe success\n", platform_name);
7b140b89	472
6ef83359	473	return 0;
7b140b89 MK	474	}
7b140b89 MK	475
4c62e976	476	static int vpss_remove(struct platform_device *pdev)
7b140b89	477	{
9a3e89b1	478	pm_runtime_disable(&pdev->dev);
7b140b89 MK	479	return 0;
	480	}
	481
9a3e89b1 LP	482	static int vpss_suspend(struct device *dev)
	483	{
	484	pm_runtime_put(dev);
	485	return 0;
	486	}
	487
	488	static int vpss_resume(struct device *dev)
	489	{
	490	pm_runtime_get(dev);
	491	return 0;
	492	}
	493
	494	static const struct dev_pm_ops vpss_pm_ops = {
	495	.suspend = vpss_suspend,
	496	.resume = vpss_resume,
	497	};
	498
a1b3a6ce	499	static struct platform_driver vpss_driver = {
7b140b89 MK	500	.driver = {
7b140b89 MK	501	.name = "vpss",
9a3e89b1	502	.pm = &vpss_pm_ops,
7b140b89	503	},
4c62e976	504	.remove = vpss_remove,
7b140b89 MK	505	.probe = vpss_probe,
	506	};
	507
	508	static void vpss_exit(void)
	509	{
3de93941 MH	510	iounmap(oper_cfg.vpss_regs_base2);
3de93941 MH	511	release_mem_region(VPSS_CLK_CTRL, 4);
7b140b89 MK	512	platform_driver_unregister(&vpss_driver);
	513	}
	514
	515	static int __init vpss_init(void)
	516	{
3de93941 MH	517	if (!request_mem_region(VPSS_CLK_CTRL, 4, "vpss_clock_control"))
	518	return -EBUSY;
	519
	520	oper_cfg.vpss_regs_base2 = ioremap(VPSS_CLK_CTRL, 4);
	521	writel(VPSS_CLK_CTRL_VENCCLKEN \|
	522	VPSS_CLK_CTRL_DACCLKEN, oper_cfg.vpss_regs_base2);
	523
7b140b89 MK	524	return platform_driver_register(&vpss_driver);
	525	}
	526	subsys_initcall(vpss_init);
	527	module_exit(vpss_exit);